* [PATCHv15 0/3] Intel FPGA Video and Image Processing Suite
@ 2019-06-07 14:28 Hean-Loong, Ong
2019-06-07 14:28 ` [PATCHv15 1/3] ARM:dt-bindings:display " Hean-Loong, Ong
0 siblings, 1 reply; 5+ messages in thread
From: Hean-Loong, Ong @ 2019-06-07 14:28 UTC (permalink / raw)
To: Rob Herring, Dinh Nguyen, Daniel Vetter, Randy Dunlap
Cc: devicetree, hean.loong.ong, chin.liang.see, linux-kernel,
dri-devel, linux-arm-kernel
From: Hean-Loong Ong <hean.loong.ong@intel.com>
The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver
patch here is allocating memory for information to be streamed from the
ARM/Linux to the display port.
Basically the driver just wraps the information such as the pixels to be
drawn by the Sodt IP FrameBuffer 2.
The piece of hardware in discussion is the SoC FPGA where Linux runs on
the ARM chip and the FGPA is driven by its NIOS soft core with its own
proprietary firmware.
For example the application from the ARM Linux would have to write
information on the /dev/fb0 with the information stored in the
SDRAM to be fetched by the Framebuffer 2 Soft IP and displayed
on the Display Port Monitor.
Reviewed and ACKed need to merge this into drm-misc
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Rob Herring <robh@kernel.org>
Ong Hean Loong (1):
ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite
Ong, Hean Loong (2):
ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite
ARM:drm ivip Intel FPGA Video and Image Processing Suite
.../bindings/display/altr,vip-fb2.txt | 63 ++++
MAINTAINERS | 9 +
arch/arm/configs/socfpga_defconfig | 8 +
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/ivip/Kconfig | 14 +
drivers/gpu/drm/ivip/Makefile | 6 +
drivers/gpu/drm/ivip/intel_vip_conn.c | 93 +++++
drivers/gpu/drm/ivip/intel_vip_drv.c | 335 ++++++++++++++++++
drivers/gpu/drm/ivip/intel_vip_drv.h | 73 ++++
10 files changed, 604 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
create mode 100644 drivers/gpu/drm/ivip/Kconfig
create mode 100644 drivers/gpu/drm/ivip/Makefile
create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c
create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.c
create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h
--
2.17.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCHv15 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite
2019-06-07 14:28 [PATCHv15 0/3] Intel FPGA Video and Image Processing Suite Hean-Loong, Ong
@ 2019-06-07 14:28 ` Hean-Loong, Ong
0 siblings, 0 replies; 5+ messages in thread
From: Hean-Loong, Ong @ 2019-06-07 14:28 UTC (permalink / raw)
To: Rob Herring, Dinh Nguyen, Daniel Vetter, Randy Dunlap
Cc: devicetree, linux-kernel, linux-arm-kernel, dri-devel,
hean.loong.ong, chin.liang.see, Ong
From: "Ong, Hean Loong" <hean.loong.ong@intel.com>
Device tree binding for Intel FPGA Video and Image Processing Suite.
The bindings would set the max width, max height,
bits per pixel and memory port width.
The device tree binding only supports the Intel
Arria10 devkit and its variants. Vendor name retained as altr.
Reviewed-by: Rob Herring <robh@kernel.org>
V15:
Reviewed
V14:
No Change
V13:
No change
V12:
Wrap comments and fix commit message
V11:
No change
V10:
No change
V9:
Remove Display port node
V8:
*Add port to Display port decoder
V7:
*Fix OF graph for better description
*Add description for encoder
V6:
*Description have not describe DT device in general
V5:
*remove bindings for bits per symbol as it has only one value which is 8
V4:
*fix properties that does not describe the values
V3:
*OF graph not in accordance to graph.txt
V2:
*Remove Linux driver description
V1:
*Missing vendor prefix
Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
---
.../bindings/display/altr,vip-fb2.txt | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
diff --git a/Documentation/devicetree/bindings/display/altr,vip-fb2.txt b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
new file mode 100644
index 000000000000..89a3b9e166a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
@@ -0,0 +1,63 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware: Intel FPGA SoC Arria10 and above with display port IP
+
+The Video Frame Buffer II in Video Image Processing (VIP) suite is an IP core
+that interfaces between system memory and Avalon-ST video ports. The IP core
+can be configured to support the memory reader (from memory to Avalon-ST)
+and/or memory writer (from Avalon-ST to memory) interfaces.
+
+More information the FPGA video IP component can be acquired from
+https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\
+/literature/ug/ug_vip.pdf
+
+DT-Bindings:
+=============
+Required properties:
+----------------------------
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer controller's
+ registers.
+- altr,max-width: The maximum width of the framebuffer in pixels.
+- altr,max-height: The maximum height of the framebuffer in pixels.
+- altr,mem-port-width = the bus width of the avalon master port
+ on the frame reader
+
+Optional sub-nodes:
+- ports: The connection to the encoder
+
+Connections between the Frame Buffer II and other video IP cores in the system
+are modelled using the OF graph DT bindings. The Frame Buffer II node has up
+to two OF graph ports. When the memory writer interface is enabled, port 0
+maps to the Avalon-ST Input (din) port. When the memory reader interface is
+enabled, port 1 maps to the Avalon-ST Output (dout) port.
+
+The encoder is built into the FPGA HW design and therefore would not
+be accessible from the DDR.
+
+ Port 0 Port1
+---------------------------------------------------------
+ARRIA10 AVALON_ST (DIN) AVALON_ST (DOUT)
+
+Required Properties Example:
+----------------------------
+
+framebuffer@100000280 {
+ compatible = "altr,vip-frame-buffer-2.0";
+ reg = <0x00000001 0x00000280 0x00000040>;
+ altr,max-width = <1280>;
+ altr,max-height = <720>;
+ altr,mem-port-width = <128>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ fb_output: endpoint {
+ remote-endpoint = <&dp_encoder_input>;
+ };
+ };
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCHv15 0/3] Intel FPGA Video and Image Processing Suite
@ 2019-03-15 14:54 Hean-Loong Ong
2019-03-15 14:54 ` [PATCHv15 1/3] ARM:dt-bindings:display " Hean-Loong Ong
0 siblings, 1 reply; 5+ messages in thread
From: Hean-Loong Ong @ 2019-03-15 14:54 UTC (permalink / raw)
To: Rob Herring, Dinh Nguyen, Daniel Vetter, Randy Dunlap
Cc: hean.loong.ong, devicetree, chin.liang.see, dri-devel
The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver
patch here is allocating memory for information to be streamed from the
ARM/Linux to the display port.
Basically the driver just wraps the information such as the pixels to be
drawn by the Sodt IP FrameBuffer 2.
The piece of hardware in discussion is the SoC FPGA where Linux runs on
the ARM chip and the FGPA is driven by its NIOS soft core with its own
proprietary firmware.
For example the application from the ARM Linux would have to write
information on the /dev/fb0 with the information stored in the
SDRAM to be fetched by the Framebuffer 2 Soft IP and displayed
on the Display Port Monitor.
Ong Hean Loong (1):
ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite
Ong, Hean Loong (2):
ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite
ARM:drm ivip Intel FPGA Video and Image Processing Suite
.../bindings/display/altr,vip-fb2.txt | 63 ++++
MAINTAINERS | 9 +
arch/arm/configs/socfpga_defconfig | 8 +
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/ivip/Kconfig | 14 +
drivers/gpu/drm/ivip/Makefile | 6 +
drivers/gpu/drm/ivip/intel_vip_conn.c | 93 +++++
drivers/gpu/drm/ivip/intel_vip_drv.c | 335 ++++++++++++++++++
drivers/gpu/drm/ivip/intel_vip_drv.h | 73 ++++
10 files changed, 604 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
create mode 100644 drivers/gpu/drm/ivip/Kconfig
create mode 100644 drivers/gpu/drm/ivip/Makefile
create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c
create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.c
create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h
--
2.17.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCHv15 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite
2019-03-15 14:54 [PATCHv15 0/3] " Hean-Loong Ong
@ 2019-03-15 14:54 ` Hean-Loong Ong
2019-03-25 19:32 ` Rob Herring
0 siblings, 1 reply; 5+ messages in thread
From: Hean-Loong Ong @ 2019-03-15 14:54 UTC (permalink / raw)
To: Rob Herring, Dinh Nguyen, Daniel Vetter, Randy Dunlap
Cc: hean.loong.ong, devicetree, chin.liang.see, Ong, dri-devel
From: "Ong, Hean Loong" <hean.loong.ong@intel.com>
Device tree binding for Intel FPGA Video and Image Processing Suite.
The bindings would set the max width, max height,
bits per pixel and memory port width.
The device tree binding only supports the Intel
Arria10 devkit and its variants. Vendor name retained as altr.
V12:
Wrap comments and fix commit message
V11:
No change
V10:
No change
V9:
Remove Display port node
V8:
*Add port to Display port decoder
V7:
*Fix OF graph for better description
*Add description for encoder
V6:
*Description have not describe DT device in general
V5:
*remove bindings for bits per symbol as it has only one value which is 8
V4:
*fix properties that does not describe the values
V3:
*OF graph not in accordance to graph.txt
V2:
*Remove Linux driver description
V1:
*Missing vendor prefix
Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
---
.../bindings/display/altr,vip-fb2.txt | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
diff --git a/Documentation/devicetree/bindings/display/altr,vip-fb2.txt b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
new file mode 100644
index 000000000000..89a3b9e166a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
@@ -0,0 +1,63 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware: Intel FPGA SoC Arria10 and above with display port IP
+
+The Video Frame Buffer II in Video Image Processing (VIP) suite is an IP core
+that interfaces between system memory and Avalon-ST video ports. The IP core
+can be configured to support the memory reader (from memory to Avalon-ST)
+and/or memory writer (from Avalon-ST to memory) interfaces.
+
+More information the FPGA video IP component can be acquired from
+https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\
+/literature/ug/ug_vip.pdf
+
+DT-Bindings:
+=============
+Required properties:
+----------------------------
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer controller's
+ registers.
+- altr,max-width: The maximum width of the framebuffer in pixels.
+- altr,max-height: The maximum height of the framebuffer in pixels.
+- altr,mem-port-width = the bus width of the avalon master port
+ on the frame reader
+
+Optional sub-nodes:
+- ports: The connection to the encoder
+
+Connections between the Frame Buffer II and other video IP cores in the system
+are modelled using the OF graph DT bindings. The Frame Buffer II node has up
+to two OF graph ports. When the memory writer interface is enabled, port 0
+maps to the Avalon-ST Input (din) port. When the memory reader interface is
+enabled, port 1 maps to the Avalon-ST Output (dout) port.
+
+The encoder is built into the FPGA HW design and therefore would not
+be accessible from the DDR.
+
+ Port 0 Port1
+---------------------------------------------------------
+ARRIA10 AVALON_ST (DIN) AVALON_ST (DOUT)
+
+Required Properties Example:
+----------------------------
+
+framebuffer@100000280 {
+ compatible = "altr,vip-frame-buffer-2.0";
+ reg = <0x00000001 0x00000280 0x00000040>;
+ altr,max-width = <1280>;
+ altr,max-height = <720>;
+ altr,mem-port-width = <128>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ fb_output: endpoint {
+ remote-endpoint = <&dp_encoder_input>;
+ };
+ };
+ };
+};
--
2.17.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCHv15 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite
2019-03-15 14:54 ` [PATCHv15 1/3] ARM:dt-bindings:display " Hean-Loong Ong
@ 2019-03-25 19:32 ` Rob Herring
2019-03-26 7:36 ` Ong, Hean Loong
0 siblings, 1 reply; 5+ messages in thread
From: Rob Herring @ 2019-03-25 19:32 UTC (permalink / raw)
Cc: devicetree, chin.liang.see, hean.loong.ong, Daniel Vetter,
Randy Dunlap, dri-devel
On Fri, 15 Mar 2019 22:54:33 +0800, Hean-Loong Ong wrote:
> From: "Ong, Hean Loong" <hean.loong.ong@intel.com>
>
> Device tree binding for Intel FPGA Video and Image Processing Suite.
> The bindings would set the max width, max height,
> bits per pixel and memory port width.
> The device tree binding only supports the Intel
> Arria10 devkit and its variants. Vendor name retained as altr.
>
> V12:
> Wrap comments and fix commit message
>
> V11:
> No change
>
> V10:
> No change
>
> V9:
> Remove Display port node
>
> V8:
> *Add port to Display port decoder
>
> V7:
> *Fix OF graph for better description
> *Add description for encoder
>
> V6:
> *Description have not describe DT device in general
>
> V5:
> *remove bindings for bits per symbol as it has only one value which is 8
>
> V4:
> *fix properties that does not describe the values
>
> V3:
> *OF graph not in accordance to graph.txt
>
> V2:
> *Remove Linux driver description
>
> V1:
> *Missing vendor prefix
>
> Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
> ---
> .../bindings/display/altr,vip-fb2.txt | 63 +++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCHv15 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite
2019-03-25 19:32 ` Rob Herring
@ 2019-03-26 7:36 ` Ong, Hean Loong
0 siblings, 0 replies; 5+ messages in thread
From: Ong, Hean Loong @ 2019-03-26 7:36 UTC (permalink / raw)
To: Rob Herring
Cc: Daniel Vetter, Randy Dunlap, See, Chin Liang, dri-devel, devicetree
Hi,
May I know of the patches would be integrated into drm-misc ?
BR
Hean Loong
Internal Global Dial: 2 701 6773
Direct Line: +60 4 636 6773
>-----Original Message-----
>From: Rob Herring <robh@kernel.org>
>Sent: Tuesday, March 26, 2019 3:32 AM
>To: Ong, Hean Loong <hean.loong.ong@intel.com>
>Cc: Daniel Vetter <daniel.vetter@ffwll.ch>; Randy Dunlap
><rdunlap@infradead.org>; devicetree@vger.kernel.org; dri-
>devel@lists.freedesktop.org; Ong, Hean Loong <hean.loong.ong@intel.com>;
>See, Chin Liang <chin.liang.see@intel.com>
>Subject: Re: [PATCHv15 1/3] ARM:dt-bindings:display Intel FPGA Video and
>Image Processing Suite
>
>On Fri, 15 Mar 2019 22:54:33 +0800, Hean-Loong Ong wrote:
>> From: "Ong, Hean Loong" <hean.loong.ong@intel.com>
>>
>> Device tree binding for Intel FPGA Video and Image Processing Suite.
>> The bindings would set the max width, max height, bits per pixel and
>> memory port width.
>> The device tree binding only supports the Intel
>> Arria10 devkit and its variants. Vendor name retained as altr.
>>
>> V12:
>> Wrap comments and fix commit message
>>
>> V11:
>> No change
>>
>> V10:
>> No change
>>
>> V9:
>> Remove Display port node
>>
>> V8:
>> *Add port to Display port decoder
>>
>> V7:
>> *Fix OF graph for better description
>> *Add description for encoder
>>
>> V6:
>> *Description have not describe DT device in general
>>
>> V5:
>> *remove bindings for bits per symbol as it has only one value which is
>> 8
>>
>> V4:
>> *fix properties that does not describe the values
>>
>> V3:
>> *OF graph not in accordance to graph.txt
>>
>> V2:
>> *Remove Linux driver description
>>
>> V1:
>> *Missing vendor prefix
>>
>> Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
>> ---
>> .../bindings/display/altr,vip-fb2.txt | 63 +++++++++++++++++++
>> 1 file changed, 63 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/display/altr,vip-fb2.txt
>>
>
>Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 5+ messages in thread
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2019-03-15 14:54 [PATCHv15 0/3] " Hean-Loong Ong
2019-03-15 14:54 ` [PATCHv15 1/3] ARM:dt-bindings:display " Hean-Loong Ong
2019-03-25 19:32 ` Rob Herring
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