* [PATCH v2 05/17] drm/msm/dpu: Use OPP API to set clk/perf state
[not found] <1587132279-27659-1-git-send-email-rnayak@codeaurora.org>
@ 2020-04-17 14:04 ` Rajendra Nayak
2020-04-17 18:17 ` Matthias Kaehlcke
2020-04-17 14:04 ` [PATCH v2 06/17] drm/msm: dsi: " Rajendra Nayak
1 sibling, 1 reply; 4+ messages in thread
From: Rajendra Nayak @ 2020-04-17 14:04 UTC (permalink / raw)
To: viresh.kumar, sboyd, bjorn.andersson, agross
Cc: devicetree, Rajendra Nayak, linux-arm-msm, linux-kernel,
dri-devel, mka, Sean Paul
On some qualcomm platforms DPU needs to express a perforamnce state
requirement on a power domain depennding on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 20 +++++++++++++++++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++++
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 11f2beb..fe5717df 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -7,6 +7,7 @@
#include <linux/debugfs.h>
#include <linux/errno.h>
#include <linux/mutex.h>
+#include <linux/pm_opp.h>
#include <linux/sort.h>
#include <linux/clk.h>
#include <linux/bitmap.h>
@@ -239,7 +240,7 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
rate = core_clk->max_rate;
core_clk->rate = rate;
- return msm_dss_clk_set_rate(core_clk, 1);
+ return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate);
}
static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ce19f1d..cfce642 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -10,6 +10,7 @@
#include <linux/debugfs.h>
#include <linux/dma-buf.h>
#include <linux/of_irq.h>
+#include <linux/pm_opp.h>
#include <drm/drm_crtc.h>
#include <drm/drm_file.h>
@@ -1033,11 +1034,18 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
if (!dpu_kms)
return -ENOMEM;
+ dpu_kms->opp = dev_pm_opp_set_clkname(dev, "core");
+ if (IS_ERR(dpu_kms->opp))
+ return PTR_ERR(dpu_kms->opp);
+ /* OPP table is optional */
+ if (!dev_pm_opp_of_add_table(dev))
+ dpu_kms->opp_table = true;
+
mp = &dpu_kms->mp;
ret = msm_dss_parse_clock(pdev, mp);
if (ret) {
DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
- return ret;
+ goto err;
}
platform_set_drvdata(pdev, dpu_kms);
@@ -1051,6 +1059,11 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
priv->kms = &dpu_kms->base;
return ret;
+err:
+ if (dpu_kms->opp_table)
+ dev_pm_opp_of_remove_table(dev);
+ dev_pm_opp_put_clkname(dpu_kms->opp);
+ return ret;
}
static void dpu_unbind(struct device *dev, struct device *master, void *data)
@@ -1059,6 +1072,9 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data)
struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
struct dss_module_power *mp = &dpu_kms->mp;
+ if (dpu_kms->opp_table)
+ dev_pm_opp_of_remove_table(dev);
+ dev_pm_opp_put_clkname(dpu_kms->opp);
msm_dss_put_clk(mp->clk_config, mp->num_clk);
devm_kfree(&pdev->dev, mp->clk_config);
mp->num_clk = 0;
@@ -1090,6 +1106,8 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev)
struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
struct dss_module_power *mp = &dpu_kms->mp;
+ /* Drop the performance state vote */
+ dev_pm_opp_set_rate(dev, 0);
rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
if (rc)
DPU_ERROR("clock disable failed rc:%d\n", rc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 211f5de9..0060709 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -128,6 +128,10 @@ struct dpu_kms {
struct platform_device *pdev;
bool rpm_enabled;
+
+ struct opp_table *opp;
+ bool opp_table;
+
struct dss_module_power mp;
/* reference count bandwidth requests, so we know when we can
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 06/17] drm/msm: dsi: Use OPP API to set clk/perf state
[not found] <1587132279-27659-1-git-send-email-rnayak@codeaurora.org>
2020-04-17 14:04 ` [PATCH v2 05/17] drm/msm/dpu: Use OPP API to set clk/perf state Rajendra Nayak
@ 2020-04-17 14:04 ` Rajendra Nayak
1 sibling, 0 replies; 4+ messages in thread
From: Rajendra Nayak @ 2020-04-17 14:04 UTC (permalink / raw)
To: viresh.kumar, sboyd, bjorn.andersson, agross
Cc: devicetree, Rajendra Nayak, linux-arm-msm, linux-kernel,
dri-devel, mka, Sean Paul
On SDM845 DSI needs to express a perforamnce state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 4 +--
drivers/gpu/drm/msm/dsi/dsi_host.c | 53 ++++++++++++++++++++++++++++++++++++++
3 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 4de771d..ba7583c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -180,10 +180,12 @@ int msm_dsi_runtime_suspend(struct device *dev);
int msm_dsi_runtime_resume(struct device *dev);
int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host);
int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host);
+int dsi_link_clk_set_rate_6g_v2(struct msm_dsi_host *msm_host);
int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host);
int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host);
void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host);
void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host);
+void dsi_link_clk_disable_6g_v2(struct msm_dsi_host *msm_host);
int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size);
int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size);
void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 813d69d..773c4fe 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -210,9 +210,9 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
};
static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
- .link_clk_set_rate = dsi_link_clk_set_rate_6g,
+ .link_clk_set_rate = dsi_link_clk_set_rate_6g_v2,
.link_clk_enable = dsi_link_clk_enable_6g,
- .link_clk_disable = dsi_link_clk_disable_6g,
+ .link_clk_disable = dsi_link_clk_disable_6g_v2,
.clk_init_ver = dsi_clk_init_6g_v2,
.tx_buf_alloc = dsi_tx_buf_alloc_6g,
.tx_buf_get = dsi_tx_buf_get_6g,
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 11ae5b8..d532fab 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -14,6 +14,7 @@
#include <linux/of_graph.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/pm_opp.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spinlock.h>
@@ -111,6 +112,9 @@ struct msm_dsi_host {
struct clk *pixel_clk_src;
struct clk *byte_intf_clk;
+ struct opp_table *opp;
+ bool opp_table;
+
u32 byte_clk_rate;
u32 pixel_clk_rate;
u32 esc_clk_rate;
@@ -537,6 +541,38 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
return 0;
}
+int dsi_link_clk_set_rate_6g_v2(struct msm_dsi_host *msm_host)
+{
+ int ret;
+ struct device *dev = &msm_host->pdev->dev;
+
+ DBG("Set clk rates: pclk=%d, byteclk=%d",
+ msm_host->mode->clock, msm_host->byte_clk_rate);
+
+ ret = dev_pm_opp_set_rate(dev, msm_host->byte_clk_rate);
+ if (ret) {
+ pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
+ if (ret) {
+ pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
+ return ret;
+ }
+
+ if (msm_host->byte_intf_clk) {
+ ret = clk_set_rate(msm_host->byte_intf_clk,
+ msm_host->byte_clk_rate / 2);
+ if (ret) {
+ pr_err("%s: Failed to set rate byte intf clk, %d\n",
+ __func__, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
{
@@ -665,6 +701,13 @@ void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
clk_disable_unprepare(msm_host->byte_clk);
}
+void dsi_link_clk_disable_6g_v2(struct msm_dsi_host *msm_host)
+{
+ /* Drop the performance state vote */
+ dev_pm_opp_set_rate(&msm_host->pdev->dev, 0);
+ dsi_link_clk_disable_6g(msm_host);
+}
+
void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
{
clk_disable_unprepare(msm_host->pixel_clk);
@@ -1879,6 +1922,13 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi)
goto fail;
}
+ msm_host->opp = dev_pm_opp_set_clkname(&pdev->dev, "byte");
+ if (IS_ERR(msm_host->opp))
+ return PTR_ERR(msm_host->opp);
+ /* OPP table is optional */
+ if (!dev_pm_opp_of_add_table(&pdev->dev))
+ msm_host->opp_table = true;
+
init_completion(&msm_host->dma_comp);
init_completion(&msm_host->video_comp);
mutex_init(&msm_host->dev_mutex);
@@ -1904,6 +1954,9 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host)
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
DBG("");
+ if (msm_host->opp_table)
+ dev_pm_opp_of_remove_table(&msm_host->pdev->dev);
+ dev_pm_opp_put_clkname(msm_host->opp);
dsi_tx_buf_free(msm_host);
if (msm_host->workqueue) {
flush_workqueue(msm_host->workqueue);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 05/17] drm/msm/dpu: Use OPP API to set clk/perf state
2020-04-17 14:04 ` [PATCH v2 05/17] drm/msm/dpu: Use OPP API to set clk/perf state Rajendra Nayak
@ 2020-04-17 18:17 ` Matthias Kaehlcke
2020-04-18 8:12 ` Rajendra Nayak
0 siblings, 1 reply; 4+ messages in thread
From: Matthias Kaehlcke @ 2020-04-17 18:17 UTC (permalink / raw)
To: Rajendra Nayak
Cc: devicetree, sboyd, viresh.kumar, linux-kernel, dri-devel,
bjorn.andersson, agross, linux-arm-msm, Sean Paul
Hi Rajendra,
I have essentially the same comments as for "tty: serial: qcom_geni_serial:
Use OPP API to set clk/perf state" (https://patchwork.kernel.org/patch/11495209/).
about error handling of 'dev_pm_opp_of_add_table' and misleading struct
member names 'opp'/'opp_table'. Please apply the requested changes to the
entire series unless you disagree (we can keep the discussion in the patch
referenced above).
On Fri, Apr 17, 2020 at 07:34:27PM +0530, Rajendra Nayak wrote:
> On some qualcomm platforms DPU needs to express a perforamnce state
> requirement on a power domain depennding on the clock rates.
> Use OPP table from DT to register with OPP framework and use
> dev_pm_opp_set_rate() to set the clk/perf state.
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Cc: Rob Clark <robdclark@gmail.com>
> Cc: Sean Paul <sean@poorly.run>
> Cc: dri-devel@lists.freedesktop.org
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 3 ++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 20 +++++++++++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++++
> 3 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index 11f2beb..fe5717df 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -7,6 +7,7 @@
> #include <linux/debugfs.h>
> #include <linux/errno.h>
> #include <linux/mutex.h>
> +#include <linux/pm_opp.h>
> #include <linux/sort.h>
> #include <linux/clk.h>
> #include <linux/bitmap.h>
> @@ -239,7 +240,7 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
> rate = core_clk->max_rate;
>
> core_clk->rate = rate;
> - return msm_dss_clk_set_rate(core_clk, 1);
> + return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate);
> }
>
> static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index ce19f1d..cfce642 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -10,6 +10,7 @@
> #include <linux/debugfs.h>
> #include <linux/dma-buf.h>
> #include <linux/of_irq.h>
> +#include <linux/pm_opp.h>
>
> #include <drm/drm_crtc.h>
> #include <drm/drm_file.h>
> @@ -1033,11 +1034,18 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
> if (!dpu_kms)
> return -ENOMEM;
>
> + dpu_kms->opp = dev_pm_opp_set_clkname(dev, "core");
> + if (IS_ERR(dpu_kms->opp))
> + return PTR_ERR(dpu_kms->opp);
> + /* OPP table is optional */
> + if (!dev_pm_opp_of_add_table(dev))
> + dpu_kms->opp_table = true;
> +
> mp = &dpu_kms->mp;
> ret = msm_dss_parse_clock(pdev, mp);
> if (ret) {
> DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
> - return ret;
> + goto err;
> }
>
> platform_set_drvdata(pdev, dpu_kms);
> @@ -1051,6 +1059,11 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
>
> priv->kms = &dpu_kms->base;
> return ret;
> +err:
> + if (dpu_kms->opp_table)
> + dev_pm_opp_of_remove_table(dev);
> + dev_pm_opp_put_clkname(dpu_kms->opp);
> + return ret;
> }
>
> static void dpu_unbind(struct device *dev, struct device *master, void *data)
> @@ -1059,6 +1072,9 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data)
> struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
> struct dss_module_power *mp = &dpu_kms->mp;
>
> + if (dpu_kms->opp_table)
> + dev_pm_opp_of_remove_table(dev);
> + dev_pm_opp_put_clkname(dpu_kms->opp);
> msm_dss_put_clk(mp->clk_config, mp->num_clk);
> devm_kfree(&pdev->dev, mp->clk_config);
> mp->num_clk = 0;
> @@ -1090,6 +1106,8 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev)
> struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
> struct dss_module_power *mp = &dpu_kms->mp;
>
> + /* Drop the performance state vote */
> + dev_pm_opp_set_rate(dev, 0);
> rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
> if (rc)
> DPU_ERROR("clock disable failed rc:%d\n", rc);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index 211f5de9..0060709 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -128,6 +128,10 @@ struct dpu_kms {
>
> struct platform_device *pdev;
> bool rpm_enabled;
> +
> + struct opp_table *opp;
> + bool opp_table;
> +
> struct dss_module_power mp;
>
> /* reference count bandwidth requests, so we know when we can
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 05/17] drm/msm/dpu: Use OPP API to set clk/perf state
2020-04-17 18:17 ` Matthias Kaehlcke
@ 2020-04-18 8:12 ` Rajendra Nayak
0 siblings, 0 replies; 4+ messages in thread
From: Rajendra Nayak @ 2020-04-18 8:12 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: devicetree, sboyd, viresh.kumar, linux-kernel, dri-devel,
bjorn.andersson, agross, linux-arm-msm, Sean Paul
On 4/17/2020 11:47 PM, Matthias Kaehlcke wrote:
> Hi Rajendra,
>
> I have essentially the same comments as for "tty: serial: qcom_geni_serial:
> Use OPP API to set clk/perf state" (https://patchwork.kernel.org/patch/11495209/).
> about error handling of 'dev_pm_opp_of_add_table' and misleading struct
> member names 'opp'/'opp_table'. Please apply the requested changes to the
> entire series unless you disagree (we can keep the discussion in the patch
> referenced above).
Thanks, yes, I will apply those changes across the series and respin.
Will wait a few days to see I get any more feedback.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 4+ messages in thread
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[not found] <1587132279-27659-1-git-send-email-rnayak@codeaurora.org>
2020-04-17 14:04 ` [PATCH v2 05/17] drm/msm/dpu: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-17 18:17 ` Matthias Kaehlcke
2020-04-18 8:12 ` Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 06/17] drm/msm: dsi: " Rajendra Nayak
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