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* [PATCH] drm/edid: Fix off-by-one in DispID DTD pixel clock
@ 2020-04-23 15:17 Ville Syrjala
  2020-04-23 18:45 ` [Intel-gfx] " Manasi Navare
  2020-04-26 15:03 ` Sasha Levin
  0 siblings, 2 replies; 3+ messages in thread
From: Ville Syrjala @ 2020-04-23 15:17 UTC (permalink / raw)
  To: dri-devel; +Cc: intel-gfx, stable

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DispID DTD pixel clock is documented as:
"00 00 00 h → FF FF FF h | Pixel clock ÷ 10,000 0.01 → 167,772.16 Mega Pixels per Sec"
Which seems to imply that we to add one to the raw value.

Reality seems to agree as there are tiled displays in the wild
which currently show a 10kHz difference in the pixel clock
between the tiles (one tile gets its mode from the base EDID,
the other from the DispID block).

Cc: stable@vger.kernel.org
References: https://gitlab.freedesktop.org/drm/intel/-/issues/27
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_edid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 43b6ca364daa..544d2603f5fc 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5120,7 +5120,7 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d
 	struct drm_display_mode *mode;
 	unsigned pixel_clock = (timings->pixel_clock[0] |
 				(timings->pixel_clock[1] << 8) |
-				(timings->pixel_clock[2] << 16));
+				(timings->pixel_clock[2] << 16)) + 1;
 	unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
 	unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
 	unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
-- 
2.24.1

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^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/edid: Fix off-by-one in DispID DTD pixel clock
  2020-04-23 15:17 [PATCH] drm/edid: Fix off-by-one in DispID DTD pixel clock Ville Syrjala
@ 2020-04-23 18:45 ` Manasi Navare
  2020-04-26 15:03 ` Sasha Levin
  1 sibling, 0 replies; 3+ messages in thread
From: Manasi Navare @ 2020-04-23 18:45 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx, stable, dri-devel

On Thu, Apr 23, 2020 at 06:17:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The DispID DTD pixel clock is documented as:
> "00 00 00 h → FF FF FF h | Pixel clock ÷ 10,000 0.01 → 167,772.16 Mega Pixels per Sec"
> Which seems to imply that we to add one to the raw value.
> 
> Reality seems to agree as there are tiled displays in the wild
> which currently show a 10kHz difference in the pixel clock
> between the tiles (one tile gets its mode from the base EDID,
> the other from the DispID block).
> 
> Cc: stable@vger.kernel.org
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/27
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Makes total sense,

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/drm_edid.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 43b6ca364daa..544d2603f5fc 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5120,7 +5120,7 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d
>  	struct drm_display_mode *mode;
>  	unsigned pixel_clock = (timings->pixel_clock[0] |
>  				(timings->pixel_clock[1] << 8) |
> -				(timings->pixel_clock[2] << 16));
> +				(timings->pixel_clock[2] << 16)) + 1;
>  	unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
>  	unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
>  	unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] drm/edid: Fix off-by-one in DispID DTD pixel clock
  2020-04-23 15:17 [PATCH] drm/edid: Fix off-by-one in DispID DTD pixel clock Ville Syrjala
  2020-04-23 18:45 ` [Intel-gfx] " Manasi Navare
@ 2020-04-26 15:03 ` Sasha Levin
  1 sibling, 0 replies; 3+ messages in thread
From: Sasha Levin @ 2020-04-26 15:03 UTC (permalink / raw)
  To: Sasha Levin, Ville Syrjala, Ville Syrjälä, dri-devel
  Cc: intel-gfx, stable

Hi

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.6.7, v5.4.35, v4.19.118, v4.14.177, v4.9.220, v4.4.220.

v5.6.7: Build OK!
v5.4.35: Build OK!
v4.19.118: Build OK!
v4.14.177: Build OK!
v4.9.220: Build OK!
v4.4.220: Failed to apply! Possible dependencies:
    3a4a2ea39f86 ("drm/displayid: Iterate over all DisplayID blocks")
    5e546cd5b3bc ("drm/edid: move displayid tiled block parsing into separate function.")
    a39ed680bddb ("drm/edid: add displayid detailed 1 timings to the modelist. (v1.1)")
    c97291774c1b ("drm/edid: move displayid validation to it's own function.")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

-- 
Thanks
Sasha
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^ permalink raw reply	[flat|nested] 3+ messages in thread

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2020-04-23 15:17 [PATCH] drm/edid: Fix off-by-one in DispID DTD pixel clock Ville Syrjala
2020-04-23 18:45 ` [Intel-gfx] " Manasi Navare
2020-04-26 15:03 ` Sasha Levin

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