* [PATCH 1/8] drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250
2020-05-26 3:22 [PATCH 0/8] Initial SM8150 and SM8250 DPU bringup Jonathan Marek
@ 2020-05-26 3:22 ` Jonathan Marek
2020-05-26 3:22 ` [PATCH 2/8] drm/msm/dpu: update UBWC config " Jonathan Marek
` (6 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Jonathan Marek @ 2020-05-26 3:22 UTC (permalink / raw)
To: freedreno
Cc: Raviteja Tamatam, David Airlie,
open list:DRM DRIVER FOR MSM ADRENO GPU, open list,
open list:DRM DRIVER FOR MSM ADRENO GPU, Stephen Boyd,
Alexios Zavras, Kalyan Thota, Thomas Gleixner, Sean Paul,
Allison Randal
All DPU versions starting from 4.0 use the sdm845 version, so check for
that instead of checking each version individually. This chooses the right
function for sm8150 and sm8250.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 37becd43bd54..4b8baf71423f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -152,14 +152,13 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m,
unsigned long features)
{
ops->setup_mixer_out = dpu_hw_lm_setup_out;
- if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion)
- || IS_SC7180_TARGET(m->hwversion))
+ if (m->hwversion >= DPU_HW_VER_400)
ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845;
else
ops->setup_blend_config = dpu_hw_lm_setup_blend_config;
ops->setup_alpha_out = dpu_hw_lm_setup_color3;
ops->setup_border_color = dpu_hw_lm_setup_border_color;
-};
+}
static struct dpu_hw_blk_ops dpu_hw_ops;
--
2.26.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 2/8] drm/msm/dpu: update UBWC config for sm8150 and sm8250
2020-05-26 3:22 [PATCH 0/8] Initial SM8150 and SM8250 DPU bringup Jonathan Marek
2020-05-26 3:22 ` [PATCH 1/8] drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250 Jonathan Marek
@ 2020-05-26 3:22 ` Jonathan Marek
2020-05-26 3:22 ` [PATCH 3/8] drm/msm/dpu: move some sspp caps to dpu_caps Jonathan Marek
` (5 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Jonathan Marek @ 2020-05-26 3:22 UTC (permalink / raw)
To: freedreno
Cc: Shubhashree Dhar, David Airlie,
open list:DRM DRIVER FOR MSM ADRENO GPU, Sam Ravnborg,
Chandan Uddaraju, open list:DRM DRIVER FOR MSM ADRENO GPU,
Abhinav Kumar, Stephen Boyd, Jayant Shekhar, Alexios Zavras,
Kalyan Thota, Thomas Gleixner, Sean Paul, Allison Randal,
Raviteja Tamatam, Greg Kroah-Hartman, open list, Zheng Bin,
Drew Davenport, Georgi Djakov
Update the UBWC registers to the right values for sm8150 and sm8250.
This removes broken dpu_hw_reset_ubwc, which doesn't work because the
"force blk offset to zero to access beginning of register region" hack is
copied from downstream, where mapped region starts 0x1000 below what is
used in the upstream driver.
Also simplifies the overly complicated change that was introduced in
e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 --
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 16 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 18 -----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 7 --
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 75 ++++++-------------
6 files changed, 42 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1b960d9d1b33..3b48257886c6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1090,12 +1090,6 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
return;
}
- if (dpu_enc->cur_master->hw_mdptop &&
- dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
- dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
- dpu_enc->cur_master->hw_mdptop,
- dpu_kms->catalog);
-
_dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 09df7d87dd43..f45f031a3a05 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -37,7 +37,9 @@
#define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */
#define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */
#define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
-#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */
+#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */
+#define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */
+#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
@@ -65,10 +67,9 @@ enum {
DPU_HW_UBWC_VER_10 = 0x100,
DPU_HW_UBWC_VER_20 = 0x200,
DPU_HW_UBWC_VER_30 = 0x300,
+ DPU_HW_UBWC_VER_40 = 0x400,
};
-#define IS_UBWC_20_SUPPORTED(rev) ((rev) >= DPU_HW_UBWC_VER_20)
-
/**
* MDP TOP BLOCK features
* @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
@@ -426,7 +427,6 @@ struct dpu_clk_ctrl_reg {
struct dpu_mdp_cfg {
DPU_HW_BLK_INFO;
u32 highest_bank_bit;
- u32 ubwc_static;
u32 ubwc_swizzle;
struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 82c5dbfdabc7..c940b69435e1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -303,11 +303,25 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
DPU_FETCH_CONFIG_RESET_VALUE |
ctx->mdp->highest_bank_bit << 18);
- if (IS_UBWC_20_SUPPORTED(ctx->catalog->caps->ubwc_version)) {
+ switch (ctx->catalog->caps->ubwc_version) {
+ case DPU_HW_UBWC_VER_10:
+ /* TODO: UBWC v1 case */
+ break;
+ case DPU_HW_UBWC_VER_20:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
fast_clear | (ctx->mdp->ubwc_swizzle) |
(ctx->mdp->highest_bank_bit << 4));
+ break;
+ case DPU_HW_UBWC_VER_30:
+ DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ BIT(30) | (ctx->mdp->ubwc_swizzle) |
+ (ctx->mdp->highest_bank_bit << 4));
+ break;
+ case DPU_HW_UBWC_VER_40:
+ DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
+ break;
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index f9af52ae9f3e..01b76766a9a8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -8,7 +8,6 @@
#include "dpu_kms.h"
#define SSPP_SPARE 0x28
-#define UBWC_STATIC 0x144
#define FLD_SPLIT_DISPLAY_CMD BIT(1)
#define FLD_SMART_PANEL_FREE_RUN BIT(2)
@@ -249,22 +248,6 @@ static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp,
status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
}
-static void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m)
-{
- struct dpu_hw_blk_reg_map c;
-
- if (!mdp || !m)
- return;
-
- if (!IS_UBWC_20_SUPPORTED(m->caps->ubwc_version))
- return;
-
- /* force blk offset to zero to access beginning of register region */
- c = mdp->hw;
- c.blk_off = 0x0;
- DPU_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);
-}
-
static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp)
{
struct dpu_hw_blk_reg_map *c;
@@ -285,7 +268,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
ops->get_danger_status = dpu_hw_get_danger_status;
ops->setup_vsync_source = dpu_hw_setup_vsync_source;
ops->get_safe_status = dpu_hw_get_safe_status;
- ops->reset_ubwc = dpu_hw_reset_ubwc;
ops->intf_audio_select = dpu_hw_intf_audio_select;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
index 1d9d32edf619..8018fff5667a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
@@ -126,13 +126,6 @@ struct dpu_hw_mdp_ops {
void (*get_safe_status)(struct dpu_hw_mdp *mdp,
struct dpu_danger_safe_status *status);
- /**
- * reset_ubwc - reset top level UBWC configuration
- * @mdp: mdp top context driver
- * @m: pointer to mdss catalog data
- */
- void (*reset_ubwc)(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m);
-
/**
* intf_audio_select - select the external interface for audio
* @mdp: mdp top context driver
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 80d3cfc14007..fcfc3d6b71e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -15,6 +15,10 @@
#define HW_REV 0x0
#define HW_INTR_STATUS 0x0010
+#define UBWC_STATIC 0x144
+#define UBWC_CTRL_2 0x150
+#define UBWC_PREDICTION_MODE 0x154
+
/* Max BW defined in KBps */
#define MAX_BW 6800000
@@ -23,17 +27,6 @@ struct dpu_irq_controller {
struct irq_domain *domain;
};
-struct dpu_hw_cfg {
- u32 val;
- u32 offset;
-};
-
-struct dpu_mdss_hw_init_handler {
- u32 hw_rev;
- u32 hw_reg_count;
- struct dpu_hw_cfg* hw_cfg;
-};
-
struct dpu_mdss {
struct msm_mdss base;
void __iomem *mmio;
@@ -44,44 +37,6 @@ struct dpu_mdss {
u32 num_paths;
};
-static struct dpu_hw_cfg hw_cfg[] = {
- {
- /* UBWC global settings */
- .val = 0x1E,
- .offset = 0x144,
- }
-};
-
-static struct dpu_mdss_hw_init_handler cfg_handler[] = {
- { .hw_rev = DPU_HW_VER_620,
- .hw_reg_count = ARRAY_SIZE(hw_cfg),
- .hw_cfg = hw_cfg
- },
-};
-
-static void dpu_mdss_hw_init(struct dpu_mdss *dpu_mdss, u32 hw_rev)
-{
- int i;
- u32 count = 0;
- struct dpu_hw_cfg *hw_cfg = NULL;
-
- for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
- if (cfg_handler[i].hw_rev == hw_rev) {
- hw_cfg = cfg_handler[i].hw_cfg;
- count = cfg_handler[i].hw_reg_count;
- break;
- }
- }
-
- for (i = 0; i < count; i++ ) {
- writel_relaxed(hw_cfg->val,
- dpu_mdss->mmio + hw_cfg->offset);
- hw_cfg++;
- }
-
- return;
-}
-
static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
struct dpu_mdss *dpu_mdss)
{
@@ -224,7 +179,6 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = &dpu_mdss->mp;
int ret;
- u32 mdss_rev;
dpu_mdss_icc_request_bw(mdss);
@@ -234,8 +188,25 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
return ret;
}
- mdss_rev = readl_relaxed(dpu_mdss->mmio + HW_REV);
- dpu_mdss_hw_init(dpu_mdss, mdss_rev);
+ /*
+ * ubwc config is part of the "mdss" region which is not accessible
+ * from the rest of the driver. hardcode known configurations here
+ */
+ switch (readl_relaxed(dpu_mdss->mmio + HW_REV)) {
+ case DPU_HW_VER_500:
+ case DPU_HW_VER_501:
+ writel_relaxed(0x420, dpu_mdss->mmio + UBWC_STATIC);
+ break;
+ case DPU_HW_VER_600:
+ /* TODO: 0x102e for LP_DDR4 */
+ writel_relaxed(0x103e, dpu_mdss->mmio + UBWC_STATIC);
+ writel_relaxed(2, dpu_mdss->mmio + UBWC_CTRL_2);
+ writel_relaxed(1, dpu_mdss->mmio + UBWC_PREDICTION_MODE);
+ break;
+ case DPU_HW_VER_620:
+ writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC);
+ break;
+ }
return ret;
}
--
2.26.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 3/8] drm/msm/dpu: move some sspp caps to dpu_caps
2020-05-26 3:22 [PATCH 0/8] Initial SM8150 and SM8250 DPU bringup Jonathan Marek
2020-05-26 3:22 ` [PATCH 1/8] drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250 Jonathan Marek
2020-05-26 3:22 ` [PATCH 2/8] drm/msm/dpu: update UBWC config " Jonathan Marek
@ 2020-05-26 3:22 ` Jonathan Marek
2020-05-26 3:22 ` [PATCH 4/8] drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845 Jonathan Marek
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Jonathan Marek @ 2020-05-26 3:22 UTC (permalink / raw)
To: freedreno
Cc: Shubhashree Dhar, open list, Raviteja Tamatam, David Airlie,
Sam Ravnborg, open list:DRM DRIVER FOR MSM ADRENO GPU,
Greg Kroah-Hartman, open list:DRM DRIVER FOR MSM ADRENO GPU,
Stephen Boyd, zhengbin, Kalyan Thota, Thomas Gleixner, Sean Paul,
Allison Randal, Brian Masney
This isn't something that ever changes between planes, so move it to
dpu_caps struct. Making this change will allow more re-use in the
"SSPP sub blocks config" part of the catalog, in particular when adding
support for SM8150 and SM8250 which have different max_linewidth.
This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation
is not supported on the newest DPU versions. (note that decimation is not
implemented, so this changes nothing)
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++++------
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 24 +++++++------------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 ++---
3 files changed, 17 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c567917541e8..496407f1cd08 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -68,6 +68,10 @@ static const struct dpu_caps sdm845_dpu_caps = {
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
};
static const struct dpu_caps sc7180_dpu_caps = {
@@ -78,6 +82,8 @@ static const struct dpu_caps sc7180_dpu_caps = {
.ubwc_version = DPU_HW_UBWC_VER_20,
.has_dim_layer = true,
.has_idle_pc = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
static const struct dpu_mdp_cfg sdm845_mdp[] = {
@@ -176,16 +182,9 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
*************************************************************/
/* SSPP common configuration */
-static const struct dpu_sspp_blks_common sdm845_sspp_common = {
- .maxlinewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
- .maxhdeciexp = MAX_HORZ_DECIMATION,
- .maxvdeciexp = MAX_VERT_DECIMATION,
-};
#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
{ \
- .common = &sdm845_sspp_common, \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
.smart_dma_priority = sdma_pri, \
@@ -205,7 +204,6 @@ static const struct dpu_sspp_blks_common sdm845_sspp_common = {
#define _DMA_SBLK(num, sdma_pri) \
{ \
- .common = &sdm845_sspp_common, \
.maxdwnscale = SSPP_UNITY_SCALE, \
.maxupscale = SSPP_UNITY_SCALE, \
.smart_dma_priority = sdma_pri, \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f45f031a3a05..7a8d1c6658d2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -290,6 +290,10 @@ struct dpu_qos_lut_tbl {
* @has_dim_layer dim layer feature status
* @has_idle_pc indicate if idle power collapse feature is supported
* @has_3d_merge indicate if 3D merge is supported
+ * @max_linewidth max linewidth for sspp
+ * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes
+ * @max_hdeci_exp max horizontal decimation supported (max is 2^value)
+ * @max_vdeci_exp max vertical decimation supported (max is 2^value)
*/
struct dpu_caps {
u32 max_mixer_width;
@@ -301,22 +305,11 @@ struct dpu_caps {
bool has_dim_layer;
bool has_idle_pc;
bool has_3d_merge;
-};
-
-/**
- * struct dpu_sspp_blks_common : SSPP sub-blocks common configuration
- * @maxwidth: max pixelwidth supported by this pipe
- * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes
- * @maxhdeciexp: max horizontal decimation supported by this pipe
- * (max is 2^value)
- * @maxvdeciexp: max vertical decimation supported by this pipe
- * (max is 2^value)
- */
-struct dpu_sspp_blks_common {
- u32 maxlinewidth;
+ /* SSPP limits */
+ u32 max_linewidth;
u32 pixel_ram_size;
- u32 maxhdeciexp;
- u32 maxvdeciexp;
+ u32 max_hdeci_exp;
+ u32 max_vdeci_exp;
};
/**
@@ -342,7 +335,6 @@ struct dpu_sspp_blks_common {
* @virt_num_formats: Number of supported formats for virtual planes
*/
struct dpu_sspp_sub_blks {
- const struct dpu_sspp_blks_common *common;
u32 creq_vblank;
u32 danger_vblank;
u32 maxdwnscale;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 3b9c33e694bf..33f6c56f01ed 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -153,7 +153,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
pdpu = to_dpu_plane(plane);
pstate = to_dpu_plane_state(plane->state);
- fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size;
+ fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
if (!tmp->base.state->visible)
@@ -709,7 +709,7 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
* So we cannot support more than half of the supported SSPP
* width for tiled formats.
*/
- width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth;
+ width_threshold = dpu_plane[i]->catalog->caps->max_linewidth;
if (has_tiled_rect)
width_threshold /= 2;
@@ -887,7 +887,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
fb_rect.x2 = state->fb->width;
fb_rect.y2 = state->fb->height;
- max_linewidth = pdpu->pipe_sblk->common->maxlinewidth;
+ max_linewidth = pdpu->catalog->caps->max_linewidth;
fmt = to_dpu_format(msm_framebuffer_format(state->fb));
--
2.26.1
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 4/8] drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845
2020-05-26 3:22 [PATCH 0/8] Initial SM8150 and SM8250 DPU bringup Jonathan Marek
` (2 preceding siblings ...)
2020-05-26 3:22 ` [PATCH 3/8] drm/msm/dpu: move some sspp caps to dpu_caps Jonathan Marek
@ 2020-05-26 3:22 ` Jonathan Marek
2020-05-26 3:22 ` [PATCH 5/8] drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3 Jonathan Marek
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Jonathan Marek @ 2020-05-26 3:22 UTC (permalink / raw)
To: freedreno
Cc: Shubhashree Dhar, Raviteja Tamatam, David Airlie,
Greg Kroah-Hartman, open list:DRM DRIVER FOR MSM ADRENO GPU,
open list, open list:DRM DRIVER FOR MSM ADRENO GPU, Stephen Boyd,
Kalyan Thota, Thomas Gleixner, Sean Paul, Allison Randal
The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it.
This also adds separate feature bits for INTF (based on downstream) instead
of using CTL feature bit for it, and removes the unnecessary NULL check in
the added bind_pingpong_blk function.
Fixes: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath for SC7180 target")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 ++-------
3 files changed, 27 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 496407f1cd08..1e64fa08c219 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -41,6 +41,10 @@
#define PINGPONG_SDM845_SPLIT_MASK \
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
+#define INTF_SDM845_MASK (0)
+
+#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
+
#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
#define DEFAULT_DPU_LINE_WIDTH 2048
#define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
@@ -376,26 +380,26 @@ static struct dpu_pingpong_cfg sc7180_pp[] = {
/*************************************************************
* INTF sub blocks config
*************************************************************/
-#define INTF_BLK(_name, _id, _base, _type, _ctrl_id) \
+#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _features) \
{\
.name = _name, .id = _id, \
.base = _base, .len = 0x280, \
- .features = BIT(DPU_CTL_ACTIVE_CFG), \
+ .features = _features, \
.type = _type, \
.controller_id = _ctrl_id, \
.prog_fetch_lines_worst_case = 24 \
}
static const struct dpu_intf_cfg sdm845_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0),
- INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0),
- INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1),
- INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1),
+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SDM845_MASK),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SDM845_MASK),
+ INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SDM845_MASK),
+ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SDM845_MASK),
};
static const struct dpu_intf_cfg sc7180_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0),
- INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0),
+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK),
};
/*************************************************************
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 7a8d1c6658d2..31ddb2be9c57 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -175,6 +175,19 @@ enum {
DPU_CTL_MAX
};
+/**
+ * INTF sub-blocks
+ * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
+ * pixel data arrives to this INTF
+ * @DPU_INTF_TE INTF block has TE configuration support
+ * @DPU_INTF_MAX
+ */
+enum {
+ DPU_INTF_INPUT_CTRL = 0x1,
+ DPU_INTF_TE,
+ DPU_INTF_MAX
+};
+
/**
* VBIF sub-blocks and features
* @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index efe9a5719c6b..64f556d693dd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -225,14 +225,9 @@ static void dpu_hw_intf_bind_pingpong_blk(
bool enable,
const enum dpu_pingpong pp)
{
- struct dpu_hw_blk_reg_map *c;
+ struct dpu_hw_blk_reg_map *c = &intf->hw;
u32 mux_cfg;
- if (!intf)
- return;
-
- c = &intf->hw;
-
mux_cfg = DPU_REG_READ(c, INTF_MUX);
mux_cfg &= ~0xf;
@@ -280,7 +275,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
ops->get_status = dpu_hw_intf_get_status;
ops->enable_timing = dpu_hw_intf_enable_timing_engine;
ops->get_line_count = dpu_hw_intf_get_line_count;
- if (cap & BIT(DPU_CTL_ACTIVE_CFG))
+ if (cap & BIT(DPU_INTF_INPUT_CTRL))
ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
}
--
2.26.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 5/8] drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3
2020-05-26 3:22 [PATCH 0/8] Initial SM8150 and SM8250 DPU bringup Jonathan Marek
` (3 preceding siblings ...)
2020-05-26 3:22 ` [PATCH 4/8] drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845 Jonathan Marek
@ 2020-05-26 3:22 ` Jonathan Marek
2020-05-26 3:22 ` [PATCH 6/8] drm/msm/dpu: intf timing path for displayport Jonathan Marek
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Jonathan Marek @ 2020-05-26 3:22 UTC (permalink / raw)
To: freedreno
Cc: David Airlie, open list:DRM DRIVER FOR MSM ADRENO GPU, open list,
open list:DRM DRIVER FOR MSM ADRENO GPU, Stephen Boyd,
Alexios Zavras, Kalyan Thota, Thomas Gleixner, Sean Paul,
Allison Randal
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 20 ++------------------
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 831e5f7a9b7f..996666afdd66 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -245,30 +245,14 @@ static int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx,
static int dpu_hw_ctl_get_bitmask_intf_v1(struct dpu_hw_ctl *ctx,
u32 *flushbits, enum dpu_intf intf)
{
- switch (intf) {
- case INTF_0:
- case INTF_1:
- *flushbits |= BIT(31);
- break;
- default:
- return 0;
- }
+ *flushbits |= BIT(31);
return 0;
}
static int dpu_hw_ctl_active_get_bitmask_intf(struct dpu_hw_ctl *ctx,
u32 *flushbits, enum dpu_intf intf)
{
- switch (intf) {
- case INTF_0:
- *flushbits |= BIT(0);
- break;
- case INTF_1:
- *flushbits |= BIT(1);
- break;
- default:
- return 0;
- }
+ *flushbits |= BIT(intf - INTF_0);
return 0;
}
--
2.26.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6/8] drm/msm/dpu: intf timing path for displayport
2020-05-26 3:22 [PATCH 0/8] Initial SM8150 and SM8250 DPU bringup Jonathan Marek
` (4 preceding siblings ...)
2020-05-26 3:22 ` [PATCH 5/8] drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3 Jonathan Marek
@ 2020-05-26 3:22 ` Jonathan Marek
2020-05-26 3:22 ` [PATCH 7/8] drm/msm/dpu: add SM8150 to hw catalog Jonathan Marek
2020-05-26 3:22 ` [PATCH 8/8] drm/msm/dpu: add SM8250 " Jonathan Marek
7 siblings, 0 replies; 11+ messages in thread
From: Jonathan Marek @ 2020-05-26 3:22 UTC (permalink / raw)
To: freedreno
Cc: Shubhashree Dhar, Raviteja Tamatam, David Airlie,
open list:DRM DRIVER FOR MSM ADRENO GPU, open list,
open list:DRM DRIVER FOR MSM ADRENO GPU, Stephen Boyd,
Alexios Zavras, Kalyan Thota, Thomas Gleixner, Sean Paul
Calculate the correct timings for displayport, from downstream driver.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 64f556d693dd..6f0f54588124 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -107,11 +107,6 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
p->hsync_skew - 1;
- if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
- display_v_start += p->hsync_pulse_width + p->h_back_porch;
- display_v_end -= p->h_front_porch;
- }
-
hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
hsync_end_x = hsync_period - p->h_front_porch - 1;
@@ -144,10 +139,25 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
+ if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
+ active_h_start = hsync_start_x;
+ active_h_end = active_h_start + p->xres - 1;
+ active_v_start = display_v_start;
+ active_v_end = active_v_start + (p->yres * hsync_period) - 1;
+
+ display_v_start += p->hsync_pulse_width + p->h_back_porch;
+
+ active_hctl = (active_h_end << 16) | active_h_start;
+ display_hctl = active_hctl;
+ }
+
den_polarity = 0;
if (ctx->cap->type == INTF_HDMI) {
hsync_polarity = p->yres >= 720 ? 0 : 1;
vsync_polarity = p->yres >= 720 ? 0 : 1;
+ } else if (ctx->cap->type == INTF_DP) {
+ hsync_polarity = p->hsync_polarity;
+ vsync_polarity = p->vsync_polarity;
} else {
hsync_polarity = 0;
vsync_polarity = 0;
--
2.26.1
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 7/8] drm/msm/dpu: add SM8150 to hw catalog
2020-05-26 3:22 [PATCH 0/8] Initial SM8150 and SM8250 DPU bringup Jonathan Marek
` (5 preceding siblings ...)
2020-05-26 3:22 ` [PATCH 6/8] drm/msm/dpu: intf timing path for displayport Jonathan Marek
@ 2020-05-26 3:22 ` Jonathan Marek
2020-06-11 14:37 ` Dmitry Baryshkov
2020-05-26 3:22 ` [PATCH 8/8] drm/msm/dpu: add SM8250 " Jonathan Marek
7 siblings, 1 reply; 11+ messages in thread
From: Jonathan Marek @ 2020-05-26 3:22 UTC (permalink / raw)
To: freedreno
Cc: Shubhashree Dhar, Raviteja Tamatam, David Airlie,
Greg Kroah-Hartman, open list:DRM DRIVER FOR MSM ADRENO GPU,
open list, open list:DRM DRIVER FOR MSM ADRENO GPU, Stephen Boyd,
Alexios Zavras, Kalyan Thota, Thomas Gleixner, Sean Paul,
Allison Randal
This brings up basic video mode functionality for SM8150 DPU. Command mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is also untested.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 147 ++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
2 files changed, 149 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1e64fa08c219..f99622870676 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -90,6 +90,23 @@ static const struct dpu_caps sc7180_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8150_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .max_linewidth = 4096,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2_5,
+ .ubwc_version = DPU_HW_UBWC_VER_30,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
static const struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -181,6 +198,39 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8150_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG)
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG)
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG)
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG)
+ },
+};
+
/*************************************************************
* SSPP sub blocks config
*************************************************************/
@@ -335,6 +385,23 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
&sc7180_lm_sblk, PINGPONG_1, LM_0),
};
+/* SM8150 */
+
+static const struct dpu_lm_cfg sm8150_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ &sdm845_lm_sblk, PINGPONG_0, LM_1),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ &sdm845_lm_sblk, PINGPONG_1, LM_0),
+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
+ &sdm845_lm_sblk, PINGPONG_2, LM_3),
+ LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
+ &sdm845_lm_sblk, PINGPONG_3, LM_2),
+ LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
+ &sdm845_lm_sblk, PINGPONG_4, LM_5),
+ LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
+ &sdm845_lm_sblk, PINGPONG_5, LM_4),
+};
+
/*************************************************************
* PINGPONG sub blocks config
*************************************************************/
@@ -377,6 +444,15 @@ static struct dpu_pingpong_cfg sc7180_pp[] = {
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
};
+static const struct dpu_pingpong_cfg sm8150_pp[] = {
+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000),
+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x71000),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x71800),
+ PP_BLK("pingpong_4", PINGPONG_4, 0x72000),
+ PP_BLK("pingpong_5", PINGPONG_5, 0x72800),
+};
+
/*************************************************************
* INTF sub blocks config
*************************************************************/
@@ -402,6 +478,13 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK),
};
+static const struct dpu_intf_cfg sm8150_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK),
+ INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SC7180_MASK),
+ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SC7180_MASK),
+};
+
/*************************************************************
* VBIF sub blocks config
*************************************************************/
@@ -432,6 +515,10 @@ static const struct dpu_reg_dma_cfg sdm845_regdma = {
.base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
};
+static const struct dpu_reg_dma_cfg sm8150_regdma = {
+ .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
+};
+
/*************************************************************
* PERF data config
*************************************************************/
@@ -456,6 +543,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222335777},
};
+static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
+ {.fl = 0, .lut = 0x0011222222223357 },
+};
+
static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
{.fl = 10, .lut = 0x344556677},
{.fl = 11, .lut = 0x3344556677},
@@ -540,6 +631,31 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
},
};
+static const struct dpu_perf_cfg sm8150_perf_data = {
+ .max_bw_low = 12800000,
+ .max_bw_high = 12800000,
+ .min_core_ib = 2400000,
+ .min_llcc_ib = 800000,
+ .min_dram_ib = 800000,
+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm8150_qos_linear),
+ .entries = sm8150_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+};
+
/*************************************************************
* Hardware catalog init
*************************************************************/
@@ -602,9 +718,40 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
};
}
+/*
+ * sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets
+ * and instance counts.
+ */
+static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
+{
+ *dpu_cfg = (struct dpu_mdss_cfg){
+ .caps = &sm8150_dpu_caps,
+ .mdp_count = ARRAY_SIZE(sdm845_mdp),
+ .mdp = sdm845_mdp,
+ .ctl_count = ARRAY_SIZE(sm8150_ctl),
+ .ctl = sm8150_ctl,
+ .sspp_count = ARRAY_SIZE(sdm845_sspp),
+ .sspp = sdm845_sspp,
+ .mixer_count = ARRAY_SIZE(sm8150_lm),
+ .mixer = sm8150_lm,
+ .pingpong_count = ARRAY_SIZE(sm8150_pp),
+ .pingpong = sm8150_pp,
+ .intf_count = ARRAY_SIZE(sm8150_intf),
+ .intf = sm8150_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = sm8150_regdma,
+ .perf = sm8150_perf_data,
+ .mdss_irqs = 0x3ff,
+ };
+}
+
static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
{ .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
+ { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init},
+ { .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
{ .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 686882132bf6..d5a7db81ae24 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -170,6 +170,7 @@ enum dpu_ctl {
CTL_2,
CTL_3,
CTL_4,
+ CTL_5,
CTL_MAX
};
@@ -179,6 +180,7 @@ enum dpu_pingpong {
PINGPONG_2,
PINGPONG_3,
PINGPONG_4,
+ PINGPONG_5,
PINGPONG_S0,
PINGPONG_MAX
};
--
2.26.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 7/8] drm/msm/dpu: add SM8150 to hw catalog
2020-05-26 3:22 ` [PATCH 7/8] drm/msm/dpu: add SM8150 to hw catalog Jonathan Marek
@ 2020-06-11 14:37 ` Dmitry Baryshkov
2020-06-11 14:45 ` Jonathan Marek
0 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2020-06-11 14:37 UTC (permalink / raw)
To: Jonathan Marek, freedreno
Cc: Shubhashree Dhar, Raviteja Tamatam, David Airlie,
Greg Kroah-Hartman, open list:DRM DRIVER FOR MSM ADRENO GPU,
open list, open list:DRM DRIVER FOR MSM ADRENO GPU, Stephen Boyd,
Alexios Zavras, Kalyan Thota, Thomas Gleixner, Sean Paul,
Allison Randal
On 26/05/2020 06:22, Jonathan Marek wrote:
> This brings up basic video mode functionality for SM8150 DPU. Command mode
> and dual mixer/intf configurations are not working, future patches will
> address this. Scaler functionality and multiple planes is also untested.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 147 ++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
> 2 files changed, 149 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 1e64fa08c219..f99622870676 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -90,6 +90,23 @@ static const struct dpu_caps sc7180_dpu_caps = {
> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> };
>
> +static const struct dpu_caps sm8150_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0xb,
> + .max_linewidth = 4096,
> + .qseed_type = DPU_SSPP_SCALER_QSEED3,
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2_5,
It seems you missed sending a patch adding support for
DPU_SSPP_SMART_DMA_V2_5. Could you please point to it?
--
With best wishes
Dmitry
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 7/8] drm/msm/dpu: add SM8150 to hw catalog
2020-06-11 14:37 ` Dmitry Baryshkov
@ 2020-06-11 14:45 ` Jonathan Marek
0 siblings, 0 replies; 11+ messages in thread
From: Jonathan Marek @ 2020-06-11 14:45 UTC (permalink / raw)
To: Dmitry Baryshkov, freedreno
Cc: Shubhashree Dhar, Raviteja Tamatam, David Airlie,
Greg Kroah-Hartman, open list:DRM DRIVER FOR MSM ADRENO GPU,
open list, open list:DRM DRIVER FOR MSM ADRENO GPU, Stephen Boyd,
Alexios Zavras, Kalyan Thota, Thomas Gleixner, Sean Paul,
Allison Randal
On 6/11/20 10:37 AM, Dmitry Baryshkov wrote:
> On 26/05/2020 06:22, Jonathan Marek wrote:
>> This brings up basic video mode functionality for SM8150 DPU. Command
>> mode
>> and dual mixer/intf configurations are not working, future patches will
>> address this. Scaler functionality and multiple planes is also untested.
>>
>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 147 ++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
>> 2 files changed, 149 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 1e64fa08c219..f99622870676 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -90,6 +90,23 @@ static const struct dpu_caps sc7180_dpu_caps = {
>> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> };
>> +static const struct dpu_caps sm8150_dpu_caps = {
>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> + .max_mixer_blendstages = 0xb,
>> + .max_linewidth = 4096,
>> + .qseed_type = DPU_SSPP_SCALER_QSEED3,
>> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2_5,
>
> It seems you missed sending a patch adding support for
> DPU_SSPP_SMART_DMA_V2_5. Could you please point to it?
>
>
There are no other changes related to that, the driver never checks
smart_dma_rev and the correct version number is only set for when the
driver supports it (if ever).
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 8/8] drm/msm/dpu: add SM8250 to hw catalog
2020-05-26 3:22 [PATCH 0/8] Initial SM8150 and SM8250 DPU bringup Jonathan Marek
` (6 preceding siblings ...)
2020-05-26 3:22 ` [PATCH 7/8] drm/msm/dpu: add SM8150 to hw catalog Jonathan Marek
@ 2020-05-26 3:22 ` Jonathan Marek
7 siblings, 0 replies; 11+ messages in thread
From: Jonathan Marek @ 2020-05-26 3:22 UTC (permalink / raw)
To: freedreno
Cc: Shubhashree Dhar, Raviteja Tamatam, David Airlie, Sam Ravnborg,
open list:DRM DRIVER FOR MSM ADRENO GPU, open list,
open list:DRM DRIVER FOR MSM ADRENO GPU, Stephen Boyd,
Kalyan Thota, Thomas Gleixner, Sean Paul
This brings up basic video mode functionality for SM8250 DPU. Command mode
and dual mixer/intf configurations are not working, future patches will
address this. Scaler functionality and multiple planes is also untested.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 106 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +
2 files changed, 109 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index f99622870676..711ec1e6a543 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -107,6 +107,21 @@ static const struct dpu_caps sm8150_dpu_caps = {
.max_vdeci_exp = MAX_VERT_DECIMATION,
};
+static const struct dpu_caps sm8250_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .max_linewidth = 4096,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3, /* TODO: qseed3 lite */
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2_5,
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -149,6 +164,33 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8250_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x45C,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2B4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2BC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2C4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2B4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2BC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2C4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2BC, .bit_off = 20},
+ },
+};
+
/*************************************************************
* CTL sub blocks config
*************************************************************/
@@ -519,6 +561,14 @@ static const struct dpu_reg_dma_cfg sm8150_regdma = {
.base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
};
+static const struct dpu_reg_dma_cfg sm8250_regdma = {
+ .base = 0x0,
+ .version = 0x00010002,
+ .trigger_sel_off = 0x119c,
+ .xin_id = 7,
+ .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
+};
+
/*************************************************************
* PERF data config
*************************************************************/
@@ -656,6 +706,31 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
},
};
+static const struct dpu_perf_cfg sm8250_perf_data = {
+ .max_bw_low = 13700000,
+ .max_bw_high = 16600000,
+ .min_core_ib = 4800000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 800000,
+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+};
+
/*************************************************************
* Hardware catalog init
*************************************************************/
@@ -747,11 +822,42 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
};
}
+/*
+ * sm8250_cfg_init(): populate sm8250 dpu sub-blocks reg offsets
+ * and instance counts.
+ */
+static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
+{
+ *dpu_cfg = (struct dpu_mdss_cfg){
+ .caps = &sm8250_dpu_caps,
+ .mdp_count = ARRAY_SIZE(sm8250_mdp),
+ .mdp = sm8250_mdp,
+ .ctl_count = ARRAY_SIZE(sm8150_ctl),
+ .ctl = sm8150_ctl,
+ /* TODO: sspp qseed version differs from 845 */
+ .sspp_count = ARRAY_SIZE(sdm845_sspp),
+ .sspp = sdm845_sspp,
+ .mixer_count = ARRAY_SIZE(sm8150_lm),
+ .mixer = sm8150_lm,
+ .pingpong_count = ARRAY_SIZE(sm8150_pp),
+ .pingpong = sm8150_pp,
+ .intf_count = ARRAY_SIZE(sm8150_intf),
+ .intf = sm8150_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = sm8250_regdma,
+ .perf = sm8250_perf_data,
+ .mdss_irqs = 0xff,
+ };
+}
+
static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
{ .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
{ .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init},
{ .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
+ { .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init},
{ .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 31ddb2be9c57..cdd200194c4f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -408,6 +408,7 @@ enum dpu_clk_ctrl_type {
DPU_CLK_CTRL_CURSOR0,
DPU_CLK_CTRL_CURSOR1,
DPU_CLK_CTRL_INLINE_ROT0_SSPP,
+ DPU_CLK_CTRL_REG_DMA,
DPU_CLK_CTRL_MAX,
};
@@ -577,6 +578,8 @@ struct dpu_reg_dma_cfg {
DPU_HW_BLK_INFO;
u32 version;
u32 trigger_sel_off;
+ u32 xin_id;
+ enum dpu_clk_ctrl_type clk_ctrl;
};
/**
--
2.26.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread