* [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions
@ 2020-09-18 11:40 Jani Nikula
2020-09-18 11:40 ` [PATCH 2/2] drm/dp: add a number of DP 2.0 DPCD definitions Jani Nikula
2020-09-18 19:29 ` [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions Navare, Manasi
0 siblings, 2 replies; 6+ messages in thread
From: Jani Nikula @ 2020-09-18 11:40 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula
Add the subheadings from the DP spec. No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c9f2851904d0..388083b4716b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -106,8 +106,9 @@ struct drm_device;
#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
-/* AUX CH addresses */
-/* DPCD */
+/* DPCD Field Address Mapping */
+
+/* Receiver Capability */
#define DP_DPCD_REV 0x000
# define DP_DPCD_REV_10 0x10
# define DP_DPCD_REV_11 0x11
@@ -426,7 +427,7 @@ struct drm_device;
#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
-/* link configuration */
+/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
# define DP_LINK_BW_1_62 0x06
@@ -580,6 +581,7 @@ struct drm_device;
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
+/* Link/Sink Device Status */
#define DP_SINK_COUNT 0x200
/* prior to 1.2 bit 7 was reserved mbz */
# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
@@ -779,20 +781,27 @@ struct drm_device;
#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
/* up to ID_SLOT_63 at 0x2ff */
+/* Source Device-specific */
#define DP_SOURCE_OUI 0x300
+
+/* Sink Device-specific */
#define DP_SINK_OUI 0x400
+
+/* Branch Device-specific */
#define DP_BRANCH_OUI 0x500
#define DP_BRANCH_ID 0x503
#define DP_BRANCH_REVISION_START 0x509
#define DP_BRANCH_HW_REV 0x509
#define DP_BRANCH_SW_REV 0x50A
+/* Link/Sink Device Power Control */
#define DP_SET_POWER 0x600
# define DP_SET_POWER_D0 0x1
# define DP_SET_POWER_D3 0x2
# define DP_SET_POWER_MASK 0x3
# define DP_SET_POWER_D3_AUX_ON 0x5
+/* eDP-specific */
#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
# define DP_EDP_11 0x00
# define DP_EDP_12 0x01
@@ -876,11 +885,13 @@ struct drm_device;
#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
+/* Sideband MSG Buffers */
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
+/* DPRX Event Status Indicator */
#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
/* 0-5 sink count */
# define DP_SINK_COUNT_CP_READY (1 << 6)
@@ -934,6 +945,7 @@ struct drm_device;
#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
+/* Extended Receiver Capability */
#define DP_DP13_DPCD_REV 0x2200
#define DP_DP13_MAX_LINK_RATE 0x2201
@@ -947,6 +959,7 @@ struct drm_device;
# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
+/* Protocol Converter Extension */
/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
#define DP_CEC_TUNNELING_CAPABILITY 0x3000
# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
@@ -1013,6 +1026,7 @@ struct drm_device;
#define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
+/* HDCP 1.3 and HDCP 2.2 */
#define DP_AUX_HDCP_BKSV 0x68000
#define DP_AUX_HDCP_RI_PRIME 0x68005
#define DP_AUX_HDCP_AKSV 0x68007
@@ -1058,7 +1072,7 @@ struct drm_device;
#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
-/* Link Training (LT)-tunable PHY Repeaters */
+/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
--
2.20.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/dp: add a number of DP 2.0 DPCD definitions
2020-09-18 11:40 [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions Jani Nikula
@ 2020-09-18 11:40 ` Jani Nikula
2020-09-18 19:53 ` Navare, Manasi
2020-09-18 19:29 ` [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions Navare, Manasi
1 sibling, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2020-09-18 11:40 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula
Prepare for future with DP 2.0 DPCD definitions, with a couple of
related drive-by cleanups. No functional changes.
v2: Send the version that actually builds.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 52 ++++++++++++++++++++++++++++++++-----
1 file changed, 45 insertions(+), 7 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 388083b4716b..e144b4b9d79a 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -125,6 +125,7 @@ struct drm_device;
#define DP_MAX_DOWNSPREAD 0x003
# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
+# define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */
# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
# define DP_TPS4_SUPPORTED (1 << 7)
@@ -142,6 +143,7 @@ struct drm_device;
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
# define DP_CAP_ANSI_8B10B (1 << 0)
+# define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */
#define DP_DOWN_STREAM_PORT_COUNT 0x007
# define DP_PORT_COUNT_MASK 0x0f
@@ -185,8 +187,14 @@ struct drm_device;
#define DP_FAUX_CAP 0x020 /* 1.2 */
# define DP_FAUX_CAP_1 (1 << 0)
+#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */
+# define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
+# define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)
+# define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)
+
#define DP_MSTM_CAP 0x021 /* 1.2 */
# define DP_MST_CAP (1 << 0)
+# define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */
#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
@@ -434,6 +442,9 @@ struct drm_device;
# define DP_LINK_BW_2_7 0x0a
# define DP_LINK_BW_5_4 0x14 /* 1.2 */
# define DP_LINK_BW_8_1 0x1e /* 1.4 */
+# define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */
+# define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */
+# define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */
#define DP_LANE_COUNT_SET 0x101
# define DP_LANE_COUNT_MASK 0x0f
@@ -485,12 +496,15 @@ struct drm_device;
# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
+# define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */
+
#define DP_DOWNSPREAD_CTRL 0x107
# define DP_SPREAD_AMP_0_5 (1 << 4)
# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
# define DP_SET_ANSI_8B10B (1 << 0)
+# define DP_SET_ANSI_128B132B (1 << 1)
#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
/* bitmask as for DP_I2C_SPEED_CAP */
@@ -509,8 +523,19 @@ struct drm_device;
# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
# define DP_LINK_QUAL_PATTERN_PRBS7 3
# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
-# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
-# define DP_LINK_QUAL_PATTERN_MASK 7
+# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5
+# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6
+# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7
+/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */
+# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
+# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
+# define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
+# define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
+# define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
+# define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
+# define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
+# define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
+# define DP_LINK_QUAL_PATTERN_SQUARE 0x48
#define DP_TRAINING_LANE0_1_SET2 0x10f
#define DP_TRAINING_LANE2_3_SET2 0x110
@@ -613,9 +638,9 @@ struct drm_device;
#define DP_LINK_STATUS_UPDATED (1 << 7)
#define DP_SINK_STATUS 0x205
-
-#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
-#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
+# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
+# define DP_RECEIVE_PORT_1_STATUS (1 << 1)
+# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
#define DP_ADJUST_REQUEST_LANE0_1 0x206
#define DP_ADJUST_REQUEST_LANE2_3 0x207
@@ -628,6 +653,12 @@ struct drm_device;
# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
+/* DP 2.0 128b/132b Link Layer */
+# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
+# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
+# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
+# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
+
#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
# define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
@@ -945,9 +976,8 @@ struct drm_device;
#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
-/* Extended Receiver Capability */
+/* Extended Receiver Capability: See DP_DPCD_REV for definitions */
#define DP_DP13_DPCD_REV 0x2200
-#define DP_DP13_MAX_LINK_RATE 0x2201
#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
# define DP_GTC_CAP (1 << 0) /* DP 1.3 */
@@ -959,6 +989,14 @@ struct drm_device;
# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
+#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */
+# define DP_UHBR10 (1 << 0)
+# define DP_UHBR20 (1 << 1)
+# define DP_UHBR13_5 (1 << 2)
+
+#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
+# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
+
/* Protocol Converter Extension */
/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
#define DP_CEC_TUNNELING_CAPABILITY 0x3000
--
2.20.1
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions
2020-09-18 11:40 [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions Jani Nikula
2020-09-18 11:40 ` [PATCH 2/2] drm/dp: add a number of DP 2.0 DPCD definitions Jani Nikula
@ 2020-09-18 19:29 ` Navare, Manasi
2020-09-24 8:33 ` Jani Nikula
1 sibling, 1 reply; 6+ messages in thread
From: Navare, Manasi @ 2020-09-18 19:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: dri-devel
On Fri, Sep 18, 2020 at 02:40:16PM +0300, Jani Nikula wrote:
> Add the subheadings from the DP spec. No functional changes.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Looks good to me
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> include/drm/drm_dp_helper.h | 22 ++++++++++++++++++----
> 1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c9f2851904d0..388083b4716b 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -106,8 +106,9 @@ struct drm_device;
> #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
> #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
>
> -/* AUX CH addresses */
> -/* DPCD */
> +/* DPCD Field Address Mapping */
> +
> +/* Receiver Capability */
> #define DP_DPCD_REV 0x000
> # define DP_DPCD_REV_10 0x10
> # define DP_DPCD_REV_11 0x11
> @@ -426,7 +427,7 @@ struct drm_device;
> #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
> #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
>
> -/* link configuration */
> +/* Link Configuration */
> #define DP_LINK_BW_SET 0x100
> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> # define DP_LINK_BW_1_62 0x06
> @@ -580,6 +581,7 @@ struct drm_device;
> #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
> #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
>
> +/* Link/Sink Device Status */
> #define DP_SINK_COUNT 0x200
> /* prior to 1.2 bit 7 was reserved mbz */
> # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
> @@ -779,20 +781,27 @@ struct drm_device;
> #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
> /* up to ID_SLOT_63 at 0x2ff */
>
> +/* Source Device-specific */
> #define DP_SOURCE_OUI 0x300
> +
> +/* Sink Device-specific */
> #define DP_SINK_OUI 0x400
> +
> +/* Branch Device-specific */
> #define DP_BRANCH_OUI 0x500
> #define DP_BRANCH_ID 0x503
> #define DP_BRANCH_REVISION_START 0x509
> #define DP_BRANCH_HW_REV 0x509
> #define DP_BRANCH_SW_REV 0x50A
>
> +/* Link/Sink Device Power Control */
> #define DP_SET_POWER 0x600
> # define DP_SET_POWER_D0 0x1
> # define DP_SET_POWER_D3 0x2
> # define DP_SET_POWER_MASK 0x3
> # define DP_SET_POWER_D3_AUX_ON 0x5
>
> +/* eDP-specific */
> #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
> # define DP_EDP_11 0x00
> # define DP_EDP_12 0x01
> @@ -876,11 +885,13 @@ struct drm_device;
> #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
> #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
>
> +/* Sideband MSG Buffers */
> #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
> #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
>
> +/* DPRX Event Status Indicator */
> #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
> /* 0-5 sink count */
> # define DP_SINK_COUNT_CP_READY (1 << 6)
> @@ -934,6 +945,7 @@ struct drm_device;
> #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
> #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
>
> +/* Extended Receiver Capability */
> #define DP_DP13_DPCD_REV 0x2200
> #define DP_DP13_MAX_LINK_RATE 0x2201
>
> @@ -947,6 +959,7 @@ struct drm_device;
> # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
> # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
>
> +/* Protocol Converter Extension */
> /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
> #define DP_CEC_TUNNELING_CAPABILITY 0x3000
> # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
> @@ -1013,6 +1026,7 @@ struct drm_device;
> #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
> # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
>
> +/* HDCP 1.3 and HDCP 2.2 */
> #define DP_AUX_HDCP_BKSV 0x68000
> #define DP_AUX_HDCP_RI_PRIME 0x68005
> #define DP_AUX_HDCP_AKSV 0x68007
> @@ -1058,7 +1072,7 @@ struct drm_device;
> #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
> #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
>
> -/* Link Training (LT)-tunable PHY Repeaters */
> +/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
> #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
> #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
> #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
> --
> 2.20.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/dp: add a number of DP 2.0 DPCD definitions
2020-09-18 11:40 ` [PATCH 2/2] drm/dp: add a number of DP 2.0 DPCD definitions Jani Nikula
@ 2020-09-18 19:53 ` Navare, Manasi
0 siblings, 0 replies; 6+ messages in thread
From: Navare, Manasi @ 2020-09-18 19:53 UTC (permalink / raw)
To: Jani Nikula; +Cc: dri-devel
On Fri, Sep 18, 2020 at 02:40:17PM +0300, Jani Nikula wrote:
> Prepare for future with DP 2.0 DPCD definitions, with a couple of
> related drive-by cleanups. No functional changes.
>
> v2: Send the version that actually builds.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Verified the below DP 2.0 DPCD registers from the DP 2.0 spec
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> include/drm/drm_dp_helper.h | 52 ++++++++++++++++++++++++++++++++-----
> 1 file changed, 45 insertions(+), 7 deletions(-)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 388083b4716b..e144b4b9d79a 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -125,6 +125,7 @@ struct drm_device;
>
> #define DP_MAX_DOWNSPREAD 0x003
> # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
> +# define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */
> # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
> # define DP_TPS4_SUPPORTED (1 << 7)
>
> @@ -142,6 +143,7 @@ struct drm_device;
>
> #define DP_MAIN_LINK_CHANNEL_CODING 0x006
> # define DP_CAP_ANSI_8B10B (1 << 0)
> +# define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */
>
> #define DP_DOWN_STREAM_PORT_COUNT 0x007
> # define DP_PORT_COUNT_MASK 0x0f
> @@ -185,8 +187,14 @@ struct drm_device;
> #define DP_FAUX_CAP 0x020 /* 1.2 */
> # define DP_FAUX_CAP_1 (1 << 0)
>
> +#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */
> +# define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
> +# define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)
> +# define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)
> +
> #define DP_MSTM_CAP 0x021 /* 1.2 */
> # define DP_MST_CAP (1 << 0)
> +# define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */
>
> #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
>
> @@ -434,6 +442,9 @@ struct drm_device;
> # define DP_LINK_BW_2_7 0x0a
> # define DP_LINK_BW_5_4 0x14 /* 1.2 */
> # define DP_LINK_BW_8_1 0x1e /* 1.4 */
> +# define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */
> +# define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */
> +# define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */
>
> #define DP_LANE_COUNT_SET 0x101
> # define DP_LANE_COUNT_MASK 0x0f
> @@ -485,12 +496,15 @@ struct drm_device;
> # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
> # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
>
> +# define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */
> +
> #define DP_DOWNSPREAD_CTRL 0x107
> # define DP_SPREAD_AMP_0_5 (1 << 4)
> # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
>
> #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
> # define DP_SET_ANSI_8B10B (1 << 0)
> +# define DP_SET_ANSI_128B132B (1 << 1)
>
> #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
> /* bitmask as for DP_I2C_SPEED_CAP */
> @@ -509,8 +523,19 @@ struct drm_device;
> # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
> # define DP_LINK_QUAL_PATTERN_PRBS7 3
> # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
> -# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
> -# define DP_LINK_QUAL_PATTERN_MASK 7
> +# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5
> +# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6
> +# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7
> +/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */
> +# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
> +# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
> +# define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
> +# define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
> +# define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
> +# define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
> +# define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
> +# define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
> +# define DP_LINK_QUAL_PATTERN_SQUARE 0x48
>
> #define DP_TRAINING_LANE0_1_SET2 0x10f
> #define DP_TRAINING_LANE2_3_SET2 0x110
> @@ -613,9 +638,9 @@ struct drm_device;
> #define DP_LINK_STATUS_UPDATED (1 << 7)
>
> #define DP_SINK_STATUS 0x205
> -
> -#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
> -#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
> +# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
> +# define DP_RECEIVE_PORT_1_STATUS (1 << 1)
> +# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
>
> #define DP_ADJUST_REQUEST_LANE0_1 0x206
> #define DP_ADJUST_REQUEST_LANE2_3 0x207
> @@ -628,6 +653,12 @@ struct drm_device;
> # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
> # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
>
> +/* DP 2.0 128b/132b Link Layer */
> +# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
> +# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
> +# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
> +# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
> +
> #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
> # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
> # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
> @@ -945,9 +976,8 @@ struct drm_device;
> #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
> #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
>
> -/* Extended Receiver Capability */
> +/* Extended Receiver Capability: See DP_DPCD_REV for definitions */
> #define DP_DP13_DPCD_REV 0x2200
> -#define DP_DP13_MAX_LINK_RATE 0x2201
>
> #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
> # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
> @@ -959,6 +989,14 @@ struct drm_device;
> # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
> # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
>
> +#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */
> +# define DP_UHBR10 (1 << 0)
> +# define DP_UHBR20 (1 << 1)
> +# define DP_UHBR13_5 (1 << 2)
> +
> +#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
> +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
> +
> /* Protocol Converter Extension */
> /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
> #define DP_CEC_TUNNELING_CAPABILITY 0x3000
> --
> 2.20.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions
2020-09-18 19:29 ` [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions Navare, Manasi
@ 2020-09-24 8:33 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2020-09-24 8:33 UTC (permalink / raw)
To: Navare, Manasi; +Cc: dri-devel
On Fri, 18 Sep 2020, "Navare, Manasi" <manasi.d.navare@intel.com> wrote:
> On Fri, Sep 18, 2020 at 02:40:16PM +0300, Jani Nikula wrote:
>> Add the subheadings from the DP spec. No functional changes.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Looks good to me
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Thanks, pushed both to drm-misc-next.
BR,
Jani.
>
> Manasi
>
>> ---
>> include/drm/drm_dp_helper.h | 22 ++++++++++++++++++----
>> 1 file changed, 18 insertions(+), 4 deletions(-)
>>
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index c9f2851904d0..388083b4716b 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -106,8 +106,9 @@ struct drm_device;
>> #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
>> #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
>>
>> -/* AUX CH addresses */
>> -/* DPCD */
>> +/* DPCD Field Address Mapping */
>> +
>> +/* Receiver Capability */
>> #define DP_DPCD_REV 0x000
>> # define DP_DPCD_REV_10 0x10
>> # define DP_DPCD_REV_11 0x11
>> @@ -426,7 +427,7 @@ struct drm_device;
>> #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
>> #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
>>
>> -/* link configuration */
>> +/* Link Configuration */
>> #define DP_LINK_BW_SET 0x100
>> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
>> # define DP_LINK_BW_1_62 0x06
>> @@ -580,6 +581,7 @@ struct drm_device;
>> #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>> #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
>>
>> +/* Link/Sink Device Status */
>> #define DP_SINK_COUNT 0x200
>> /* prior to 1.2 bit 7 was reserved mbz */
>> # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
>> @@ -779,20 +781,27 @@ struct drm_device;
>> #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
>> /* up to ID_SLOT_63 at 0x2ff */
>>
>> +/* Source Device-specific */
>> #define DP_SOURCE_OUI 0x300
>> +
>> +/* Sink Device-specific */
>> #define DP_SINK_OUI 0x400
>> +
>> +/* Branch Device-specific */
>> #define DP_BRANCH_OUI 0x500
>> #define DP_BRANCH_ID 0x503
>> #define DP_BRANCH_REVISION_START 0x509
>> #define DP_BRANCH_HW_REV 0x509
>> #define DP_BRANCH_SW_REV 0x50A
>>
>> +/* Link/Sink Device Power Control */
>> #define DP_SET_POWER 0x600
>> # define DP_SET_POWER_D0 0x1
>> # define DP_SET_POWER_D3 0x2
>> # define DP_SET_POWER_MASK 0x3
>> # define DP_SET_POWER_D3_AUX_ON 0x5
>>
>> +/* eDP-specific */
>> #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
>> # define DP_EDP_11 0x00
>> # define DP_EDP_12 0x01
>> @@ -876,11 +885,13 @@ struct drm_device;
>> #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
>> #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
>>
>> +/* Sideband MSG Buffers */
>> #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
>> #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
>> #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
>> #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
>>
>> +/* DPRX Event Status Indicator */
>> #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
>> /* 0-5 sink count */
>> # define DP_SINK_COUNT_CP_READY (1 << 6)
>> @@ -934,6 +945,7 @@ struct drm_device;
>> #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
>> #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
>>
>> +/* Extended Receiver Capability */
>> #define DP_DP13_DPCD_REV 0x2200
>> #define DP_DP13_MAX_LINK_RATE 0x2201
>>
>> @@ -947,6 +959,7 @@ struct drm_device;
>> # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
>> # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
>>
>> +/* Protocol Converter Extension */
>> /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
>> #define DP_CEC_TUNNELING_CAPABILITY 0x3000
>> # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
>> @@ -1013,6 +1026,7 @@ struct drm_device;
>> #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
>> # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
>>
>> +/* HDCP 1.3 and HDCP 2.2 */
>> #define DP_AUX_HDCP_BKSV 0x68000
>> #define DP_AUX_HDCP_RI_PRIME 0x68005
>> #define DP_AUX_HDCP_AKSV 0x68007
>> @@ -1058,7 +1072,7 @@ struct drm_device;
>> #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
>> #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
>>
>> -/* Link Training (LT)-tunable PHY Repeaters */
>> +/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
>> #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
>> #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
>> #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
>> --
>> 2.20.1
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions
@ 2020-09-17 10:50 Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2020-09-17 10:50 UTC (permalink / raw)
To: dri-devel; +Cc: jani.nikula
Add the subheadings from the DP spec. No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5c45195ced32..3d9900e7d57c 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -104,8 +104,9 @@
#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
-/* AUX CH addresses */
-/* DPCD */
+/* DPCD Field Address Mapping */
+
+/* Receiver Capability */
#define DP_DPCD_REV 0x000
# define DP_DPCD_REV_10 0x10
# define DP_DPCD_REV_11 0x11
@@ -407,7 +408,7 @@
#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
-/* link configuration */
+/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
# define DP_LINK_BW_1_62 0x06
@@ -561,6 +562,7 @@
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
+/* Link/Sink Device Status */
#define DP_SINK_COUNT 0x200
/* prior to 1.2 bit 7 was reserved mbz */
# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
@@ -760,20 +762,27 @@
#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
/* up to ID_SLOT_63 at 0x2ff */
+/* Source Device-specific */
#define DP_SOURCE_OUI 0x300
+
+/* Sink Device-specific */
#define DP_SINK_OUI 0x400
+
+/* Branch Device-specific */
#define DP_BRANCH_OUI 0x500
#define DP_BRANCH_ID 0x503
#define DP_BRANCH_REVISION_START 0x509
#define DP_BRANCH_HW_REV 0x509
#define DP_BRANCH_SW_REV 0x50A
+/* Link/Sink Device Power Control */
#define DP_SET_POWER 0x600
# define DP_SET_POWER_D0 0x1
# define DP_SET_POWER_D3 0x2
# define DP_SET_POWER_MASK 0x3
# define DP_SET_POWER_D3_AUX_ON 0x5
+/* eDP-specific */
#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
# define DP_EDP_11 0x00
# define DP_EDP_12 0x01
@@ -857,11 +866,13 @@
#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
+/* Sideband MSG Buffers */
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
+/* DPRX Event Status Indicator */
#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
/* 0-5 sink count */
# define DP_SINK_COUNT_CP_READY (1 << 6)
@@ -915,6 +926,7 @@
#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
+/* Extended Receiver Capability */
#define DP_DP13_DPCD_REV 0x2200
#define DP_DP13_MAX_LINK_RATE 0x2201
@@ -928,6 +940,7 @@
# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
+/* Protocol Converter Extension */
/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
#define DP_CEC_TUNNELING_CAPABILITY 0x3000
# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
@@ -984,6 +997,7 @@
#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
+/* HDCP 1.3 and HDCP 2.2 */
#define DP_AUX_HDCP_BKSV 0x68000
#define DP_AUX_HDCP_RI_PRIME 0x68005
#define DP_AUX_HDCP_AKSV 0x68007
@@ -1029,7 +1043,7 @@
#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
-/* Link Training (LT)-tunable PHY Repeaters */
+/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
--
2.20.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-09-24 8:33 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-09-18 11:40 [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions Jani Nikula
2020-09-18 11:40 ` [PATCH 2/2] drm/dp: add a number of DP 2.0 DPCD definitions Jani Nikula
2020-09-18 19:53 ` Navare, Manasi
2020-09-18 19:29 ` [PATCH 1/2] drm/dp: add subheadings to DPCD address definitions Navare, Manasi
2020-09-24 8:33 ` Jani Nikula
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