* [PATCH 1/4] drm/msm/dsi_pll_7nm: restore VCO rate during restore_state
@ 2020-10-15 19:03 Dmitry Baryshkov
2020-10-15 19:03 ` [PATCH 2/4] drm/msm/dsi_pll_10nm: " Dmitry Baryshkov
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2020-10-15 19:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Jonathan Marek
Cc: Jeffrey Hugo, Stephen Boyd, linux-arm-msm, Harigovindan P,
dri-devel, David Airlie, freedreno
PHY disable/enable resets PLL registers to default values. Thus in
addition to restoring several registers we also need to restore VCO rate
settings.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
index de0dfb815125..93bf142e4a4e 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
@@ -585,6 +585,7 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll)
struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
void __iomem *phy_base = pll_7nm->phy_cmn_mmio;
u32 val;
+ int ret;
val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
val &= ~0x3;
@@ -599,6 +600,13 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll)
val |= cached->pll_mux;
pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
+ ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);
+ if (ret) {
+ DRM_DEV_ERROR(&pll_7nm->pdev->dev,
+ "restore vco rate failed. ret=%d\n", ret);
+ return ret;
+ }
+
DBG("DSI PLL%d", pll_7nm->id);
return 0;
--
2.28.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/4] drm/msm/dsi_pll_10nm: restore VCO rate during restore_state
2020-10-15 19:03 [PATCH 1/4] drm/msm/dsi_pll_7nm: restore VCO rate during restore_state Dmitry Baryshkov
@ 2020-10-15 19:03 ` Dmitry Baryshkov
2020-10-15 19:03 ` [PATCH 3/4] drm/msm/dsi_phy_7nm: implement PHY disabling Dmitry Baryshkov
2020-10-15 19:03 ` [PATCH 4/4] drm/msm/dsi_phy_10nm: " Dmitry Baryshkov
2 siblings, 0 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2020-10-15 19:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Jonathan Marek
Cc: Jeffrey Hugo, Stephen Boyd, linux-arm-msm, Harigovindan P,
dri-devel, David Airlie, freedreno
PHY disable/enable resets PLL registers to default values. Thus in
addition to restoring several registers we also need to restore VCO rate
settings.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: c6659785dfb3 ("drm/msm/dsi/pll: call vco set rate explicitly")
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 6ac04fc303f5..e4e9bf04b736 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -559,6 +559,7 @@ static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll)
struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
u32 val;
+ int ret;
val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
val &= ~0x3;
@@ -573,6 +574,13 @@ static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll)
val |= cached->pll_mux;
pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
+ ret = dsi_pll_10nm_vco_set_rate(&pll->clk_hw, pll_10nm->vco_current_rate, pll_10nm->vco_ref_clk_rate);
+ if (ret) {
+ DRM_DEV_ERROR(&pll_10nm->pdev->dev,
+ "restore vco rate failed. ret=%d\n", ret);
+ return ret;
+ }
+
DBG("DSI PLL%d", pll_10nm->id);
return 0;
--
2.28.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/4] drm/msm/dsi_phy_7nm: implement PHY disabling
2020-10-15 19:03 [PATCH 1/4] drm/msm/dsi_pll_7nm: restore VCO rate during restore_state Dmitry Baryshkov
2020-10-15 19:03 ` [PATCH 2/4] drm/msm/dsi_pll_10nm: " Dmitry Baryshkov
@ 2020-10-15 19:03 ` Dmitry Baryshkov
2020-10-15 19:03 ` [PATCH 4/4] drm/msm/dsi_phy_10nm: " Dmitry Baryshkov
2 siblings, 0 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2020-10-15 19:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Jonathan Marek
Cc: Jeffrey Hugo, Stephen Boyd, linux-arm-msm, Harigovindan P,
dri-devel, David Airlie, freedreno
Implement phy_disable() callback to disable DSI PHY lanes and blocks
when phy is not used.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 255b5f5ab2ce..79c034ae075d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -200,7 +200,28 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
{
- /* TODO */
+ void __iomem *base = phy->base;
+ u32 data;
+
+ DBG("");
+
+ if (dsi_phy_hw_v4_0_is_pll_on(phy))
+ pr_warn("Turning OFF PHY while PLL is on\n");
+
+ dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
+ data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
+
+ /* disable all lanes */
+ data &= ~0x1F;
+ dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
+ dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0);
+
+ /* Turn off all PHY blocks */
+ dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00);
+ /* make sure phy is turned off */
+ wmb();
+
+ DBG("DSI%d PHY disabled", phy->id);
}
static int dsi_7nm_phy_init(struct msm_dsi_phy *phy)
--
2.28.0
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dri-devel@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 4/4] drm/msm/dsi_phy_10nm: implement PHY disabling
2020-10-15 19:03 [PATCH 1/4] drm/msm/dsi_pll_7nm: restore VCO rate during restore_state Dmitry Baryshkov
2020-10-15 19:03 ` [PATCH 2/4] drm/msm/dsi_pll_10nm: " Dmitry Baryshkov
2020-10-15 19:03 ` [PATCH 3/4] drm/msm/dsi_phy_7nm: implement PHY disabling Dmitry Baryshkov
@ 2020-10-15 19:03 ` Dmitry Baryshkov
2 siblings, 0 replies; 4+ messages in thread
From: Dmitry Baryshkov @ 2020-10-15 19:03 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Jonathan Marek
Cc: Jeffrey Hugo, Stephen Boyd, linux-arm-msm, Harigovindan P,
dri-devel, David Airlie, freedreno
Implement phy_disable() callback to disable DSI PHY lanes and blocks
when phy is not used.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: ff73ff194060 ("drm/msm/dsi: Populate the 10nm PHY funcs")
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 47403d4f2d28..d1b92d4dc197 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -192,6 +192,28 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy)
{
+ void __iomem *base = phy->base;
+ u32 data;
+
+ DBG("");
+
+ if (dsi_phy_hw_v3_0_is_pll_on(phy))
+ pr_warn("Turning OFF PHY while PLL is on\n");
+
+ dsi_phy_hw_v3_0_config_lpcdrx(phy, false);
+ data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
+
+ /* disable all lanes */
+ data &= ~0x1F;
+ dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
+ dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0);
+
+ /* Turn off all PHY blocks */
+ dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x00);
+ /* make sure phy is turned off */
+ wmb();
+
+ DBG("DSI%d PHY disabled", phy->id);
}
static int dsi_10nm_phy_init(struct msm_dsi_phy *phy)
--
2.28.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-10-17 19:05 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-10-15 19:03 [PATCH 1/4] drm/msm/dsi_pll_7nm: restore VCO rate during restore_state Dmitry Baryshkov
2020-10-15 19:03 ` [PATCH 2/4] drm/msm/dsi_pll_10nm: " Dmitry Baryshkov
2020-10-15 19:03 ` [PATCH 3/4] drm/msm/dsi_phy_7nm: implement PHY disabling Dmitry Baryshkov
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