* [PATCH v2 1/2] drm/vc4: hdmi: Make sure our clock rate is within limits @ 2020-10-29 12:25 Maxime Ripard 2020-10-29 12:25 ` [PATCH v2 2/2] drm/vc4: hdmi: Block odd horizontal timings Maxime Ripard 2020-11-19 11:19 ` [PATCH v2 1/2] drm/vc4: hdmi: Make sure our clock rate is within limits Dave Stevenson 0 siblings, 2 replies; 5+ messages in thread From: Maxime Ripard @ 2020-10-29 12:25 UTC (permalink / raw) To: Mark Rutland, Rob Herring, Frank Rowand, Daniel Vetter, David Airlie, Maarten Lankhorst, Thomas Zimmermann, Maxime Ripard, Eric Anholt Cc: devicetree, Tim Gover, Dave Stevenson, dri-devel, bcm-kernel-feedback-list, linux-rpi-kernel, Phil Elwell, linux-arm-kernel The HDMI controller cannot go above a certain pixel rate limit depending on the generations, but that limit is only enforced in mode_valid at the moment, which means that we won't advertise modes that exceed that limit, but the userspace is still free to try to setup a mode that would. Implement atomic_check to make sure we check it in that scenario too. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- Changes from v1: - Added that patch to resolve a conflict --- drivers/gpu/drm/vc4/vc4_hdmi.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index e8f99e290655..3d0338822cd2 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -760,6 +760,20 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) { } +static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_display_mode *mode = &crtc_state->adjusted_mode; + struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); + unsigned long long pixel_rate = mode->clock * 1000; + + if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) + return -EINVAL; + + return 0; +} + static enum drm_mode_status vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, const struct drm_display_mode *mode) @@ -773,6 +787,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, } static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { + .atomic_check = vc4_hdmi_encoder_atomic_check, .mode_valid = vc4_hdmi_encoder_mode_valid, .disable = vc4_hdmi_encoder_disable, .enable = vc4_hdmi_encoder_enable, -- 2.26.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] drm/vc4: hdmi: Block odd horizontal timings 2020-10-29 12:25 [PATCH v2 1/2] drm/vc4: hdmi: Make sure our clock rate is within limits Maxime Ripard @ 2020-10-29 12:25 ` Maxime Ripard 2020-11-19 11:14 ` Dave Stevenson 2020-11-19 11:19 ` [PATCH v2 1/2] drm/vc4: hdmi: Make sure our clock rate is within limits Dave Stevenson 1 sibling, 1 reply; 5+ messages in thread From: Maxime Ripard @ 2020-10-29 12:25 UTC (permalink / raw) To: Mark Rutland, Rob Herring, Frank Rowand, Daniel Vetter, David Airlie, Maarten Lankhorst, Thomas Zimmermann, Maxime Ripard, Eric Anholt Cc: devicetree, Tim Gover, Dave Stevenson, dri-devel, bcm-kernel-feedback-list, linux-rpi-kernel, Phil Elwell, linux-arm-kernel The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels per clock cycle, and cannot deal with odd timings. Let's reject any mode with such timings. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- Changes from v1: - s/broken/unsupported/ --- drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++++ drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 3d0338822cd2..506c12454086 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -768,6 +768,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); unsigned long long pixel_rate = mode->clock * 1000; + if (vc4_hdmi->variant->unsupported_odd_h_timings && + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || + (mode->hsync_end % 2) || (mode->htotal % 2))) + return -EINVAL; + if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) return -EINVAL; @@ -780,6 +785,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, { struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); + if (vc4_hdmi->variant->unsupported_odd_h_timings && + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || + (mode->hsync_end % 2) || (mode->htotal % 2))) + return MODE_H_ILLEGAL; + if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) return MODE_CLOCK_HIGH; @@ -1830,6 +1840,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { PHY_LANE_2, PHY_LANE_CK, }, + .unsupported_odd_h_timings = true, .init_resources = vc5_hdmi_init_resources, .csc_setup = vc5_hdmi_csc_setup, @@ -1855,6 +1866,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { PHY_LANE_CK, PHY_LANE_2, }, + .unsupported_odd_h_timings = true, .init_resources = vc5_hdmi_init_resources, .csc_setup = vc5_hdmi_csc_setup, diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h index 63c6f8bddf1d..6815e93b1a48 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h @@ -62,6 +62,9 @@ struct vc4_hdmi_variant { */ enum vc4_hdmi_phy_channel phy_lane_mapping[4]; + /* The BCM2711 cannot deal with odd horizontal pixel timings */ + bool unsupported_odd_h_timings; + /* Callback to get the resources (memory region, interrupts, * clocks, etc) for that variant. */ -- 2.26.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] drm/vc4: hdmi: Block odd horizontal timings 2020-10-29 12:25 ` [PATCH v2 2/2] drm/vc4: hdmi: Block odd horizontal timings Maxime Ripard @ 2020-11-19 11:14 ` Dave Stevenson 2020-11-19 13:29 ` Maxime Ripard 0 siblings, 1 reply; 5+ messages in thread From: Dave Stevenson @ 2020-11-19 11:14 UTC (permalink / raw) To: Maxime Ripard Cc: Mark Rutland, devicetree, Tim Gover, David Airlie, DRI Development, Rob Herring, bcm-kernel-feedback-list, linux-rpi-kernel, Thomas Zimmermann, Daniel Vetter, Frank Rowand, Phil Elwell, linux-arm-kernel Hi Maxime Thanks for the rewording :-) On Thu, 29 Oct 2020 at 12:25, Maxime Ripard <maxime@cerno.tech> wrote: > > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels > per clock cycle, and cannot deal with odd timings. > > Let's reject any mode with such timings. > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> > --- > > Changes from v1: > - s/broken/unsupported/ > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++++ > drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++ > 2 files changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index 3d0338822cd2..506c12454086 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -768,6 +768,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, > struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > unsigned long long pixel_rate = mode->clock * 1000; > > + if (vc4_hdmi->variant->unsupported_odd_h_timings && > + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || > + (mode->hsync_end % 2) || (mode->htotal % 2))) > + return -EINVAL; > + > if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) > return -EINVAL; > > @@ -780,6 +785,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, > { > struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > > + if (vc4_hdmi->variant->unsupported_odd_h_timings && > + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || > + (mode->hsync_end % 2) || (mode->htotal % 2))) > + return MODE_H_ILLEGAL; > + > if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) > return MODE_CLOCK_HIGH; > > @@ -1830,6 +1840,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { > PHY_LANE_2, > PHY_LANE_CK, > }, > + .unsupported_odd_h_timings = true, > > .init_resources = vc5_hdmi_init_resources, > .csc_setup = vc5_hdmi_csc_setup, > @@ -1855,6 +1866,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { > PHY_LANE_CK, > PHY_LANE_2, > }, > + .unsupported_odd_h_timings = true, > > .init_resources = vc5_hdmi_init_resources, > .csc_setup = vc5_hdmi_csc_setup, > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h > index 63c6f8bddf1d..6815e93b1a48 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.h > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h > @@ -62,6 +62,9 @@ struct vc4_hdmi_variant { > */ > enum vc4_hdmi_phy_channel phy_lane_mapping[4]; > > + /* The BCM2711 cannot deal with odd horizontal pixel timings */ > + bool unsupported_odd_h_timings; > + > /* Callback to get the resources (memory region, interrupts, > * clocks, etc) for that variant. > */ > -- > 2.26.2 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] drm/vc4: hdmi: Block odd horizontal timings 2020-11-19 11:14 ` Dave Stevenson @ 2020-11-19 13:29 ` Maxime Ripard 0 siblings, 0 replies; 5+ messages in thread From: Maxime Ripard @ 2020-11-19 13:29 UTC (permalink / raw) To: Dave Stevenson Cc: Mark Rutland, devicetree, Tim Gover, David Airlie, DRI Development, Rob Herring, bcm-kernel-feedback-list, linux-rpi-kernel, Thomas Zimmermann, Daniel Vetter, Frank Rowand, Phil Elwell, linux-arm-kernel [-- Attachment #1.1: Type: text/plain, Size: 550 bytes --] On Thu, Nov 19, 2020 at 11:14:50AM +0000, Dave Stevenson wrote: > Hi Maxime > > Thanks for the rewording :-) > > On Thu, 29 Oct 2020 at 12:25, Maxime Ripard <maxime@cerno.tech> wrote: > > > > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels > > per clock cycle, and cannot deal with odd timings. > > > > Let's reject any mode with such timings. > > > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > > Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Applied both patches, thanks! Maxime [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] drm/vc4: hdmi: Make sure our clock rate is within limits 2020-10-29 12:25 [PATCH v2 1/2] drm/vc4: hdmi: Make sure our clock rate is within limits Maxime Ripard 2020-10-29 12:25 ` [PATCH v2 2/2] drm/vc4: hdmi: Block odd horizontal timings Maxime Ripard @ 2020-11-19 11:19 ` Dave Stevenson 1 sibling, 0 replies; 5+ messages in thread From: Dave Stevenson @ 2020-11-19 11:19 UTC (permalink / raw) To: Maxime Ripard Cc: Mark Rutland, devicetree, Tim Gover, David Airlie, DRI Development, Rob Herring, bcm-kernel-feedback-list, linux-rpi-kernel, Thomas Zimmermann, Daniel Vetter, Frank Rowand, Phil Elwell, linux-arm-kernel Hi Maxime On Thu, 29 Oct 2020 at 12:25, Maxime Ripard <maxime@cerno.tech> wrote: > > The HDMI controller cannot go above a certain pixel rate limit depending on > the generations, but that limit is only enforced in mode_valid at the > moment, which means that we won't advertise modes that exceed that limit, > but the userspace is still free to try to setup a mode that would. > > Implement atomic_check to make sure we check it in that scenario too. > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> > --- > > Changes from v1: > - Added that patch to resolve a conflict > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index e8f99e290655..3d0338822cd2 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -760,6 +760,20 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) > { > } > > +static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, > + struct drm_crtc_state *crtc_state, > + struct drm_connector_state *conn_state) > +{ > + struct drm_display_mode *mode = &crtc_state->adjusted_mode; > + struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > + unsigned long long pixel_rate = mode->clock * 1000; > + > + if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) > + return -EINVAL; > + > + return 0; > +} > + > static enum drm_mode_status > vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, > const struct drm_display_mode *mode) > @@ -773,6 +787,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, > } > > static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { > + .atomic_check = vc4_hdmi_encoder_atomic_check, > .mode_valid = vc4_hdmi_encoder_mode_valid, > .disable = vc4_hdmi_encoder_disable, > .enable = vc4_hdmi_encoder_enable, > -- > 2.26.2 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-11-19 20:32 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-10-29 12:25 [PATCH v2 1/2] drm/vc4: hdmi: Make sure our clock rate is within limits Maxime Ripard 2020-10-29 12:25 ` [PATCH v2 2/2] drm/vc4: hdmi: Block odd horizontal timings Maxime Ripard 2020-11-19 11:14 ` Dave Stevenson 2020-11-19 13:29 ` Maxime Ripard 2020-11-19 11:19 ` [PATCH v2 1/2] drm/vc4: hdmi: Make sure our clock rate is within limits Dave Stevenson
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