From: Matthew Brost <matthew.brost@intel.com>
To: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 06/47] drm/i915/guc: Optimize CTB writes and reads
Date: Fri, 25 Jun 2021 11:26:56 -0700 [thread overview]
Message-ID: <20210625182654.GA18715@sdutt-i7> (raw)
In-Reply-To: <a44cf19c-d84d-6408-5571-b9a35bb2b3ce@intel.com>
On Fri, Jun 25, 2021 at 03:09:29PM +0200, Michal Wajdeczko wrote:
>
>
> On 24.06.2021 09:04, Matthew Brost wrote:
> > CTB writes are now in the path of command submission and should be
> > optimized for performance. Rather than reading CTB descriptor values
> > (e.g. head, tail) which could result in accesses across the PCIe bus,
> > store shadow local copies and only read/write the descriptor values when
> > absolutely necessary. Also store the current space in the each channel
> > locally.
> >
> > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 76 ++++++++++++++---------
> > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 6 ++
> > 2 files changed, 51 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > index 27ec30b5ef47..1fd5c69358ef 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > @@ -130,6 +130,10 @@ static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
> > static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
> > {
> > ctb->broken = false;
> > + ctb->tail = 0;
> > + ctb->head = 0;
> > + ctb->space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size);
> > +
> > guc_ct_buffer_desc_init(ctb->desc);
> > }
> >
> > @@ -383,10 +387,8 @@ static int ct_write(struct intel_guc_ct *ct,
> > {
> > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> > struct guc_ct_buffer_desc *desc = ctb->desc;
> > - u32 head = desc->head;
> > - u32 tail = desc->tail;
> > + u32 tail = ctb->tail;
> > u32 size = ctb->size;
> > - u32 used;
> > u32 header;
> > u32 hxg;
> > u32 *cmds = ctb->cmds;
> > @@ -398,25 +400,14 @@ static int ct_write(struct intel_guc_ct *ct,
> > if (unlikely(desc->status))
> > goto corrupted;
> >
> > - if (unlikely((tail | head) >= size)) {
> > +#ifdef CONFIG_DRM_I915_DEBUG_GUC
>
> since we are caching tail, we may want to check if it's sill correct:
>
> tail = READ_ONCE(desc->tail);
> if (unlikely(tail != ctb->tail)) {
> CT_ERROR(ct, "Tail was modified %u != %u\n",
> tail, ctb->tail);
> desc->status |= GUC_CTB_STATUS_MISMATCH;
> goto corrupted;
> }
>
> and since we own the tail then we can be more strict:
>
> GEM_BUG_ON(tail > size);
>
> and then finally just check GuC head:
>
> head = READ_ONCE(desc->head);
> if (unlikely(head >= size)) {
> ...
>
Sure, but still hidden behind CONFIG_DRM_I915_DEBUG_GUC, right?
> > + if (unlikely((desc->tail | desc->head) >= size)) {
> > CT_ERROR(ct, "Invalid offsets head=%u tail=%u (size=%u)\n",
> > - head, tail, size);
> > + desc->head, desc->tail, size);
> > desc->status |= GUC_CTB_STATUS_OVERFLOW;
> > goto corrupted;
> > }
> > -
> > - /*
> > - * tail == head condition indicates empty. GuC FW does not support
> > - * using up the entire buffer to get tail == head meaning full.
> > - */
> > - if (tail < head)
> > - used = (size - head) + tail;
> > - else
> > - used = tail - head;
> > -
> > - /* make sure there is a space including extra dw for the fence */
> > - if (unlikely(used + len + 1 >= size))
> > - return -ENOSPC;
> > +#endif
> >
> > /*
> > * dw0: CT header (including fence)
> > @@ -457,7 +448,9 @@ static int ct_write(struct intel_guc_ct *ct,
> > write_barrier(ct);
> >
> > /* now update descriptor */
> > + ctb->tail = tail;
> > WRITE_ONCE(desc->tail, tail);
> > + ctb->space -= len + 1;
>
> this magic "1" is likely GUC_CTB_MSG_MIN_LEN, right ?
>
Yes.
> >
> > return 0;
> >
> > @@ -473,7 +466,7 @@ static int ct_write(struct intel_guc_ct *ct,
> > * @req: pointer to pending request
> > * @status: placeholder for status
> > *
> > - * For each sent request, Guc shall send bac CT response message.
> > + * For each sent request, GuC shall send back CT response message.
> > * Our message handler will update status of tracked request once
> > * response message with given fence is received. Wait here and
> > * check for valid response status value.
> > @@ -520,24 +513,35 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct)
> > return ret;
> > }
> >
> > -static inline bool h2g_has_room(struct intel_guc_ct_buffer *ctb, u32 len_dw)
> > +static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw)
> > {
> > - struct guc_ct_buffer_desc *desc = ctb->desc;
> > - u32 head = READ_ONCE(desc->head);
> > + struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> > + u32 head;
> > u32 space;
> >
> > - space = CIRC_SPACE(desc->tail, head, ctb->size);
> > + if (ctb->space >= len_dw)
> > + return true;
> > +
> > + head = READ_ONCE(ctb->desc->head);
> > + if (unlikely(head > ctb->size)) {
> > + CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u size=%u\n",
> > + ctb->desc->head, ctb->desc->tail, ctb->size);
> > + ctb->desc->status |= GUC_CTB_STATUS_OVERFLOW;
> > + ctb->broken = true;
> > + return false;
> > + }
> > +
> > + space = CIRC_SPACE(ctb->tail, head, ctb->size);
> > + ctb->space = space;
>
> maybe here we could mark stall_time ?
>
> if (space >= len_dw)
> return true;
>
> if (ct->stall_time == KTIME_MAX)
> ct->stall_time = ktime_get();
> return false;
>
No. See my eariler comment [1] about why I'd rather leave this to the
caller.
[1] https://patchwork.freedesktop.org/patch/440703/?series=91840&rev=1
> >
> > return space >= len_dw;
>
> btw, maybe to avoid filling CTB to the last dword, this should be
>
> space > len_dw
>
CIRC_SPACE leaves an extra DW already.
> note the earlier comment:
>
> /*
> * tail == head condition indicates empty. GuC FW does not support
> * using up the entire buffer to get tail == head meaning full.
> */
>
Yes, again CIRC_SPACE uses this same algorithm.
Matt
> > }
> >
> > static int has_room_nb(struct intel_guc_ct *ct, u32 len_dw)
> > {
> > - struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
> > -
> > lockdep_assert_held(&ct->ctbs.send.lock);
> >
> > - if (unlikely(!h2g_has_room(ctb, len_dw))) {
> > + if (unlikely(!h2g_has_room(ct, len_dw))) {
> > if (ct->stall_time == KTIME_MAX)
> > ct->stall_time = ktime_get();
> >
> > @@ -606,10 +610,10 @@ static int ct_send(struct intel_guc_ct *ct,
> > */
> > retry:
> > spin_lock_irqsave(&ct->ctbs.send.lock, flags);
> > - if (unlikely(!h2g_has_room(ctb, len + 1))) {
> > + if (unlikely(!h2g_has_room(ct, len + 1))) {
> > if (ct->stall_time == KTIME_MAX)
> > ct->stall_time = ktime_get();
> > - spin_unlock_irqrestore(&ct->ctbs.send.lock, flags);
> > + spin_unlock_irqrestore(&ctb->lock, flags);
> >
> > if (unlikely(ct_deadlocked(ct)))
> > return -EIO;
> > @@ -632,7 +636,7 @@ static int ct_send(struct intel_guc_ct *ct,
> >
> > err = ct_write(ct, action, len, fence, 0);
> >
> > - spin_unlock_irqrestore(&ct->ctbs.send.lock, flags);
> > + spin_unlock_irqrestore(&ctb->lock, flags);
> >
> > if (unlikely(err))
> > goto unlink;
> > @@ -720,7 +724,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> > {
> > struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
> > struct guc_ct_buffer_desc *desc = ctb->desc;
> > - u32 head = desc->head;
> > + u32 head = ctb->head;
> > u32 tail = desc->tail;
> > u32 size = ctb->size;
> > u32 *cmds = ctb->cmds;
> > @@ -735,12 +739,21 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> > if (unlikely(desc->status))
> > goto corrupted;
> >
> > - if (unlikely((tail | head) >= size)) {
> > +#ifdef CONFIG_DRM_I915_DEBUG_GUC
>
> as above we may want to check if our cached head was not modified
>
> > + if (unlikely((desc->tail | desc->head) >= size)) {
> > CT_ERROR(ct, "Invalid offsets head=%u tail=%u (size=%u)\n",
> > head, tail, size);
> > desc->status |= GUC_CTB_STATUS_OVERFLOW;
> > goto corrupted;
> > }
> > +#else
> > + if (unlikely((tail | ctb->head) >= size)) {
> > + CT_ERROR(ct, "Invalid offsets head=%u tail=%u (size=%u)\n",
> > + head, tail, size);
> > + desc->status |= GUC_CTB_STATUS_OVERFLOW;
> > + goto corrupted;
> > + }
> > +#endif
> >
> > /* tail == head condition indicates empty */
> > available = tail - head;
> > @@ -790,6 +803,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
> > }
> > CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg);
> >
> > + ctb->head = head;
> > /* now update descriptor */
> > WRITE_ONCE(desc->head, head);
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> > index 55ef7c52472f..9924335e2ee6 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> > @@ -33,6 +33,9 @@ struct intel_guc;
> > * @desc: pointer to the buffer descriptor
> > * @cmds: pointer to the commands buffer
> > * @size: size of the commands buffer in dwords
> > + * @head: local shadow copy of head in dwords
> > + * @tail: local shadow copy of tail in dwords
> > + * @space: local shadow copy of space in dwords
> > * @broken: flag to indicate if descriptor data is broken
> > */
> > struct intel_guc_ct_buffer {
> > @@ -40,6 +43,9 @@ struct intel_guc_ct_buffer {
> > struct guc_ct_buffer_desc *desc;
> > u32 *cmds;
> > u32 size;
> > + u32 tail;
> > + u32 head;
> > + u32 space;
>
> in later patch this is changing to atomic_t
> maybe we can start with it ?
>
> > bool broken;
> > };
> >
> >
next prev parent reply other threads:[~2021-06-25 18:33 UTC|newest]
Thread overview: 166+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 7:04 [PATCH 00/47] GuC submission support Matthew Brost
2021-06-24 7:04 ` [PATCH 01/47] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-24 17:23 ` Michal Wajdeczko
2021-06-24 7:04 ` [PATCH 02/47] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-06-25 11:58 ` [Intel-gfx] " Michal Wajdeczko
2021-06-24 7:04 ` [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-06-24 13:49 ` Michal Wajdeczko
2021-06-24 15:41 ` Matthew Brost
2021-06-25 12:03 ` Michal Wajdeczko
2021-06-24 7:04 ` [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-06-24 14:48 ` [Intel-gfx] " Michal Wajdeczko
2021-06-24 15:49 ` Matthew Brost
2021-06-24 17:02 ` Michal Wajdeczko
2021-06-24 22:41 ` Matthew Brost
2021-06-25 11:50 ` Michal Wajdeczko
2021-06-25 17:53 ` Matthew Brost
2021-06-24 22:47 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 05/47] drm/i915/guc: Add stall timer to " Matthew Brost
2021-06-24 17:37 ` [Intel-gfx] " Michal Wajdeczko
2021-06-24 23:01 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 06/47] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-06-25 13:09 ` [Intel-gfx] " Michal Wajdeczko
2021-06-25 18:26 ` Matthew Brost [this message]
2021-06-25 20:28 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 07/47] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-06-24 7:04 ` [PATCH 08/47] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-06-29 21:11 ` John Harrison
2021-06-30 0:30 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 09/47] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-06-25 19:44 ` John Harrison
2021-06-24 7:04 ` [PATCH 10/47] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-06-25 13:17 ` Michal Wajdeczko
2021-06-25 17:26 ` Matthew Brost
2021-06-29 21:20 ` John Harrison
2021-06-24 7:04 ` [PATCH 11/47] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-06-29 22:04 ` John Harrison
2021-06-30 0:41 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 12/47] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-06-29 22:09 ` John Harrison
2021-06-24 7:04 ` [PATCH 13/47] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-06-25 13:25 ` Michal Wajdeczko
2021-06-25 17:46 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 14/47] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-07-09 22:39 ` John Harrison
2021-06-24 7:04 ` [PATCH 15/47] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-07-09 22:48 ` John Harrison
2021-06-24 7:04 ` [PATCH 16/47] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-07-09 22:53 ` John Harrison
2021-07-10 3:00 ` Matthew Brost
2021-07-12 17:57 ` John Harrison
2021-07-12 18:11 ` [Intel-gfx] " Daniel Vetter
2021-06-24 7:04 ` [PATCH 17/47] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-07-09 22:59 ` John Harrison
2021-07-10 3:36 ` Matthew Brost
2021-07-12 17:54 ` John Harrison
2021-06-24 7:04 ` [PATCH 18/47] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-07-09 23:03 ` John Harrison
2021-06-24 7:04 ` [PATCH 19/47] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-07-15 1:51 ` Daniele Ceraolo Spurio
2021-06-24 7:04 ` [PATCH 20/47] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-07-09 23:53 ` John Harrison
2021-07-15 0:07 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 21/47] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-07-13 18:36 ` John Harrison
2021-07-15 0:06 ` Matthew Brost
2021-07-15 0:12 ` John Harrison
2021-06-24 7:04 ` [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-07-10 0:16 ` John Harrison
2021-07-10 3:55 ` Matthew Brost
2021-07-17 4:09 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 23/47] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-07-12 18:05 ` John Harrison
2021-07-12 20:59 ` Matthew Brost
2021-07-12 21:37 ` John Harrison
2021-07-13 8:51 ` Michal Wajdeczko
2021-07-14 23:56 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 24/47] drm/i915/guc: Add several request trace points Matthew Brost
2021-07-12 18:08 ` John Harrison
2021-07-13 9:06 ` [Intel-gfx] " Tvrtko Ursulin
2021-07-20 1:59 ` Matthew Brost
2021-07-22 13:55 ` Tvrtko Ursulin
2021-06-24 7:04 ` [PATCH 25/47] drm/i915: Add intel_context tracing Matthew Brost
2021-07-12 18:10 ` John Harrison
2021-07-12 21:47 ` Matthew Brost
2021-07-12 21:51 ` John Harrison
2021-06-24 7:04 ` [PATCH 26/47] drm/i915/guc: GuC virtual engines Matthew Brost
2021-07-15 1:21 ` Daniele Ceraolo Spurio
2021-06-24 7:04 ` [PATCH 27/47] drm/i915: Track 'serial' counts for " Matthew Brost
2021-07-12 18:11 ` John Harrison
2021-07-12 20:06 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 28/47] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-07-12 18:23 ` John Harrison
2021-07-12 20:05 ` Matthew Brost
2021-07-12 21:36 ` [Intel-gfx] " Matthew Brost
2021-07-12 21:48 ` John Harrison
2021-06-24 7:04 ` [PATCH 29/47] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-07-12 18:23 ` John Harrison
2021-06-24 7:04 ` [PATCH 30/47] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-07-12 19:19 ` John Harrison
2021-06-24 7:05 ` [PATCH 31/47] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-07-12 19:58 ` John Harrison
2021-07-15 0:53 ` Matthew Brost
2021-07-15 9:36 ` [Intel-gfx] " Tvrtko Ursulin
2021-07-26 22:48 ` Matthew Brost
2021-07-27 8:56 ` Tvrtko Ursulin
2021-07-27 18:30 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-07-12 20:01 ` John Harrison
2021-06-24 7:05 ` [PATCH 33/47] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-07-12 20:11 ` John Harrison
2021-06-24 7:05 ` [PATCH 34/47] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-07-12 22:56 ` John Harrison
2021-06-24 7:05 ` [PATCH 35/47] drm/i915/guc: Handle context reset notification Matthew Brost
2021-07-12 22:58 ` John Harrison
2021-07-15 0:32 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 36/47] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-07-12 22:59 ` John Harrison
2021-06-24 7:05 ` [PATCH 37/47] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-07-12 23:00 ` John Harrison
2021-06-24 7:05 ` [PATCH 38/47] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-06-24 7:05 ` [PATCH 39/47] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-06-24 15:55 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:05 ` [PATCH 40/47] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-06-24 16:19 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:05 ` [PATCH 41/47] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-07-12 23:05 ` John Harrison
2021-06-24 7:05 ` [PATCH 42/47] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-07-15 0:43 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:05 ` [PATCH 43/47] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-06-25 0:59 ` [Intel-gfx] " Matthew Brost
2021-06-25 19:10 ` John Harrison
2021-07-10 18:56 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 44/47] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-06-25 1:10 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:05 ` [PATCH 45/47] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-06-24 16:34 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 46/47] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-06-24 7:05 ` [PATCH 47/47] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-06-30 8:22 ` Martin Peres
2021-06-30 18:00 ` Matthew Brost
2021-07-01 18:24 ` Martin Peres
2021-07-02 8:13 ` Martin Peres
2021-07-02 13:06 ` Michal Wajdeczko
2021-07-02 13:12 ` Martin Peres
2021-07-02 14:08 ` Michal Wajdeczko
2021-06-30 18:58 ` John Harrison
2021-07-01 8:14 ` Pekka Paalanen
2021-07-01 18:27 ` Martin Peres
2021-07-01 19:28 ` [Intel-gfx] " Daniel Vetter
2021-07-02 7:29 ` Pekka Paalanen
2021-07-02 8:09 ` Martin Peres
2021-07-02 15:07 ` Michal Wajdeczko
2021-07-03 8:21 ` Martin Peres
2021-07-07 0:57 ` John Harrison
2021-07-07 7:47 ` Pekka Paalanen
2021-07-07 10:11 ` Michal Wajdeczko
2021-07-15 0:49 ` Matthew Brost
2021-10-22 9:35 ` [PATCH 00/47] GuC submission support Joonas Lahtinen
2021-10-22 16:42 ` Matthew Brost
2021-10-25 9:37 ` Joonas Lahtinen
2021-10-25 15:15 ` Matthew Brost
2021-10-26 8:59 ` Joonas Lahtinen
2021-10-26 15:43 ` Matthew Brost
2021-10-26 15:51 ` Matthew Brost
2021-10-27 9:21 ` Joonas Lahtinen
2021-10-25 17:06 ` John Harrison
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210625182654.GA18715@sdutt-i7 \
--to=matthew.brost@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=michal.wajdeczko@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).