* [PATCH v2 0/3] drm/vc4: Support for 30 bits YUV formats
@ 2021-12-06 11:01 Maxime Ripard
2021-12-06 11:01 ` [PATCH v2 1/3] drm/fourcc: Add packed 10bit YUV 4:2:0 format Maxime Ripard
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Maxime Ripard @ 2021-12-06 11:01 UTC (permalink / raw)
To: Daniel Vetter, David Airlie, Maarten Lankhorst,
Thomas Zimmermann, Maxime Ripard
Cc: Tim Gover, Dom Cobley, Phil Elwell, dri-devel, Dave Stevenson
Hi,
Here are a few patches adding support for the P030 and the BT709 and BT2020
colorspaces.
Let me know what you think,
Maxime
Changes from v1:
- Reworded the format description
- Fixed use before initialisation
Dave Stevenson (3):
drm/fourcc: Add packed 10bit YUV 4:2:0 format
drm/vc4: plane: Add support for DRM_FORMAT_P030
drm/vc4: plane: Add support for YUV color encodings and ranges
drivers/gpu/drm/drm_fourcc.c | 3 +
drivers/gpu/drm/vc4/vc4_plane.c | 199 ++++++++++++++++++++++++++------
drivers/gpu/drm/vc4/vc4_regs.h | 19 ++-
include/uapi/drm/drm_fourcc.h | 11 ++
4 files changed, 193 insertions(+), 39 deletions(-)
--
2.33.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/3] drm/fourcc: Add packed 10bit YUV 4:2:0 format
2021-12-06 11:01 [PATCH v2 0/3] drm/vc4: Support for 30 bits YUV formats Maxime Ripard
@ 2021-12-06 11:01 ` Maxime Ripard
2021-12-06 12:02 ` Dave Stevenson
2021-12-06 11:01 ` [PATCH v2 2/3] drm/vc4: plane: Add support for DRM_FORMAT_P030 Maxime Ripard
2021-12-06 11:01 ` [PATCH v2 3/3] drm/vc4: plane: Add support for YUV color encodings and ranges Maxime Ripard
2 siblings, 1 reply; 6+ messages in thread
From: Maxime Ripard @ 2021-12-06 11:01 UTC (permalink / raw)
To: Daniel Vetter, David Airlie, Maarten Lankhorst,
Thomas Zimmermann, Maxime Ripard
Cc: Tim Gover, Dom Cobley, Phil Elwell, dri-devel, Dave Stevenson
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
Adds a format that is 3 10bit YUV 4:2:0 samples packed into
a 32bit work (with 2 spare bits).
Supported on Broadcom BCM2711 chips.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 25837b1d6639..07741b678798 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -269,6 +269,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
.num_planes = 3, .char_per_block = { 2, 2, 2 },
.block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
.vsub = 0, .is_yuv = true },
+ { .format = DRM_FORMAT_P030, .depth = 0, .num_planes = 2,
+ .char_per_block = { 4, 8, 0 }, .block_w = { 3, 3, 0 }, .block_h = { 1, 1, 0 },
+ .hsub = 2, .vsub = 2, .is_yuv = true},
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 7f652c96845b..fc0c1454d275 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -314,6 +314,13 @@ extern "C" {
*/
#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
+/* 2 plane YCbCr420.
+ * 3 10 bit components and 2 padding bits packed into 4 bytes.
+ * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
+ * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
+ */
+#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
+
/* 3 plane non-subsampled (444) YCbCr
* 16 bits per component, but only 10 bits are used and 6 bits are padded
* index 0: Y plane, [15:0] Y:x [10:6] little endian
@@ -854,6 +861,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
* and UV. Some SAND-using hardware stores UV in a separate tiled
* image from Y to reduce the column height, which is not supported
* with these modifiers.
+ *
+ * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
+ * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
+ * wide, but as this is a 10 bpp format that translates to 96 pixels.
*/
#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
--
2.33.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] drm/vc4: plane: Add support for DRM_FORMAT_P030
2021-12-06 11:01 [PATCH v2 0/3] drm/vc4: Support for 30 bits YUV formats Maxime Ripard
2021-12-06 11:01 ` [PATCH v2 1/3] drm/fourcc: Add packed 10bit YUV 4:2:0 format Maxime Ripard
@ 2021-12-06 11:01 ` Maxime Ripard
2021-12-06 11:01 ` [PATCH v2 3/3] drm/vc4: plane: Add support for YUV color encodings and ranges Maxime Ripard
2 siblings, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2021-12-06 11:01 UTC (permalink / raw)
To: Daniel Vetter, David Airlie, Maarten Lankhorst,
Thomas Zimmermann, Maxime Ripard
Cc: Tim Gover, Dom Cobley, Phil Elwell, dri-devel, Dave Stevenson
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
The P030 format, used with the DRM_FORMAT_MOD_BROADCOM_SAND128 modifier,
is a format output by the video decoder on the BCM2711.
Add native support to the KMS planes for that format.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_plane.c | 128 ++++++++++++++++++++++++--------
1 file changed, 97 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index ac761c683663..18627b240a55 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -33,6 +33,7 @@ static const struct hvs_format {
u32 hvs; /* HVS_FORMAT_* */
u32 pixel_order;
u32 pixel_order_hvs5;
+ bool hvs5_only;
} hvs_formats[] = {
{
.drm = DRM_FORMAT_XRGB8888,
@@ -128,6 +129,12 @@ static const struct hvs_format {
.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
.pixel_order = HVS_PIXEL_ORDER_XYCRCB,
},
+ {
+ .drm = DRM_FORMAT_P030,
+ .hvs = HVS_PIXEL_FORMAT_YCBCR_10BIT,
+ .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
+ .hvs5_only = true,
+ },
};
static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
@@ -762,47 +769,91 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
case DRM_FORMAT_MOD_BROADCOM_SAND128:
case DRM_FORMAT_MOD_BROADCOM_SAND256: {
uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
- u32 tile_w, tile, x_off, pix_per_tile;
-
- hvs_format = HVS_PIXEL_FORMAT_H264;
-
- switch (base_format_mod) {
- case DRM_FORMAT_MOD_BROADCOM_SAND64:
- tiling = SCALER_CTL0_TILING_64B;
- tile_w = 64;
- break;
- case DRM_FORMAT_MOD_BROADCOM_SAND128:
- tiling = SCALER_CTL0_TILING_128B;
- tile_w = 128;
- break;
- case DRM_FORMAT_MOD_BROADCOM_SAND256:
- tiling = SCALER_CTL0_TILING_256B_OR_T;
- tile_w = 256;
- break;
- default:
- break;
- }
if (param > SCALER_TILE_HEIGHT_MASK) {
- DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
+ DRM_DEBUG_KMS("SAND height too large (%d)\n",
+ param);
return -EINVAL;
}
- pix_per_tile = tile_w / fb->format->cpp[0];
- tile = vc4_state->src_x / pix_per_tile;
- x_off = vc4_state->src_x % pix_per_tile;
+ if (fb->format->format == DRM_FORMAT_P030) {
+ hvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;
+ tiling = SCALER_CTL0_TILING_128B;
+ } else {
+ hvs_format = HVS_PIXEL_FORMAT_H264;
+
+ switch (base_format_mod) {
+ case DRM_FORMAT_MOD_BROADCOM_SAND64:
+ tiling = SCALER_CTL0_TILING_64B;
+ break;
+ case DRM_FORMAT_MOD_BROADCOM_SAND128:
+ tiling = SCALER_CTL0_TILING_128B;
+ break;
+ case DRM_FORMAT_MOD_BROADCOM_SAND256:
+ tiling = SCALER_CTL0_TILING_256B_OR_T;
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
+ }
/* Adjust the base pointer to the first pixel to be scanned
* out.
+ *
+ * For P030, y_ptr [31:4] is the 128bit word for the start pixel
+ * y_ptr [3:0] is the pixel (0-11) contained within that 128bit
+ * word that should be taken as the first pixel.
+ * Ditto uv_ptr [31:4] vs [3:0], however [3:0] contains the
+ * element within the 128bit word, eg for pixel 3 the value
+ * should be 6.
*/
for (i = 0; i < num_planes; i++) {
+ u32 tile_w, tile, x_off, pix_per_tile;
+
+ if (fb->format->format == DRM_FORMAT_P030) {
+ /*
+ * Spec says: bits [31:4] of the given address
+ * should point to the 128-bit word containing
+ * the desired starting pixel, and bits[3:0]
+ * should be between 0 and 11, indicating which
+ * of the 12-pixels in that 128-bit word is the
+ * first pixel to be used
+ */
+ u32 remaining_pixels = vc4_state->src_x % 96;
+ u32 aligned = remaining_pixels / 12;
+ u32 last_bits = remaining_pixels % 12;
+
+ x_off = aligned * 16 + last_bits;
+ tile_w = 128;
+ pix_per_tile = 96;
+ } else {
+ switch (base_format_mod) {
+ case DRM_FORMAT_MOD_BROADCOM_SAND64:
+ tile_w = 64;
+ break;
+ case DRM_FORMAT_MOD_BROADCOM_SAND128:
+ tile_w = 128;
+ break;
+ case DRM_FORMAT_MOD_BROADCOM_SAND256:
+ tile_w = 256;
+ break;
+ default:
+ break;
+ }
+ pix_per_tile = tile_w / fb->format->cpp[0];
+ x_off = (vc4_state->src_x % pix_per_tile) /
+ (i ? h_subsample : 1) *
+ fb->format->cpp[i];
+ }
+
+ tile = vc4_state->src_x / pix_per_tile;
+
vc4_state->offsets[i] += param * tile_w * tile;
vc4_state->offsets[i] += src_y /
(i ? v_subsample : 1) *
tile_w;
- vc4_state->offsets[i] += x_off /
- (i ? h_subsample : 1) *
- fb->format->cpp[i];
+ vc4_state->offsets[i] += x_off & ~(i ? 1 : 0);
}
pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
@@ -955,7 +1006,8 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
/* Pitch word 1/2 */
for (i = 1; i < num_planes; i++) {
- if (hvs_format != HVS_PIXEL_FORMAT_H264) {
+ if (hvs_format != HVS_PIXEL_FORMAT_H264 &&
+ hvs_format != HVS_PIXEL_FORMAT_YCBCR_10BIT) {
vc4_dlist_write(vc4_state,
VC4_SET_FIELD(fb->pitches[i],
SCALER_SRC_PITCH));
@@ -1315,6 +1367,13 @@ static bool vc4_format_mod_supported(struct drm_plane *plane,
default:
return false;
}
+ case DRM_FORMAT_P030:
+ switch (fourcc_mod_broadcom_mod(modifier)) {
+ case DRM_FORMAT_MOD_BROADCOM_SAND128:
+ return true;
+ default:
+ return false;
+ }
case DRM_FORMAT_RGBX1010102:
case DRM_FORMAT_BGRX1010102:
case DRM_FORMAT_RGBA1010102:
@@ -1347,8 +1406,11 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
struct drm_plane *plane = NULL;
struct vc4_plane *vc4_plane;
u32 formats[ARRAY_SIZE(hvs_formats)];
+ int num_formats = 0;
int ret = 0;
unsigned i;
+ bool hvs5 = of_device_is_compatible(dev->dev->of_node,
+ "brcm,bcm2711-vc5");
static const uint64_t modifiers[] = {
DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
DRM_FORMAT_MOD_BROADCOM_SAND128,
@@ -1363,13 +1425,17 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
if (!vc4_plane)
return ERR_PTR(-ENOMEM);
- for (i = 0; i < ARRAY_SIZE(hvs_formats); i++)
- formats[i] = hvs_formats[i].drm;
+ for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
+ if (!hvs_formats[i].hvs5_only || hvs5) {
+ formats[num_formats] = hvs_formats[i].drm;
+ num_formats++;
+ }
+ }
plane = &vc4_plane->base;
ret = drm_universal_plane_init(dev, plane, 0,
&vc4_plane_funcs,
- formats, ARRAY_SIZE(formats),
+ formats, num_formats,
modifiers, type, NULL);
if (ret)
return ERR_PTR(ret);
--
2.33.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] drm/vc4: plane: Add support for YUV color encodings and ranges
2021-12-06 11:01 [PATCH v2 0/3] drm/vc4: Support for 30 bits YUV formats Maxime Ripard
2021-12-06 11:01 ` [PATCH v2 1/3] drm/fourcc: Add packed 10bit YUV 4:2:0 format Maxime Ripard
2021-12-06 11:01 ` [PATCH v2 2/3] drm/vc4: plane: Add support for DRM_FORMAT_P030 Maxime Ripard
@ 2021-12-06 11:01 ` Maxime Ripard
2021-12-06 12:05 ` Dave Stevenson
2 siblings, 1 reply; 6+ messages in thread
From: Maxime Ripard @ 2021-12-06 11:01 UTC (permalink / raw)
To: Daniel Vetter, David Airlie, Maarten Lankhorst,
Thomas Zimmermann, Maxime Ripard
Cc: Dom Cobley, Tim Gover, Dave Stevenson, dri-devel, Dave Stevenson,
Phil Elwell
From: Dave Stevenson <dave.stevenson@raspberrypi.org>
The BT601/BT709 color encoding and limited vs full
range properties were not being exposed, defaulting
always to BT601 limited range.
Expose the parameters and set the registers appropriately.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_plane.c | 71 +++++++++++++++++++++++++++++++--
drivers/gpu/drm/vc4/vc4_regs.h | 19 ++++++---
2 files changed, 82 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 18627b240a55..1155b0beb620 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -623,6 +623,51 @@ static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
return 0;
}
+/*
+ * The colorspace conversion matrices are held in 3 entries in the dlist.
+ * Create an array of them, with entries for each full and limited mode, and
+ * each supported colorspace.
+ */
+static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {
+ {
+ /* Limited range */
+ {
+ /* BT601 */
+ SCALER_CSC0_ITR_R_601_5,
+ SCALER_CSC1_ITR_R_601_5,
+ SCALER_CSC2_ITR_R_601_5,
+ }, {
+ /* BT709 */
+ SCALER_CSC0_ITR_R_709_3,
+ SCALER_CSC1_ITR_R_709_3,
+ SCALER_CSC2_ITR_R_709_3,
+ }, {
+ /* BT2020 */
+ SCALER_CSC0_ITR_R_2020,
+ SCALER_CSC1_ITR_R_2020,
+ SCALER_CSC2_ITR_R_2020,
+ }
+ }, {
+ /* Full range */
+ {
+ /* JFIF */
+ SCALER_CSC0_JPEG_JFIF,
+ SCALER_CSC1_JPEG_JFIF,
+ SCALER_CSC2_JPEG_JFIF,
+ }, {
+ /* BT709 */
+ SCALER_CSC0_ITR_R_709_3_FR,
+ SCALER_CSC1_ITR_R_709_3_FR,
+ SCALER_CSC2_ITR_R_709_3_FR,
+ }, {
+ /* BT2020 */
+ SCALER_CSC0_ITR_R_2020_FR,
+ SCALER_CSC1_ITR_R_2020_FR,
+ SCALER_CSC2_ITR_R_2020_FR,
+ }
+ }
+};
+
/* Writes out a full display list for an active plane to the plane's
* private dlist state.
*/
@@ -1018,9 +1063,20 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
/* Colorspace conversion words */
if (vc4_state->is_yuv) {
- vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
- vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
- vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
+ enum drm_color_encoding color_encoding = state->color_encoding;
+ enum drm_color_range color_range = state->color_range;
+ const u32 *ccm;
+
+ if (color_encoding >= DRM_COLOR_ENCODING_MAX)
+ color_encoding = DRM_COLOR_YCBCR_BT601;
+ if (color_range >= DRM_COLOR_RANGE_MAX)
+ color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
+
+ ccm = colorspace_coeffs[color_range][color_encoding];
+
+ vc4_dlist_write(vc4_state, ccm[0]);
+ vc4_dlist_write(vc4_state, ccm[1]);
+ vc4_dlist_write(vc4_state, ccm[2]);
}
vc4_state->lbm_offset = 0;
@@ -1449,6 +1505,15 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
DRM_MODE_REFLECT_X |
DRM_MODE_REFLECT_Y);
+ drm_plane_create_color_properties(plane,
+ BIT(DRM_COLOR_YCBCR_BT601) |
+ BIT(DRM_COLOR_YCBCR_BT709) |
+ BIT(DRM_COLOR_YCBCR_BT2020),
+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
+ BIT(DRM_COLOR_YCBCR_FULL_RANGE),
+ DRM_COLOR_YCBCR_BT709,
+ DRM_COLOR_YCBCR_LIMITED_RANGE);
+
return plane;
}
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 489f921ef44d..7538b84a6dca 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -975,7 +975,10 @@ enum hvs_pixel_format {
#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
#define SCALER_CSC0_ITR_R_601_5 0x00f00000
#define SCALER_CSC0_ITR_R_709_3 0x00f00000
+#define SCALER_CSC0_ITR_R_2020 0x00f00000
#define SCALER_CSC0_JPEG_JFIF 0x00000000
+#define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
+#define SCALER_CSC0_ITR_R_2020_FR 0x00000000
/* S2.8 contribution of Cb to Green */
#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
@@ -990,8 +993,11 @@ enum hvs_pixel_format {
#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
-#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
-#define SCALER_CSC1_JPEG_JFIF 0xea34a400
+#define SCALER_CSC1_ITR_R_709_3 0xf27784a8
+#define SCALER_CSC1_ITR_R_2020 0xf43594a8
+#define SCALER_CSC1_JPEG_JFIF 0xea349400
+#define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400
+#define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400
/* S2.8 contribution of Cb to Red */
#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
@@ -1002,9 +1008,12 @@ enum hvs_pixel_format {
/* S2.8 contribution of Cb to Blue */
#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
-#define SCALER_CSC2_ITR_R_601_5 0x00066204
-#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
-#define SCALER_CSC2_JPEG_JFIF 0x000599c5
+#define SCALER_CSC2_ITR_R_601_5 0x00066604
+#define SCALER_CSC2_ITR_R_709_3 0x00072e1d
+#define SCALER_CSC2_ITR_R_2020 0x0006b624
+#define SCALER_CSC2_JPEG_JFIF 0x00059dc6
+#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
+#define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2
#define SCALER_TPZ0_VERT_RECALC BIT(31)
#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
--
2.33.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/3] drm/fourcc: Add packed 10bit YUV 4:2:0 format
2021-12-06 11:01 ` [PATCH v2 1/3] drm/fourcc: Add packed 10bit YUV 4:2:0 format Maxime Ripard
@ 2021-12-06 12:02 ` Dave Stevenson
0 siblings, 0 replies; 6+ messages in thread
From: Dave Stevenson @ 2021-12-06 12:02 UTC (permalink / raw)
To: Maxime Ripard
Cc: Dom Cobley, Tim Gover, David Airlie, DRI Development,
Thomas Zimmermann, Daniel Vetter, Phil Elwell
On Mon, 6 Dec 2021 at 11:01, Maxime Ripard <maxime@cerno.tech> wrote:
>
> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
>
> Adds a format that is 3 10bit YUV 4:2:0 samples packed into
> a 32bit work (with 2 spare bits).
Quite possibly my typo, but
s/work/word
> Supported on Broadcom BCM2711 chips.
>
> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---
> drivers/gpu/drm/drm_fourcc.c | 3 +++
> include/uapi/drm/drm_fourcc.h | 11 +++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 25837b1d6639..07741b678798 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -269,6 +269,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
> .num_planes = 3, .char_per_block = { 2, 2, 2 },
> .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
> .vsub = 0, .is_yuv = true },
> + { .format = DRM_FORMAT_P030, .depth = 0, .num_planes = 2,
> + .char_per_block = { 4, 8, 0 }, .block_w = { 3, 3, 0 }, .block_h = { 1, 1, 0 },
> + .hsub = 2, .vsub = 2, .is_yuv = true},
> };
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 7f652c96845b..fc0c1454d275 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -314,6 +314,13 @@ extern "C" {
> */
> #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
>
> +/* 2 plane YCbCr420.
> + * 3 10 bit components and 2 padding bits packed into 4 bytes.
> + * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
> + * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
> + */
> +#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
> +
> /* 3 plane non-subsampled (444) YCbCr
> * 16 bits per component, but only 10 bits are used and 6 bits are padded
> * index 0: Y plane, [15:0] Y:x [10:6] little endian
> @@ -854,6 +861,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
> * and UV. Some SAND-using hardware stores UV in a separate tiled
> * image from Y to reduce the column height, which is not supported
> * with these modifiers.
> + *
> + * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
> + * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
> + * wide, but as this is a 10 bpp format that translates to 96 pixels.
> */
>
> #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
> --
> 2.33.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/3] drm/vc4: plane: Add support for YUV color encodings and ranges
2021-12-06 11:01 ` [PATCH v2 3/3] drm/vc4: plane: Add support for YUV color encodings and ranges Maxime Ripard
@ 2021-12-06 12:05 ` Dave Stevenson
0 siblings, 0 replies; 6+ messages in thread
From: Dave Stevenson @ 2021-12-06 12:05 UTC (permalink / raw)
To: Maxime Ripard
Cc: Dom Cobley, Tim Gover, Dave Stevenson, David Airlie,
DRI Development, Thomas Zimmermann, Daniel Vetter, Phil Elwell
On Mon, 6 Dec 2021 at 11:02, Maxime Ripard <maxime@cerno.tech> wrote:
>
> From: Dave Stevenson <dave.stevenson@raspberrypi.org>
Minor note that we've changed to raspberrypi.com instead of .org, but
it currently forwards through anyway. The other two patches have the
.com address.
> The BT601/BT709 color encoding and limited vs full
> range properties were not being exposed, defaulting
> always to BT601 limited range.
>
> Expose the parameters and set the registers appropriately.
>
> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---
> drivers/gpu/drm/vc4/vc4_plane.c | 71 +++++++++++++++++++++++++++++++--
> drivers/gpu/drm/vc4/vc4_regs.h | 19 ++++++---
> 2 files changed, 82 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
> index 18627b240a55..1155b0beb620 100644
> --- a/drivers/gpu/drm/vc4/vc4_plane.c
> +++ b/drivers/gpu/drm/vc4/vc4_plane.c
> @@ -623,6 +623,51 @@ static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
> return 0;
> }
>
> +/*
> + * The colorspace conversion matrices are held in 3 entries in the dlist.
> + * Create an array of them, with entries for each full and limited mode, and
> + * each supported colorspace.
> + */
> +static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {
> + {
> + /* Limited range */
> + {
> + /* BT601 */
> + SCALER_CSC0_ITR_R_601_5,
> + SCALER_CSC1_ITR_R_601_5,
> + SCALER_CSC2_ITR_R_601_5,
> + }, {
> + /* BT709 */
> + SCALER_CSC0_ITR_R_709_3,
> + SCALER_CSC1_ITR_R_709_3,
> + SCALER_CSC2_ITR_R_709_3,
> + }, {
> + /* BT2020 */
> + SCALER_CSC0_ITR_R_2020,
> + SCALER_CSC1_ITR_R_2020,
> + SCALER_CSC2_ITR_R_2020,
> + }
> + }, {
> + /* Full range */
> + {
> + /* JFIF */
> + SCALER_CSC0_JPEG_JFIF,
> + SCALER_CSC1_JPEG_JFIF,
> + SCALER_CSC2_JPEG_JFIF,
> + }, {
> + /* BT709 */
> + SCALER_CSC0_ITR_R_709_3_FR,
> + SCALER_CSC1_ITR_R_709_3_FR,
> + SCALER_CSC2_ITR_R_709_3_FR,
> + }, {
> + /* BT2020 */
> + SCALER_CSC0_ITR_R_2020_FR,
> + SCALER_CSC1_ITR_R_2020_FR,
> + SCALER_CSC2_ITR_R_2020_FR,
> + }
> + }
> +};
> +
> /* Writes out a full display list for an active plane to the plane's
> * private dlist state.
> */
> @@ -1018,9 +1063,20 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
>
> /* Colorspace conversion words */
> if (vc4_state->is_yuv) {
> - vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
> - vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
> - vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
> + enum drm_color_encoding color_encoding = state->color_encoding;
> + enum drm_color_range color_range = state->color_range;
> + const u32 *ccm;
> +
> + if (color_encoding >= DRM_COLOR_ENCODING_MAX)
> + color_encoding = DRM_COLOR_YCBCR_BT601;
> + if (color_range >= DRM_COLOR_RANGE_MAX)
> + color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
> +
> + ccm = colorspace_coeffs[color_range][color_encoding];
> +
> + vc4_dlist_write(vc4_state, ccm[0]);
> + vc4_dlist_write(vc4_state, ccm[1]);
> + vc4_dlist_write(vc4_state, ccm[2]);
> }
>
> vc4_state->lbm_offset = 0;
> @@ -1449,6 +1505,15 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
> DRM_MODE_REFLECT_X |
> DRM_MODE_REFLECT_Y);
>
> + drm_plane_create_color_properties(plane,
> + BIT(DRM_COLOR_YCBCR_BT601) |
> + BIT(DRM_COLOR_YCBCR_BT709) |
> + BIT(DRM_COLOR_YCBCR_BT2020),
> + BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
> + BIT(DRM_COLOR_YCBCR_FULL_RANGE),
> + DRM_COLOR_YCBCR_BT709,
> + DRM_COLOR_YCBCR_LIMITED_RANGE);
> +
> return plane;
> }
>
> diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
> index 489f921ef44d..7538b84a6dca 100644
> --- a/drivers/gpu/drm/vc4/vc4_regs.h
> +++ b/drivers/gpu/drm/vc4/vc4_regs.h
> @@ -975,7 +975,10 @@ enum hvs_pixel_format {
> #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
> #define SCALER_CSC0_ITR_R_601_5 0x00f00000
> #define SCALER_CSC0_ITR_R_709_3 0x00f00000
> +#define SCALER_CSC0_ITR_R_2020 0x00f00000
> #define SCALER_CSC0_JPEG_JFIF 0x00000000
> +#define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
> +#define SCALER_CSC0_ITR_R_2020_FR 0x00000000
>
> /* S2.8 contribution of Cb to Green */
> #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
> @@ -990,8 +993,11 @@ enum hvs_pixel_format {
> #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
> #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
> #define SCALER_CSC1_ITR_R_601_5 0xe73304a8
> -#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
> -#define SCALER_CSC1_JPEG_JFIF 0xea34a400
> +#define SCALER_CSC1_ITR_R_709_3 0xf27784a8
> +#define SCALER_CSC1_ITR_R_2020 0xf43594a8
> +#define SCALER_CSC1_JPEG_JFIF 0xea349400
> +#define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400
> +#define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400
>
> /* S2.8 contribution of Cb to Red */
> #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
> @@ -1002,9 +1008,12 @@ enum hvs_pixel_format {
> /* S2.8 contribution of Cb to Blue */
> #define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
> #define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
> -#define SCALER_CSC2_ITR_R_601_5 0x00066204
> -#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
> -#define SCALER_CSC2_JPEG_JFIF 0x000599c5
> +#define SCALER_CSC2_ITR_R_601_5 0x00066604
> +#define SCALER_CSC2_ITR_R_709_3 0x00072e1d
> +#define SCALER_CSC2_ITR_R_2020 0x0006b624
> +#define SCALER_CSC2_JPEG_JFIF 0x00059dc6
> +#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
> +#define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2
>
> #define SCALER_TPZ0_VERT_RECALC BIT(31)
> #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
> --
> 2.33.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-12-06 12:05 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-06 11:01 [PATCH v2 0/3] drm/vc4: Support for 30 bits YUV formats Maxime Ripard
2021-12-06 11:01 ` [PATCH v2 1/3] drm/fourcc: Add packed 10bit YUV 4:2:0 format Maxime Ripard
2021-12-06 12:02 ` Dave Stevenson
2021-12-06 11:01 ` [PATCH v2 2/3] drm/vc4: plane: Add support for DRM_FORMAT_P030 Maxime Ripard
2021-12-06 11:01 ` [PATCH v2 3/3] drm/vc4: plane: Add support for YUV color encodings and ranges Maxime Ripard
2021-12-06 12:05 ` Dave Stevenson
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