* [PATCH] drm/msm: Fix range size vs end confusion
@ 2022-04-07 20:28 Rob Clark
2022-04-08 12:21 ` Dmitry Baryshkov
0 siblings, 1 reply; 2+ messages in thread
From: Rob Clark @ 2022-04-07 20:28 UTC (permalink / raw)
To: dri-devel
Cc: Rob Clark, Jonathan Marek, Akhil P Oommen, David Airlie,
linux-arm-msm, Abhinav Kumar, Jordan Crouse, Sean Paul,
Dmitry Baryshkov, freedreno, open list
From: Rob Clark <robdclark@chromium.org>
The fourth param is size, rather than range_end.
Note that we could increase the address space size if we had a way to
prevent buffers from spanning a 4G split, mostly just to avoid fw bugs
with 64b math.
Fixes: 84c31ee16f90 ("drm/msm/a6xx: Add support for per-instance pagetables")
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 17de46fc4bf2..80d57608b34a 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1742,7 +1742,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu)
return ERR_CAST(mmu);
return msm_gem_address_space_create(mmu,
- "gpu", 0x100000000ULL, 0x1ffffffffULL);
+ "gpu", 0x100000000ULL, SZ_4G);
}
static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
--
2.35.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/msm: Fix range size vs end confusion
2022-04-07 20:28 [PATCH] drm/msm: Fix range size vs end confusion Rob Clark
@ 2022-04-08 12:21 ` Dmitry Baryshkov
0 siblings, 0 replies; 2+ messages in thread
From: Dmitry Baryshkov @ 2022-04-08 12:21 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, freedreno, Jonathan Marek, David Airlie,
linux-arm-msm, Abhinav Kumar, dri-devel, Jordan Crouse,
Akhil P Oommen, Sean Paul, open list
On Thu, 7 Apr 2022 at 23:27, Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> The fourth param is size, rather than range_end.
>
> Note that we could increase the address space size if we had a way to
> prevent buffers from spanning a 4G split, mostly just to avoid fw bugs
> with 64b math.
>
> Fixes: 84c31ee16f90 ("drm/msm/a6xx: Add support for per-instance pagetables")
> Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 17de46fc4bf2..80d57608b34a 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1742,7 +1742,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu)
> return ERR_CAST(mmu);
>
> return msm_gem_address_space_create(mmu,
> - "gpu", 0x100000000ULL, 0x1ffffffffULL);
> + "gpu", 0x100000000ULL, SZ_4G);
> }
>
> static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
> --
> 2.35.1
>
--
With best wishes
Dmitry
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