[PATCH v0.5 0/9] i.MX8MP HDMI support

[PATCH v0.5 0/9] i.MX8MP HDMI support

[Lucas Stach]

Hi all,

second round of the i.MX8MP HDMI work. Still not split up into proper
parts for merging through the various trees this needs to go into, but
should make it easy for people to test.

I've worked in the feedback I got from the last round, including fixing
the system hang that could happen when the drivers were built as modules.

Series is based on linux-next/master, as there are some prerequisite
patches in both the drm and imx tree already. The last patch from [1]
and the patches from [2] need to be applied. Please note that this series
expects the sync polarity from the LCDIF to be set according to the
comments I made in [2]. Please test and provide feedback.

Regards,
Lucas

[1] https://lore.kernel.org/all/20220406153402.1265474-1-l.stach@pengutronix.de/
[2] https://lore.kernel.org/all/20220322142853.125880-1-marex@denx.de/

Lucas Stach (9):
  dt-bindings: display: imx: add binding for i.MX8MP HDMI TX
  drm/imx: add bridge wrapper driver for i.MX8MP DWC HDMI
  dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI
  drm/imx: add driver for HDMI TX Parallel Video Interface
  dt-bindings: phy: add binding for the i.MX8MP HDMI PHY
  phy: freescale: add Samsung HDMI PHY
  arm64: dts: imx8mp: add HDMI irqsteer
  arm64: dts: imx8mp: add HDMI display pipeline
  arm64: dts: imx8mp-evk: enable HDMI

 .../display/imx/fsl,imx8mp-hdmi-pvi.yaml      |   83 ++
 .../bindings/display/imx/fsl,imx8mp-hdmi.yaml |   73 ++
 .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml     |   62 +
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts  |   19 +
 arch/arm64/boot/dts/freescale/imx8mp.dtsi     |   94 ++
 drivers/gpu/drm/imx/Kconfig                   |    1 +
 drivers/gpu/drm/imx/Makefile                  |    2 +
 drivers/gpu/drm/imx/bridge/Kconfig            |   18 +
 drivers/gpu/drm/imx/bridge/Makefile           |    4 +
 drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c     |  201 +++
 drivers/gpu/drm/imx/bridge/imx-hdmi.c         |  141 +++
 drivers/phy/freescale/Kconfig                 |    6 +
 drivers/phy/freescale/Makefile                |    1 +
 drivers/phy/freescale/phy-fsl-samsung-hdmi.c  | 1078 +++++++++++++++++
 14 files changed, 1783 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
 create mode 100644 drivers/gpu/drm/imx/bridge/Kconfig
 create mode 100644 drivers/gpu/drm/imx/bridge/Makefile
 create mode 100644 drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c
 create mode 100644 drivers/gpu/drm/imx/bridge/imx-hdmi.c
 create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c

-- 
2.30.2

[PATCH v0.5 1/9] dt-bindings: display: imx: add binding for i.MX8MP HDMI TX

[Lucas Stach]

The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
core with a little bit of SoC integration around it.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../bindings/display/imx/fsl,imx8mp-hdmi.yaml | 73 +++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
new file mode 100644
index 000000000000..bd9a2b135176
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8MP DWC HDMI TX Encoder
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description: |
+  The HDMI transmitter is a Synopsys DesignWare HDMI 2.0 TX controller IP.
+
+allOf:
+  - $ref: ../bridge/synopsys,dw-hdmi.yaml#
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8mp-hdmi
+
+  reg:
+    maxItems: 1
+
+  reg-io-width:
+    const: 1
+
+  clocks:
+    maxItems: 5
+
+  clock-names:
+    items:
+      - {}
+      - {}
+      - const: cec
+      - const: pix
+      - const: fdcc 
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/power/imx8mp-power.h>
+
+    hdmi@32fd8000 {
+        compatible = "fsl,imx8mp-hdmi";
+        reg = <0x32fd8000 0x7eff>;
+        interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+                 <&clk IMX8MP_CLK_HDMI_REF_266M>,
+                 <&clk IMX8MP_CLK_32K>,
+                 <&hdmi_tx_phy>;
+        clock-names = "iahb", "isfr", "cec", "pix";
+        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
+        reg-io-width = <1>;
+    };
-- 
2.30.2

Re: [PATCH v0.5 1/9] dt-bindings: display: imx: add binding for i.MX8MP HDMI TX

[Rob Herring]

On Fri, 06 May 2022 20:10:26 +0200, Lucas Stach wrote:
> The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
> core with a little bit of SoC integration around it.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../bindings/display/imx/fsl,imx8mp-hdmi.yaml | 73 +++++++++++++++++++
>  1 file changed, 73 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.example.dts:36.45-46 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1401: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH v0.5 1/9] dt-bindings: display: imx: add binding for i.MX8MP HDMI TX

[Marek Vasut]

On 5/6/22 20:10, Lucas Stach wrote:
> The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
> core with a little bit of SoC integration around it.

You can add

Tested-by: Marek Vasut <marex@denx.de>

to the entire series.

Re: [PATCH v0.5 1/9] dt-bindings: display: imx: add binding for i.MX8MP HDMI TX

[Rob Herring]

On Fri, May 06, 2022 at 08:10:26PM +0200, Lucas Stach wrote:
> The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
> core with a little bit of SoC integration around it.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../bindings/display/imx/fsl,imx8mp-hdmi.yaml | 73 +++++++++++++++++++
>  1 file changed, 73 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
> new file mode 100644
> index 000000000000..bd9a2b135176
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8MP DWC HDMI TX Encoder
> +
> +maintainers:
> +  - Lucas Stach <l.stach@pengutronix.de>
> +
> +description: |
> +  The HDMI transmitter is a Synopsys DesignWare HDMI 2.0 TX controller IP.
> +
> +allOf:
> +  - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx8mp-hdmi
> +
> +  reg:
> +    maxItems: 1
> +
> +  reg-io-width:
> +    const: 1
> +
> +  clocks:
> +    maxItems: 5
> +
> +  clock-names:
> +    items:
> +      - {}
> +      - {}
> +      - const: cec
> +      - const: pix
> +      - const: fdcc 
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/clock/imx8mp-clock.h>
> +    #include <dt-bindings/power/imx8mp-power.h>
> +
> +    hdmi@32fd8000 {
> +        compatible = "fsl,imx8mp-hdmi";
> +        reg = <0x32fd8000 0x7eff>;
> +        interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
> +                 <&clk IMX8MP_CLK_HDMI_REF_266M>,
> +                 <&clk IMX8MP_CLK_32K>,
> +                 <&hdmi_tx_phy>;
> +        clock-names = "iahb", "isfr", "cec", "pix";

The schema says there are 5 entries.

> +        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
> +        reg-io-width = <1>;
> +    };
> -- 
> 2.30.2
> 
> 

[PATCH v0.5 2/9] drm/imx: add bridge wrapper driver for i.MX8MP DWC HDMI

[Lucas Stach]

Add a simple wrapper driver for the DWC HDMI bridge driver that
implements the few bits that are necessary to abstract the i.MX8MP
SoC integration.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/gpu/drm/imx/Kconfig           |   1 +
 drivers/gpu/drm/imx/Makefile          |   2 +
 drivers/gpu/drm/imx/bridge/Kconfig    |  10 ++
 drivers/gpu/drm/imx/bridge/Makefile   |   3 +
 drivers/gpu/drm/imx/bridge/imx-hdmi.c | 141 ++++++++++++++++++++++++++
 5 files changed, 157 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/bridge/Kconfig
 create mode 100644 drivers/gpu/drm/imx/bridge/Makefile
 create mode 100644 drivers/gpu/drm/imx/bridge/imx-hdmi.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index bb9738c7c825..88b054c095c6 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -42,3 +42,4 @@ config DRM_IMX_HDMI
 	  Choose this if you want to use HDMI on i.MX6.
 
 source "drivers/gpu/drm/imx/dcss/Kconfig"
+source "drivers/gpu/drm/imx/bridge/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index b644deffe948..861403d11af6 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -10,3 +10,5 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
 obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
+
+obj-y += bridge/
diff --git a/drivers/gpu/drm/imx/bridge/Kconfig b/drivers/gpu/drm/imx/bridge/Kconfig
new file mode 100644
index 000000000000..d63a09ca63dd
--- /dev/null
+++ b/drivers/gpu/drm/imx/bridge/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config DRM_IMX_DW_HDMI_BRIDGE
+	tristate "i.MX8MP HDMI bridge support"
+	depends on (ARCH_MXC && ARM64) || COMPILE_TEST
+	depends on DRM && OF
+	select DRM_DW_HDMI
+	help
+	  Enable support for the internal HDMI encoder on i.MX8MP SoC
+
diff --git a/drivers/gpu/drm/imx/bridge/Makefile b/drivers/gpu/drm/imx/bridge/Makefile
new file mode 100644
index 000000000000..1cfe9623c0d8
--- /dev/null
+++ b/drivers/gpu/drm/imx/bridge/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_DRM_IMX_DW_HDMI_BRIDGE)	+= imx-hdmi.o
diff --git a/drivers/gpu/drm/imx/bridge/imx-hdmi.c b/drivers/gpu/drm/imx/bridge/imx-hdmi.c
new file mode 100644
index 000000000000..66089bc690c8
--- /dev/null
+++ b/drivers/gpu/drm/imx/bridge/imx-hdmi.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <drm/bridge/dw_hdmi.h>
+#include <drm/drm_modes.h>
+#include <linux/clk.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+struct imx_hdmi {
+	struct dw_hdmi_plat_data plat_data;
+	struct dw_hdmi *dw_hdmi;
+	struct clk *pixclk;
+	struct clk *fdcc;
+};
+
+static enum drm_mode_status
+imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
+		       const struct drm_display_info *info,
+		       const struct drm_display_mode *mode)
+{
+	struct imx_hdmi *hdmi = (struct imx_hdmi *)data;
+
+	if (mode->clock < 13500)
+		return MODE_CLOCK_LOW;
+
+	if (mode->clock > 297000)
+		return MODE_CLOCK_HIGH;
+
+	if (clk_round_rate(hdmi->pixclk, mode->clock * 1000) !=
+	    mode->clock * 1000)
+		return MODE_CLOCK_RANGE;
+
+	/* We don't support double-clocked and Interlaced modes */
+	if ((mode->flags & DRM_MODE_FLAG_DBLCLK) ||
+	    (mode->flags & DRM_MODE_FLAG_INTERLACE))
+		return MODE_BAD;
+
+	return MODE_OK;
+}
+
+static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data,
+				const struct drm_display_info *display,
+				const struct drm_display_mode *mode)
+{
+	return 0;
+}
+
+static void imx8mp_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void *data)
+{
+}
+
+static const struct dw_hdmi_phy_ops imx8mp_hdmi_phy_ops = {
+	.init		= imx8mp_hdmi_phy_init,
+	.disable	= imx8mp_hdmi_phy_disable,
+	.read_hpd	= dw_hdmi_phy_read_hpd,
+	.update_hpd	= dw_hdmi_phy_update_hpd,
+	.setup_hpd	= dw_hdmi_phy_setup_hpd,
+};
+
+static int imx_dw_hdmi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct dw_hdmi_plat_data *plat_data;
+	struct imx_hdmi *hdmi;
+	int ret;
+
+	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
+	if (!hdmi)
+		return -ENOMEM;
+
+	plat_data = &hdmi->plat_data;
+
+	hdmi->pixclk = devm_clk_get(dev, "pix");
+	if (IS_ERR(hdmi->pixclk))
+		return dev_err_probe(dev, PTR_ERR(hdmi->pixclk),
+				     "Unable to get pixel clock\n");
+
+	hdmi->fdcc = devm_clk_get(dev, "fdcc");
+	if (IS_ERR(hdmi->fdcc))
+		return dev_err_probe(dev, PTR_ERR(hdmi->fdcc),
+				     "Unable to get FDCC clock\n");
+
+	ret = clk_prepare_enable(hdmi->fdcc);
+	if (ret)
+		return dev_err_probe(dev, ret, "Unable to enable FDCC clock\n");
+
+	plat_data->mode_valid = imx8mp_hdmi_mode_valid;
+	plat_data->phy_ops = &imx8mp_hdmi_phy_ops;
+	plat_data->phy_name = "SAMSUNG HDMI TX PHY";
+	plat_data->priv_data = hdmi;
+
+	hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data);
+	if (IS_ERR(hdmi->dw_hdmi))
+		return PTR_ERR(hdmi->dw_hdmi);
+
+	/*
+	 * Just release PHY core from reset, all other power management is done
+	 * by the PHY driver.
+	 */
+	dw_hdmi_phy_gen1_reset(hdmi->dw_hdmi);
+
+	platform_set_drvdata(pdev, hdmi);
+
+	return 0;
+}
+
+static int imx_dw_hdmi_remove(struct platform_device *pdev)
+{
+	struct imx_hdmi *hdmi = platform_get_drvdata(pdev);
+
+	dw_hdmi_remove(hdmi->dw_hdmi);
+
+	clk_disable_unprepare(hdmi->fdcc);
+
+	return 0;
+}
+
+static const struct of_device_id imx_dw_hdmi_of_table[] = {
+	{ .compatible = "fsl,imx8mp-hdmi" },
+	{ /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx_dw_hdmi_of_table);
+
+static struct platform_driver im_dw_hdmi_platform_driver = {
+	.probe		= imx_dw_hdmi_probe,
+	.remove		= imx_dw_hdmi_remove,
+	.driver		= {
+		.name	= "imx-dw-hdmi",
+		.of_match_table = imx_dw_hdmi_of_table,
+	},
+};
+
+module_platform_driver(im_dw_hdmi_platform_driver);
+
+MODULE_DESCRIPTION("i.MX8M HDMI encoder driver");
+MODULE_LICENSE("GPL");
-- 
2.30.2

[PATCH v0.5 3/9] dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI

[Lucas Stach]

Add binding for the i.MX8MP HDMI parallel video interface block.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../display/imx/fsl,imx8mp-hdmi-pvi.yaml      | 83 +++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
new file mode 100644
index 000000000000..bf25d29c03ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8MP HDMI Parallel Video Interface
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+description: |
+  The HDMI parallel video interface is timing and sync generator block in the
+  i.MX8MP SoC, that sits between the video source and the HDMI TX controller.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8mp-hdmi-pvi
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description: |
+      This device has two video ports.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Input from the LCDIF controller.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Output to the HDMI TX controller
+
+    anyOf:
+      - required:
+          - port@0
+      - required:
+          - port@1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/power/imx8mp-power.h>
+
+    display-bridge@32fc4000 {
+        compatible = "fsl,imx8mp-hdmi-pvi";
+        reg = <0x32fc4000 0x40>;
+        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                pvi_from_lcdif3: endpoint {
+                    remote-endpoint = <&lcdif3_to_pvi>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                pvi_to_hdmi_tx: endpoint {
+                    remote-endpoint = <&hdmi_tx_from_pvi>;
+                };
+            };
+        };
+    };
-- 
2.30.2

Re: [PATCH v0.5 3/9] dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI

[Rob Herring]

On Fri, 06 May 2022 20:10:28 +0200, Lucas Stach wrote:
> Add binding for the i.MX8MP HDMI parallel video interface block.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../display/imx/fsl,imx8mp-hdmi-pvi.yaml      | 83 +++++++++++++++++++
>  1 file changed, 83 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.example.dts:26.45-46 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1401: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

[PATCH v0.5 4/9] drm/imx: add driver for HDMI TX Parallel Video Interface

[Lucas Stach]

This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a
full timing generator and can switch between different video sources. On
the i.MX8MP however the only supported source is the LCDIF. The block
just needs to be powered up and told about the polarity of the video
sync signals to act in bypass mode.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/gpu/drm/imx/bridge/Kconfig        |   8 +
 drivers/gpu/drm/imx/bridge/Makefile       |   1 +
 drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c | 201 ++++++++++++++++++++++
 3 files changed, 210 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c

diff --git a/drivers/gpu/drm/imx/bridge/Kconfig b/drivers/gpu/drm/imx/bridge/Kconfig
index d63a09ca63dd..1f74f73c790e 100644
--- a/drivers/gpu/drm/imx/bridge/Kconfig
+++ b/drivers/gpu/drm/imx/bridge/Kconfig
@@ -8,3 +8,11 @@ config DRM_IMX_DW_HDMI_BRIDGE
 	help
 	  Enable support for the internal HDMI encoder on i.MX8MP SoC
 
+config DRM_IMX_HDMI_PVI
+	tristate "i.MX8MP HDMI PVI bridge support"
+	depends on (ARCH_MXC && ARM64) || COMPILE_TEST
+	depends on DRM && OF
+	help
+	  Enable support for the internal HDMI TX Parallel Video Interface
+	  found on the i.MX8MP SoC.
+
diff --git a/drivers/gpu/drm/imx/bridge/Makefile b/drivers/gpu/drm/imx/bridge/Makefile
index 1cfe9623c0d8..512ea98722b8 100644
--- a/drivers/gpu/drm/imx/bridge/Makefile
+++ b/drivers/gpu/drm/imx/bridge/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 
 obj-$(CONFIG_DRM_IMX_DW_HDMI_BRIDGE)	+= imx-hdmi.o
+obj-$(CONFIG_DRM_IMX_HDMI_PVI)		+= imx-hdmi-pvi.o
diff --git a/drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c b/drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c
new file mode 100644
index 000000000000..962779dc539e
--- /dev/null
+++ b/drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_crtc.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/pm_runtime.h>
+
+#define HTX_PVI_CTL	0x0
+#define  PVI_CTL_OP_VSYNC_POL	BIT(18)
+#define  PVI_CTL_OP_HSYNC_POL	BIT(17)
+#define  PVI_CTL_OP_DE_POL	BIT(16)
+#define  PVI_CTL_INP_VSYNC_POL	BIT(14)
+#define  PVI_CTL_INP_HSYNC_POL	BIT(13)
+#define  PVI_CTL_INP_DE_POL	BIT(12)
+#define  PVI_CTL_INPUT_LCDIF	BIT(2)
+#define  PVI_CTL_EN		BIT(0)
+
+struct imx_hdmi_pvi {
+	struct drm_bridge	bridge;
+	struct device		*dev;
+	struct drm_bridge	*next_bridge;
+	void __iomem		*regs;
+};
+
+static inline struct imx_hdmi_pvi *
+to_imx_hdmi_pvi(struct drm_bridge *bridge)
+{
+	return container_of(bridge, struct imx_hdmi_pvi, bridge);
+}
+
+static int imx_hdmi_pvi_bridge_attach(struct drm_bridge *bridge,
+				enum drm_bridge_attach_flags flags)
+{
+	struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge);
+
+	return drm_bridge_attach(bridge->encoder, pvi->next_bridge, bridge, flags);
+}
+
+static void imx_hdmi_pvi_bridge_enable(struct drm_bridge *bridge,
+				       struct drm_bridge_state *bridge_state)
+{
+	struct drm_atomic_state *state = bridge_state->base.state;
+	struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge);
+	struct drm_connector_state *conn_state;
+	const struct drm_display_mode *mode;
+	struct drm_crtc_state *crtc_state;
+	struct drm_connector *connector;
+	u32 bus_flags, val;
+
+	connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
+	conn_state = drm_atomic_get_new_connector_state(state, connector);
+	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
+
+	if (WARN_ON(pm_runtime_resume_and_get(pvi->dev)))
+		return;
+
+	mode = &crtc_state->adjusted_mode;
+
+	val = PVI_CTL_INPUT_LCDIF;
+
+	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
+		val |= PVI_CTL_OP_VSYNC_POL | PVI_CTL_INP_VSYNC_POL;
+
+	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
+		val |= PVI_CTL_OP_HSYNC_POL | PVI_CTL_INP_HSYNC_POL;
+
+	if (pvi->next_bridge->timings)
+		bus_flags = pvi->next_bridge->timings->input_bus_flags;
+	else if (bridge_state)
+		bus_flags = bridge_state->input_bus_cfg.flags;
+
+	if (bus_flags & DRM_BUS_FLAG_DE_HIGH)
+		val |= PVI_CTL_OP_DE_POL | PVI_CTL_INP_DE_POL;
+
+	writel(val, pvi->regs + HTX_PVI_CTL);
+	val |= PVI_CTL_EN;
+	writel(val, pvi->regs + HTX_PVI_CTL);
+}
+
+static void imx_hdmi_pvi_bridge_disable(struct drm_bridge *bridge,
+					struct drm_bridge_state *bridge_state)
+{
+	struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge);
+
+	writel(0x0, pvi->regs + HTX_PVI_CTL);
+
+	pm_runtime_put(pvi->dev);
+}
+
+static u32 *pvi_bridge_get_input_bus_fmts(struct drm_bridge *bridge,
+					  struct drm_bridge_state *bridge_state,
+					  struct drm_crtc_state *crtc_state,
+					  struct drm_connector_state *conn_state,
+					  u32 output_fmt,
+					  unsigned int *num_input_fmts)
+{
+	struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge);
+	struct drm_bridge *next_bridge = pvi->next_bridge;
+	struct drm_bridge_state *next_state;
+
+	if (!next_bridge->funcs->atomic_get_input_bus_fmts)
+		return 0;
+
+	next_state = drm_atomic_get_new_bridge_state(crtc_state->state,
+						     next_bridge);
+
+	return next_bridge->funcs->atomic_get_input_bus_fmts(next_bridge,
+							     next_state,
+							     crtc_state,
+							     conn_state,
+							     output_fmt,
+							     num_input_fmts);
+}
+
+static const struct drm_bridge_funcs imx_hdmi_pvi_bridge_funcs = {
+	.attach		= imx_hdmi_pvi_bridge_attach,
+	.atomic_enable	= imx_hdmi_pvi_bridge_enable,
+	.atomic_disable	= imx_hdmi_pvi_bridge_disable,
+	.atomic_get_input_bus_fmts = pvi_bridge_get_input_bus_fmts,
+	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+	.atomic_reset = drm_atomic_helper_bridge_reset,
+};
+
+static int imx_hdmi_pvi_probe(struct platform_device *pdev)
+{
+	struct device_node *remote;
+	struct imx_hdmi_pvi *pvi;
+
+	pvi = devm_kzalloc(&pdev->dev, sizeof(*pvi), GFP_KERNEL);
+	if (!pvi)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, pvi);
+	pvi->dev = &pdev->dev;
+
+	pvi->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(pvi->regs))
+		return PTR_ERR(pvi->regs);
+
+	/* Get the next bridge in the pipeline. */
+	remote = of_graph_get_remote_node(pdev->dev.of_node, 1, -1);
+	if (!remote)
+		return -EINVAL;
+
+	pvi->next_bridge = of_drm_find_bridge(remote);
+	of_node_put(remote);
+
+	if (!pvi->next_bridge)
+		return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
+				     "could not find next bridge\n");
+
+	/* Register the bridge. */
+	pvi->bridge.funcs = &imx_hdmi_pvi_bridge_funcs;
+	pvi->bridge.of_node = pdev->dev.of_node;
+	pvi->bridge.timings = pvi->next_bridge->timings;
+
+	drm_bridge_add(&pvi->bridge);
+
+	pm_runtime_enable(&pdev->dev);
+
+	return 0;
+}
+
+static int imx_hdmi_pvi_remove(struct platform_device *pdev)
+{
+	struct imx_hdmi_pvi *pvi = platform_get_drvdata(pdev);
+
+	drm_bridge_remove(&pvi->bridge);
+
+	return 0;
+}
+
+static const struct of_device_id imx_hdmi_pvi_match[] = {
+	{
+		.compatible = "fsl,imx8mp-hdmi-pvi",
+	}, {
+		/* sentinel */
+	},
+};
+MODULE_DEVICE_TABLE(of, imx_hdmi_pvi_match);
+
+static struct platform_driver imx_hdmi_pvi_driver = {
+	.probe	= imx_hdmi_pvi_probe,
+	.remove	= imx_hdmi_pvi_remove,
+	.driver		= {
+		.name = "imx-hdmi-pvi",
+		.of_match_table	= imx_hdmi_pvi_match,
+	},
+};
+module_platform_driver(imx_hdmi_pvi_driver);
+
+MODULE_DESCRIPTION("i.MX8MP HDMI TX Parallel Video Interface bridge driver");
+MODULE_LICENSE("GPL");
-- 
2.30.2

[PATCH v0.5 5/9] dt-bindings: phy: add binding for the i.MX8MP HDMI PHY

[Lucas Stach]

Add a DT binding for the HDMI PHY found on the i.MX8MP SoC.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml     | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
new file mode 100644
index 000000000000..bc21c073e92a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8MP HDMI PHY binding
+
+maintainers:
+  - Lucas Stach <l.stach@pengutronix.de>
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8mp-hdmi-phy
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 0
+
+  clocks:
+    minItems: 2
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: apb
+      - const: ref
+
+  "#phy-cells":
+    const: 0
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clocks
+  - clock-names
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/power/imx8mp-power.h>
+
+    phy@32fdff00 {
+        compatible = "fsl,imx8mp-hdmi-phy";
+        reg = <0x32fdff00 0x100>;
+        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+                 <&clk IMX8MP_CLK_HDMI_24M>;
+        clock-names = "apb", "ref";
+        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
+        #clock-cells = <0>;
+        #phy-cells = <0>;
+    };
-- 
2.30.2

Re: [PATCH v0.5 5/9] dt-bindings: phy: add binding for the i.MX8MP HDMI PHY

[Rob Herring]

On Fri, 06 May 2022 20:10:30 +0200, Lucas Stach wrote:
> Add a DT binding for the HDMI PHY found on the i.MX8MP SoC.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml     | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.example.dts:29.45-46 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1401: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH v0.5 5/9] dt-bindings: phy: add binding for the i.MX8MP HDMI PHY

[Rob Herring]

On Fri, May 06, 2022 at 08:10:30PM +0200, Lucas Stach wrote:
> Add a DT binding for the HDMI PHY found on the i.MX8MP SoC.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml     | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
> new file mode 100644
> index 000000000000..bc21c073e92a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8MP HDMI PHY binding
> +
> +maintainers:
> +  - Lucas Stach <l.stach@pengutronix.de>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx8mp-hdmi-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#clock-cells":
> +    const: 0
> +
> +  clocks:
> +    minItems: 2
> +    maxItems: 2
> +
> +  clock-names:
> +    items:
> +      - const: apb
> +      - const: ref
> +
> +  "#phy-cells":
> +    const: 0
> +
> +  power-domains:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"
> +  - clocks
> +  - clock-names
> +  - power-domains

#phy-cells should be required.

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/imx8mp-clock.h>
> +    #include <dt-bindings/power/imx8mp-power.h>
> +
> +    phy@32fdff00 {
> +        compatible = "fsl,imx8mp-hdmi-phy";
> +        reg = <0x32fdff00 0x100>;
> +        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
> +                 <&clk IMX8MP_CLK_HDMI_24M>;
> +        clock-names = "apb", "ref";
> +        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
> +        #clock-cells = <0>;
> +        #phy-cells = <0>;
> +    };
> -- 
> 2.30.2
> 
> 

[PATCH v0.5 6/9] phy: freescale: add Samsung HDMI PHY

[Lucas Stach]

This adds the driver for the Samsung HDMI PHY found on the
i.MX8MP SoC.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/phy/freescale/Kconfig                |    6 +
 drivers/phy/freescale/Makefile               |    1 +
 drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 1078 ++++++++++++++++++
 3 files changed, 1085 insertions(+)
 create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c

diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
index f9c54cd02036..e88cc2212370 100644
--- a/drivers/phy/freescale/Kconfig
+++ b/drivers/phy/freescale/Kconfig
@@ -26,6 +26,12 @@ config PHY_FSL_IMX8M_PCIE
 	  Enable this to add support for the PCIE PHY as found on
 	  i.MX8M family of SOCs.
 
+config PHY_FSL_SAMSUNG_HDMI_PHY
+	tristate "Samsung HDMI PHY support"
+	depends on OF && HAS_IOMEM
+	help
+	  Enable this to add support for the Samsung HDMI PHY in i.MX8MP.
+
 endif
 
 config PHY_FSL_LYNX_28G
diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
index 3518d5dbe8a7..46a26929376d 100644
--- a/drivers/phy/freescale/Makefile
+++ b/drivers/phy/freescale/Makefile
@@ -2,4 +2,5 @@
 obj-$(CONFIG_PHY_FSL_IMX8MQ_USB)	+= phy-fsl-imx8mq-usb.o
 obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)	+= phy-fsl-imx8-mipi-dphy.o
 obj-$(CONFIG_PHY_FSL_IMX8M_PCIE)	+= phy-fsl-imx8m-pcie.o
+obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY)  += phy-fsl-samsung-hdmi.o
 obj-$(CONFIG_PHY_FSL_LYNX_28G)		+= phy-fsl-lynx-28g.o
diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
new file mode 100644
index 000000000000..6d20a5ce44e6
--- /dev/null
+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
@@ -0,0 +1,1078 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#define HDMI_TX_CONTROL0		0x200
+#define  HDMI_TX_CONTROL_PHY_PWRDWN	BIT(3)
+
+#define PHY_REG_33		0x84
+#define  REG33_MODE_SET_DONE	BIT(7)
+#define  REG33_FIX_DA		BIT(1)
+
+#define PHY_REG_34		0x88
+#define  REG34_PHY_READY	BIT(7)
+#define  REG34_PLL_LOCK		BIT(6)
+#define  REG34_PHY_CLK_READY	BIT(5)
+
+
+#define PHY_PLL_REGS_NUM 48
+
+struct phy_config {
+	u32	clk_rate;
+	u8 regs[PHY_PLL_REGS_NUM];
+};
+
+const struct phy_config phy_pll_cfg[] = {
+	{	22250000, {
+			0x00, 0xD1, 0x4B, 0xF1, 0x89, 0x88, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x00, 0x15, 0x25, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		23750000, {
+			0x00, 0xD1, 0x50, 0xF1, 0x86, 0x85, 0x80, 0x40,
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+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		70000000, {
+			0x00, 0xD1, 0x58, 0x58, 0x8B, 0x88, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0xB0, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		72000000, {
+			0x00, 0xD1, 0x5A, 0x50, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0xAB, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		72072000, {
+			0x00, 0xD1, 0x5A, 0x52, 0xFD, 0x0C, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0xAB, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		74176000, {
+			0x00, 0xD1, 0x5D, 0x58, 0xDB, 0xA2, 0x88, 0x41,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0xA6, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		74250000, {
+			0x00, 0xD1, 0x5C, 0x52, 0x90, 0x0D, 0x84, 0x41,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0xA6, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		78500000, {
+			0x00, 0xD1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x9D, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		80000000, {
+			0x00, 0xD1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x9A, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		82000000, {
+			0x00, 0xD1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x96, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		82500000, {
+			0x00, 0xD1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x95, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		89000000, {
+			0x00, 0xD1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x8B, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		90000000, {
+			0x00, 0xD1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x89, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x85, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		94000000, {
+			0x00, 0xD1, 0x4E, 0x32, 0xA7, 0x10, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x83, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		95000000, {
+			0x00, 0xD1, 0x50, 0x31, 0x86, 0x85, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x82, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		98901099, {
+			0x00, 0xD1, 0x52, 0x3A, 0xDB, 0x4C, 0x88, 0x47,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x7D, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		99000000, {
+			0x00, 0xD1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47,
+			0x4F, 0x30, 0x33, 0x65, 0x10, 0x7D, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		100699300, {
+			0x00, 0xD1, 0x54, 0x3C, 0xC3, 0x8F, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xF5, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		100800000, {
+			0x00, 0xD1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xF4, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		102500000, {
+			0x00, 0xD1, 0x55, 0x32, 0x8C, 0x05, 0x90, 0x4B,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xF0, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		104750000, {
+			0x00, 0xD1, 0x57, 0x32, 0x98, 0x07, 0x90, 0x49,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xEB, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		106500000, {
+			0x00, 0xD1, 0x58, 0x32, 0x84, 0x03, 0x82, 0x41,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xE7, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		107000000, {
+			0x00, 0xD1, 0x5A, 0x32, 0x89, 0x88, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xE6, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		108000000, {
+			0x00, 0xD1, 0x5A, 0x30, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xE4, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		108108000, {
+			0x00, 0xD1, 0x5A, 0x32, 0xFD, 0x0C, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xE4, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		118000000, {
+			0x00, 0xD1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xD1, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		118800000, {
+			0x00, 0xD1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xCF, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		123000000, {
+			0x00, 0xD1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xC8, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		127000000, {
+			0x00, 0xD1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xC2, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		135000000, {
+			0x00, 0xD1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB7, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		135580000, {
+			0x00, 0xD1, 0x71, 0x39, 0xE9, 0x82, 0x9C, 0x5B,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB6, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		137520000, {
+			0x00, 0xD1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB3, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		138750000, {
+			0x00, 0xD1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4D,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB2, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		140000000, {
+			0x00, 0xD1, 0x75, 0x36, 0xA7, 0x90, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB0, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		144000000, {
+			0x00, 0xD1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xAB, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		148352000, {
+			0x00, 0xD1, 0x7B, 0x35, 0xDB, 0x39, 0x90, 0x45,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xA6, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		148500000, {
+			0x00, 0xD1, 0x7B, 0x35, 0x84, 0x03, 0x90, 0x45,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xA6, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		154000000, {
+			0x00, 0xD1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0xA0, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		157000000, {
+			0x00, 0xD1, 0x41, 0x11, 0xA7, 0x14, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0x9D, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		160000000, {
+			0x00, 0xD1, 0x42, 0x12, 0xA1, 0x20, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0x9A, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		162000000, {
+			0x00, 0xD1, 0x43, 0x18, 0x8B, 0x08, 0x96, 0x55,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0x98, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		164000000, {
+			0x00, 0xD1, 0x45, 0x11, 0x83, 0x82, 0x90, 0x4B,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0x96, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		165000000, {
+			0x00, 0xD1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4B,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0x95, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		180000000, {
+			0x00, 0xD1, 0x4B, 0x10, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0x89, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		185625000, {
+			0x00, 0xD1, 0x4E, 0x12, 0x9A, 0x95, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0x85, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		188000000, {
+			0x00, 0xD1, 0x4E, 0x12, 0xA7, 0x10, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0x83, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		198000000, {
+			0x00, 0xD1, 0x52, 0x12, 0x82, 0x01, 0x88, 0x47,
+			0x4F, 0x30, 0x33, 0x65, 0x20, 0x7D, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		205000000, {
+			0x00, 0xD1, 0x55, 0x12, 0x8C, 0x05, 0x90, 0x4B,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xF0, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		209500000, {
+			0x00, 0xD1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xEB, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		213000000, {
+			0x00, 0xD1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xE7, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		216000000, {
+			0x00, 0xD1, 0x5A, 0x10, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		216216000, {
+			0x00, 0xD1, 0x5A, 0x12, 0xFD, 0x0C, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		237600000, {
+			0x00, 0xD1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xCF, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		254000000, {
+			0x00, 0xD1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xC2, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		277500000, {
+			0x00, 0xD1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4D,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xB2, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		288000000, {
+			0x00, 0xD1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xAB, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	}, {
+		297000000, {
+			0x00, 0xD1, 0x7B, 0x15, 0x84, 0x03, 0x90, 0x45,
+			0x4F, 0x30, 0x33, 0x65, 0x30, 0xA6, 0x24, 0x80,
+			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
+			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
+		},
+	},
+};
+
+struct fsl_samsung_hdmi_phy {
+	struct device *dev;
+	void __iomem *regs;
+	struct clk *apbclk;
+	struct clk *refclk;
+
+	/* clk provider */
+	struct clk_hw hw;
+	const struct phy_config *cur_cfg;
+};
+
+static inline struct fsl_samsung_hdmi_phy *
+to_fsl_samsung_hdmi_phy(struct clk_hw *hw)
+{
+	return container_of(hw, struct fsl_samsung_hdmi_phy, hw);
+}
+
+static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
+					  const struct phy_config *cfg)
+{
+	int i, ret;
+	u8 val;
+
+	/* HDMI PHY init */
+	writeb(REG33_FIX_DA, phy->regs + PHY_REG_33);
+
+	for (i = 0; i < PHY_PLL_REGS_NUM; i++)
+		writeb(cfg->regs[i], phy->regs + i * 4);
+
+	writeb(REG33_FIX_DA | REG33_MODE_SET_DONE , phy->regs + PHY_REG_33);
+
+	ret = readb_poll_timeout(phy->regs + PHY_REG_34, val,
+					 val & REG34_PLL_LOCK,
+					 50, 20000);
+	if (ret)
+		dev_err(phy->dev, "PLL failed to lock\n");
+
+	return ret;
+}
+
+static unsigned long phy_clk_recalc_rate(struct clk_hw *hw,
+					 unsigned long parent_rate)
+{
+	struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
+
+	if (!phy->cur_cfg)
+		return 74250000;
+
+	return phy->cur_cfg->clk_rate;
+}
+
+static long phy_clk_round_rate(struct clk_hw *hw,
+			       unsigned long rate, unsigned long *parent_rate)
+{
+	int i;
+
+	for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
+		if (phy_pll_cfg[i].clk_rate <= rate)
+			return phy_pll_cfg[i].clk_rate;
+
+	return -EINVAL;
+}
+
+static int phy_clk_set_rate(struct clk_hw *hw,
+			    unsigned long rate, unsigned long parent_rate)
+{
+	struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
+	int i;
+
+	for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
+		if (phy_pll_cfg[i].clk_rate <= rate)
+			break;
+
+	if (i < 0)
+		return -EINVAL;
+
+	phy->cur_cfg = &phy_pll_cfg[i];
+
+	return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
+}
+
+static const struct clk_ops phy_clk_ops = {
+	.recalc_rate = phy_clk_recalc_rate,
+	.round_rate = phy_clk_round_rate,
+	.set_rate = phy_clk_set_rate,
+};
+
+static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy)
+{
+	struct device *dev = phy->dev;
+	struct device_node *np = dev->of_node;
+	struct clk_init_data init;
+	const char *parent_name;
+	struct clk *phyclk;
+	int ret;
+
+	parent_name = __clk_get_name(phy->refclk);
+
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+	init.flags = 0;
+	init.name = "hdmi_pclk";
+	init.ops = &phy_clk_ops;
+
+	phy->hw.init = &init;
+
+	phyclk = devm_clk_register(dev, &phy->hw);
+	if (IS_ERR(phyclk))
+		return dev_err_probe(dev, PTR_ERR(phyclk),
+				     "failed to register clock\n");
+
+	ret = of_clk_add_provider(np, of_clk_src_simple_get, phyclk);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "failed to register clock provider\n");
+
+	return 0;
+}
+
+static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev)
+{
+	struct fsl_samsung_hdmi_phy *phy;
+	int ret;
+
+	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, phy);
+	phy->dev = &pdev->dev;
+
+	phy->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(phy->regs))
+		return PTR_ERR(phy->regs);
+
+	phy->apbclk = devm_clk_get(phy->dev, "apb");
+	if (IS_ERR(phy->apbclk))
+		return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk),
+				     "failed to get apb clk\n");
+
+	phy->refclk = devm_clk_get(phy->dev, "ref");
+	if (IS_ERR(phy->refclk))
+		return dev_err_probe(phy->dev, PTR_ERR(phy->refclk),
+				     "failed to get ref clk\n");
+
+	ret = clk_prepare_enable(phy->apbclk);
+	if (ret) {
+		dev_err(phy->dev, "failed to enable apbclk\n");
+		return ret;
+	}
+
+	pm_runtime_get_noresume(phy->dev);
+	pm_runtime_set_active(phy->dev);
+	pm_runtime_enable(phy->dev);
+
+	ret = phy_clk_register(phy);
+	if (ret) {
+		dev_err(&pdev->dev, "register clk failed\n");
+		goto register_clk_failed;
+	}
+
+	pm_runtime_put(phy->dev);
+
+	return 0;
+
+register_clk_failed:
+	clk_disable_unprepare(phy->apbclk);
+
+	return ret;
+}
+
+static int fsl_samsung_hdmi_phy_remove(struct platform_device *pdev)
+{
+	of_clk_del_provider(pdev->dev.of_node);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int fsl_samsung_hdmi_phy_suspend(struct device *dev)
+{
+	struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(phy->apbclk);
+
+	return 0;
+}
+
+static int fsl_samsung_hdmi_phy_resume(struct device *dev)
+{
+	struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = clk_prepare_enable(phy->apbclk);
+	if (ret) {
+		dev_err(phy->dev, "failed to enable apbclk\n");
+		return ret;
+	}
+
+	if (phy->cur_cfg)
+		ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
+
+	return ret;
+
+}
+#endif
+
+static const struct dev_pm_ops fsl_samsung_hdmi_phy_pm_ops = {
+	SET_RUNTIME_PM_OPS(fsl_samsung_hdmi_phy_suspend,
+			   fsl_samsung_hdmi_phy_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				pm_runtime_force_resume)
+};
+
+static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = {
+	{
+		.compatible = "fsl,imx8mp-hdmi-phy",
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match);
+
+static struct platform_driver fsl_samsung_hdmi_phy_driver = {
+	.probe  = fsl_samsung_hdmi_phy_probe,
+	.remove = fsl_samsung_hdmi_phy_remove,
+	.driver = {
+		.name = "fsl-samsung-hdmi-phy",
+		.of_match_table = fsl_samsung_hdmi_phy_of_match,
+		.pm = &fsl_samsung_hdmi_phy_pm_ops,
+	},
+};
+module_platform_driver(fsl_samsung_hdmi_phy_driver);
+
+MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>");
+MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.30.2

Re: [PATCH v0.5 6/9] phy: freescale: add Samsung HDMI PHY

[Marek Vasut]

[...]

> +static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev)
> +{
> +	struct fsl_samsung_hdmi_phy *phy;
> +	int ret;
> +
> +	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
> +	if (!phy)
> +		return -ENOMEM;
> +
> +	platform_set_drvdata(pdev, phy);
> +	phy->dev = &pdev->dev;
> +
> +	phy->regs = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(phy->regs))
> +		return PTR_ERR(phy->regs);
> +
> +	phy->apbclk = devm_clk_get(phy->dev, "apb");
> +	if (IS_ERR(phy->apbclk))
> +		return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk),
> +				     "failed to get apb clk\n");
> +
> +	phy->refclk = devm_clk_get(phy->dev, "ref");
> +	if (IS_ERR(phy->refclk))
> +		return dev_err_probe(phy->dev, PTR_ERR(phy->refclk),
> +				     "failed to get ref clk\n");
> +
> +	ret = clk_prepare_enable(phy->apbclk);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to enable apbclk\n");
> +		return ret;
> +	}

dev_err_probe() here too ?

Re: [PATCH v0.5 6/9] phy: freescale: add Samsung HDMI PHY

[Vinod Koul]

On 06-05-22, 20:10, Lucas Stach wrote:
> This adds the driver for the Samsung HDMI PHY found on the
> i.MX8MP SoC.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/phy/freescale/Kconfig                |    6 +
>  drivers/phy/freescale/Makefile               |    1 +
>  drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 1078 ++++++++++++++++++
>  3 files changed, 1085 insertions(+)
>  create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> 
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index f9c54cd02036..e88cc2212370 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -26,6 +26,12 @@ config PHY_FSL_IMX8M_PCIE
>  	  Enable this to add support for the PCIE PHY as found on
>  	  i.MX8M family of SOCs.
>  
> +config PHY_FSL_SAMSUNG_HDMI_PHY
> +	tristate "Samsung HDMI PHY support"
> +	depends on OF && HAS_IOMEM
> +	help
> +	  Enable this to add support for the Samsung HDMI PHY in i.MX8MP.
> +
>  endif
>  
>  config PHY_FSL_LYNX_28G
> diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
> index 3518d5dbe8a7..46a26929376d 100644
> --- a/drivers/phy/freescale/Makefile
> +++ b/drivers/phy/freescale/Makefile
> @@ -2,4 +2,5 @@
>  obj-$(CONFIG_PHY_FSL_IMX8MQ_USB)	+= phy-fsl-imx8mq-usb.o
>  obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)	+= phy-fsl-imx8-mipi-dphy.o
>  obj-$(CONFIG_PHY_FSL_IMX8M_PCIE)	+= phy-fsl-imx8m-pcie.o
> +obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY)  += phy-fsl-samsung-hdmi.o
>  obj-$(CONFIG_PHY_FSL_LYNX_28G)		+= phy-fsl-lynx-28g.o
> diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> new file mode 100644
> index 000000000000..6d20a5ce44e6
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> @@ -0,0 +1,1078 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020 NXP
> + * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#define HDMI_TX_CONTROL0		0x200
> +#define  HDMI_TX_CONTROL_PHY_PWRDWN	BIT(3)
> +
> +#define PHY_REG_33		0x84
> +#define  REG33_MODE_SET_DONE	BIT(7)
> +#define  REG33_FIX_DA		BIT(1)
> +
> +#define PHY_REG_34		0x88
> +#define  REG34_PHY_READY	BIT(7)
> +#define  REG34_PLL_LOCK		BIT(6)
> +#define  REG34_PHY_CLK_READY	BIT(5)
> +
> +
> +#define PHY_PLL_REGS_NUM 48
> +
> +struct phy_config {
> +	u32	clk_rate;
> +	u8 regs[PHY_PLL_REGS_NUM];
> +};
> +
> +const struct phy_config phy_pll_cfg[] = {
> +	{	22250000, {
> +			0x00, 0xD1, 0x4B, 0xF1, 0x89, 0x88, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x15, 0x25, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,

So we have only opaque register values we program for each rate...? No
documentation for these registers?

Also, will these be same across different SoC and boards as well..?
Typically tuning parameters will differ for each board...

> +		},
> +	}, {
> +		23750000, {
> +			0x00, 0xD1, 0x50, 0xF1, 0x86, 0x85, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x03, 0x25, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	},{
> +		24000000, {
> +			0x00, 0xD1, 0x50, 0xF0, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x01, 0x25, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	},{
> +		24024000, {
> +			0x00, 0xD1, 0x50, 0xF1, 0x99, 0x02, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x00, 0x25, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		25175000, {
> +			0x00, 0xD1, 0x54, 0xFC, 0xCC, 0x91, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xF5, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		25200000, {
> +			0x00, 0xD1, 0x54, 0xF0, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xF4, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		26750000, {
> +			0x00, 0xD1, 0x5A, 0xF2, 0x89, 0x88, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xE6, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		27000000, {
> +			0x00, 0xD1, 0x5A, 0xF0, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		27027000, {
> +			0x00, 0xD1, 0x5A, 0xF2, 0xFD, 0x0C, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xE4, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		29500000, {
> +			0x00, 0xD1, 0x62, 0xF4, 0x95, 0x08, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xD1, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		30750000, {
> +			0x00, 0xD1, 0x66, 0xF4, 0x82, 0x01, 0x88, 0x45,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xC8, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		30888000, {
> +			0x00, 0xD1, 0x66, 0xF4, 0x99, 0x18, 0x88, 0x45,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xC7, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		33750000, {
> +			0x00, 0xD1, 0x70, 0xF4, 0x82, 0x01, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xB7, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8F, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		35000000, {
> +			0x00, 0xD1, 0x58, 0xB8, 0x8B, 0x88, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xB0, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		36000000, {
> +			0x00, 0xD1, 0x5A, 0xB0, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xAB, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		36036000, {
> +			0x00, 0xD1, 0x5A, 0xB2, 0xFD, 0x0C, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0xAB, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		40000000, {
> +			0x00, 0xD1, 0x64, 0xB0, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x9A, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x8B, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		43200000, {
> +			0x00, 0xD1, 0x5A, 0x90, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x8F, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		43243200, {
> +			0x00, 0xD1, 0x5A, 0x92, 0xFD, 0x0C, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x8F, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		44500000, {
> +			0x00, 0xD1, 0x5C, 0x92, 0x98, 0x11, 0x84, 0x41,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x8B, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		47000000, {
> +			0x00, 0xD1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x83, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		47500000, {
> +			0x00, 0xD1, 0x63, 0x96, 0xA1, 0x82, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x00, 0x82, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x89, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		50349650, {
> +			0x00, 0xD1, 0x54, 0x7C, 0xC3, 0x8F, 0x80, 0x40,
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> +		},
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> +		102500000, {
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> +		},
> +	}, {
> +		104750000, {
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> +		},
> +	}, {
> +		106500000, {
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> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		107000000, {
> +			0x00, 0xD1, 0x5A, 0x32, 0x89, 0x88, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xE6, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		108000000, {
> +			0x00, 0xD1, 0x5A, 0x30, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xE4, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		108108000, {
> +			0x00, 0xD1, 0x5A, 0x32, 0xFD, 0x0C, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xE4, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		118000000, {
> +			0x00, 0xD1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xD1, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		118800000, {
> +			0x00, 0xD1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xCF, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		123000000, {
> +			0x00, 0xD1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xC8, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		127000000, {
> +			0x00, 0xD1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xC2, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		135000000, {
> +			0x00, 0xD1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB7, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		135580000, {
> +			0x00, 0xD1, 0x71, 0x39, 0xE9, 0x82, 0x9C, 0x5B,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB6, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		137520000, {
> +			0x00, 0xD1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB3, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		138750000, {
> +			0x00, 0xD1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4D,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB2, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		140000000, {
> +			0x00, 0xD1, 0x75, 0x36, 0xA7, 0x90, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xB0, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		144000000, {
> +			0x00, 0xD1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xAB, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		148352000, {
> +			0x00, 0xD1, 0x7B, 0x35, 0xDB, 0x39, 0x90, 0x45,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xA6, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		148500000, {
> +			0x00, 0xD1, 0x7B, 0x35, 0x84, 0x03, 0x90, 0x45,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xA6, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x83, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		154000000, {
> +			0x00, 0xD1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0xA0, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		157000000, {
> +			0x00, 0xD1, 0x41, 0x11, 0xA7, 0x14, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0x9D, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		160000000, {
> +			0x00, 0xD1, 0x42, 0x12, 0xA1, 0x20, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0x9A, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		162000000, {
> +			0x00, 0xD1, 0x43, 0x18, 0x8B, 0x08, 0x96, 0x55,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0x98, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		164000000, {
> +			0x00, 0xD1, 0x45, 0x11, 0x83, 0x82, 0x90, 0x4B,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0x96, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		165000000, {
> +			0x00, 0xD1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4B,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0x95, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		180000000, {
> +			0x00, 0xD1, 0x4B, 0x10, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0x89, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		185625000, {
> +			0x00, 0xD1, 0x4E, 0x12, 0x9A, 0x95, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0x85, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		188000000, {
> +			0x00, 0xD1, 0x4E, 0x12, 0xA7, 0x10, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0x83, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		198000000, {
> +			0x00, 0xD1, 0x52, 0x12, 0x82, 0x01, 0x88, 0x47,
> +			0x4F, 0x30, 0x33, 0x65, 0x20, 0x7D, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		205000000, {
> +			0x00, 0xD1, 0x55, 0x12, 0x8C, 0x05, 0x90, 0x4B,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xF0, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		209500000, {
> +			0x00, 0xD1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xEB, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		213000000, {
> +			0x00, 0xD1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xE7, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		216000000, {
> +			0x00, 0xD1, 0x5A, 0x10, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		216216000, {
> +			0x00, 0xD1, 0x5A, 0x12, 0xFD, 0x0C, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xE4, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		237600000, {
> +			0x00, 0xD1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xCF, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		254000000, {
> +			0x00, 0xD1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xC2, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		277500000, {
> +			0x00, 0xD1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4D,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xB2, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		288000000, {
> +			0x00, 0xD1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xAB, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	}, {
> +		297000000, {
> +			0x00, 0xD1, 0x7B, 0x15, 0x84, 0x03, 0x90, 0x45,
> +			0x4F, 0x30, 0x33, 0x65, 0x30, 0xA6, 0x24, 0x80,
> +			0x6C, 0xF2, 0x67, 0x00, 0x10, 0x81, 0x30, 0x32,
> +			0x60, 0x8F, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
> +			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +			0x00, 0xE0, 0x83, 0x0F, 0x3E, 0xF8, 0x00, 0x00,
> +		},
> +	},
> +};
> +
> +struct fsl_samsung_hdmi_phy {
> +	struct device *dev;
> +	void __iomem *regs;
> +	struct clk *apbclk;
> +	struct clk *refclk;
> +
> +	/* clk provider */
> +	struct clk_hw hw;
> +	const struct phy_config *cur_cfg;
> +};
> +
> +static inline struct fsl_samsung_hdmi_phy *
> +to_fsl_samsung_hdmi_phy(struct clk_hw *hw)
> +{
> +	return container_of(hw, struct fsl_samsung_hdmi_phy, hw);
> +}
> +
> +static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
> +					  const struct phy_config *cfg)
> +{
> +	int i, ret;
> +	u8 val;
> +
> +	/* HDMI PHY init */
> +	writeb(REG33_FIX_DA, phy->regs + PHY_REG_33);
> +
> +	for (i = 0; i < PHY_PLL_REGS_NUM; i++)
> +		writeb(cfg->regs[i], phy->regs + i * 4);
> +
> +	writeb(REG33_FIX_DA | REG33_MODE_SET_DONE , phy->regs + PHY_REG_33);
> +
> +	ret = readb_poll_timeout(phy->regs + PHY_REG_34, val,
> +					 val & REG34_PLL_LOCK,
> +					 50, 20000);
> +	if (ret)
> +		dev_err(phy->dev, "PLL failed to lock\n");
> +
> +	return ret;
> +}
> +
> +static unsigned long phy_clk_recalc_rate(struct clk_hw *hw,
> +					 unsigned long parent_rate)
> +{
> +	struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
> +
> +	if (!phy->cur_cfg)
> +		return 74250000;
> +
> +	return phy->cur_cfg->clk_rate;
> +}
> +
> +static long phy_clk_round_rate(struct clk_hw *hw,
> +			       unsigned long rate, unsigned long *parent_rate)
> +{
> +	int i;
> +
> +	for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
> +		if (phy_pll_cfg[i].clk_rate <= rate)
> +			return phy_pll_cfg[i].clk_rate;
> +
> +	return -EINVAL;
> +}
> +
> +static int phy_clk_set_rate(struct clk_hw *hw,
> +			    unsigned long rate, unsigned long parent_rate)
> +{
> +	struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);
> +	int i;
> +
> +	for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)
> +		if (phy_pll_cfg[i].clk_rate <= rate)
> +			break;
> +
> +	if (i < 0)
> +		return -EINVAL;
> +
> +	phy->cur_cfg = &phy_pll_cfg[i];
> +
> +	return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
> +}
> +
> +static const struct clk_ops phy_clk_ops = {
> +	.recalc_rate = phy_clk_recalc_rate,
> +	.round_rate = phy_clk_round_rate,
> +	.set_rate = phy_clk_set_rate,
> +};
> +
> +static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy)
> +{
> +	struct device *dev = phy->dev;
> +	struct device_node *np = dev->of_node;
> +	struct clk_init_data init;
> +	const char *parent_name;
> +	struct clk *phyclk;
> +	int ret;
> +
> +	parent_name = __clk_get_name(phy->refclk);
> +
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +	init.flags = 0;
> +	init.name = "hdmi_pclk";
> +	init.ops = &phy_clk_ops;
> +
> +	phy->hw.init = &init;
> +
> +	phyclk = devm_clk_register(dev, &phy->hw);
> +	if (IS_ERR(phyclk))
> +		return dev_err_probe(dev, PTR_ERR(phyclk),
> +				     "failed to register clock\n");
> +
> +	ret = of_clk_add_provider(np, of_clk_src_simple_get, phyclk);
> +	if (ret)
> +		return dev_err_probe(dev, ret,
> +				     "failed to register clock provider\n");
> +
> +	return 0;
> +}
> +
> +static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev)
> +{
> +	struct fsl_samsung_hdmi_phy *phy;
> +	int ret;
> +
> +	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
> +	if (!phy)
> +		return -ENOMEM;
> +
> +	platform_set_drvdata(pdev, phy);
> +	phy->dev = &pdev->dev;
> +
> +	phy->regs = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(phy->regs))
> +		return PTR_ERR(phy->regs);
> +
> +	phy->apbclk = devm_clk_get(phy->dev, "apb");
> +	if (IS_ERR(phy->apbclk))
> +		return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk),
> +				     "failed to get apb clk\n");
> +
> +	phy->refclk = devm_clk_get(phy->dev, "ref");
> +	if (IS_ERR(phy->refclk))
> +		return dev_err_probe(phy->dev, PTR_ERR(phy->refclk),
> +				     "failed to get ref clk\n");
> +
> +	ret = clk_prepare_enable(phy->apbclk);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to enable apbclk\n");
> +		return ret;
> +	}
> +
> +	pm_runtime_get_noresume(phy->dev);
> +	pm_runtime_set_active(phy->dev);
> +	pm_runtime_enable(phy->dev);
> +
> +	ret = phy_clk_register(phy);
> +	if (ret) {
> +		dev_err(&pdev->dev, "register clk failed\n");
> +		goto register_clk_failed;
> +	}
> +
> +	pm_runtime_put(phy->dev);
> +
> +	return 0;
> +
> +register_clk_failed:
> +	clk_disable_unprepare(phy->apbclk);
> +
> +	return ret;
> +}
> +
> +static int fsl_samsung_hdmi_phy_remove(struct platform_device *pdev)
> +{
> +	of_clk_del_provider(pdev->dev.of_node);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int fsl_samsung_hdmi_phy_suspend(struct device *dev)
> +{
> +	struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
> +
> +	clk_disable_unprepare(phy->apbclk);
> +
> +	return 0;
> +}
> +
> +static int fsl_samsung_hdmi_phy_resume(struct device *dev)
> +{
> +	struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);
> +	int ret = 0;
> +
> +	ret = clk_prepare_enable(phy->apbclk);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to enable apbclk\n");
> +		return ret;
> +	}
> +
> +	if (phy->cur_cfg)
> +		ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);
> +
> +	return ret;
> +
> +}
> +#endif
> +
> +static const struct dev_pm_ops fsl_samsung_hdmi_phy_pm_ops = {
> +	SET_RUNTIME_PM_OPS(fsl_samsung_hdmi_phy_suspend,
> +			   fsl_samsung_hdmi_phy_resume, NULL)
> +	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
> +				pm_runtime_force_resume)
> +};
> +
> +static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = {
> +	{
> +		.compatible = "fsl,imx8mp-hdmi-phy",
> +	}, {
> +		/* sentinel */
> +	}
> +};
> +MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match);
> +
> +static struct platform_driver fsl_samsung_hdmi_phy_driver = {
> +	.probe  = fsl_samsung_hdmi_phy_probe,
> +	.remove = fsl_samsung_hdmi_phy_remove,
> +	.driver = {
> +		.name = "fsl-samsung-hdmi-phy",
> +		.of_match_table = fsl_samsung_hdmi_phy_of_match,
> +		.pm = &fsl_samsung_hdmi_phy_pm_ops,
> +	},
> +};
> +module_platform_driver(fsl_samsung_hdmi_phy_driver);
> +
> +MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>");
> +MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver");
> +MODULE_LICENSE("GPL v2");
> -- 
> 2.30.2
> 
> 
> -- 
> linux-phy mailing list
> linux-phy@lists.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy

-- 
~Vinod

[PATCH v0.5 7/9] arm64: dts: imx8mp: add HDMI irqsteer

[Lucas Stach]

The HDMI irqsteer is a secondary interrupt controller within the HDMI
subsystem that maps all HDMI peripheral IRQs into a single upstream
IRQ line.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d33794bcdc15..6fcbfe9d59b8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1111,6 +1111,19 @@ hdmi_blk_ctrl: blk-ctrl@32fc0000 {
 						     "hdmi-tx", "hdmi-tx-phy";
 				#power-domain-cells = <1>;
 			};
+
+			irqsteer_hdmi: interrupt-controller@32fc2000 {
+				compatible = "fsl,imx-irqsteer";
+				reg = <0x32fc2000 0x44>;
+				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				fsl,channel = <1>;
+				fsl,num-irqs = <64>;
+				clocks = <&clk IMX8MP_CLK_HDMI_APB>;
+				clock-names = "ipg";
+				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
+			};
 		};
 
 		gpu3d: gpu@38000000 {
-- 
2.30.2

[PATCH v0.5 8/9] arm64: dts: imx8mp: add HDMI display pipeline

[Lucas Stach]

This adds the DT nodes for all the peripherals that make up the
HDMI display pipeline.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 81 +++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 6fcbfe9d59b8..47173ece95a5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1124,6 +1124,87 @@ irqsteer_hdmi: interrupt-controller@32fc2000 {
 				clock-names = "ipg";
 				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
 			};
+
+			hdmi_pvi: display-bridge@32fc4000 {
+				compatible = "fsl,imx8mp-hdmi-pvi";
+				reg = <0x32fc4000 0x40>;
+				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						pvi_from_lcdif3: endpoint {
+							remote-endpoint = <&lcdif3_to_pvi>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						pvi_to_hdmi_tx: endpoint {
+							remote-endpoint = <&hdmi_tx_from_pvi>;
+						};
+					};
+				};
+			};
+
+			lcdif3: display-controller@32fc6000 {
+				compatible = "fsl,imx8mp-lcdif";
+				reg = <0x32fc6000 0x238>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&irqsteer_hdmi>;
+				clocks = <&hdmi_tx_phy>,
+					 <&clk IMX8MP_CLK_HDMI_APB>,
+					 <&clk IMX8MP_CLK_HDMI_ROOT>;
+				clock-names = "pix", "axi", "disp_axi";
+				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
+
+				port {
+					lcdif3_to_pvi: endpoint {
+						remote-endpoint = <&pvi_from_lcdif3>;
+					};
+				};
+			};
+
+			hdmi_tx: hdmi@32fd8000 {
+				compatible = "fsl,imx8mp-hdmi";
+				reg = <0x32fd8000 0x7eff>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&irqsteer_hdmi>;
+				clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+					 <&clk IMX8MP_CLK_HDMI_REF_266M>,
+					 <&clk IMX8MP_CLK_HDMI_FDCC_TST>,
+					 <&clk IMX8MP_CLK_32K>,
+					 <&hdmi_tx_phy>;
+				clock-names = "iahb", "isfr", "fdcc", "cec", "pix";
+				assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
+				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
+				reg-io-width = <1>;
+				status = "disabled";
+
+				port {
+					hdmi_tx_from_pvi: endpoint {
+						remote-endpoint = <&pvi_to_hdmi_tx>;
+					};
+				};
+			};
+
+			hdmi_tx_phy: phy@32fdff00 {
+				compatible = "fsl,imx8mp-hdmi-phy";
+				reg = <0x32fdff00 0x100>;
+				clocks = <&clk IMX8MP_CLK_HDMI_APB>,
+					 <&clk IMX8MP_CLK_HDMI_24M>;
+				clock-names = "apb", "ref";
+				assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
+				assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
+				#clock-cells = <0>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		gpu3d: gpu@38000000 {
-- 
2.30.2

[PATCH v0.5 9/9] arm64: dts: imx8mp-evk: enable HDMI

[Lucas Stach]

Enable the DT nodes for HDMI TX and PHY and add the pinctrl for the few
involved pins that are configurable.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 4c3ac4214a2c..fdf851865ba9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -197,6 +197,16 @@ ethphy1: ethernet-phy@1 {
 	};
 };
 
+&hdmi_tx {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	status = "okay";
+};
+
+&hdmi_tx_phy {
+	status = "okay";
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -465,6 +475,15 @@ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
 		>;
 	};
 
+	pinctrl_hdmi: hdmigrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c3
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c3
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x19
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x19
+		>;
+	};
+
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
-- 
2.30.2

Re: (EXT) [PATCH v0.5 0/9] i.MX8MP HDMI support

[Alexander Stein]

Hi Lucas,

Am Freitag, 6. Mai 2022, 20:10:25 CEST schrieb Lucas Stach:
> second round of the i.MX8MP HDMI work. Still not split up into proper
> parts for merging through the various trees this needs to go into, but
> should make it easy for people to test.
> 
> I've worked in the feedback I got from the last round, including fixing
> the system hang that could happen when the drivers were built as modules.
> 
> Series is based on linux-next/master, as there are some prerequisite
> patches in both the drm and imx tree already. The last patch from [1]
> and the patches from [2] need to be applied. Please note that this series
> expects the sync polarity from the LCDIF to be set according to the
> comments I made in [2]. Please test and provide feedback.

Thanks for the 2nd round of HDMI support patches. Sorry I wasn't able to reply 
to your questions, but the PLL locking seems to be gone on my system.

I still get the error
> imx-lcdif 32fc6000.display-controller: Unknown media bus format 0x200f

To answer the other question on the last patchset
> Do have a 4k HDMI display connected that wants to do YUV input? That's
> something I have to admit I didn't test yet and would be likely to
> cause this bus format selection.

This is a FullHD HDMI monitor, ASUS PB238Q. Apparently the color format is 
YCBCR422. From what I can see is that 
dw_hdmi_bridge_atomic_get_output_bus_fmts() adds MEDIA_BUS_FMT_UYVY8_1X16 
(0x200f) to the output formats. This is then passed to 
select_bus_fmt_recursive() on the bridge chain. For 0x200f 
dw_hdmi_bridge_atomic_get_input_bus_fmts() returns 3 input formats with 
MEDIA_BUS_FMT_UYVY8_1X16 being the 1st.
Each entry is then probed on pvi_bridge_get_input_bus_fmts(), which just 
forwards to dw_hdmi_bridge_atomic_get_input_bus_fmts().
Note: At this point it is only checked whether the input format can be output.
As 0x200f is supported by dw_hdmi this format will finally be selected, which 
is not supported by lcdif_kms, resulting in the error message above.

A quick&dirty hack to workaround is the following diff which just changes the 
order of the format to be tested:
---8<---
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2816,9 +2816,9 @@ static u32 
*dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
                input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
                break;
        case MEDIA_BUS_FMT_UYVY8_1X16:
+               input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
                input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
                input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
-               input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
                break;
 
        /* 10bit */
---8<---
With this MEDIA_BUS_FMT_RGB888_1X24 is probed 1st (and selected) which 
actually is supported by lcdif_kms.

For the records, I used this diff for lcdif driver to fix the polarity issue
---8<---
--- a/drivers/gpu/drm/mxsfb/lcdif_kms.c
+++ b/drivers/gpu/drm/mxsfb/lcdif_kms.c
@@ -89,12 +89,12 @@ static void lcdif_set_mode(struct lcdif_drm_private 
*lcdif, u32 bus_flags)
        struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
        u32 ctrl = 0;
 
-       if (m->flags & DRM_MODE_FLAG_PHSYNC)
+       if (m->flags & DRM_MODE_FLAG_NHSYNC)
                ctrl |= CTRL_INV_HS;
-       if (m->flags & DRM_MODE_FLAG_PVSYNC)
+       if (m->flags & DRM_MODE_FLAG_NVSYNC)
                ctrl |= CTRL_INV_VS;
        /* Make sure Data Enable is high active by default */
-       if (!(bus_flags & DRM_BUS_FLAG_DE_LOW))
+       if ((bus_flags & DRM_BUS_FLAG_DE_LOW))
                ctrl |= CTRL_INV_DE;
        if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
                ctrl |= CTRL_INV_PXCK;
---8<---

With both changes from above I can see the weston desktop.

Alexander

> [1]
> https://lore.kernel.org/all/20220406153402.1265474-1-l.stach@pengutronix.de
> / [2] https://lore.kernel.org/all/20220322142853.125880-1-marex@denx.de/
> 
> Lucas Stach (9):
>   dt-bindings: display: imx: add binding for i.MX8MP HDMI TX
>   drm/imx: add bridge wrapper driver for i.MX8MP DWC HDMI
>   dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI
>   drm/imx: add driver for HDMI TX Parallel Video Interface
>   dt-bindings: phy: add binding for the i.MX8MP HDMI PHY
>   phy: freescale: add Samsung HDMI PHY
>   arm64: dts: imx8mp: add HDMI irqsteer
>   arm64: dts: imx8mp: add HDMI display pipeline
>   arm64: dts: imx8mp-evk: enable HDMI
> 
>  .../display/imx/fsl,imx8mp-hdmi-pvi.yaml      |   83 ++
>  .../bindings/display/imx/fsl,imx8mp-hdmi.yaml |   73 ++
>  .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml     |   62 +
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts  |   19 +
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi     |   94 ++
>  drivers/gpu/drm/imx/Kconfig                   |    1 +
>  drivers/gpu/drm/imx/Makefile                  |    2 +
>  drivers/gpu/drm/imx/bridge/Kconfig            |   18 +
>  drivers/gpu/drm/imx/bridge/Makefile           |    4 +
>  drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c     |  201 +++
>  drivers/gpu/drm/imx/bridge/imx-hdmi.c         |  141 +++
>  drivers/phy/freescale/Kconfig                 |    6 +
>  drivers/phy/freescale/Makefile                |    1 +
>  drivers/phy/freescale/phy-fsl-samsung-hdmi.c  | 1078 +++++++++++++++++
>  14 files changed, 1783 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
> create mode 100644
> Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml create
> mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
> create mode 100644 drivers/gpu/drm/imx/bridge/Kconfig
>  create mode 100644 drivers/gpu/drm/imx/bridge/Makefile
>  create mode 100644 drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c
>  create mode 100644 drivers/gpu/drm/imx/bridge/imx-hdmi.c
>  create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c

Re: (EXT) [PATCH v0.5 0/9] i.MX8MP HDMI support

[Marek Vasut]

On 5/9/22 11:44, Alexander Stein wrote:
> Hi Lucas,
> 
> Am Freitag, 6. Mai 2022, 20:10:25 CEST schrieb Lucas Stach:
>> second round of the i.MX8MP HDMI work. Still not split up into proper
>> parts for merging through the various trees this needs to go into, but
>> should make it easy for people to test.
>>
>> I've worked in the feedback I got from the last round, including fixing
>> the system hang that could happen when the drivers were built as modules.
>>
>> Series is based on linux-next/master, as there are some prerequisite
>> patches in both the drm and imx tree already. The last patch from [1]
>> and the patches from [2] need to be applied. Please note that this series
>> expects the sync polarity from the LCDIF to be set according to the
>> comments I made in [2]. Please test and provide feedback.
> 
> Thanks for the 2nd round of HDMI support patches. Sorry I wasn't able to reply
> to your questions, but the PLL locking seems to be gone on my system.
> 
> I still get the error
>> imx-lcdif 32fc6000.display-controller: Unknown media bus format 0x200f
> 
> To answer the other question on the last patchset
>> Do have a 4k HDMI display connected that wants to do YUV input? That's
>> something I have to admit I didn't test yet and would be likely to
>> cause this bus format selection.
> 
> This is a FullHD HDMI monitor, ASUS PB238Q. Apparently the color format is
> YCBCR422. From what I can see is that
> dw_hdmi_bridge_atomic_get_output_bus_fmts() adds MEDIA_BUS_FMT_UYVY8_1X16
> (0x200f) to the output formats. This is then passed to

Try LCDIFv3 v3 patchset I just posted, that should work then.

Re: [PATCH v0.5 0/9] i.MX8MP HDMI support

[Tommaso Merciai]

Hello Lucas,

On Fri, May 06, 2022 at 08:10:25PM +0200, Lucas Stach wrote:
> Hi all,
> 
> second round of the i.MX8MP HDMI work. Still not split up into proper
> parts for merging through the various trees this needs to go into, but
> should make it easy for people to test.
> 
> I've worked in the feedback I got from the last round, including fixing
> the system hang that could happen when the drivers were built as modules.
> 
> Series is based on linux-next/master, as there are some prerequisite
> patches in both the drm and imx tree already. The last patch from [1]
> and the patches from [2] need to be applied. Please note that this series
> expects the sync polarity from the LCDIF to be set according to the
> comments I made in [2]. Please test and provide feedback.
> 
> Regards,
> Lucas

I tested your series on Linux 6.2.0-rc8
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>

Thanks for your work!

Regards,
Tommaso

> 
> [1] https://lore.kernel.org/all/20220406153402.1265474-1-l.stach@pengutronix.de/
> [2] https://lore.kernel.org/all/20220322142853.125880-1-marex@denx.de/
> 
> Lucas Stach (9):
>   dt-bindings: display: imx: add binding for i.MX8MP HDMI TX
>   drm/imx: add bridge wrapper driver for i.MX8MP DWC HDMI
>   dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI
>   drm/imx: add driver for HDMI TX Parallel Video Interface
>   dt-bindings: phy: add binding for the i.MX8MP HDMI PHY
>   phy: freescale: add Samsung HDMI PHY
>   arm64: dts: imx8mp: add HDMI irqsteer
>   arm64: dts: imx8mp: add HDMI display pipeline
>   arm64: dts: imx8mp-evk: enable HDMI
> 
>  .../display/imx/fsl,imx8mp-hdmi-pvi.yaml      |   83 ++
>  .../bindings/display/imx/fsl,imx8mp-hdmi.yaml |   73 ++
>  .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml     |   62 +
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts  |   19 +
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi     |   94 ++
>  drivers/gpu/drm/imx/Kconfig                   |    1 +
>  drivers/gpu/drm/imx/Makefile                  |    2 +
>  drivers/gpu/drm/imx/bridge/Kconfig            |   18 +
>  drivers/gpu/drm/imx/bridge/Makefile           |    4 +
>  drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c     |  201 +++
>  drivers/gpu/drm/imx/bridge/imx-hdmi.c         |  141 +++
>  drivers/phy/freescale/Kconfig                 |    6 +
>  drivers/phy/freescale/Makefile                |    1 +
>  drivers/phy/freescale/phy-fsl-samsung-hdmi.c  | 1078 +++++++++++++++++
>  14 files changed, 1783 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
>  create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
>  create mode 100644 drivers/gpu/drm/imx/bridge/Kconfig
>  create mode 100644 drivers/gpu/drm/imx/bridge/Makefile
>  create mode 100644 drivers/gpu/drm/imx/bridge/imx-hdmi-pvi.c
>  create mode 100644 drivers/gpu/drm/imx/bridge/imx-hdmi.c
>  create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> 
> -- 
> 2.30.2
> 
>