From: Biju Das <biju.das.jz@bp.renesas.com>
To: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: devicetree@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
dri-devel@lists.freedesktop.org,
Biju Das <biju.das@bp.renesas.com>,
linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH v5 09/10] dt-bindings: display: Document Renesas RZ/G2L DU bindings
Date: Wed, 27 Jul 2022 17:07:52 +0100 [thread overview]
Message-ID: <20220727160753.1774761-10-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220727160753.1774761-1-biju.das.jz@bp.renesas.com>
The RZ/G2L LCD controller is composed of Frame Compression Processor
(FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
The DU module supports the following hardware features
− Display Parallel Interface (DPI) and MIPI LINK Video Interface
− Display timing master
− Generates video timings
− Selecting the polarity of output DCLK, HSYNC, VSYNC, and DE
− Supports Progressive
− Input data format (from VSPD): RGB888, RGB666
− Output data format: same as Input data format
− Supporting Full HD (1920 pixels x 1080 lines) for MIPI-DSI Output
− Supporting WXGA (1280 pixels x 800 lines) for Parallel Output
This patch document DU module found on RZ/G2L LCDC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v4->v5:
* Added Rb tag from Rob.
v3->v4:
* Changed compatible name from renesas,du-r9a07g044->renesas,r9a07g044-du
* started using same compatible for RZ/G2{L,LC}
v3: New patch
---
.../bindings/display/renesas,rzg2l-du.yaml | 124 ++++++++++++++++++
1 file changed, 124 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
new file mode 100644
index 000000000000..7626043debd8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Display Unit (DU)
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
+ and RZ/V2L SoCs.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r9a07g044-du # RZ/G2{L,LC}
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main clock
+ - description: Register access clock
+ - description: Video clock
+
+ clock-names:
+ items:
+ - const: aclk
+ - const: pclk
+ - const: vclk
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ The connections to the DU output video ports are modeled using the OF
+ graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+ The number of ports and their assignment are model-dependent. Each port
+ shall have a single endpoint.
+
+ patternProperties:
+ "^port@[0-1]$":
+ $ref: /schemas/graph.yaml#/properties/port
+ unevaluatedProperties: false
+
+ required:
+ - port@0
+
+ unevaluatedProperties: false
+
+ renesas,vsps:
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ items:
+ - description: phandle to VSP instance that serves the DU channel
+ - description: Channel index identifying the LIF instance in that VSP
+ description:
+ A list of phandle and channel index tuples to the VSPs that handle the
+ memory interfaces for the DU channels.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - power-domains
+ - ports
+ - renesas,vsps
+
+additionalProperties: false
+
+examples:
+ # RZ/G2L DU
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ display@10890000 {
+ compatible = "renesas,r9a07g044-du";
+ reg = <0x10890000 0x10000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+ <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+ clock-names = "aclk", "pclk", "vclk";
+ resets = <&cpg R9A07G044_LCDC_RESET_N>;
+ power-domains = <&cpg>;
+
+ renesas,vsps = <&vspd0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ endpoint {
+ };
+ };
+ };
+ };
+
+...
--
2.25.1
next prev parent reply other threads:[~2022-07-27 16:09 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-27 16:07 [PATCH v5 00/10] Add RZ/G2L Display support Biju Das
2022-07-27 16:07 ` [PATCH v5 01/10] drm: rcar-du: Move rcar_du_vsp_plane_prepare_fb() Biju Das
2022-07-27 16:07 ` [PATCH v5 02/10] drm: rcar-du: Move rcar_du_vsp_plane_cleanup_fb() Biju Das
2022-07-27 16:07 ` [PATCH v5 03/10] drm: rcar-du: Move rcar_du_vsp_plane_atomic_update() Biju Das
2022-07-27 16:07 ` [PATCH v5 04/10] drm: rcar-du: Add rcar_du_lib_fb_create() Biju Das
2022-08-18 9:29 ` Geert Uytterhoeven
2022-08-24 8:57 ` Biju Das
2022-07-27 16:07 ` [PATCH v5 05/10] drm: rcar-du: Add rcar_du_lib_mode_cfg_helper_fns() Biju Das
2022-07-27 16:07 ` [PATCH v5 06/10] drm: rcar-du: Move rcar_du_encoders_init() Biju Das
2022-07-27 16:07 ` [PATCH v5 07/10] drm: rcar-du: Move rcar_du_properties_init() Biju Das
2022-07-27 16:07 ` [PATCH v5 08/10] drm: rcar-du: Add rcar_du_lib_vsps_init() Biju Das
2022-07-27 16:07 ` Biju Das [this message]
2022-07-27 16:07 ` [PATCH v5 10/10] drm: rcar-du: Add RZ/G2L DU Support Biju Das
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