* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-08-15 17:35 Stanislav Lisovskiy 2022-08-15 17:35 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-08-15 17:35 ` [PATCH 2/2] drm/i915: Add DSC support to MST path Stanislav Lisovskiy 0 siblings, 2 replies; 12+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++------ drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 ++++++++++++++++++++ include/drm/display/drm_dp.h | 10 +- 4 files changed, 215 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-08-15 17:35 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy @ 2022-08-15 17:35 ` Stanislav Lisovskiy 2022-08-15 17:35 ` [PATCH 2/2] drm/i915: Add DSC support to MST path Stanislav Lisovskiy 1 sibling, 0 replies; 12+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- include/drm/display/drm_dp.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9e3aff7e68bb..0d05e3172f96 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] drm/i915: Add DSC support to MST path 2022-08-15 17:35 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-08-15 17:35 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy @ 2022-08-15 17:35 ` Stanislav Lisovskiy 1 sibling, 0 replies; 12+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Whenever we are not able to get enough timeslots for required PBN, let's try to allocate those using DSC, just same way as we do for SST. v2: Removed intel_dp_mst_dsc_compute_config and refactored intel_dp_dsc_compute_config to support timeslots as a parameter(Ville Syrjälä) v3: - Rebased - Added a debug to see that we at least try reserving VCPI slots using DSC, because currently its not visible from the logs, thus making debugging more tricky. - Moved timeslots to numerator, where it should be. v4: - Call drm_dp_mst_atomic_check already during link config computation, because we need to know already by this moment if uncompressed amount of VCPI slots needed can fit, otherwise we need to use DSC. (thanks to Vinod Govindapillai for pointing this out) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++------ drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 ++++++++++++++++++++ 3 files changed, 206 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 32292c0be2bd..1f6dc52251c2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) } static void intel_dp_unset_edid(struct intel_dp *intel_dp); -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915) return 6144 * 8; } -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - u32 pipe_bpp) +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots) { u32 bits_per_pixel, max_bpp_small_joiner_ram; int i; @@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, * for SST -> TimeSlotsPerMTP is 1, * for MST -> TimeSlotsPerMTP has to be calculated */ - bits_per_pixel = (link_clock * lane_count * 8) / + bits_per_pixel = (link_clock * lane_count * 8) * timeslots / intel_dp_mode_to_fec_clock(mode_clock); + drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / @@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, return bits_per_pixel << 4; } -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, - int mode_clock, int mode_hdisplay, - bool bigjoiner) +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 min_slice_count, i; @@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, return MODE_OK; } -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, - int hdisplay, int clock) +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, target_clock, mode->hdisplay, bigjoiner, - pipe_bpp) >> 4; + pipe_bpp, 1) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1354,7 +1355,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; @@ -1444,10 +1445,11 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } -static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state, - struct link_config_limits *limits) +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); @@ -1498,7 +1500,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, - pipe_bpp); + pipe_bpp, + timeslots); dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, adjusted_mode->crtc_clock, @@ -1510,41 +1513,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_output_bpp >> 4, - pipe_config->pipe_bpp); + dsc_max_output_bpp >> 4, + pipe_config->pipe_bpp); pipe_config->dsc.slice_count = dsc_dp_slice_count; + drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", + pipe_config->dsc.compressed_bpp, + pipe_config->dsc.slice_count); } - - /* As of today we support DSC for only RGB */ - if (intel_dp->force_dsc_bpp) { - if (intel_dp->force_dsc_bpp >= 8 && - intel_dp->force_dsc_bpp < pipe_bpp) { - drm_dbg_kms(&dev_priv->drm, - "DSC BPP forced to %d", - intel_dp->force_dsc_bpp); - pipe_config->dsc.compressed_bpp = - intel_dp->force_dsc_bpp; - } else { - drm_dbg_kms(&dev_priv->drm, - "Invalid DSC BPP %d", - intel_dp->force_dsc_bpp); - } - } - /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even * then we need to use 2 VDSC instances. */ - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || - pipe_config->bigjoiner_pipes) { - if (pipe_config->dsc.slice_count < 2) { + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { + if (pipe_config->dsc.slice_count > 1) { + pipe_config->dsc.dsc_split = true; + } else { drm_dbg_kms(&dev_priv->drm, "Cannot split stream to use 2 VDSC instances\n"); return -EINVAL; } - - pipe_config->dsc.dsc_split = true; } ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); @@ -1633,7 +1621,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, str_yes_no(ret), str_yes_no(joiner_needs_dsc), str_yes_no(intel_dp->force_dsc_en)); ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, - conn_state, &limits); + conn_state, &limits, 1); if (ret < 0) return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index a54902c713a3..c6539a6915e9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -56,6 +56,11 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder); int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); @@ -96,6 +101,18 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots); +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner); +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 14d2a64193b2..b4d68c324e68 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -99,6 +99,84 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, return 0; } +static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + struct link_config_limits *limits) +{ + struct drm_atomic_state *state = crtc_state->uapi.state; + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); + struct intel_dp *intel_dp = &intel_mst->primary->dp; + struct intel_connector *connector = + to_intel_connector(conn_state->connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, + DP_DPCD_QUIRK_CONSTANT_N); + int bpp, slots = -EINVAL; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int min_bpp, max_bpp; + u8 dsc_max_bpc; + + crtc_state->lane_count = limits->max_lane_count; + crtc_state->port_clock = limits->max_rate; + + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ + if (DISPLAY_VER(i915) >= 12) + dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); + else + dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc); + + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp); + min_bpp = limits->min_bpp; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (max_bpp >= dsc_bpc[i] * 3) + if (min_bpp > dsc_bpc[i] * 3) + min_bpp = dsc_bpc[i] * 3; + } + + drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n", + min_bpp, max_bpp); + + for (bpp = max_bpp; bpp >= min_bpp; bpp -= 2 * 3) { + crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, + bpp << 4, + true); + + slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, + connector->port, + crtc_state->pbn, 0); + + drm_dbg_kms(&i915->drm, "Trying bpp %d got %d pbn %d slots\n", + bpp, crtc_state->pbn, slots); + + if (slots == -EDEADLK) + return slots; + if (slots >= 0) + break; + } + + if (slots < 0) { + drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", + slots); + return slots; + } + + intel_link_compute_m_n(crtc_state->pipe_bpp, + crtc_state->lane_count, + adjusted_mode->crtc_clock, + crtc_state->port_clock, + &crtc_state->dp_m_n, + constant_n, crtc_state->fec_enable); + crtc_state->dp_m_n.tu = slots; + + return 0; +} static int intel_dp_mst_update_slots(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -127,6 +205,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_atomic_state *state = pipe_config->uapi.state; struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); struct intel_dp *intel_dp = &intel_mst->primary->dp; struct intel_connector *connector = @@ -175,6 +254,38 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, ret = intel_dp_mst_compute_link_config(encoder, pipe_config, conn_state, &limits); + + if (ret == -EDEADLK) + return ret; + + /* + * We need to check if VCPI slots allocated can actually fit already + * here, to decide whether we use DSC or not. + * If either intel_dp_mst_compute_link_config or that one fails, + * then we try DSC as last resort. + */ + if (!ret) + ret = drm_dp_mst_atomic_check(state); + + /* enable compression if the mode doesn't fit available BW */ + drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); + if (ret || intel_dp->force_dsc_en) { + /* + * Try to get at least some timeslots and then see, if + * we can fit there with DSC. + */ + drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n"); + + ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config, + conn_state, &limits); + if (ret < 0) + return ret; + + ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, + conn_state, &limits, + pipe_config->dp_m_n.tu); + } + if (ret) return ret; @@ -713,6 +824,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; int ret; + bool dsc = false, bigjoiner = false; + u16 dsc_max_output_bpp = 0; + u8 dsc_slice_count = 0; + int target_clock = mode->clock; if (drm_connector_is_unregistered(connector)) { *status = MODE_ERROR; @@ -750,6 +865,48 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, return 0; } + if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { + bigjoiner = true; + max_dotclk *= 2; + } + + if (DISPLAY_VER(dev_priv) >= 10 && + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + /* + * TBD pass the connector BPC, + * for now U8_MAX so that max BPC on that platform would be picked + */ + int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + + if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + dsc_max_output_bpp = + intel_dp_dsc_get_output_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + pipe_bpp, 1) >> 4; + dsc_slice_count = + intel_dp_dsc_get_slice_count(intel_dp, + target_clock, + mode->hdisplay, + bigjoiner); + } + + dsc = dsc_max_output_bpp && dsc_slice_count; + } + + /* + * Big joiner configuration needs DSC for TGL which is not true for + * XE_LPD where uncompressed joiner is supported. + */ + if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) + return MODE_CLOCK_HIGH; + + if (mode_rate > max_rate && !dsc) + return MODE_CLOCK_HIGH; + *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); return 0; } -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-08-22 9:40 Stanislav Lisovskiy 0 siblings, 0 replies; 12+ messages in thread From: Stanislav Lisovskiy @ 2022-08-22 9:40 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 73 ++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 ++++++++++++++++++++ include/drm/display/drm_dp.h | 10 +- 4 files changed, 214 insertions(+), 43 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-08-10 8:17 Stanislav Lisovskiy 2022-08-10 20:02 ` Lyude Paul 0 siblings, 1 reply; 12+ messages in thread From: Stanislav Lisovskiy @ 2022-08-10 8:17 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 76 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 145 ++++++++++++++++++++ include/drm/display/drm_dp.h | 10 +- 4 files changed, 203 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/2] Add DP MST DSC support to i915 2022-08-10 8:17 Stanislav Lisovskiy @ 2022-08-10 20:02 ` Lyude Paul 2022-08-11 7:33 ` Lisovskiy, Stanislav 0 siblings, 1 reply; 12+ messages in thread From: Lyude Paul @ 2022-08-10 20:02 UTC (permalink / raw) To: Stanislav Lisovskiy, intel-gfx Cc: jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Btw, what's the plan for this? Figured I'd ask since I noticed this on the ML, nd I'm now finishing up getting the atomic only MST patches I've been working on merged :) On Wed, 2022-08-10 at 11:17 +0300, Stanislav Lisovskiy wrote: > Currently we have only DSC support for DP SST. > > Stanislav Lisovskiy (2): > drm: Add missing DP DSC extended capability definitions. > drm/i915: Add DSC support to MST path > > drivers/gpu/drm/i915/display/intel_dp.c | 76 +++++----- > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 145 ++++++++++++++++++++ > include/drm/display/drm_dp.h | 10 +- > 4 files changed, 203 insertions(+), 45 deletions(-) > -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/2] Add DP MST DSC support to i915 2022-08-10 20:02 ` Lyude Paul @ 2022-08-11 7:33 ` Lisovskiy, Stanislav 2022-08-11 18:11 ` Navare, Manasi 2022-08-11 19:54 ` Lyude Paul 0 siblings, 2 replies; 12+ messages in thread From: Lisovskiy, Stanislav @ 2022-08-11 7:33 UTC (permalink / raw) To: Lyude Paul Cc: jani.nikula, manasi.d.navare, intel-gfx, jani.saarinen, dri-devel On Wed, Aug 10, 2022 at 04:02:08PM -0400, Lyude Paul wrote: > Btw, what's the plan for this? Figured I'd ask since I noticed this on the ML, > nd I'm now finishing up getting the atomic only MST patches I've been working > on merged :) Current plan is that I need to fix this, as current implementation doesn't seem to work because of my wrong assumption that drm_dp_mst_find_vcpi_slots will fail if no slots are available and then we can fallback to DSC. In reality that function can return whatever bogus value it wants, like 71 slots, while you have only 63 available. The real check is done in drm_dp_mst_atomic_check, which would of course reject that configuration, however by that moment its going to be too late for swithcing to DSC. So looke like I will have to move that check at least partly to where DSC/no DSC decision is done. However if there are multiple displays we get another problem, lets say we have 2 displays requiring 40 vcpi slots each in DSC mode with certain input bpp. We have now either option to reject the whole config or go back and try with another bpp to check if we can reduce amount of slots. Because by default we choose the first one which fits, however by the time when compute_config is called, we still don't have all config computed, which might lead to that last crtc can either run our of vcpi slots or we will have to go back and try recalculating with higher compression ratio. My other question was that DSC was supposed to be "visually" lossless, wondering why we are still trying with different bpps? Could have just set highest compression ratio right away. So need to sort this out first before floating new series. Stan > > On Wed, 2022-08-10 at 11:17 +0300, Stanislav Lisovskiy wrote: > > Currently we have only DSC support for DP SST. > > > > Stanislav Lisovskiy (2): > > drm: Add missing DP DSC extended capability definitions. > > drm/i915: Add DSC support to MST path > > > > drivers/gpu/drm/i915/display/intel_dp.c | 76 +++++----- > > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 145 ++++++++++++++++++++ > > include/drm/display/drm_dp.h | 10 +- > > 4 files changed, 203 insertions(+), 45 deletions(-) > > > > -- > Cheers, > Lyude Paul (she/her) > Software Engineer at Red Hat > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/2] Add DP MST DSC support to i915 2022-08-11 7:33 ` Lisovskiy, Stanislav @ 2022-08-11 18:11 ` Navare, Manasi 2022-08-11 19:54 ` Lyude Paul 1 sibling, 0 replies; 12+ messages in thread From: Navare, Manasi @ 2022-08-11 18:11 UTC (permalink / raw) To: Lisovskiy, Stanislav; +Cc: jani.nikula, intel-gfx, jani.saarinen, dri-devel On Thu, Aug 11, 2022 at 10:33:51AM +0300, Lisovskiy, Stanislav wrote: > On Wed, Aug 10, 2022 at 04:02:08PM -0400, Lyude Paul wrote: > > Btw, what's the plan for this? Figured I'd ask since I noticed this on the ML, > > nd I'm now finishing up getting the atomic only MST patches I've been working > > on merged :) > > Current plan is that I need to fix this, as current implementation doesn't > seem to work because of my wrong assumption that drm_dp_mst_find_vcpi_slots > will fail if no slots are available and then we can fallback to DSC. > > In reality that function can return whatever bogus value it wants, like > 71 slots, while you have only 63 available. The real check is done in > drm_dp_mst_atomic_check, which would of course reject that configuration, > however by that moment its going to be too late for swithcing to DSC. > > So looke like I will have to move that check at least partly to where DSC/no DSC decision is done. However if there are multiple displays we get > another problem, lets say we have 2 displays requiring 40 vcpi slots each in DSC > mode with certain input bpp. > We have now either option to reject the whole config or go back and try with > another bpp to check if we can reduce amount of slots. > Because by default we choose the first one which fits, however by the time when > compute_config is called, we still don't have all config computed, which might > lead to that last crtc can either run our of vcpi slots or we will have to > go back and try recalculating with higher compression ratio. > > My other question was that DSC was supposed to be "visually" lossless, wondering > why we are still trying with different bpps? Could have just set highest > compression ratio right away. We do want to still maintain as high pic quality as possible. So we try to find out the min compression ration that will make the mode fit into the available link BW. Manasi > > So need to sort this out first before floating new series. > > Stan > > > > > On Wed, 2022-08-10 at 11:17 +0300, Stanislav Lisovskiy wrote: > > > Currently we have only DSC support for DP SST. > > > > > > Stanislav Lisovskiy (2): > > > drm: Add missing DP DSC extended capability definitions. > > > drm/i915: Add DSC support to MST path > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 76 +++++----- > > > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 145 ++++++++++++++++++++ > > > include/drm/display/drm_dp.h | 10 +- > > > 4 files changed, 203 insertions(+), 45 deletions(-) > > > > > > > -- > > Cheers, > > Lyude Paul (she/her) > > Software Engineer at Red Hat > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/2] Add DP MST DSC support to i915 2022-08-11 7:33 ` Lisovskiy, Stanislav 2022-08-11 18:11 ` Navare, Manasi @ 2022-08-11 19:54 ` Lyude Paul 1 sibling, 0 replies; 12+ messages in thread From: Lyude Paul @ 2022-08-11 19:54 UTC (permalink / raw) To: Lisovskiy, Stanislav Cc: jani.nikula, manasi.d.navare, intel-gfx, jani.saarinen, dri-devel On Thu, 2022-08-11 at 10:33 +0300, Lisovskiy, Stanislav wrote: > On Wed, Aug 10, 2022 at 04:02:08PM -0400, Lyude Paul wrote: > > Btw, what's the plan for this? Figured I'd ask since I noticed this on the ML, > > nd I'm now finishing up getting the atomic only MST patches I've been working > > on merged :) > > Current plan is that I need to fix this, as current implementation doesn't > seem to work because of my wrong assumption that drm_dp_mst_find_vcpi_slots > will fail if no slots are available and then we can fallback to DSC. > > In reality that function can return whatever bogus value it wants, like > 71 slots, while you have only 63 available. The real check is done in > drm_dp_mst_atomic_check, which would of course reject that configuration, > however by that moment its going to be too late for swithcing to DSC. > Yeah - the drm_dp_mst_find_vcpi_slots() bit is intentional, as we need to be able to ensure that calls to it are idempotent since it may be called multiple times. We also don't actually know whether or not we've gone past the max number of slots until atomic check since there's not necessarily a guarantee towards which order we process disabling CRTCs and process enabling them, hence why we wait towards the end to check this. The eventual plan that I'd like to see happen is to basically teach drm_dp_mst_atomic_check() to indicate when a display state needs to be recalculated in order to fit into the current bandwidth limitations. There's a number of ways we could accomplish this, one I've been thinking about in particular is maybe having drivers provide a minimum and maximum bandwidth value, so that we could also have the helpers indicate to the driver which sinks can be recalculated. Also FWIW: the reason I've been working on: https://patchwork.freedesktop.org/series/107073/ Is to make all of this easier by making sure all of the payload info is in the MST atomic state. > So looke like I will have to move that check at least partly to where DSC/no DSC decision is done. However if there are multiple displays we get > another problem, lets say we have 2 displays requiring 40 vcpi slots each in DSC > mode with certain input bpp. > We have now either option to reject the whole config or go back and try with > another bpp to check if we can reduce amount of slots. > Because by default we choose the first one which fits, however by the time when > compute_config is called, we still don't have all config computed, which might > lead to that last crtc can either run our of vcpi slots or we will have to > go back and try recalculating with higher compression ratio. Having to go back and recalculate with a higher compression ratio is to be expected to some extent I'm fairly sure, as I don't really think there's any other sensible way we could figure this out besides recalculating the state multiple times. Keep in mind too - doing stuff like calling a CRTC's atomic check multiple times is totally normal and expected to work in DRM anyhow. > > My other question was that DSC was supposed to be "visually" lossless, wondering > why we are still trying with different bpps? Could have just set highest > compression ratio right away. I think this is a misunderstanding, at least while talking to AMD the impression I've gotten is that DSC isn't actually totally loseless - which is why their driver currently tries to use the least amount of compression possible. Otherwise I would say we should just enable it at max all of the time. Also, annoyingly most of the logic for doing this is currently stuck in amdgpu's driver. but please feel free to move it out into helpers! If we want good DSC support that's definitely going to help quite a bunch since they've worked out a lot of this already, and there's probably even improvements we can make upon their logic. > > So need to sort this out first before floating new series. > > Stan > > > > > On Wed, 2022-08-10 at 11:17 +0300, Stanislav Lisovskiy wrote: > > > Currently we have only DSC support for DP SST. > > > > > > Stanislav Lisovskiy (2): > > > drm: Add missing DP DSC extended capability definitions. > > > drm/i915: Add DSC support to MST path > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 76 +++++----- > > > drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 145 ++++++++++++++++++++ > > > include/drm/display/drm_dp.h | 10 +- > > > 4 files changed, 203 insertions(+), 45 deletions(-) > > > > > > > -- > > Cheers, > > Lyude Paul (she/her) > > Software Engineer at Red Hat > > > -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-04-11 16:25 Stanislav Lisovskiy 0 siblings, 0 replies; 12+ messages in thread From: Stanislav Lisovskiy @ 2022-04-11 16:25 UTC (permalink / raw) To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.nikula, dri-devel, jani.saarinen Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 75 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 10 +- 4 files changed, 200 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-03-21 9:10 Stanislav Lisovskiy 0 siblings, 0 replies; 12+ messages in thread From: Stanislav Lisovskiy @ 2022-03-21 9:10 UTC (permalink / raw) To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/dp/drm_dp.c | 25 ++++ drivers/gpu/drm/i915/display/intel_dp.c | 75 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 11 +- 5 files changed, 226 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-03-17 16:33 Stanislav Lisovskiy 0 siblings, 0 replies; 12+ messages in thread From: Stanislav Lisovskiy @ 2022-03-17 16:33 UTC (permalink / raw) To: intel-gfx; +Cc: manasi.d.navare, Stanislav.Lisovskiy, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/dp/drm_dp.c | 25 ++++ drivers/gpu/drm/i915/display/intel_dp.c | 138 ++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 146 +++++++++++++++++++- include/drm/dp/drm_dp_helper.h | 11 +- 5 files changed, 320 insertions(+), 17 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-08-22 9:40 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-08-15 17:35 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-08-15 17:35 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-08-15 17:35 ` [PATCH 2/2] drm/i915: Add DSC support to MST path Stanislav Lisovskiy -- strict thread matches above, loose matches on Subject: below -- 2022-08-22 9:40 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-08-10 8:17 Stanislav Lisovskiy 2022-08-10 20:02 ` Lyude Paul 2022-08-11 7:33 ` Lisovskiy, Stanislav 2022-08-11 18:11 ` Navare, Manasi 2022-08-11 19:54 ` Lyude Paul 2022-04-11 16:25 Stanislav Lisovskiy 2022-03-21 9:10 Stanislav Lisovskiy 2022-03-17 16:33 Stanislav Lisovskiy
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