From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [PATCH v2 13/21] drm/i915: Extract wm latency adjustment to its own function
Date: Thu, 18 Aug 2022 16:41:54 -0700 [thread overview]
Message-ID: <20220818234202.451742-14-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20220818234202.451742-1-radhakrishna.sripada@intel.com>
Watermark latency is adjusted in cases when latency is 0us for level
greater than 1, the subsequent levels are disabled. Extract this logic
into its own function.
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 88 ++++++++++++++++++---------------
1 file changed, 48 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef7553b494ea..898e56d2eaf7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2861,15 +2861,59 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
result->enable = true;
}
+static void
+adjust_wm_latency(u16 wm[], int max_level, int read_latency,
+ bool wm_lv_0_adjust_needed)
+{
+ int i, level;
+
+ /*
+ * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
+ * need to be disabled. We make sure to sanitize the values out
+ * of the punit to satisfy this requirement.
+ */
+ for (level = 1; level <= max_level; level++) {
+ if (wm[level] == 0) {
+ for (i = level + 1; i <= max_level; i++)
+ wm[i] = 0;
+
+ max_level = level - 1;
+ break;
+ }
+ }
+
+ /*
+ * WaWmMemoryReadLatency
+ *
+ * punit doesn't take into account the read latency so we need
+ * to add proper adjustement to each valid level we retrieve
+ * from the punit when level 0 response data is 0us.
+ */
+ if (wm[0] == 0) {
+ for (level = 0; level <= max_level; level++)
+ wm[level] += read_latency;
+ }
+
+ /*
+ * WA Level-0 adjustment for 16GB DIMMs: SKL+
+ * If we could not get dimm info enable this WA to prevent from
+ * any underrun. If not able to get Dimm info assume 16GB dimm
+ * to avoid any underrun.
+ */
+ if (wm_lv_0_adjust_needed)
+ wm[0] += 1;
+}
+
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
u16 wm[])
{
struct intel_uncore *uncore = &dev_priv->uncore;
if (DISPLAY_VER(dev_priv) >= 9) {
+ int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
u32 val;
- int ret, i;
- int level, max_level = ilk_wm_max_level(dev_priv);
+ int ret;
+ int max_level = ilk_wm_max_level(dev_priv);
int mult = IS_DG2(dev_priv) ? 2 : 1;
/* read the first set of memory latencies[0:3] */
@@ -2909,44 +2953,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
- /*
- * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
- * need to be disabled. We make sure to sanitize the values out
- * of the punit to satisfy this requirement.
- */
- for (level = 1; level <= max_level; level++) {
- if (wm[level] == 0) {
- for (i = level + 1; i <= max_level; i++)
- wm[i] = 0;
-
- max_level = level - 1;
-
- break;
- }
- }
-
- /*
- * WaWmMemoryReadLatency
- *
- * punit doesn't take into account the read latency so we need
- * to add proper adjustement to each valid level we retrieve
- * from the punit when level 0 response data is 0us.
- */
- if (wm[0] == 0) {
- u8 adjust = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
-
- for (level = 0; level <= max_level; level++)
- wm[level] += adjust;
- }
-
- /*
- * WA Level-0 adjustment for 16GB DIMMs: SKL+
- * If we could not get dimm info enable this WA to prevent from
- * any underrun. If not able to get Dimm info assume 16GB dimm
- * to avoid any underrun.
- */
- if (dev_priv->dram_info.wm_lv_0_adjust_needed)
- wm[0] += 1;
+ adjust_wm_latency(wm, max_level, read_latency,
+ dev_priv->dram_info.wm_lv_0_adjust_needed);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
--
2.25.1
next prev parent reply other threads:[~2022-08-18 23:43 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 23:41 [PATCH v2 00/21] Initial Meteorlake Support Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 01/21] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
2022-08-19 19:04 ` [Intel-gfx] " Matt Roper
2022-08-24 10:10 ` Jani Nikula
2022-08-18 23:41 ` [PATCH v2 02/21] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
2022-08-24 8:11 ` [Intel-gfx] " Balasubramani Vivekanandan
2022-08-18 23:41 ` [PATCH v2 03/21] drm/i915/mtl: MMIO range is now 4MB Radhakrishna Sripada
2022-08-24 13:25 ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [PATCH v2 04/21] drm/i915/mtl: Don't mask off CCS according to DSS fusing Radhakrishna Sripada
2022-08-24 14:54 ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [PATCH v2 05/21] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-08-25 10:33 ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [PATCH v2 06/21] drm/i915/mtl: Add PCH support Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 07/21] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
2022-08-19 19:17 ` Matt Roper
2022-08-18 23:41 ` [PATCH v2 08/21] drm/i915/mtl: Add VBT port and AUX_CH mapping Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 09/21] drm/i915/mtl: Add support for MTL in Display Init sequences Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 10/21] drm/i915/mtl: Add display power wells Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 11/21] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 12/21] drm/i915/mtl: Fix rawclk for Meteorlake PCH Radhakrishna Sripada
2022-08-18 23:41 ` Radhakrishna Sripada [this message]
2022-08-19 19:26 ` [PATCH v2 13/21] drm/i915: Extract wm latency adjustment to its own function Matt Roper
2022-08-18 23:41 ` [PATCH v2 14/21] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM Radhakrishna Sripada
2022-08-19 19:31 ` Matt Roper
2022-08-18 23:41 ` [PATCH v2 15/21] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
2022-08-27 0:03 ` Matt Roper
2022-08-18 23:41 ` [PATCH v2 16/21] drm/i915/mtl: Update memory bandwidth parameters Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 17/21] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 18/21] drm/i915/mtl: Reuse adl-p DBUF calculations Radhakrishna Sripada
2022-08-18 23:42 ` [PATCH v2 19/21] drm/i915/display/mtl: Extend MBUS programming Radhakrishna Sripada
2022-08-18 23:42 ` [PATCH v2 20/21] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
2022-08-18 23:42 ` [PATCH v2 21/21] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
2022-08-19 19:46 ` [Intel-gfx] " Matt Roper
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