From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
To: Radhakrishna Sripada <radhakrishna.sripada@intel.com>,
<intel-gfx@lists.freedesktop.org>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v2 05/21] drm/i915/mtl: Define engine context layouts
Date: Thu, 25 Aug 2022 16:03:40 +0530 [thread overview]
Message-ID: <YwdQBIViVSqNQ0pv@bala-ubuntu> (raw)
In-Reply-To: <20220818234202.451742-6-radhakrishna.sripada@intel.com>
On 18.08.2022 16:41, Radhakrishna Sripada wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> The part of the media and blitter engine contexts that we care about for
> setting up an initial state are the same on MTL as they were on DG2
> (and PVC), so we need to update the driver conditions to re-use the DG2
> context table.
>
> For render/compute engines, the part of the context images are nearly
> the same, although the layout had a very slight change --- one POSH
> register was removed and the placement of some LRI/noops adjusted
> slightly to compensate.
>
> Bspec: 46261, 46260, 45585
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 47 ++++++++++++++++++++++++++++-
> 1 file changed, 46 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index eec73c66406c..d3833cbaabcb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -606,6 +606,49 @@ static const u8 dg2_rcs_offsets[] = {
> END
> };
>
> +static const u8 mtl_rcs_offsets[] = {
> + NOP(1),
> + LRI(15, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
Inspecting Bspecs 46261 and 46260 indicates the following 2 registers
are replaced by NOP for MTL. Can you check?
> + REG(0x120),
> + REG(0x124),
> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + NOP(2),
> + LRI(2, POSTED),
> + REG16(0x5a8),
> + REG16(0x5ac),
> +
> + NOP(6),
> + LRI(1, 0),
> + REG(0x0c8),
> +
> + END
> +};
> +
> #undef END
> #undef REG16
> #undef REG
> @@ -624,7 +667,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> !intel_engine_has_relative_mmio(engine));
>
> if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> + return mtl_rcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_rcs_offsets;
> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> return xehp_rcs_offsets;
Similarly from Bpsec 45582, the same 2 registers indicated above is
replaced by NOP even in Copy and Blitter engine contexts in MTL compared
to DG2. So we have to create a new structure for MTL for Copy and Media
engine contexts.
Regards,
Bala
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-08-25 10:33 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 23:41 [PATCH v2 00/21] Initial Meteorlake Support Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 01/21] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
2022-08-19 19:04 ` [Intel-gfx] " Matt Roper
2022-08-24 10:10 ` Jani Nikula
2022-08-18 23:41 ` [PATCH v2 02/21] drm/i915: Parse and set stepping for platforms with GMD Radhakrishna Sripada
2022-08-24 8:11 ` [Intel-gfx] " Balasubramani Vivekanandan
2022-08-18 23:41 ` [PATCH v2 03/21] drm/i915/mtl: MMIO range is now 4MB Radhakrishna Sripada
2022-08-24 13:25 ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [PATCH v2 04/21] drm/i915/mtl: Don't mask off CCS according to DSS fusing Radhakrishna Sripada
2022-08-24 14:54 ` Balasubramani Vivekanandan
2022-08-18 23:41 ` [PATCH v2 05/21] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-08-25 10:33 ` Balasubramani Vivekanandan [this message]
2022-08-18 23:41 ` [PATCH v2 06/21] drm/i915/mtl: Add PCH support Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 07/21] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
2022-08-19 19:17 ` Matt Roper
2022-08-18 23:41 ` [PATCH v2 08/21] drm/i915/mtl: Add VBT port and AUX_CH mapping Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 09/21] drm/i915/mtl: Add support for MTL in Display Init sequences Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 10/21] drm/i915/mtl: Add display power wells Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 11/21] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 12/21] drm/i915/mtl: Fix rawclk for Meteorlake PCH Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 13/21] drm/i915: Extract wm latency adjustment to its own function Radhakrishna Sripada
2022-08-19 19:26 ` Matt Roper
2022-08-18 23:41 ` [PATCH v2 14/21] drm/i915/mtl: memory latency data from LATENCY_LPX_LPY for WM Radhakrishna Sripada
2022-08-19 19:31 ` Matt Roper
2022-08-18 23:41 ` [PATCH v2 15/21] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
2022-08-27 0:03 ` Matt Roper
2022-08-18 23:41 ` [PATCH v2 16/21] drm/i915/mtl: Update memory bandwidth parameters Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 17/21] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
2022-08-18 23:41 ` [PATCH v2 18/21] drm/i915/mtl: Reuse adl-p DBUF calculations Radhakrishna Sripada
2022-08-18 23:42 ` [PATCH v2 19/21] drm/i915/display/mtl: Extend MBUS programming Radhakrishna Sripada
2022-08-18 23:42 ` [PATCH v2 20/21] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
2022-08-18 23:42 ` [PATCH v2 21/21] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
2022-08-19 19:46 ` [Intel-gfx] " Matt Roper
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