* [PATCH 0/8] i915: Add "standalone media" support for MTL
@ 2022-08-29 17:02 Matt Roper
2022-08-29 17:02 ` [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume} Matt Roper
` (7 more replies)
0 siblings, 8 replies; 18+ messages in thread
From: Matt Roper @ 2022-08-29 17:02 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, radhakrishna.sripada
Starting with MTL, media functionality has moved into a new, second GT
at the hardware level. This new GT, referred to as "standalone media"
in the spec, has its own GuC, power management/forcewake, etc. The
general non-engine GT registers for standalone media start at 0x380000,
but otherwise use the same MMIO offsets as the primary GT.
Standalone media has a lot of similarity to the remote tiles
present on platforms like xehpsdv and pvc, and our i915 implementation
can share much of the general "multi GT" infrastructure between the two
types of platforms. However there are a few notable differences
we must deal with:
- The 0x380000 offset only applies to the non-engine GT registers
(which the specs refer to as "GSI" registers). The engine registers
remain at their usual locations (e.g., 0x1C0000 for VCS0).
- Unlike platforms with remote tiles, all interrupt handling for
standalone media still happens via the primary GT.
Matt Roper (8):
drm/i915: Move locking and unclaimed check into
mmio_debug_{suspend,resume}
drm/i915: Only hook up uncore->debug for primary uncore
drm/i915: Use managed allocations for extra uncore objects
drm/i915: Prepare more multi-GT initialization
drm/i915: Rename and expose common GT early init routine
drm/i915/xelpmp: Expose media as another GT
drm/i915/mtl: Use primary GT's irq lock for media GT
drm/i915/mtl: Hook up interrupts for standalone media
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 +--
drivers/gpu/drm/i915/gt/intel_gt.c | 88 ++++++++++++++-----
drivers/gpu/drm/i915/gt/intel_gt.h | 4 +-
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 35 ++++++--
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 8 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 10 +++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 26 +++---
drivers/gpu/drm/i915/gt/intel_sa_media.c | 47 ++++++++++
drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 ++++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 24 ++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_driver.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_pci.c | 15 ++++
drivers/gpu/drm/i915/intel_device_info.h | 19 ++++
drivers/gpu/drm/i915/intel_uncore.c | 80 +++++++++++------
drivers/gpu/drm/i915/intel_uncore.h | 23 ++++-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +-
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 14 +--
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 4 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
25 files changed, 340 insertions(+), 116 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
--
2.37.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume}
2022-08-29 17:02 [PATCH 0/8] i915: Add "standalone media" support for MTL Matt Roper
@ 2022-08-29 17:02 ` Matt Roper
2022-08-30 22:49 ` [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend,resume} Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 2/8] drm/i915: Only hook up uncore->debug for primary uncore Matt Roper
` (6 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Matt Roper @ 2022-08-29 17:02 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, radhakrishna.sripada
Moving the locking for MMIO debug (and the final check for unclaimed
accesses when resuming debug after a userspace-initiated forcewake) will
make it simpler to completely skip MMIO debug handling on uncores that
don't support it in future patches.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 41 +++++++++++++++--------------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 9b81b2543ce2..e717ea55484a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -50,23 +50,33 @@ intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
mmio_debug->unclaimed_mmio_check = 1;
}
-static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug)
+static void mmio_debug_suspend(struct intel_uncore *uncore)
{
- lockdep_assert_held(&mmio_debug->lock);
+ spin_lock(&uncore->debug->lock);
/* Save and disable mmio debugging for the user bypass */
- if (!mmio_debug->suspend_count++) {
- mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check;
- mmio_debug->unclaimed_mmio_check = 0;
+ if (!uncore->debug->suspend_count++) {
+ uncore->debug->saved_mmio_check = uncore->debug->unclaimed_mmio_check;
+ uncore->debug->unclaimed_mmio_check = 0;
}
+
+ spin_unlock(&uncore->debug->lock);
}
-static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
+static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);
+
+static void mmio_debug_resume(struct intel_uncore *uncore)
{
- lockdep_assert_held(&mmio_debug->lock);
+ spin_lock(&uncore->debug->lock);
+
+ if (!--uncore->debug->suspend_count)
+ uncore->debug->unclaimed_mmio_check = uncore->debug->saved_mmio_check;
- if (!--mmio_debug->suspend_count)
- mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check;
+ if (check_for_unclaimed_mmio(uncore))
+ drm_info(&uncore->i915->drm,
+ "Invalid mmio detected during user access\n");
+
+ spin_unlock(&uncore->debug->lock);
}
static const char * const forcewake_domain_names[] = {
@@ -677,9 +687,7 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
spin_lock_irq(&uncore->lock);
if (!uncore->user_forcewake_count++) {
intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
- spin_lock(&uncore->debug->lock);
- mmio_debug_suspend(uncore->debug);
- spin_unlock(&uncore->debug->lock);
+ mmio_debug_suspend(uncore);
}
spin_unlock_irq(&uncore->lock);
}
@@ -695,14 +703,7 @@ void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
{
spin_lock_irq(&uncore->lock);
if (!--uncore->user_forcewake_count) {
- spin_lock(&uncore->debug->lock);
- mmio_debug_resume(uncore->debug);
-
- if (check_for_unclaimed_mmio(uncore))
- drm_info(&uncore->i915->drm,
- "Invalid mmio detected during user access\n");
- spin_unlock(&uncore->debug->lock);
-
+ mmio_debug_resume(uncore);
intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
}
spin_unlock_irq(&uncore->lock);
--
2.37.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/8] drm/i915: Only hook up uncore->debug for primary uncore
2022-08-29 17:02 [PATCH 0/8] i915: Add "standalone media" support for MTL Matt Roper
2022-08-29 17:02 ` [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume} Matt Roper
@ 2022-08-29 17:02 ` Matt Roper
2022-08-31 0:01 ` Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 3/8] drm/i915: Use managed allocations for extra uncore objects Matt Roper
` (5 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Matt Roper @ 2022-08-29 17:02 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, radhakrishna.sripada
The original intent of intel_uncore_mmio_debug as described in commit
0a9b26306d6a ("drm/i915: split out uncore_mmio_debug") was to be a
singleton structure that could be shared between multiple GTs' uncore
objects in a multi-tile system. Somehow we went off track and
started allocating separate instances of this structure for each GT,
which defeats that original goal.
But in reality, there isn't even a need to share the mmio_debug between
multiple GTs; on all modern platforms (i.e., everything after gen7)
unclaimed register accesses are something that can only be detected for
display registers. There's no point in grabbing the debug spinlock and
checking for unclaimed accesses on an uncore used by an xehpsdv or pvc
remote tile GT, or the uncore used by a mtl standalone media GT since
all of the display accesses go through the primary intel_uncore.
The simplest solution is to simply leave uncore->debug NULL on all
intel_uncore instances except for the primary one. This will allow us
to avoid the pointless debug spinlock acquisition we've been doing on
MMIO accesses coming in through these intel_uncores.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 9 ---------
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 23 ++++++++++++++++++-----
drivers/gpu/drm/i915/intel_uncore.h | 3 +--
4 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index e4bac2431e41..a82b5e2e0d83 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -781,21 +781,13 @@ static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
int ret;
if (!gt_is_root(gt)) {
- struct intel_uncore_mmio_debug *mmio_debug;
struct intel_uncore *uncore;
uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
if (!uncore)
return -ENOMEM;
- mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
- if (!mmio_debug) {
- kfree(uncore);
- return -ENOMEM;
- }
-
gt->uncore = uncore;
- gt->uncore->debug = mmio_debug;
__intel_gt_init_early(gt);
}
@@ -817,7 +809,6 @@ intel_gt_tile_cleanup(struct intel_gt *gt)
intel_uncore_cleanup_mmio(gt->uncore);
if (!gt_is_root(gt)) {
- kfree(gt->uncore->debug);
kfree(gt->uncore);
kfree(gt);
}
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 053a7dab5506..de9020771836 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -326,7 +326,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
intel_device_info_subplatform_init(dev_priv);
intel_step_init(dev_priv);
- intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
+ intel_uncore_mmio_debug_init_early(dev_priv);
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e717ea55484a..6841f76533f9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -44,14 +44,19 @@ fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
}
void
-intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
+intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
{
- spin_lock_init(&mmio_debug->lock);
- mmio_debug->unclaimed_mmio_check = 1;
+ spin_lock_init(&i915->mmio_debug.lock);
+ i915->mmio_debug.unclaimed_mmio_check = 1;
+
+ i915->uncore.debug = &i915->mmio_debug;
}
static void mmio_debug_suspend(struct intel_uncore *uncore)
{
+ if (!uncore->debug)
+ return;
+
spin_lock(&uncore->debug->lock);
/* Save and disable mmio debugging for the user bypass */
@@ -67,6 +72,9 @@ static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);
static void mmio_debug_resume(struct intel_uncore *uncore)
{
+ if (!uncore->debug)
+ return;
+
spin_lock(&uncore->debug->lock);
if (!--uncore->debug->suspend_count)
@@ -1705,7 +1713,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
const bool read,
const bool before)
{
- if (likely(!uncore->i915->params.mmio_debug))
+ if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug)
return;
/* interrupts are disabled and re-enabled around uncore->lock usage */
@@ -2267,7 +2275,6 @@ void intel_uncore_init_early(struct intel_uncore *uncore,
uncore->i915 = gt->i915;
uncore->gt = gt;
uncore->rpm = >->i915->runtime_pm;
- uncore->debug = >->i915->mmio_debug;
}
static void uncore_raw_init(struct intel_uncore *uncore)
@@ -2578,6 +2585,9 @@ bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
{
bool ret;
+ if (!uncore->debug)
+ return false;
+
spin_lock_irq(&uncore->debug->lock);
ret = check_for_unclaimed_mmio(uncore);
spin_unlock_irq(&uncore->debug->lock);
@@ -2590,6 +2600,9 @@ intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
{
bool ret = false;
+ if (drm_WARN_ON(&uncore->i915->drm, !uncore->debug))
+ return false;
+
spin_lock_irq(&uncore->debug->lock);
if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index b1fa912a65e7..6100d0f4498a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -210,8 +210,7 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore)
return uncore->flags & UNCORE_HAS_FIFO;
}
-void
-intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
+void intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915);
void intel_uncore_init_early(struct intel_uncore *uncore,
struct intel_gt *gt);
int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
--
2.37.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/8] drm/i915: Use managed allocations for extra uncore objects
2022-08-29 17:02 [PATCH 0/8] i915: Add "standalone media" support for MTL Matt Roper
2022-08-29 17:02 ` [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume} Matt Roper
2022-08-29 17:02 ` [PATCH 2/8] drm/i915: Only hook up uncore->debug for primary uncore Matt Roper
@ 2022-08-29 17:02 ` Matt Roper
2022-08-31 0:03 ` Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 4/8] drm/i915: Prepare more multi-GT initialization Matt Roper
` (4 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Matt Roper @ 2022-08-29 17:02 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, radhakrishna.sripada
We're slowly transitioning the init-time kzalloc's of the driver over to
DRM-managed allocations; let's make sure the uncore objects allocated
for non-root GTs are thus allocated.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index a82b5e2e0d83..cf7aab7adb30 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -783,7 +783,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
if (!gt_is_root(gt)) {
struct intel_uncore *uncore;
- uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
+ uncore = drmm_kzalloc(>->i915->drm, sizeof(*uncore), GFP_KERNEL);
if (!uncore)
return -ENOMEM;
@@ -808,10 +808,8 @@ intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
- if (!gt_is_root(gt)) {
- kfree(gt->uncore);
+ if (!gt_is_root(gt))
kfree(gt);
- }
}
int intel_gt_probe_all(struct drm_i915_private *i915)
--
2.37.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/8] drm/i915: Prepare more multi-GT initialization
2022-08-29 17:02 [PATCH 0/8] i915: Add "standalone media" support for MTL Matt Roper
` (2 preceding siblings ...)
2022-08-29 17:02 ` [PATCH 3/8] drm/i915: Use managed allocations for extra uncore objects Matt Roper
@ 2022-08-29 17:02 ` Matt Roper
2022-08-29 20:46 ` [PATCH v2 " Matt Roper
2022-08-31 0:27 ` [PATCH " Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 5/8] drm/i915: Rename and expose common GT early init routine Matt Roper
` (3 subsequent siblings)
7 siblings, 2 replies; 18+ messages in thread
From: Matt Roper @ 2022-08-29 17:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Aravind Iddamsetty, dri-devel, radhakrishna.sripada
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
immediate MTL media enabling, this same framework will also be used
farther down the road when we enable remote tiles on xehpsdv and pvc.
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 48 +++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_gt.h | 1 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 16 +++++++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
7 files changed, 67 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..41acc285e8bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index cf7aab7adb30..7c0525e96155 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -807,17 +807,16 @@ static void
intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
-
- if (!gt_is_root(gt))
- kfree(gt);
}
int intel_gt_probe_all(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_gt *gt = &i915->gt0;
+ const struct intel_gt_definition *gtdef;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
@@ -828,14 +827,55 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
* and it has been already initialized early during probe
* in i915_driver_probe()
*/
+ gt->i915 = i915;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
i915->gt[0] = gt;
- /* TODO: add more tiles */
+ for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
+ gtdef->setup != NULL;
+ i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
+ gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ gt->i915 = i915;
+ gt->name = gtdef->name;
+ gt->type = gtdef->type;
+ gt->info.engine_mask = gtdef->engine_mask;
+ gt->info.id = i;
+
+ drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
+ if (GEM_WARN_ON(range_overflows_t(resource_size_t,
+ gtdef->mapping_base,
+ SZ_16M,
+ pci_resource_len(pdev, mmio_bar)))) {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ if (ret)
+ goto err;
+
+ i915->gt[i] = gt;
+ }
+
return 0;
+
+err:
+ i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
+ intel_gt_release_all(i915);
+
+ return ret;
}
int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 40b06adf509a..4d8779529cc2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
-
void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 4d56f7d5a3be..3bd36caee321 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -83,6 +83,9 @@ struct gt_defaults {
struct intel_gt {
struct drm_i915_private *i915;
+ const char *name;
+ enum intel_gt_type type;
+
struct intel_uncore *uncore;
struct i915_ggtt *ggtt;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 443ed6dac92a..d45dca70bfa6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1061,6 +1061,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
+
/*
* Platform has the dedicated compression control state for each lmem surfaces
* stored in lmem to support the 3D and media compression formats.
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 0ccde94b225f..e0b79dc0fccc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -244,6 +244,20 @@ struct intel_runtime_info {
};
};
+enum intel_gt_type {
+ GT_PRIMARY,
+ GT_TILE,
+};
+
+struct intel_gt_definition {
+ enum intel_gt_type type;
+ char *name;
+ int (*setup)(struct intel_gt *gt,
+ phys_addr_t phys_addr);
+ u32 mapping_base;
+ intel_engine_mask_t engine_mask;
+};
+
struct intel_device_info {
struct ip_version media;
@@ -251,6 +265,8 @@ struct intel_device_info {
unsigned int dma_mask_size; /* available DMA address bits */
+ const struct intel_gt_definition *extra_gt_list;
+
u8 gt; /* GT number, 0 if undefined */
#define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index f5904e659ef2..915d58ba383e 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -115,6 +115,7 @@ static struct dev_pm_domain pm_domain = {
static void mock_gt_probe(struct drm_i915_private *i915)
{
i915->gt[0] = &i915->gt0;
+ i915->gt[0]->name = "Mock GT";
}
struct drm_i915_private *mock_gem_device(void)
--
2.37.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/8] drm/i915: Rename and expose common GT early init routine
2022-08-29 17:02 [PATCH 0/8] i915: Add "standalone media" support for MTL Matt Roper
` (3 preceding siblings ...)
2022-08-29 17:02 ` [PATCH 4/8] drm/i915: Prepare more multi-GT initialization Matt Roper
@ 2022-08-29 17:02 ` Matt Roper
2022-08-31 0:33 ` Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 6/8] drm/i915/xelpmp: Expose media as another GT Matt Roper
` (2 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Matt Roper @ 2022-08-29 17:02 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, radhakrishna.sripada
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 7c0525e96155..d21ec11346a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -35,7 +35,7 @@
#include "intel_uncore.h"
#include "shmem_utils.h"
-static void __intel_gt_init_early(struct intel_gt *gt)
+void intel_gt_common_init_early(struct intel_gt *gt)
{
spin_lock_init(>->irq_lock);
@@ -65,7 +65,7 @@ void intel_root_gt_init_early(struct drm_i915_private *i915)
gt->i915 = i915;
gt->uncore = &i915->uncore;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -789,7 +789,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
gt->uncore = uncore;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
intel_uncore_init_early(gt->uncore, gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 4d8779529cc2..c9a359f35d0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -44,6 +44,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
return container_of(gsc, struct intel_gt, gsc);
}
+void intel_gt_common_init_early(struct intel_gt *gt);
void intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
--
2.37.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 6/8] drm/i915/xelpmp: Expose media as another GT
2022-08-29 17:02 [PATCH 0/8] i915: Add "standalone media" support for MTL Matt Roper
` (4 preceding siblings ...)
2022-08-29 17:02 ` [PATCH 5/8] drm/i915: Rename and expose common GT early init routine Matt Roper
@ 2022-08-29 17:02 ` Matt Roper
2022-09-01 23:31 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-29 17:02 ` [PATCH 7/8] drm/i915/mtl: Use primary GT's irq lock for media GT Matt Roper
2022-08-29 17:02 ` [PATCH 8/8] drm/i915/mtl: Hook up interrupts for standalone media Matt Roper
7 siblings, 1 reply; 18+ messages in thread
From: Matt Roper @ 2022-08-29 17:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Aravind Iddamsetty, dri-devel, radhakrishna.sripada
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++++++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++++
drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 ++++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +++++++++
drivers/gpu/drm/i915/i915_pci.c | 15 +++++++++
drivers/gpu/drm/i915/intel_device_info.h | 5 ++-
drivers/gpu/drm/i915/intel_uncore.c | 16 ++++++++--
drivers/gpu/drm/i915/intel_uncore.h | 20 ++++++++++--
9 files changed, 123 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..e83e4cd46968 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -123,6 +123,7 @@ gt-y += \
gt/intel_ring.o \
gt/intel_ring_submission.o \
gt/intel_rps.o \
+ gt/intel_sa_media.o \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index d21ec11346a5..2a29502289cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -776,10 +776,15 @@ void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
}
}
-static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
+static int intel_gt_tile_setup(struct intel_gt *gt,
+ phys_addr_t phys_addr,
+ u32 gsi_offset)
{
int ret;
+ /* GSI offset is only applicable for media GTs */
+ drm_WARN_ON(>->i915->drm, gsi_offset);
+
if (!gt_is_root(gt)) {
struct intel_uncore *uncore;
@@ -832,7 +837,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
- ret = intel_gt_tile_setup(gt, phys_addr);
+ ret = intel_gt_tile_setup(gt, phys_addr, 0);
if (ret)
return ret;
@@ -862,7 +867,8 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
goto err;
}
- ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base,
+ gtdef->gsi_offset);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 94f9ddcfb3a5..05a40ef33258 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1576,4 +1576,12 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
+/*
+ * Standalone Media's non-engine GT registers are located at their regular GT
+ * offsets plus 0x380000. This extra offset is stored inside the intel_uncore
+ * structure so that the existing code can be used for both GTs without
+ * modification.
+ */
+#define MTL_MEDIA_GSI_BASE 0x380000
+
#endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c
new file mode 100644
index 000000000000..8c5c519457cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <drm/drm_managed.h>
+
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_sa_media.h"
+
+int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
+ u32 gsi_offset)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore;
+
+ uncore = drmm_kzalloc(&i915->drm, sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ uncore->gsi_offset = gsi_offset;
+
+ intel_gt_common_init_early(gt);
+ intel_uncore_init_early(uncore, gt);
+
+ /*
+ * Standalone media shares the general MMIO space with the primary
+ * GT. We'll re-use the primary GT's mapping.
+ */
+ uncore->regs = i915->uncore.regs;
+ if (drm_WARN_ON(&i915->drm, uncore->regs == NULL))
+ return -EIO;
+
+ gt->uncore = uncore;
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.h b/drivers/gpu/drm/i915/gt/intel_sa_media.h
new file mode 100644
index 000000000000..3afb310de932
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+#ifndef __INTEL_SA_MEDIA__
+#define __INTEL_SA_MEDIA__
+
+#include <linux/types.h>
+
+struct intel_gt;
+
+int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
+ u32 gsi_offset);
+
+#endif /* __INTEL_SA_MEDIA_H__ */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 857e8bb6865c..7183778a69c2 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -26,6 +26,9 @@
#include <drm/drm_drv.h>
#include <drm/i915_pciids.h>
+#include "gt/intel_gt_regs.h"
+#include "gt/intel_sa_media.h"
+
#include "i915_driver.h"
#include "i915_drv.h"
#include "i915_pci.h"
@@ -1114,6 +1117,17 @@ static const struct intel_device_info pvc_info = {
.display.has_cdclk_crawl = 1, \
.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
+static const struct intel_gt_definition xelpmp_extra_gt[] = {
+ {
+ .type = GT_MEDIA,
+ .name = "Standalone Media GT",
+ .setup = intel_sa_mediagt_setup,
+ .gsi_offset = MTL_MEDIA_GSI_BASE,
+ .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ },
+ {}
+};
+
__maybe_unused
static const struct intel_device_info mtl_info = {
XE_HP_FEATURES,
@@ -1127,6 +1141,7 @@ static const struct intel_device_info mtl_info = {
.media.ver = 13,
PLATFORM(INTEL_METEORLAKE),
.display.has_modular_fia = 1,
+ .extra_gt_list = xelpmp_extra_gt,
.has_flat_ccs = 0,
.has_snoop = 1,
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e0b79dc0fccc..eb4bcf65e91e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -247,14 +247,17 @@ struct intel_runtime_info {
enum intel_gt_type {
GT_PRIMARY,
GT_TILE,
+ GT_MEDIA,
};
struct intel_gt_definition {
enum intel_gt_type type;
char *name;
int (*setup)(struct intel_gt *gt,
- phys_addr_t phys_addr);
+ phys_addr_t phys_addr,
+ u32 gsi_offset);
u32 mapping_base;
+ u32 gsi_offset;
intel_engine_mask_t engine_mask;
};
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 6841f76533f9..be88fb95cb45 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1780,10 +1780,15 @@ __gen2_read(64)
#undef GEN2_READ_FOOTER
#undef GEN2_READ_HEADER
+#define IS_GSI_REG(reg) ((reg) < 0x40000)
+
#define GEN6_READ_HEADER(x) \
- u32 offset = i915_mmio_reg_offset(reg); \
+ u32 offset; \
unsigned long irqflags; \
u##x val = 0; \
+ if (IS_GSI_REG(reg.reg)) \
+ reg.reg += uncore->gsi_offset; \
+ offset = i915_mmio_reg_offset(reg); \
assert_rpm_wakelock_held(uncore->rpm); \
spin_lock_irqsave(&uncore->lock, irqflags); \
unclaimed_reg_debug(uncore, reg, true, true)
@@ -1885,8 +1890,11 @@ __gen2_write(32)
#undef GEN2_WRITE_HEADER
#define GEN6_WRITE_HEADER \
- u32 offset = i915_mmio_reg_offset(reg); \
+ u32 offset; \
unsigned long irqflags; \
+ if (IS_GSI_REG(reg.reg)) \
+ reg.reg += uncore->gsi_offset; \
+ offset = i915_mmio_reg_offset(reg); \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
assert_rpm_wakelock_held(uncore->rpm); \
spin_lock_irqsave(&uncore->lock, irqflags); \
@@ -2265,6 +2273,10 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
{
+ /* The media GT re-uses the primary GT's register mapping */
+ if (uncore->gt->type == GT_MEDIA)
+ return;
+
iounmap(uncore->regs);
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 6100d0f4498a..1b7311a4b98b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -135,6 +135,16 @@ struct intel_uncore {
spinlock_t lock; /** lock is also taken in irq contexts. */
+ /*
+ * Do we need to apply an additional offset to reach the beginning
+ * of the basic non-engine GT registers (referred to as "GSI" on
+ * newer platforms, or "GT block" on older platforms)? If so, we'll
+ * track that here and apply it transparently to registers in the
+ * appropriate range to maintain compatibility with our existing
+ * register definitions and GT code.
+ */
+ u32 gsi_offset;
+
unsigned int flags;
#define UNCORE_HAS_FORCEWAKE BIT(0)
#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
@@ -298,14 +308,20 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
i915_reg_t reg) \
{ \
- return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if (offset < 0x40000) \
+ offset += uncore->gsi_offset; \
+ return read##s__(uncore->regs + offset); \
}
#define __raw_write(x__, s__) \
static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
i915_reg_t reg, u##x__ val) \
{ \
- write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if (offset < 0x40000) \
+ offset += uncore->gsi_offset; \
+ write##s__(val, uncore->regs + offset); \
}
__raw_read(8, b)
__raw_read(16, w)
--
2.37.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 7/8] drm/i915/mtl: Use primary GT's irq lock for media GT
2022-08-29 17:02 [PATCH 0/8] i915: Add "standalone media" support for MTL Matt Roper
` (5 preceding siblings ...)
2022-08-29 17:02 ` [PATCH 6/8] drm/i915/xelpmp: Expose media as another GT Matt Roper
@ 2022-08-29 17:02 ` Matt Roper
2022-09-01 23:39 ` Ceraolo Spurio, Daniele
2022-08-29 17:02 ` [PATCH 8/8] drm/i915/mtl: Hook up interrupts for standalone media Matt Roper
7 siblings, 1 reply; 18+ messages in thread
From: Matt Roper @ 2022-08-29 17:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniele Ceraolo Spurio, dri-devel, radhakrishna.sripada
When we hook up interrupts (in the next patch), interrupts for the media
GT are still processed as part of the primary GT's interrupt flow. As
such, we should share the same IRQ lock with the primary GT. Let's
convert gt->irq_lock into a pointer and just point the media GT's
instance at the same lock the primary GT is using.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +++---
drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++--
drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++++++------
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 8 +++---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 26 +++++++++----------
drivers/gpu/drm/i915/gt/intel_sa_media.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 24 ++++++++---------
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +--
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +--
drivers/gpu/drm/i915/i915_driver.c | 4 ++-
drivers/gpu/drm/i915/i915_irq.c | 4 +--
drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +--
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 14 +++++-----
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 4 +--
16 files changed, 77 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 41acc285e8bf..6e0122b3dca2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1688,9 +1688,9 @@ bool intel_engine_irq_enable(struct intel_engine_cs *engine)
return false;
/* Caller disables interrupts */
- spin_lock(&engine->gt->irq_lock);
+ spin_lock(engine->gt->irq_lock);
engine->irq_enable(engine);
- spin_unlock(&engine->gt->irq_lock);
+ spin_unlock(engine->gt->irq_lock);
return true;
}
@@ -1701,9 +1701,9 @@ void intel_engine_irq_disable(struct intel_engine_cs *engine)
return;
/* Caller disables interrupts */
- spin_lock(&engine->gt->irq_lock);
+ spin_lock(engine->gt->irq_lock);
engine->irq_disable(engine);
- spin_unlock(&engine->gt->irq_lock);
+ spin_unlock(engine->gt->irq_lock);
}
void intel_engines_reset_default_submission(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2a29502289cb..b974a6d23281 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -37,7 +37,7 @@
void intel_gt_common_init_early(struct intel_gt *gt)
{
- spin_lock_init(>->irq_lock);
+ spin_lock_init(gt->irq_lock);
INIT_LIST_HEAD(>->closed_vma);
spin_lock_init(>->closed_lock);
@@ -58,14 +58,19 @@ void intel_gt_common_init_early(struct intel_gt *gt)
}
/* Preliminary initialization of Tile 0 */
-void intel_root_gt_init_early(struct drm_i915_private *i915)
+int intel_root_gt_init_early(struct drm_i915_private *i915)
{
struct intel_gt *gt = to_gt(i915);
gt->i915 = i915;
gt->uncore = &i915->uncore;
+ gt->irq_lock = drmm_kzalloc(&i915->drm, sizeof(*gt->irq_lock), GFP_KERNEL);
+ if (!gt->irq_lock)
+ return -ENOMEM;
intel_gt_common_init_early(gt);
+
+ return 0;
}
static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -787,12 +792,18 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
if (!gt_is_root(gt)) {
struct intel_uncore *uncore;
+ spinlock_t *irq_lock;
uncore = drmm_kzalloc(>->i915->drm, sizeof(*uncore), GFP_KERNEL);
if (!uncore)
return -ENOMEM;
+ irq_lock = drmm_kzalloc(>->i915->drm, sizeof(*irq_lock), GFP_KERNEL);
+ if (!irq_lock)
+ return -ENOMEM;
+
gt->uncore = uncore;
+ gt->irq_lock = irq_lock;
intel_gt_common_init_early(gt);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index c9a359f35d0f..2ee582e287c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -45,7 +45,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
}
void intel_gt_common_init_early(struct intel_gt *gt);
-void intel_root_gt_init_early(struct drm_i915_private *i915);
+int intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
int __must_check intel_gt_init_hw(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 3a72d4fd0214..0dfd0c42d00d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -29,7 +29,7 @@ gen11_gt_engine_identity(struct intel_gt *gt,
u32 timeout_ts;
u32 ident;
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
@@ -120,7 +120,7 @@ gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
unsigned long intr_dw;
unsigned int bit;
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
@@ -138,14 +138,14 @@ void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
{
unsigned int bank;
- spin_lock(>->irq_lock);
+ spin_lock(gt->irq_lock);
for (bank = 0; bank < 2; bank++) {
if (master_ctl & GEN11_GT_DW_IRQ(bank))
gen11_gt_bank_handler(gt, bank);
}
- spin_unlock(>->irq_lock);
+ spin_unlock(gt->irq_lock);
}
bool gen11_gt_reset_one_iir(struct intel_gt *gt,
@@ -154,7 +154,7 @@ bool gen11_gt_reset_one_iir(struct intel_gt *gt,
void __iomem * const regs = gt->uncore->regs;
u32 dw;
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
if (dw & BIT(bit)) {
@@ -310,9 +310,9 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)
if (!HAS_L3_DPF(gt->i915))
return;
- spin_lock(>->irq_lock);
+ spin_lock(gt->irq_lock);
gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915));
- spin_unlock(>->irq_lock);
+ spin_unlock(gt->irq_lock);
if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
gt->i915->l3_parity.which_slice |= 1 << 1;
@@ -434,7 +434,7 @@ static void gen5_gt_update_irq(struct intel_gt *gt,
u32 interrupt_mask,
u32 enabled_irq_mask)
{
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
index 11060f5a4c89..52f2a28b2058 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
@@ -37,7 +37,7 @@ static void gen6_gt_pm_update_irq(struct intel_gt *gt,
WARN_ON(enabled_irq_mask & ~interrupt_mask);
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
new_val = gt->pm_imr;
new_val &= ~interrupt_mask;
@@ -64,7 +64,7 @@ void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
struct intel_uncore *uncore = gt->uncore;
i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
intel_uncore_write(uncore, reg, reset_mask);
intel_uncore_write(uncore, reg, reset_mask);
@@ -92,7 +92,7 @@ static void write_pm_ier(struct intel_gt *gt)
void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
{
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
gt->pm_ier |= enable_mask;
write_pm_ier(gt);
@@ -101,7 +101,7 @@ void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask)
{
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
gt->pm_ier &= ~disable_mask;
gen6_gt_pm_mask_irq(gt, disable_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 3bd36caee321..7c15c67b7913 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -157,7 +157,7 @@ struct intel_gt {
struct intel_rc6 rc6;
struct intel_rps rps;
- spinlock_t irq_lock;
+ spinlock_t *irq_lock;
u32 gt_imr;
u32 pm_ier;
u32 pm_imr;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 8c289a032103..7595aa72af9c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -194,9 +194,9 @@ static void rps_enable_interrupts(struct intel_rps *rps)
rps_reset_ei(rps);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
gen6_gt_pm_enable_irq(gt, rps->pm_events);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
intel_uncore_write(gt->uncore,
GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
@@ -217,14 +217,14 @@ static void rps_reset_interrupts(struct intel_rps *rps)
{
struct intel_gt *gt = rps_to_gt(rps);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
if (GRAPHICS_VER(gt->i915) >= 11)
gen11_rps_reset_interrupts(rps);
else
gen6_rps_reset_interrupts(rps);
rps->pm_iir = 0;
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
}
static void rps_disable_interrupts(struct intel_rps *rps)
@@ -234,9 +234,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
intel_uncore_write(gt->uncore,
GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
intel_synchronize_irq(gt->i915);
@@ -1794,10 +1794,10 @@ static void rps_work(struct work_struct *work)
int new_freq, adj, min, max;
u32 pm_iir = 0;
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
pm_iir = fetch_and_zero(&rps->pm_iir) & rps->pm_events;
client_boost = atomic_read(&rps->num_waiters);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
/* Make sure we didn't queue anything we're not going to process. */
if (!pm_iir && !client_boost)
@@ -1870,9 +1870,9 @@ static void rps_work(struct work_struct *work)
mutex_unlock(&rps->lock);
out:
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
gen6_gt_pm_unmask_irq(gt, rps->pm_events);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
}
void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
@@ -1880,7 +1880,7 @@ void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
struct intel_gt *gt = rps_to_gt(rps);
const u32 events = rps->pm_events & pm_iir;
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
if (unlikely(!events))
return;
@@ -1900,7 +1900,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
events = pm_iir & rps->pm_events;
if (events) {
- spin_lock(>->irq_lock);
+ spin_lock(gt->irq_lock);
GT_TRACE(gt, "irq events:%x\n", events);
@@ -1908,7 +1908,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
rps->pm_iir |= events;
schedule_work(&rps->work);
- spin_unlock(>->irq_lock);
+ spin_unlock(gt->irq_lock);
}
if (GRAPHICS_VER(gt->i915) >= 8)
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c
index 8c5c519457cc..cf3053710bbf 100644
--- a/drivers/gpu/drm/i915/gt/intel_sa_media.c
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -21,6 +21,7 @@ int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
uncore->gsi_offset = gsi_offset;
+ gt->irq_lock = &i915->irq_lock;
intel_gt_common_init_early(gt);
intel_uncore_init_early(uncore, gt);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 24451d000a6a..bac06e3d6f2c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -82,9 +82,9 @@ static void gen9_reset_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>->i915->runtime_pm);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
}
static void gen9_enable_guc_interrupts(struct intel_guc *guc)
@@ -93,11 +93,11 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>->i915->runtime_pm);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
gt->pm_guc_events);
gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
}
static void gen9_disable_guc_interrupts(struct intel_guc *guc)
@@ -106,11 +106,11 @@ static void gen9_disable_guc_interrupts(struct intel_guc *guc)
assert_rpm_wakelock_held(>->i915->runtime_pm);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
intel_synchronize_irq(gt->i915);
gen9_reset_guc_interrupts(guc);
@@ -120,9 +120,9 @@ static void gen11_reset_guc_interrupts(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
gen11_gt_reset_one_iir(gt, 0, GEN11_GUC);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
}
static void gen11_enable_guc_interrupts(struct intel_guc *guc)
@@ -130,25 +130,25 @@ static void gen11_enable_guc_interrupts(struct intel_guc *guc)
struct intel_gt *gt = guc_to_gt(guc);
u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
intel_uncore_write(gt->uncore,
GEN11_GUC_SG_INTR_ENABLE, events);
intel_uncore_write(gt->uncore,
GEN11_GUC_SG_INTR_MASK, ~events);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
}
static void gen11_disable_guc_interrupts(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
intel_synchronize_irq(gt->i915);
gen11_reset_guc_interrupts(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0d56b615bf78..58679a1049b7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1532,8 +1532,8 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
__reset_guc_busyness_stats(guc);
/* Flush IRQ handler */
- spin_lock_irq(&guc_to_gt(guc)->irq_lock);
- spin_unlock_irq(&guc_to_gt(guc)->irq_lock);
+ spin_lock_irq(guc_to_gt(guc)->irq_lock);
+ spin_unlock_irq(guc_to_gt(guc)->irq_lock);
guc_flush_submissions(guc);
guc_flush_destroyed_contexts(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index f2e7c82985ef..ac59dffc35b5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -245,9 +245,9 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_enable_interrupts(guc);
/* check for CT messages received before we enabled interrupts */
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
intel_guc_ct_event_handler(&guc->ct);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
drm_dbg(&i915->drm, "GuC communication enabled\n");
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index de9020771836..d942ec814b47 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -357,7 +357,9 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
intel_wopcm_init_early(&dev_priv->wopcm);
- intel_root_gt_init_early(dev_priv);
+ ret = intel_root_gt_init_early(dev_priv);
+ if (ret < 0)
+ goto err_workqueues;
i915_drm_clients_init(&dev_priv->clients, dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c2f2d7b8d964..14efd58e37d7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1104,9 +1104,9 @@ static void ivb_parity_work(struct work_struct *work)
out:
drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 17109c513259..69cdaaddc4a9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -169,11 +169,11 @@ static void pxp_queue_termination(struct intel_pxp *pxp)
* We want to get the same effect as if we received a termination
* interrupt, so just pretend that we did.
*/
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
intel_pxp_mark_termination_in_progress(pxp);
pxp->session_events |= PXP_TERMINATION_REQUEST;
queue_work(system_unbound_wq, &pxp->session_work);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
}
static bool pxp_component_bound(struct intel_pxp *pxp)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 04745f914407..c28be430718a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -25,7 +25,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp)))
return;
- lockdep_assert_held(>->irq_lock);
+ lockdep_assert_held(gt->irq_lock);
if (unlikely(!iir))
return;
@@ -55,16 +55,16 @@ static inline void __pxp_set_interrupts(struct intel_gt *gt, u32 interrupts)
static inline void pxp_irq_reset(struct intel_gt *gt)
{
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
gen11_gt_reset_one_iir(gt, 0, GEN11_KCR);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
}
void intel_pxp_irq_enable(struct intel_pxp *pxp)
{
struct intel_gt *gt = pxp_to_gt(pxp);
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
if (!pxp->irq_enabled)
WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
@@ -72,7 +72,7 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp)
__pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
pxp->irq_enabled = true;
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
}
void intel_pxp_irq_disable(struct intel_pxp *pxp)
@@ -88,12 +88,12 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp)
*/
GEM_WARN_ON(intel_pxp_is_active(pxp));
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
pxp->irq_enabled = false;
__pxp_set_interrupts(gt, 0);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
intel_synchronize_irq(gt->i915);
pxp_irq_reset(gt);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index 92b00b4de240..1bb5b5249157 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -144,9 +144,9 @@ void intel_pxp_session_work(struct work_struct *work)
intel_wakeref_t wakeref;
u32 events = 0;
- spin_lock_irq(>->irq_lock);
+ spin_lock_irq(gt->irq_lock);
events = fetch_and_zero(&pxp->session_events);
- spin_unlock_irq(>->irq_lock);
+ spin_unlock_irq(gt->irq_lock);
if (!events)
return;
--
2.37.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 8/8] drm/i915/mtl: Hook up interrupts for standalone media
2022-08-29 17:02 [PATCH 0/8] i915: Add "standalone media" support for MTL Matt Roper
` (6 preceding siblings ...)
2022-08-29 17:02 ` [PATCH 7/8] drm/i915/mtl: Use primary GT's irq lock for media GT Matt Roper
@ 2022-08-29 17:02 ` Matt Roper
2022-09-01 23:42 ` Ceraolo Spurio, Daniele
7 siblings, 1 reply; 18+ messages in thread
From: Matt Roper @ 2022-08-29 17:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Anusha Srivatsa, dri-devel, radhakrishna.sripada
Top-level handling of standalone media interrupts will be processed as
part of the primary GT's interrupt handler (since primary and media GTs
share an MMIO space, unlike remote tile setups). When we get down to
the point of handling engine interrupts, we need to take care to lookup
VCS and VECS engines in the media GT rather than the primary.
There are also a couple of additional "other" instance bits that
correspond to the media GT's GuC and media GT's power management
interrupts; we need to direct those to the media GT instance as well.
Bspec: 45605
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 19 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_sa_media.c | 7 +++++++
drivers/gpu/drm/i915/i915_drv.h | 3 +++
4 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 0dfd0c42d00d..f26882fdc24c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -59,11 +59,17 @@ static void
gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
const u16 iir)
{
+ struct intel_gt *media_gt = gt->i915->media_gt;
+
if (instance == OTHER_GUC_INSTANCE)
return guc_irq_handler(>->uc.guc, iir);
+ if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt)
+ return guc_irq_handler(&media_gt->uc.guc, iir);
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt)
+ return gen11_rps_irq_handler(&media_gt->rps, iir);
if (instance == OTHER_KCR_INSTANCE)
return intel_pxp_irq_handler(>->pxp, iir);
@@ -81,6 +87,18 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
{
struct intel_engine_cs *engine;
+ /*
+ * Platforms with standalone media have their media engines in another
+ * GT.
+ */
+ if (MEDIA_VER(gt->i915) >= 13 &&
+ (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
+ if (!gt->i915->media_gt)
+ goto err;
+
+ gt = gt->i915->media_gt;
+ }
+
if (instance <= MAX_ENGINE_INSTANCE)
engine = gt->engine_class[class][instance];
else
@@ -89,6 +107,7 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
if (likely(engine))
return intel_engine_cs_irq(engine, iir);
+err:
WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
class, instance);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 05a40ef33258..21c7a225157f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1552,6 +1552,8 @@
#define OTHER_GTPM_INSTANCE 1
#define OTHER_KCR_INSTANCE 4
#define OTHER_GSC_INSTANCE 6
+#define OTHER_MEDIA_GUC_INSTANCE 16
+#define OTHER_MEDIA_GTPM_INSTANCE 17
#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c
index cf3053710bbf..41c270f103cf 100644
--- a/drivers/gpu/drm/i915/gt/intel_sa_media.c
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -36,5 +36,12 @@ int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
gt->uncore = uncore;
gt->phys_addr = phys_addr;
+ /*
+ * For current platforms we can assume there's only a single
+ * media GT and cache it for quick lookup.
+ */
+ drm_WARN_ON(&i915->drm, i915->media_gt);
+ i915->media_gt = gt;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d45dca70bfa6..917958d42805 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -497,6 +497,9 @@ struct drm_i915_private {
struct kobject *sysfs_gt;
+ /* Quick lookup of media GT (current platforms only have one) */
+ struct intel_gt *media_gt;
+
struct {
struct i915_gem_contexts {
spinlock_t lock; /* locks list */
--
2.37.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 4/8] drm/i915: Prepare more multi-GT initialization
2022-08-29 17:02 ` [PATCH 4/8] drm/i915: Prepare more multi-GT initialization Matt Roper
@ 2022-08-29 20:46 ` Matt Roper
2022-08-31 0:27 ` [PATCH " Sripada, Radhakrishna
1 sibling, 0 replies; 18+ messages in thread
From: Matt Roper @ 2022-08-29 20:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Aravind Iddamsetty, dri-devel
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
immediate MTL media enabling, this same framework will also be used
farther down the road when we enable remote tiles on xehpsdv and pvc.
v2:
- Re-add missing test for !HAS_EXTRA_GT_LIST in intel_gt_probe_all().
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 51 +++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_gt.h | 1 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 16 ++++++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
7 files changed, 70 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..41acc285e8bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index cf7aab7adb30..7b880dbed6ce 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -807,17 +807,16 @@ static void
intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
-
- if (!gt_is_root(gt))
- kfree(gt);
}
int intel_gt_probe_all(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_gt *gt = &i915->gt0;
+ const struct intel_gt_definition *gtdef;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
@@ -828,14 +827,58 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
* and it has been already initialized early during probe
* in i915_driver_probe()
*/
+ gt->i915 = i915;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
i915->gt[0] = gt;
- /* TODO: add more tiles */
+ if (!HAS_EXTRA_GT_LIST(i915))
+ return 0;
+
+ for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
+ gtdef->setup != NULL;
+ i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
+ gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ gt->i915 = i915;
+ gt->name = gtdef->name;
+ gt->type = gtdef->type;
+ gt->info.engine_mask = gtdef->engine_mask;
+ gt->info.id = i;
+
+ drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
+ if (GEM_WARN_ON(range_overflows_t(resource_size_t,
+ gtdef->mapping_base,
+ SZ_16M,
+ pci_resource_len(pdev, mmio_bar)))) {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ if (ret)
+ goto err;
+
+ i915->gt[i] = gt;
+ }
+
return 0;
+
+err:
+ i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
+ intel_gt_release_all(i915);
+
+ return ret;
}
int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 40b06adf509a..4d8779529cc2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
-
void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 4d56f7d5a3be..3bd36caee321 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -83,6 +83,9 @@ struct gt_defaults {
struct intel_gt {
struct drm_i915_private *i915;
+ const char *name;
+ enum intel_gt_type type;
+
struct intel_uncore *uncore;
struct i915_ggtt *ggtt;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 443ed6dac92a..d45dca70bfa6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1061,6 +1061,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
+
/*
* Platform has the dedicated compression control state for each lmem surfaces
* stored in lmem to support the 3D and media compression formats.
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 0ccde94b225f..e0b79dc0fccc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -244,6 +244,20 @@ struct intel_runtime_info {
};
};
+enum intel_gt_type {
+ GT_PRIMARY,
+ GT_TILE,
+};
+
+struct intel_gt_definition {
+ enum intel_gt_type type;
+ char *name;
+ int (*setup)(struct intel_gt *gt,
+ phys_addr_t phys_addr);
+ u32 mapping_base;
+ intel_engine_mask_t engine_mask;
+};
+
struct intel_device_info {
struct ip_version media;
@@ -251,6 +265,8 @@ struct intel_device_info {
unsigned int dma_mask_size; /* available DMA address bits */
+ const struct intel_gt_definition *extra_gt_list;
+
u8 gt; /* GT number, 0 if undefined */
#define DEFINE_FLAG(name) u8 name:1
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index f5904e659ef2..915d58ba383e 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -115,6 +115,7 @@ static struct dev_pm_domain pm_domain = {
static void mock_gt_probe(struct drm_i915_private *i915)
{
i915->gt[0] = &i915->gt0;
+ i915->gt[0]->name = "Mock GT";
}
struct drm_i915_private *mock_gem_device(void)
--
2.37.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* RE: [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend,resume}
2022-08-29 17:02 ` [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume} Matt Roper
@ 2022-08-30 22:49 ` Sripada, Radhakrishna
0 siblings, 0 replies; 18+ messages in thread
From: Sripada, Radhakrishna @ 2022-08-30 22:49 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Monday, August 29, 2022 10:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH 1/8] drm/i915: Move locking and unclaimed check into
> mmio_debug_{suspend,resume}
>
> Moving the locking for MMIO debug (and the final check for unclaimed
> accesses when resuming debug after a userspace-initiated forcewake) will
> make it simpler to completely skip MMIO debug handling on uncores that
> don't support it in future patches.
>
LGTM,
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 41 +++++++++++++++--------------
> 1 file changed, 21 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 9b81b2543ce2..e717ea55484a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -50,23 +50,33 @@ intel_uncore_mmio_debug_init_early(struct
> intel_uncore_mmio_debug *mmio_debug)
> mmio_debug->unclaimed_mmio_check = 1;
> }
>
> -static void mmio_debug_suspend(struct intel_uncore_mmio_debug
> *mmio_debug)
> +static void mmio_debug_suspend(struct intel_uncore *uncore)
> {
> - lockdep_assert_held(&mmio_debug->lock);
> + spin_lock(&uncore->debug->lock);
>
> /* Save and disable mmio debugging for the user bypass */
> - if (!mmio_debug->suspend_count++) {
> - mmio_debug->saved_mmio_check = mmio_debug-
> >unclaimed_mmio_check;
> - mmio_debug->unclaimed_mmio_check = 0;
> + if (!uncore->debug->suspend_count++) {
> + uncore->debug->saved_mmio_check = uncore->debug-
> >unclaimed_mmio_check;
> + uncore->debug->unclaimed_mmio_check = 0;
> }
> +
> + spin_unlock(&uncore->debug->lock);
> }
>
> -static void mmio_debug_resume(struct intel_uncore_mmio_debug
> *mmio_debug)
> +static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);
> +
> +static void mmio_debug_resume(struct intel_uncore *uncore)
> {
> - lockdep_assert_held(&mmio_debug->lock);
> + spin_lock(&uncore->debug->lock);
> +
> + if (!--uncore->debug->suspend_count)
> + uncore->debug->unclaimed_mmio_check = uncore->debug-
> >saved_mmio_check;
>
> - if (!--mmio_debug->suspend_count)
> - mmio_debug->unclaimed_mmio_check = mmio_debug-
> >saved_mmio_check;
> + if (check_for_unclaimed_mmio(uncore))
> + drm_info(&uncore->i915->drm,
> + "Invalid mmio detected during user access\n");
> +
> + spin_unlock(&uncore->debug->lock);
> }
>
> static const char * const forcewake_domain_names[] = {
> @@ -677,9 +687,7 @@ void intel_uncore_forcewake_user_get(struct
> intel_uncore *uncore)
> spin_lock_irq(&uncore->lock);
> if (!uncore->user_forcewake_count++) {
> intel_uncore_forcewake_get__locked(uncore,
> FORCEWAKE_ALL);
> - spin_lock(&uncore->debug->lock);
> - mmio_debug_suspend(uncore->debug);
> - spin_unlock(&uncore->debug->lock);
> + mmio_debug_suspend(uncore);
> }
> spin_unlock_irq(&uncore->lock);
> }
> @@ -695,14 +703,7 @@ void intel_uncore_forcewake_user_put(struct
> intel_uncore *uncore)
> {
> spin_lock_irq(&uncore->lock);
> if (!--uncore->user_forcewake_count) {
> - spin_lock(&uncore->debug->lock);
> - mmio_debug_resume(uncore->debug);
> -
> - if (check_for_unclaimed_mmio(uncore))
> - drm_info(&uncore->i915->drm,
> - "Invalid mmio detected during user access\n");
> - spin_unlock(&uncore->debug->lock);
> -
> + mmio_debug_resume(uncore);
> intel_uncore_forcewake_put__locked(uncore,
> FORCEWAKE_ALL);
> }
> spin_unlock_irq(&uncore->lock);
> --
> 2.37.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 2/8] drm/i915: Only hook up uncore->debug for primary uncore
2022-08-29 17:02 ` [PATCH 2/8] drm/i915: Only hook up uncore->debug for primary uncore Matt Roper
@ 2022-08-31 0:01 ` Sripada, Radhakrishna
0 siblings, 0 replies; 18+ messages in thread
From: Sripada, Radhakrishna @ 2022-08-31 0:01 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: dri-devel
Hi Matt,
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Monday, August 29, 2022 10:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH 2/8] drm/i915: Only hook up uncore->debug for primary uncore
>
> The original intent of intel_uncore_mmio_debug as described in commit
> 0a9b26306d6a ("drm/i915: split out uncore_mmio_debug") was to be a
> singleton structure that could be shared between multiple GTs' uncore
> objects in a multi-tile system. Somehow we went off track and
> started allocating separate instances of this structure for each GT,
> which defeats that original goal.
>
> But in reality, there isn't even a need to share the mmio_debug between
> multiple GTs; on all modern platforms (i.e., everything after gen7)
> unclaimed register accesses are something that can only be detected for
> display registers. There's no point in grabbing the debug spinlock and
> checking for unclaimed accesses on an uncore used by an xehpsdv or pvc
> remote tile GT, or the uncore used by a mtl standalone media GT since
> all of the display accesses go through the primary intel_uncore.
>
> The simplest solution is to simply leave uncore->debug NULL on all
> intel_uncore instances except for the primary one. This will allow us
> to avoid the pointless debug spinlock acquisition we've been doing on
> MMIO accesses coming in through these intel_uncores.
>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 9 ---------
> drivers/gpu/drm/i915/i915_driver.c | 2 +-
> drivers/gpu/drm/i915/intel_uncore.c | 23 ++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_uncore.h | 3 +--
> 4 files changed, 20 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index e4bac2431e41..a82b5e2e0d83 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -781,21 +781,13 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
> phys_addr_t phys_addr)
> int ret;
>
> if (!gt_is_root(gt)) {
> - struct intel_uncore_mmio_debug *mmio_debug;
> struct intel_uncore *uncore;
>
> uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
> if (!uncore)
> return -ENOMEM;
>
> - mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
> - if (!mmio_debug) {
> - kfree(uncore);
> - return -ENOMEM;
> - }
> -
> gt->uncore = uncore;
> - gt->uncore->debug = mmio_debug;
>
> __intel_gt_init_early(gt);
> }
> @@ -817,7 +809,6 @@ intel_gt_tile_cleanup(struct intel_gt *gt)
> intel_uncore_cleanup_mmio(gt->uncore);
>
> if (!gt_is_root(gt)) {
> - kfree(gt->uncore->debug);
> kfree(gt->uncore);
> kfree(gt);
> }
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index 053a7dab5506..de9020771836 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -326,7 +326,7 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> intel_device_info_subplatform_init(dev_priv);
> intel_step_init(dev_priv);
>
> - intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
> + intel_uncore_mmio_debug_init_early(dev_priv);
>
> spin_lock_init(&dev_priv->irq_lock);
> spin_lock_init(&dev_priv->gpu_error.lock);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index e717ea55484a..6841f76533f9 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -44,14 +44,19 @@ fw_domains_get(struct intel_uncore *uncore, enum
> forcewake_domains fw_domains)
> }
>
> void
> -intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug
> *mmio_debug)
> +intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915)
> {
> - spin_lock_init(&mmio_debug->lock);
> - mmio_debug->unclaimed_mmio_check = 1;
> + spin_lock_init(&i915->mmio_debug.lock);
> + i915->mmio_debug.unclaimed_mmio_check = 1;
> +
> + i915->uncore.debug = &i915->mmio_debug;
> }
>
> static void mmio_debug_suspend(struct intel_uncore *uncore)
> {
> + if (!uncore->debug)
> + return;
> +
> spin_lock(&uncore->debug->lock);
>
> /* Save and disable mmio debugging for the user bypass */
> @@ -67,6 +72,9 @@ static bool check_for_unclaimed_mmio(struct
> intel_uncore *uncore);
>
> static void mmio_debug_resume(struct intel_uncore *uncore)
> {
> + if (!uncore->debug)
> + return;
> +
> spin_lock(&uncore->debug->lock);
>
> if (!--uncore->debug->suspend_count)
> @@ -1705,7 +1713,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
> const bool read,
> const bool before)
> {
> - if (likely(!uncore->i915->params.mmio_debug))
> + if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug)
> return;
>
> /* interrupts are disabled and re-enabled around uncore->lock usage */
> @@ -2267,7 +2275,6 @@ void intel_uncore_init_early(struct intel_uncore
> *uncore,
> uncore->i915 = gt->i915;
> uncore->gt = gt;
> uncore->rpm = >->i915->runtime_pm;
> - uncore->debug = >->i915->mmio_debug;
> }
>
> static void uncore_raw_init(struct intel_uncore *uncore)
> @@ -2578,6 +2585,9 @@ bool intel_uncore_unclaimed_mmio(struct
> intel_uncore *uncore)
> {
> bool ret;
>
> + if (!uncore->debug)
> + return false;
> +
> spin_lock_irq(&uncore->debug->lock);
> ret = check_for_unclaimed_mmio(uncore);
> spin_unlock_irq(&uncore->debug->lock);
> @@ -2590,6 +2600,9 @@ intel_uncore_arm_unclaimed_mmio_detection(struct
> intel_uncore *uncore)
> {
> bool ret = false;
>
> + if (drm_WARN_ON(&uncore->i915->drm, !uncore->debug))
> + return false;
> +
> spin_lock_irq(&uncore->debug->lock);
>
> if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h
> b/drivers/gpu/drm/i915/intel_uncore.h
> index b1fa912a65e7..6100d0f4498a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -210,8 +210,7 @@ intel_uncore_has_fifo(const struct intel_uncore
> *uncore)
> return uncore->flags & UNCORE_HAS_FIFO;
> }
>
> -void
> -intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug
> *mmio_debug);
> +void intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915);
> void intel_uncore_init_early(struct intel_uncore *uncore,
> struct intel_gt *gt);
> int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t
> phys_addr);
> --
> 2.37.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 3/8] drm/i915: Use managed allocations for extra uncore objects
2022-08-29 17:02 ` [PATCH 3/8] drm/i915: Use managed allocations for extra uncore objects Matt Roper
@ 2022-08-31 0:03 ` Sripada, Radhakrishna
0 siblings, 0 replies; 18+ messages in thread
From: Sripada, Radhakrishna @ 2022-08-31 0:03 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Monday, August 29, 2022 10:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH 3/8] drm/i915: Use managed allocations for extra uncore
> objects
>
> We're slowly transitioning the init-time kzalloc's of the driver over to
> DRM-managed allocations; let's make sure the uncore objects allocated
> for non-root GTs are thus allocated.
>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
- RK Sripada
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index a82b5e2e0d83..cf7aab7adb30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -783,7 +783,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
> phys_addr_t phys_addr)
> if (!gt_is_root(gt)) {
> struct intel_uncore *uncore;
>
> - uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
> + uncore = drmm_kzalloc(>->i915->drm, sizeof(*uncore),
> GFP_KERNEL);
> if (!uncore)
> return -ENOMEM;
>
> @@ -808,10 +808,8 @@ intel_gt_tile_cleanup(struct intel_gt *gt)
> {
> intel_uncore_cleanup_mmio(gt->uncore);
>
> - if (!gt_is_root(gt)) {
> - kfree(gt->uncore);
> + if (!gt_is_root(gt))
> kfree(gt);
> - }
> }
>
> int intel_gt_probe_all(struct drm_i915_private *i915)
> --
> 2.37.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 4/8] drm/i915: Prepare more multi-GT initialization
2022-08-29 17:02 ` [PATCH 4/8] drm/i915: Prepare more multi-GT initialization Matt Roper
2022-08-29 20:46 ` [PATCH v2 " Matt Roper
@ 2022-08-31 0:27 ` Sripada, Radhakrishna
1 sibling, 0 replies; 18+ messages in thread
From: Sripada, Radhakrishna @ 2022-08-31 0:27 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: Iddamsetty, Aravind, dri-devel
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Monday, August 29, 2022 10:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Iddamsetty, Aravind
> <aravind.iddamsetty@intel.com>
> Subject: [PATCH 4/8] drm/i915: Prepare more multi-GT initialization
>
> We're going to introduce an additional intel_gt for MTL's media unit
> soon. Let's provide a bit more multi-GT initialization framework in
> preparation for that. The initialization will pull the list of GTs for
> a platform from the device info structure. Although necessary for the
> immediate MTL media enabling, this same framework will also be used
> farther down the road when we enable remote tiles on xehpsdv and pvc.
>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
LGTM.
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
- RK Sripada
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 48 +++++++++++++++++--
> drivers/gpu/drm/i915/gt/intel_gt.h | 1 -
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 16 +++++++
> .../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
> 7 files changed, 67 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 275ad72940c1..41acc285e8bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct
> intel_gt *gt)
> u16 vdbox_mask;
> u16 vebox_mask;
>
> - info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
> + GEM_BUG_ON(!info->engine_mask);
>
> if (GRAPHICS_VER(i915) < 11)
> return info->engine_mask;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index cf7aab7adb30..7c0525e96155 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -807,17 +807,16 @@ static void
> intel_gt_tile_cleanup(struct intel_gt *gt)
> {
> intel_uncore_cleanup_mmio(gt->uncore);
> -
> - if (!gt_is_root(gt))
> - kfree(gt);
> }
>
> int intel_gt_probe_all(struct drm_i915_private *i915)
> {
> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> struct intel_gt *gt = &i915->gt0;
> + const struct intel_gt_definition *gtdef;
> phys_addr_t phys_addr;
> unsigned int mmio_bar;
> + unsigned int i;
> int ret;
>
> mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR :
> GTTMMADR_BAR;
> @@ -828,14 +827,55 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> * and it has been already initialized early during probe
> * in i915_driver_probe()
> */
> + gt->i915 = i915;
> + gt->name = "Primary GT";
> + gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
> +
> + drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> ret = intel_gt_tile_setup(gt, phys_addr);
> if (ret)
> return ret;
>
> i915->gt[0] = gt;
>
> - /* TODO: add more tiles */
> + for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
> + gtdef->setup != NULL;
> + i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
> + gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
> + if (!gt) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + gt->i915 = i915;
> + gt->name = gtdef->name;
> + gt->type = gtdef->type;
> + gt->info.engine_mask = gtdef->engine_mask;
> + gt->info.id = i;
> +
> + drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> + if (GEM_WARN_ON(range_overflows_t(resource_size_t,
> + gtdef->mapping_base,
> + SZ_16M,
> + pci_resource_len(pdev,
> mmio_bar)))) {
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
> + if (ret)
> + goto err;
> +
> + i915->gt[i] = gt;
> + }
> +
> return 0;
> +
> +err:
> + i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name,
> ret);
> + intel_gt_release_all(i915);
> +
> + return ret;
> }
>
> int intel_gt_tiles_init(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 40b06adf509a..4d8779529cc2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
> void intel_gt_driver_unregister(struct intel_gt *gt);
> void intel_gt_driver_remove(struct intel_gt *gt);
> void intel_gt_driver_release(struct intel_gt *gt);
> -
> void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>
> int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 4d56f7d5a3be..3bd36caee321 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -83,6 +83,9 @@ struct gt_defaults {
>
> struct intel_gt {
> struct drm_i915_private *i915;
> + const char *name;
> + enum intel_gt_type type;
> +
> struct intel_uncore *uncore;
> struct i915_ggtt *ggtt;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 443ed6dac92a..d45dca70bfa6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1061,6 +1061,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
> #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
>
> +#define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
> +
> /*
> * Platform has the dedicated compression control state for each lmem surfaces
> * stored in lmem to support the 3D and media compression formats.
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 0ccde94b225f..e0b79dc0fccc 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -244,6 +244,20 @@ struct intel_runtime_info {
> };
> };
>
> +enum intel_gt_type {
> + GT_PRIMARY,
> + GT_TILE,
> +};
> +
> +struct intel_gt_definition {
> + enum intel_gt_type type;
> + char *name;
> + int (*setup)(struct intel_gt *gt,
> + phys_addr_t phys_addr);
> + u32 mapping_base;
> + intel_engine_mask_t engine_mask;
> +};
> +
> struct intel_device_info {
> struct ip_version media;
>
> @@ -251,6 +265,8 @@ struct intel_device_info {
>
> unsigned int dma_mask_size; /* available DMA address bits */
>
> + const struct intel_gt_definition *extra_gt_list;
> +
> u8 gt; /* GT number, 0 if undefined */
>
> #define DEFINE_FLAG(name) u8 name:1
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index f5904e659ef2..915d58ba383e 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -115,6 +115,7 @@ static struct dev_pm_domain pm_domain = {
> static void mock_gt_probe(struct drm_i915_private *i915)
> {
> i915->gt[0] = &i915->gt0;
> + i915->gt[0]->name = "Mock GT";
> }
>
> struct drm_i915_private *mock_gem_device(void)
> --
> 2.37.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 5/8] drm/i915: Rename and expose common GT early init routine
2022-08-29 17:02 ` [PATCH 5/8] drm/i915: Rename and expose common GT early init routine Matt Roper
@ 2022-08-31 0:33 ` Sripada, Radhakrishna
0 siblings, 0 replies; 18+ messages in thread
From: Sripada, Radhakrishna @ 2022-08-31 0:33 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Monday, August 29, 2022 10:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH 5/8] drm/i915: Rename and expose common GT early init
> routine
>
> The common early GT init is needed for initialization of all GT types
> (root/primary, remote tile, standalone media). Since standalone media
> (coming in the next patch) will be implemented in a separate file,
> rename and expose the function for use.
>
Reviewed-by: Radhakrishna Sripada <Radhakrishna.sripada@intel.com>
- RK Sripada
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
> drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 7c0525e96155..d21ec11346a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -35,7 +35,7 @@
> #include "intel_uncore.h"
> #include "shmem_utils.h"
>
> -static void __intel_gt_init_early(struct intel_gt *gt)
> +void intel_gt_common_init_early(struct intel_gt *gt)
> {
> spin_lock_init(>->irq_lock);
>
> @@ -65,7 +65,7 @@ void intel_root_gt_init_early(struct drm_i915_private
> *i915)
> gt->i915 = i915;
> gt->uncore = &i915->uncore;
>
> - __intel_gt_init_early(gt);
> + intel_gt_common_init_early(gt);
> }
>
> static int intel_gt_probe_lmem(struct intel_gt *gt)
> @@ -789,7 +789,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
> phys_addr_t phys_addr)
>
> gt->uncore = uncore;
>
> - __intel_gt_init_early(gt);
> + intel_gt_common_init_early(gt);
> }
>
> intel_uncore_init_early(gt->uncore, gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 4d8779529cc2..c9a359f35d0f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -44,6 +44,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc
> *gsc)
> return container_of(gsc, struct intel_gt, gsc);
> }
>
> +void intel_gt_common_init_early(struct intel_gt *gt);
> void intel_root_gt_init_early(struct drm_i915_private *i915);
> int intel_gt_assign_ggtt(struct intel_gt *gt);
> int intel_gt_init_mmio(struct intel_gt *gt);
> --
> 2.37.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 6/8] drm/i915/xelpmp: Expose media as another GT
2022-08-29 17:02 ` [PATCH 6/8] drm/i915/xelpmp: Expose media as another GT Matt Roper
@ 2022-09-01 23:31 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 18+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 23:31 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 8/29/2022 10:02 AM, Matt Roper wrote:
> Xe_LPM+ platforms have "standalone media." I.e., the media unit is
> designed as an additional GT with its own engine list, GuC, forcewake,
> etc. Let's allow platforms to include media GTs in their device info.
>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++++++--
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++++
> drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +++++++++
> drivers/gpu/drm/i915/i915_pci.c | 15 +++++++++
> drivers/gpu/drm/i915/intel_device_info.h | 5 ++-
> drivers/gpu/drm/i915/intel_uncore.c | 16 ++++++++--
> drivers/gpu/drm/i915/intel_uncore.h | 20 ++++++++++--
> 9 files changed, 123 insertions(+), 8 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 522ef9b4aff3..e83e4cd46968 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -123,6 +123,7 @@ gt-y += \
> gt/intel_ring.o \
> gt/intel_ring_submission.o \
> gt/intel_rps.o \
> + gt/intel_sa_media.o \
> gt/intel_sseu.o \
> gt/intel_sseu_debugfs.o \
> gt/intel_timeline.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index d21ec11346a5..2a29502289cb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -776,10 +776,15 @@ void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
> }
> }
>
> -static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> +static int intel_gt_tile_setup(struct intel_gt *gt,
> + phys_addr_t phys_addr,
> + u32 gsi_offset)
This is only called from intel_gt_probe_all with gsi_offset = 0, so the
extra param isn't really used at this point. I'm guessing the intent
here is to keep the function params the same as intel_sa_mediagt_setup,
so we can assign this to gtdef->setup() for "normal" extra tiles on
xehpsdv and pvc. Maybe add a comment about it above here, so no one
accidentally optimizes this out?
> {
> int ret;
>
> + /* GSI offset is only applicable for media GTs */
> + drm_WARN_ON(>->i915->drm, gsi_offset);
> +
> if (!gt_is_root(gt)) {
> struct intel_uncore *uncore;
>
> @@ -832,7 +837,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
>
> drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
> - ret = intel_gt_tile_setup(gt, phys_addr);
> + ret = intel_gt_tile_setup(gt, phys_addr, 0);
> if (ret)
> return ret;
>
> @@ -862,7 +867,8 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> goto err;
> }
>
> - ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
> + ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base,
> + gtdef->gsi_offset);
> if (ret)
> goto err;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 94f9ddcfb3a5..05a40ef33258 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1576,4 +1576,12 @@
>
> #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
>
> +/*
> + * Standalone Media's non-engine GT registers are located at their regular GT
> + * offsets plus 0x380000. This extra offset is stored inside the intel_uncore
> + * structure so that the existing code can be used for both GTs without
> + * modification.
> + */
> +#define MTL_MEDIA_GSI_BASE 0x380000
> +
> #endif /* __INTEL_GT_REGS__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> new file mode 100644
> index 000000000000..8c5c519457cc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include <drm/drm_managed.h>
> +
> +#include "i915_drv.h"
> +#include "gt/intel_gt.h"
> +#include "gt/intel_sa_media.h"
> +
> +int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
> + u32 gsi_offset)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + struct intel_uncore *uncore;
> +
> + uncore = drmm_kzalloc(&i915->drm, sizeof(*uncore), GFP_KERNEL);
> + if (!uncore)
> + return -ENOMEM;
> +
> + uncore->gsi_offset = gsi_offset;
> +
> + intel_gt_common_init_early(gt);
> + intel_uncore_init_early(uncore, gt);
Where is the initialization of this uncore completed (i.e. call to
intel_uncore_init_mmio) ? Can't find it in follow up patches and without
it the register access on the media GT would be broken since the
function pointers in the uncore struct won't be set. Not a blocker since
this is still early enabling, but I'd prefer if this limitation (and
follow up remediation plan) was stated in the commit message or cover
letter.
> +
> + /*
> + * Standalone media shares the general MMIO space with the primary
> + * GT. We'll re-use the primary GT's mapping.
> + */
> + uncore->regs = i915->uncore.regs;
> + if (drm_WARN_ON(&i915->drm, uncore->regs == NULL))
> + return -EIO;
> +
> + gt->uncore = uncore;
> + gt->phys_addr = phys_addr;
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.h b/drivers/gpu/drm/i915/gt/intel_sa_media.h
> new file mode 100644
> index 000000000000..3afb310de932
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +#ifndef __INTEL_SA_MEDIA__
> +#define __INTEL_SA_MEDIA__
> +
> +#include <linux/types.h>
> +
> +struct intel_gt;
> +
> +int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
> + u32 gsi_offset);
> +
> +#endif /* __INTEL_SA_MEDIA_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 857e8bb6865c..7183778a69c2 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -26,6 +26,9 @@
> #include <drm/drm_drv.h>
> #include <drm/i915_pciids.h>
>
> +#include "gt/intel_gt_regs.h"
> +#include "gt/intel_sa_media.h"
> +
> #include "i915_driver.h"
> #include "i915_drv.h"
> #include "i915_pci.h"
> @@ -1114,6 +1117,17 @@ static const struct intel_device_info pvc_info = {
> .display.has_cdclk_crawl = 1, \
> .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
>
> +static const struct intel_gt_definition xelpmp_extra_gt[] = {
> + {
> + .type = GT_MEDIA,
> + .name = "Standalone Media GT",
> + .setup = intel_sa_mediagt_setup,
> + .gsi_offset = MTL_MEDIA_GSI_BASE,
> + .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> + },
> + {}
> +};
> +
> __maybe_unused
> static const struct intel_device_info mtl_info = {
> XE_HP_FEATURES,
> @@ -1127,6 +1141,7 @@ static const struct intel_device_info mtl_info = {
> .media.ver = 13,
> PLATFORM(INTEL_METEORLAKE),
> .display.has_modular_fia = 1,
> + .extra_gt_list = xelpmp_extra_gt,
> .has_flat_ccs = 0,
> .has_snoop = 1,
> .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index e0b79dc0fccc..eb4bcf65e91e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -247,14 +247,17 @@ struct intel_runtime_info {
> enum intel_gt_type {
> GT_PRIMARY,
> GT_TILE,
> + GT_MEDIA,
> };
>
> struct intel_gt_definition {
> enum intel_gt_type type;
> char *name;
> int (*setup)(struct intel_gt *gt,
> - phys_addr_t phys_addr);
> + phys_addr_t phys_addr,
> + u32 gsi_offset);
> u32 mapping_base;
> + u32 gsi_offset;
> intel_engine_mask_t engine_mask;
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 6841f76533f9..be88fb95cb45 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1780,10 +1780,15 @@ __gen2_read(64)
> #undef GEN2_READ_FOOTER
> #undef GEN2_READ_HEADER
>
> +#define IS_GSI_REG(reg) ((reg) < 0x40000)
> +
> #define GEN6_READ_HEADER(x) \
> - u32 offset = i915_mmio_reg_offset(reg); \
> + u32 offset; \
> unsigned long irqflags; \
> u##x val = 0; \
> + if (IS_GSI_REG(reg.reg)) \
> + reg.reg += uncore->gsi_offset; \
> + offset = i915_mmio_reg_offset(reg); \
I was initially confused here on why you were modifying reg.reg to then
extract it, but then I realized other function further down use the reg
variable as well, so this would adapt it for them all. However, it still
seem weird to me to use both offset and reg in an interleaved way in the
code and IMO we should converge on one. It looks like there is only one
use of "offset", so maybe that's the one we can drop. Not something that
needs to be done in this patch, just reflecting on it.
> assert_rpm_wakelock_held(uncore->rpm); \
> spin_lock_irqsave(&uncore->lock, irqflags); \
> unclaimed_reg_debug(uncore, reg, true, true)
> @@ -1885,8 +1890,11 @@ __gen2_write(32)
> #undef GEN2_WRITE_HEADER
>
> #define GEN6_WRITE_HEADER \
> - u32 offset = i915_mmio_reg_offset(reg); \
> + u32 offset; \
> unsigned long irqflags; \
> + if (IS_GSI_REG(reg.reg)) \
> + reg.reg += uncore->gsi_offset; \
> + offset = i915_mmio_reg_offset(reg); \
> trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
> assert_rpm_wakelock_held(uncore->rpm); \
> spin_lock_irqsave(&uncore->lock, irqflags); \
> @@ -2265,6 +2273,10 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
>
> void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
> {
> + /* The media GT re-uses the primary GT's register mapping */
> + if (uncore->gt->type == GT_MEDIA)
> + return;
> +
> iounmap(uncore->regs);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 6100d0f4498a..1b7311a4b98b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -135,6 +135,16 @@ struct intel_uncore {
>
> spinlock_t lock; /** lock is also taken in irq contexts. */
>
> + /*
> + * Do we need to apply an additional offset to reach the beginning
> + * of the basic non-engine GT registers (referred to as "GSI" on
> + * newer platforms, or "GT block" on older platforms)? If so, we'll
> + * track that here and apply it transparently to registers in the
> + * appropriate range to maintain compatibility with our existing
> + * register definitions and GT code.
> + */
> + u32 gsi_offset;
> +
> unsigned int flags;
> #define UNCORE_HAS_FORCEWAKE BIT(0)
> #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
> @@ -298,14 +308,20 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
> static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
> i915_reg_t reg) \
> { \
> - return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
> + u32 offset = i915_mmio_reg_offset(reg); \
> + if (offset < 0x40000) \
Any reason not to have IS_GSI_REG() defined in this header and used here?
Daniele
> + offset += uncore->gsi_offset; \
> + return read##s__(uncore->regs + offset); \
> }
>
> #define __raw_write(x__, s__) \
> static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
> i915_reg_t reg, u##x__ val) \
> { \
> - write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
> + u32 offset = i915_mmio_reg_offset(reg); \
> + if (offset < 0x40000) \
> + offset += uncore->gsi_offset; \
> + write##s__(val, uncore->regs + offset); \
> }
> __raw_read(8, b)
> __raw_read(16, w)
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 7/8] drm/i915/mtl: Use primary GT's irq lock for media GT
2022-08-29 17:02 ` [PATCH 7/8] drm/i915/mtl: Use primary GT's irq lock for media GT Matt Roper
@ 2022-09-01 23:39 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 18+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 23:39 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel, radhakrishna.sripada
On 8/29/2022 10:02 AM, Matt Roper wrote:
> When we hook up interrupts (in the next patch), interrupts for the media
> GT are still processed as part of the primary GT's interrupt flow. As
> such, we should share the same IRQ lock with the primary GT. Let's
> convert gt->irq_lock into a pointer and just point the media GT's
> instance at the same lock the primary GT is using.
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +++---
> drivers/gpu/drm/i915/gt/intel_gt.c | 15 +++++++++--
> drivers/gpu/drm/i915/gt/intel_gt.h | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++++++------
> drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 8 +++---
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 26 +++++++++----------
> drivers/gpu/drm/i915/gt/intel_sa_media.c | 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 24 ++++++++---------
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +--
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +--
> drivers/gpu/drm/i915/i915_driver.c | 4 ++-
> drivers/gpu/drm/i915/i915_irq.c | 4 +--
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +--
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 14 +++++-----
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 4 +--
> 16 files changed, 77 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 41acc285e8bf..6e0122b3dca2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1688,9 +1688,9 @@ bool intel_engine_irq_enable(struct intel_engine_cs *engine)
> return false;
>
> /* Caller disables interrupts */
> - spin_lock(&engine->gt->irq_lock);
> + spin_lock(engine->gt->irq_lock);
> engine->irq_enable(engine);
> - spin_unlock(&engine->gt->irq_lock);
> + spin_unlock(engine->gt->irq_lock);
>
> return true;
> }
> @@ -1701,9 +1701,9 @@ void intel_engine_irq_disable(struct intel_engine_cs *engine)
> return;
>
> /* Caller disables interrupts */
> - spin_lock(&engine->gt->irq_lock);
> + spin_lock(engine->gt->irq_lock);
> engine->irq_disable(engine);
> - spin_unlock(&engine->gt->irq_lock);
> + spin_unlock(engine->gt->irq_lock);
> }
>
> void intel_engines_reset_default_submission(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2a29502289cb..b974a6d23281 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -37,7 +37,7 @@
>
> void intel_gt_common_init_early(struct intel_gt *gt)
> {
> - spin_lock_init(>->irq_lock);
> + spin_lock_init(gt->irq_lock);
>
> INIT_LIST_HEAD(>->closed_vma);
> spin_lock_init(>->closed_lock);
> @@ -58,14 +58,19 @@ void intel_gt_common_init_early(struct intel_gt *gt)
> }
>
> /* Preliminary initialization of Tile 0 */
> -void intel_root_gt_init_early(struct drm_i915_private *i915)
> +int intel_root_gt_init_early(struct drm_i915_private *i915)
> {
> struct intel_gt *gt = to_gt(i915);
>
> gt->i915 = i915;
> gt->uncore = &i915->uncore;
> + gt->irq_lock = drmm_kzalloc(&i915->drm, sizeof(*gt->irq_lock), GFP_KERNEL);
> + if (!gt->irq_lock)
> + return -ENOMEM;
>
> intel_gt_common_init_early(gt);
> +
> + return 0;
> }
>
> static int intel_gt_probe_lmem(struct intel_gt *gt)
> @@ -787,12 +792,18 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
>
> if (!gt_is_root(gt)) {
> struct intel_uncore *uncore;
> + spinlock_t *irq_lock;
>
> uncore = drmm_kzalloc(>->i915->drm, sizeof(*uncore), GFP_KERNEL);
> if (!uncore)
> return -ENOMEM;
>
> + irq_lock = drmm_kzalloc(>->i915->drm, sizeof(*irq_lock), GFP_KERNEL);
> + if (!irq_lock)
> + return -ENOMEM;
> +
> gt->uncore = uncore;
> + gt->irq_lock = irq_lock;
>
> intel_gt_common_init_early(gt);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index c9a359f35d0f..2ee582e287c8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -45,7 +45,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
> }
>
> void intel_gt_common_init_early(struct intel_gt *gt);
> -void intel_root_gt_init_early(struct drm_i915_private *i915);
> +int intel_root_gt_init_early(struct drm_i915_private *i915);
> int intel_gt_assign_ggtt(struct intel_gt *gt);
> int intel_gt_init_mmio(struct intel_gt *gt);
> int __must_check intel_gt_init_hw(struct intel_gt *gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 3a72d4fd0214..0dfd0c42d00d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -29,7 +29,7 @@ gen11_gt_engine_identity(struct intel_gt *gt,
> u32 timeout_ts;
> u32 ident;
>
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
>
> @@ -120,7 +120,7 @@ gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
> unsigned long intr_dw;
> unsigned int bit;
>
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
>
> @@ -138,14 +138,14 @@ void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
> {
> unsigned int bank;
>
> - spin_lock(>->irq_lock);
> + spin_lock(gt->irq_lock);
>
> for (bank = 0; bank < 2; bank++) {
> if (master_ctl & GEN11_GT_DW_IRQ(bank))
> gen11_gt_bank_handler(gt, bank);
> }
>
> - spin_unlock(>->irq_lock);
> + spin_unlock(gt->irq_lock);
> }
>
> bool gen11_gt_reset_one_iir(struct intel_gt *gt,
> @@ -154,7 +154,7 @@ bool gen11_gt_reset_one_iir(struct intel_gt *gt,
> void __iomem * const regs = gt->uncore->regs;
> u32 dw;
>
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
> if (dw & BIT(bit)) {
> @@ -310,9 +310,9 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)
> if (!HAS_L3_DPF(gt->i915))
> return;
>
> - spin_lock(>->irq_lock);
> + spin_lock(gt->irq_lock);
> gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915));
> - spin_unlock(>->irq_lock);
> + spin_unlock(gt->irq_lock);
>
> if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
> gt->i915->l3_parity.which_slice |= 1 << 1;
> @@ -434,7 +434,7 @@ static void gen5_gt_update_irq(struct intel_gt *gt,
> u32 interrupt_mask,
> u32 enabled_irq_mask)
> {
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> index 11060f5a4c89..52f2a28b2058 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> @@ -37,7 +37,7 @@ static void gen6_gt_pm_update_irq(struct intel_gt *gt,
>
> WARN_ON(enabled_irq_mask & ~interrupt_mask);
>
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> new_val = gt->pm_imr;
> new_val &= ~interrupt_mask;
> @@ -64,7 +64,7 @@ void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
> struct intel_uncore *uncore = gt->uncore;
> i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> intel_uncore_write(uncore, reg, reset_mask);
> intel_uncore_write(uncore, reg, reset_mask);
> @@ -92,7 +92,7 @@ static void write_pm_ier(struct intel_gt *gt)
>
> void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
> {
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> gt->pm_ier |= enable_mask;
> write_pm_ier(gt);
> @@ -101,7 +101,7 @@ void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
>
> void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask)
> {
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> gt->pm_ier &= ~disable_mask;
> gen6_gt_pm_mask_irq(gt, disable_mask);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 3bd36caee321..7c15c67b7913 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -157,7 +157,7 @@ struct intel_gt {
> struct intel_rc6 rc6;
> struct intel_rps rps;
>
> - spinlock_t irq_lock;
> + spinlock_t *irq_lock;
> u32 gt_imr;
> u32 pm_ier;
> u32 pm_imr;
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 8c289a032103..7595aa72af9c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -194,9 +194,9 @@ static void rps_enable_interrupts(struct intel_rps *rps)
>
> rps_reset_ei(rps);
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> gen6_gt_pm_enable_irq(gt, rps->pm_events);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
>
> intel_uncore_write(gt->uncore,
> GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
> @@ -217,14 +217,14 @@ static void rps_reset_interrupts(struct intel_rps *rps)
> {
> struct intel_gt *gt = rps_to_gt(rps);
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> if (GRAPHICS_VER(gt->i915) >= 11)
> gen11_rps_reset_interrupts(rps);
> else
> gen6_rps_reset_interrupts(rps);
>
> rps->pm_iir = 0;
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> }
>
> static void rps_disable_interrupts(struct intel_rps *rps)
> @@ -234,9 +234,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
> intel_uncore_write(gt->uncore,
> GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
>
> intel_synchronize_irq(gt->i915);
>
> @@ -1794,10 +1794,10 @@ static void rps_work(struct work_struct *work)
> int new_freq, adj, min, max;
> u32 pm_iir = 0;
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> pm_iir = fetch_and_zero(&rps->pm_iir) & rps->pm_events;
> client_boost = atomic_read(&rps->num_waiters);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
>
> /* Make sure we didn't queue anything we're not going to process. */
> if (!pm_iir && !client_boost)
> @@ -1870,9 +1870,9 @@ static void rps_work(struct work_struct *work)
> mutex_unlock(&rps->lock);
>
> out:
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> gen6_gt_pm_unmask_irq(gt, rps->pm_events);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> }
>
> void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
> @@ -1880,7 +1880,7 @@ void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
> struct intel_gt *gt = rps_to_gt(rps);
> const u32 events = rps->pm_events & pm_iir;
>
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> if (unlikely(!events))
> return;
> @@ -1900,7 +1900,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
>
> events = pm_iir & rps->pm_events;
> if (events) {
> - spin_lock(>->irq_lock);
> + spin_lock(gt->irq_lock);
>
> GT_TRACE(gt, "irq events:%x\n", events);
>
> @@ -1908,7 +1908,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
> rps->pm_iir |= events;
>
> schedule_work(&rps->work);
> - spin_unlock(>->irq_lock);
> + spin_unlock(gt->irq_lock);
> }
>
> if (GRAPHICS_VER(gt->i915) >= 8)
> diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> index 8c5c519457cc..cf3053710bbf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sa_media.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> @@ -21,6 +21,7 @@ int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
>
> uncore->gsi_offset = gsi_offset;
>
> + gt->irq_lock = &i915->irq_lock;
shouldn't this be i915->gt0->irq_lock?
> intel_gt_common_init_early(gt);
> intel_uncore_init_early(uncore, gt);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 24451d000a6a..bac06e3d6f2c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -82,9 +82,9 @@ static void gen9_reset_guc_interrupts(struct intel_guc *guc)
>
> assert_rpm_wakelock_held(>->i915->runtime_pm);
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> }
>
> static void gen9_enable_guc_interrupts(struct intel_guc *guc)
> @@ -93,11 +93,11 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc)
>
> assert_rpm_wakelock_held(>->i915->runtime_pm);
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
> gt->pm_guc_events);
> gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> }
>
> static void gen9_disable_guc_interrupts(struct intel_guc *guc)
> @@ -106,11 +106,11 @@ static void gen9_disable_guc_interrupts(struct intel_guc *guc)
>
> assert_rpm_wakelock_held(>->i915->runtime_pm);
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
>
> gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
>
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> intel_synchronize_irq(gt->i915);
>
> gen9_reset_guc_interrupts(guc);
> @@ -120,9 +120,9 @@ static void gen11_reset_guc_interrupts(struct intel_guc *guc)
> {
> struct intel_gt *gt = guc_to_gt(guc);
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> gen11_gt_reset_one_iir(gt, 0, GEN11_GUC);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> }
>
> static void gen11_enable_guc_interrupts(struct intel_guc *guc)
> @@ -130,25 +130,25 @@ static void gen11_enable_guc_interrupts(struct intel_guc *guc)
> struct intel_gt *gt = guc_to_gt(guc);
> u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
> intel_uncore_write(gt->uncore,
> GEN11_GUC_SG_INTR_ENABLE, events);
> intel_uncore_write(gt->uncore,
> GEN11_GUC_SG_INTR_MASK, ~events);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> }
>
> static void gen11_disable_guc_interrupts(struct intel_guc *guc)
> {
> struct intel_gt *gt = guc_to_gt(guc);
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
>
> intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
> intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
>
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> intel_synchronize_irq(gt->i915);
>
> gen11_reset_guc_interrupts(guc);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 0d56b615bf78..58679a1049b7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1532,8 +1532,8 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> __reset_guc_busyness_stats(guc);
>
> /* Flush IRQ handler */
> - spin_lock_irq(&guc_to_gt(guc)->irq_lock);
> - spin_unlock_irq(&guc_to_gt(guc)->irq_lock);
> + spin_lock_irq(guc_to_gt(guc)->irq_lock);
> + spin_unlock_irq(guc_to_gt(guc)->irq_lock);
>
> guc_flush_submissions(guc);
> guc_flush_destroyed_contexts(guc);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index f2e7c82985ef..ac59dffc35b5 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -245,9 +245,9 @@ static int guc_enable_communication(struct intel_guc *guc)
> intel_guc_enable_interrupts(guc);
>
> /* check for CT messages received before we enabled interrupts */
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> intel_guc_ct_event_handler(&guc->ct);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
>
> drm_dbg(&i915->drm, "GuC communication enabled\n");
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index de9020771836..d942ec814b47 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -357,7 +357,9 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> intel_wopcm_init_early(&dev_priv->wopcm);
>
> - intel_root_gt_init_early(dev_priv);
> + ret = intel_root_gt_init_early(dev_priv);
> + if (ret < 0)
> + goto err_workqueues;
I think this needs a new goto case because we need to cleanup ttm.
Daniele
>
> i915_drm_clients_init(&dev_priv->clients, dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c2f2d7b8d964..14efd58e37d7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1104,9 +1104,9 @@ static void ivb_parity_work(struct work_struct *work)
>
> out:
> drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
>
> mutex_unlock(&dev_priv->drm.struct_mutex);
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 17109c513259..69cdaaddc4a9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -169,11 +169,11 @@ static void pxp_queue_termination(struct intel_pxp *pxp)
> * We want to get the same effect as if we received a termination
> * interrupt, so just pretend that we did.
> */
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> intel_pxp_mark_termination_in_progress(pxp);
> pxp->session_events |= PXP_TERMINATION_REQUEST;
> queue_work(system_unbound_wq, &pxp->session_work);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> }
>
> static bool pxp_component_bound(struct intel_pxp *pxp)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> index 04745f914407..c28be430718a 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> @@ -25,7 +25,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp)))
> return;
>
> - lockdep_assert_held(>->irq_lock);
> + lockdep_assert_held(gt->irq_lock);
>
> if (unlikely(!iir))
> return;
> @@ -55,16 +55,16 @@ static inline void __pxp_set_interrupts(struct intel_gt *gt, u32 interrupts)
>
> static inline void pxp_irq_reset(struct intel_gt *gt)
> {
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> gen11_gt_reset_one_iir(gt, 0, GEN11_KCR);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> }
>
> void intel_pxp_irq_enable(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = pxp_to_gt(pxp);
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
>
> if (!pxp->irq_enabled)
> WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
> @@ -72,7 +72,7 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp)
> __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
> pxp->irq_enabled = true;
>
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> }
>
> void intel_pxp_irq_disable(struct intel_pxp *pxp)
> @@ -88,12 +88,12 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp)
> */
> GEM_WARN_ON(intel_pxp_is_active(pxp));
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
>
> pxp->irq_enabled = false;
> __pxp_set_interrupts(gt, 0);
>
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
> intel_synchronize_irq(gt->i915);
>
> pxp_irq_reset(gt);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> index 92b00b4de240..1bb5b5249157 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -144,9 +144,9 @@ void intel_pxp_session_work(struct work_struct *work)
> intel_wakeref_t wakeref;
> u32 events = 0;
>
> - spin_lock_irq(>->irq_lock);
> + spin_lock_irq(gt->irq_lock);
> events = fetch_and_zero(&pxp->session_events);
> - spin_unlock_irq(>->irq_lock);
> + spin_unlock_irq(gt->irq_lock);
>
> if (!events)
> return;
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 8/8] drm/i915/mtl: Hook up interrupts for standalone media
2022-08-29 17:02 ` [PATCH 8/8] drm/i915/mtl: Hook up interrupts for standalone media Matt Roper
@ 2022-09-01 23:42 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 18+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 23:42 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: Anusha Srivatsa, dri-devel, radhakrishna.sripada
On 8/29/2022 10:02 AM, Matt Roper wrote:
> Top-level handling of standalone media interrupts will be processed as
> part of the primary GT's interrupt handler (since primary and media GTs
> share an MMIO space, unlike remote tile setups). When we get down to
> the point of handling engine interrupts, we need to take care to lookup
> VCS and VECS engines in the media GT rather than the primary.
>
> There are also a couple of additional "other" instance bits that
> correspond to the media GT's GuC and media GT's power management
> interrupts; we need to direct those to the media GT instance as well.
>
> Bspec: 45605
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 19 +++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> drivers/gpu/drm/i915/gt/intel_sa_media.c | 7 +++++++
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> 4 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 0dfd0c42d00d..f26882fdc24c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -59,11 +59,17 @@ static void
> gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
> const u16 iir)
> {
> + struct intel_gt *media_gt = gt->i915->media_gt;
> +
> if (instance == OTHER_GUC_INSTANCE)
> return guc_irq_handler(>->uc.guc, iir);
> + if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt)
> + return guc_irq_handler(&media_gt->uc.guc, iir);
>
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(>->rps, iir);
> + if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt)
> + return gen11_rps_irq_handler(&media_gt->rps, iir);
>
> if (instance == OTHER_KCR_INSTANCE)
> return intel_pxp_irq_handler(>->pxp, iir);
> @@ -81,6 +87,18 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
> {
> struct intel_engine_cs *engine;
>
> + /*
> + * Platforms with standalone media have their media engines in another
> + * GT.
> + */
> + if (MEDIA_VER(gt->i915) >= 13 &&
> + (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
> + if (!gt->i915->media_gt)
> + goto err;
> +
> + gt = gt->i915->media_gt;
> + }
> +
> if (instance <= MAX_ENGINE_INSTANCE)
> engine = gt->engine_class[class][instance];
> else
> @@ -89,6 +107,7 @@ gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
> if (likely(engine))
> return intel_engine_cs_irq(engine, iir);
>
> +err:
> WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
> class, instance);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 05a40ef33258..21c7a225157f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1552,6 +1552,8 @@
> #define OTHER_GTPM_INSTANCE 1
> #define OTHER_KCR_INSTANCE 4
> #define OTHER_GSC_INSTANCE 6
> +#define OTHER_MEDIA_GUC_INSTANCE 16
> +#define OTHER_MEDIA_GTPM_INSTANCE 17
>
> #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> index cf3053710bbf..41c270f103cf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sa_media.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> @@ -36,5 +36,12 @@ int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
> gt->uncore = uncore;
> gt->phys_addr = phys_addr;
>
> + /*
> + * For current platforms we can assume there's only a single
> + * media GT and cache it for quick lookup.
> + */
> + drm_WARN_ON(&i915->drm, i915->media_gt);
> + i915->media_gt = gt;
> +
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d45dca70bfa6..917958d42805 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -497,6 +497,9 @@ struct drm_i915_private {
>
> struct kobject *sysfs_gt;
>
> + /* Quick lookup of media GT (current platforms only have one) */
> + struct intel_gt *media_gt;
> +
> struct {
> struct i915_gem_contexts {
> spinlock_t lock; /* locks list */
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-09-01 23:42 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
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2022-08-29 17:02 [PATCH 0/8] i915: Add "standalone media" support for MTL Matt Roper
2022-08-29 17:02 ` [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend, resume} Matt Roper
2022-08-30 22:49 ` [PATCH 1/8] drm/i915: Move locking and unclaimed check into mmio_debug_{suspend,resume} Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 2/8] drm/i915: Only hook up uncore->debug for primary uncore Matt Roper
2022-08-31 0:01 ` Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 3/8] drm/i915: Use managed allocations for extra uncore objects Matt Roper
2022-08-31 0:03 ` Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 4/8] drm/i915: Prepare more multi-GT initialization Matt Roper
2022-08-29 20:46 ` [PATCH v2 " Matt Roper
2022-08-31 0:27 ` [PATCH " Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 5/8] drm/i915: Rename and expose common GT early init routine Matt Roper
2022-08-31 0:33 ` Sripada, Radhakrishna
2022-08-29 17:02 ` [PATCH 6/8] drm/i915/xelpmp: Expose media as another GT Matt Roper
2022-09-01 23:31 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-29 17:02 ` [PATCH 7/8] drm/i915/mtl: Use primary GT's irq lock for media GT Matt Roper
2022-09-01 23:39 ` Ceraolo Spurio, Daniele
2022-08-29 17:02 ` [PATCH 8/8] drm/i915/mtl: Hook up interrupts for standalone media Matt Roper
2022-09-01 23:42 ` Ceraolo Spurio, Daniele
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