* [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
@ 2022-09-07 20:39 Lucas De Marchi
2022-09-07 20:39 ` [PATCH 2/2] drm/i915/gt: Extract function to apply " Lucas De Marchi
2022-09-07 22:18 ` [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling " Matt Roper
0 siblings, 2 replies; 5+ messages in thread
From: Lucas De Marchi @ 2022-09-07 20:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Check for media IP version instead of graphics since this is figuring
out the media engines' configuration. Currently the only platform with
non-matching graphics/media version is Meteor Lake: update the check in
gen11_vdbox_has_sfc() so it considers not only version 12, but also any
later version which then includes that platform.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..5cddee7c2f1d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
*/
if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
return false;
- else if (GRAPHICS_VER(i915) == 12)
+ else if (MEDIA_VER(i915) >= 12)
return (physical_vdbox % 2 == 0) ||
!(BIT(physical_vdbox - 1) & vdbox_mask);
- else if (GRAPHICS_VER(i915) == 11)
+ else if (MEDIA_VER(i915) == 11)
return logical_vdbox % 2 == 0;
- MISSING_CASE(GRAPHICS_VER(i915));
+ MISSING_CASE(MEDIA_VER(i915));
+
return false;
}
@@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
* and bits have disable semantices.
*/
media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
media_fuse = ~media_fuse;
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
GEN11_GT_VEBOX_DISABLE_SHIFT;
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
} else {
--
2.37.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/i915/gt: Extract function to apply media fuses
2022-09-07 20:39 [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses Lucas De Marchi
@ 2022-09-07 20:39 ` Lucas De Marchi
2022-09-07 22:20 ` Matt Roper
2022-09-07 22:18 ` [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling " Matt Roper
1 sibling, 1 reply; 5+ messages in thread
From: Lucas De Marchi @ 2022-09-07 20:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Just like is done for compute and copy engines, extract a function to
handle media engines. While at it, be consistent on using or not the
uncore/gt/info variable aliases.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 136 ++++++++++++----------
1 file changed, 72 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5cddee7c2f1d..5b9dfa0cd467 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -665,6 +665,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
return false;
}
+static void engine_mask_apply_media_fuses(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ unsigned int logical_vdbox = 0;
+ unsigned int i;
+ u32 media_fuse, fuse1;
+ u16 vdbox_mask;
+ u16 vebox_mask;
+
+ if (MEDIA_VER(gt->i915) < 11)
+ return;
+
+ /*
+ * On newer platforms the fusing register is called 'enable' and has
+ * enable semantics, while on older platforms it is called 'disable'
+ * and bits have disable semantices.
+ */
+ media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
+ media_fuse = ~media_fuse;
+
+ vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+ vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+ GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
+ fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
+ gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+ } else {
+ gt->info.sfc_mask = ~0;
+ }
+
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (!HAS_ENGINE(gt, _VCS(i))) {
+ vdbox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vdbox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VCS(i));
+ drm_dbg(&i915->drm, "vcs%u fused off\n", i);
+ continue;
+ }
+
+ if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
+ gt->info.vdbox_sfc_access |= BIT(i);
+ logical_vdbox++;
+ }
+ drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
+ vdbox_mask, VDBOX_MASK(gt));
+ GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
+
+ for (i = 0; i < I915_MAX_VECS; i++) {
+ if (!HAS_ENGINE(gt, _VECS(i))) {
+ vebox_mask &= ~BIT(i);
+ continue;
+ }
+
+ if (!(BIT(i) & vebox_mask)) {
+ gt->info.engine_mask &= ~BIT(_VECS(i));
+ drm_dbg(&i915->drm, "vecs%u fused off\n", i);
+ }
+ }
+ drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
+ vebox_mask, VEBOX_MASK(gt));
+ GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
+}
+
static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -673,6 +741,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
unsigned long ccs_mask;
unsigned int i;
+ if (GRAPHICS_VER(i915) < 11)
+ return;
+
if (hweight32(CCS_MASK(gt)) <= 1)
return;
@@ -730,73 +801,10 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
struct intel_gt_info *info = >->info;
- struct intel_uncore *uncore = gt->uncore;
- unsigned int logical_vdbox = 0;
- unsigned int i;
- u32 media_fuse, fuse1;
- u16 vdbox_mask;
- u16 vebox_mask;
info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
- if (GRAPHICS_VER(i915) < 11)
- return info->engine_mask;
-
- /*
- * On newer platforms the fusing register is called 'enable' and has
- * enable semantics, while on older platforms it is called 'disable'
- * and bits have disable semantices.
- */
- media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
- media_fuse = ~media_fuse;
-
- vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
- vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
- GEN11_GT_VEBOX_DISABLE_SHIFT;
-
- if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
- fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
- gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
- } else {
- gt->info.sfc_mask = ~0;
- }
-
- for (i = 0; i < I915_MAX_VCS; i++) {
- if (!HAS_ENGINE(gt, _VCS(i))) {
- vdbox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vdbox_mask)) {
- info->engine_mask &= ~BIT(_VCS(i));
- drm_dbg(&i915->drm, "vcs%u fused off\n", i);
- continue;
- }
-
- if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
- gt->info.vdbox_sfc_access |= BIT(i);
- logical_vdbox++;
- }
- drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
- vdbox_mask, VDBOX_MASK(gt));
- GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
-
- for (i = 0; i < I915_MAX_VECS; i++) {
- if (!HAS_ENGINE(gt, _VECS(i))) {
- vebox_mask &= ~BIT(i);
- continue;
- }
-
- if (!(BIT(i) & vebox_mask)) {
- info->engine_mask &= ~BIT(_VECS(i));
- drm_dbg(&i915->drm, "vecs%u fused off\n", i);
- }
- }
- drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
- vebox_mask, VEBOX_MASK(gt));
- GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
-
+ engine_mask_apply_media_fuses(gt);
engine_mask_apply_compute_fuses(gt);
engine_mask_apply_copy_fuses(gt);
--
2.37.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
2022-09-07 20:39 [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses Lucas De Marchi
2022-09-07 20:39 ` [PATCH 2/2] drm/i915/gt: Extract function to apply " Lucas De Marchi
@ 2022-09-07 22:18 ` Matt Roper
2022-09-07 22:22 ` Lucas De Marchi
1 sibling, 1 reply; 5+ messages in thread
From: Matt Roper @ 2022-09-07 22:18 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 01:39:10PM -0700, Lucas De Marchi wrote:
> Check for media IP version instead of graphics since this is figuring
> out the media engines' configuration. Currently the only platform with
> non-matching graphics/media version is Meteor Lake: update the check in
> gen11_vdbox_has_sfc() so it considers not only version 12, but also any
> later version which then includes that platform.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 275ad72940c1..5cddee7c2f1d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
> */
> if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
> return false;
> - else if (GRAPHICS_VER(i915) == 12)
> + else if (MEDIA_VER(i915) >= 12)
> return (physical_vdbox % 2 == 0) ||
> !(BIT(physical_vdbox - 1) & vdbox_mask);
> - else if (GRAPHICS_VER(i915) == 11)
> + else if (MEDIA_VER(i915) == 11)
> return logical_vdbox % 2 == 0;
>
> - MISSING_CASE(GRAPHICS_VER(i915));
> + MISSING_CASE(MEDIA_VER(i915));
Do we even still need the MISSING_CASE given that we now have an
open-ended upper bound above and this is a "gen11" function that doesn't
get called at all on old platforms?
Personally I'd axe it, but up to you. Either way,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> +
> return false;
> }
>
> @@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> * and bits have disable semantices.
> */
> media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> media_fuse = ~media_fuse;
>
> vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> GEN11_GT_VEBOX_DISABLE_SHIFT;
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> } else {
> --
> 2.37.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/i915/gt: Extract function to apply media fuses
2022-09-07 20:39 ` [PATCH 2/2] drm/i915/gt: Extract function to apply " Lucas De Marchi
@ 2022-09-07 22:20 ` Matt Roper
0 siblings, 0 replies; 5+ messages in thread
From: Matt Roper @ 2022-09-07 22:20 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 01:39:11PM -0700, Lucas De Marchi wrote:
> Just like is done for compute and copy engines, extract a function to
> handle media engines. While at it, be consistent on using or not the
> uncore/gt/info variable aliases.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 136 ++++++++++++----------
> 1 file changed, 72 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 5cddee7c2f1d..5b9dfa0cd467 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -665,6 +665,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
> return false;
> }
>
> +static void engine_mask_apply_media_fuses(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + unsigned int logical_vdbox = 0;
> + unsigned int i;
> + u32 media_fuse, fuse1;
> + u16 vdbox_mask;
> + u16 vebox_mask;
> +
> + if (MEDIA_VER(gt->i915) < 11)
> + return;
> +
> + /*
> + * On newer platforms the fusing register is called 'enable' and has
> + * enable semantics, while on older platforms it is called 'disable'
> + * and bits have disable semantices.
> + */
> + media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> + media_fuse = ~media_fuse;
> +
> + vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> + vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> + GEN11_GT_VEBOX_DISABLE_SHIFT;
> +
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> + fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
> + gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> + } else {
> + gt->info.sfc_mask = ~0;
> + }
> +
> + for (i = 0; i < I915_MAX_VCS; i++) {
> + if (!HAS_ENGINE(gt, _VCS(i))) {
> + vdbox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vdbox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VCS(i));
> + drm_dbg(&i915->drm, "vcs%u fused off\n", i);
> + continue;
> + }
> +
> + if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> + gt->info.vdbox_sfc_access |= BIT(i);
> + logical_vdbox++;
> + }
> + drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> + vdbox_mask, VDBOX_MASK(gt));
> + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> +
> + for (i = 0; i < I915_MAX_VECS; i++) {
> + if (!HAS_ENGINE(gt, _VECS(i))) {
> + vebox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vebox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VECS(i));
> + drm_dbg(&i915->drm, "vecs%u fused off\n", i);
> + }
> + }
> + drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
> + vebox_mask, VEBOX_MASK(gt));
> + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> +}
> +
> static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -673,6 +741,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> unsigned long ccs_mask;
> unsigned int i;
>
> + if (GRAPHICS_VER(i915) < 11)
> + return;
> +
> if (hweight32(CCS_MASK(gt)) <= 1)
> return;
>
> @@ -730,73 +801,10 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> struct intel_gt_info *info = >->info;
> - struct intel_uncore *uncore = gt->uncore;
> - unsigned int logical_vdbox = 0;
> - unsigned int i;
> - u32 media_fuse, fuse1;
> - u16 vdbox_mask;
> - u16 vebox_mask;
>
> info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
>
> - if (GRAPHICS_VER(i915) < 11)
> - return info->engine_mask;
> -
> - /*
> - * On newer platforms the fusing register is called 'enable' and has
> - * enable semantics, while on older platforms it is called 'disable'
> - * and bits have disable semantices.
> - */
> - media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> - media_fuse = ~media_fuse;
> -
> - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> - GEN11_GT_VEBOX_DISABLE_SHIFT;
> -
> - if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> - fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> - gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> - } else {
> - gt->info.sfc_mask = ~0;
> - }
> -
> - for (i = 0; i < I915_MAX_VCS; i++) {
> - if (!HAS_ENGINE(gt, _VCS(i))) {
> - vdbox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vdbox_mask)) {
> - info->engine_mask &= ~BIT(_VCS(i));
> - drm_dbg(&i915->drm, "vcs%u fused off\n", i);
> - continue;
> - }
> -
> - if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> - gt->info.vdbox_sfc_access |= BIT(i);
> - logical_vdbox++;
> - }
> - drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> - vdbox_mask, VDBOX_MASK(gt));
> - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> -
> - for (i = 0; i < I915_MAX_VECS; i++) {
> - if (!HAS_ENGINE(gt, _VECS(i))) {
> - vebox_mask &= ~BIT(i);
> - continue;
> - }
> -
> - if (!(BIT(i) & vebox_mask)) {
> - info->engine_mask &= ~BIT(_VECS(i));
> - drm_dbg(&i915->drm, "vecs%u fused off\n", i);
> - }
> - }
> - drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
> - vebox_mask, VEBOX_MASK(gt));
> - GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> -
> + engine_mask_apply_media_fuses(gt);
> engine_mask_apply_compute_fuses(gt);
> engine_mask_apply_copy_fuses(gt);
>
> --
> 2.37.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses
2022-09-07 22:18 ` [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling " Matt Roper
@ 2022-09-07 22:22 ` Lucas De Marchi
0 siblings, 0 replies; 5+ messages in thread
From: Lucas De Marchi @ 2022-09-07 22:22 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Wed, Sep 07, 2022 at 03:18:00PM -0700, Matt Roper wrote:
>On Wed, Sep 07, 2022 at 01:39:10PM -0700, Lucas De Marchi wrote:
>> Check for media IP version instead of graphics since this is figuring
>> out the media engines' configuration. Currently the only platform with
>> non-matching graphics/media version is Meteor Lake: update the check in
>> gen11_vdbox_has_sfc() so it considers not only version 12, but also any
>> later version which then includes that platform.
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
>> 1 file changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 275ad72940c1..5cddee7c2f1d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
>> */
>> if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
>> return false;
>> - else if (GRAPHICS_VER(i915) == 12)
>> + else if (MEDIA_VER(i915) >= 12)
>> return (physical_vdbox % 2 == 0) ||
>> !(BIT(physical_vdbox - 1) & vdbox_mask);
>> - else if (GRAPHICS_VER(i915) == 11)
>> + else if (MEDIA_VER(i915) == 11)
>> return logical_vdbox % 2 == 0;
>>
>> - MISSING_CASE(GRAPHICS_VER(i915));
>> + MISSING_CASE(MEDIA_VER(i915));
>
>Do we even still need the MISSING_CASE given that we now have an
>open-ended upper bound above and this is a "gen11" function that doesn't
>get called at all on old platforms?
>
>Personally I'd axe it, but up to you. Either way,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
yeah, I will remove it
thanks
Lucas De Marchi
>
>> +
>> return false;
>> }
>>
>> @@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> * and bits have disable semantices.
>> */
>> media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
>> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
>> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
>> media_fuse = ~media_fuse;
>>
>> vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
>> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
>> GEN11_GT_VEBOX_DISABLE_SHIFT;
>>
>> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
>> fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
>> gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
>> } else {
>> --
>> 2.37.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-09-07 22:22 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-07 20:39 [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses Lucas De Marchi
2022-09-07 20:39 ` [PATCH 2/2] drm/i915/gt: Extract function to apply " Lucas De Marchi
2022-09-07 22:20 ` Matt Roper
2022-09-07 22:18 ` [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling " Matt Roper
2022-09-07 22:22 ` Lucas De Marchi
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