* [PATCH v2 0/3] drm/i915: A couple of if/else ladder refactors
@ 2022-09-13 21:09 Lucas De Marchi
2022-09-13 21:09 ` [PATCH v2 1/3] drm/i915: Invert if/else ladder for frequency read Lucas De Marchi
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Lucas De Marchi @ 2022-09-13 21:09 UTC (permalink / raw)
To: intel-gfx, Matt Roper, Lucas De Marchi, Ville Syrjälä,
Gustavo Sousa
Cc: dri-devel
Refactor code to follow the same convention as last platform first. This
series includes one patch that had already been reviewed, for frequency read
and 2 more refactors.
v2: Fix patch 2 not considering intel_gt_check_clock_frequency() call to read
frequency (Gustavo)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Lucas De Marchi (3):
drm/i915: Invert if/else ladder for frequency read
drm/i915/gt: Extract per-platform function for frequency read
drm/i915: Invert if/else ladder for stolen init
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 51 +++-----
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 174 ++++++++++++-------------
2 files changed, 97 insertions(+), 128 deletions(-)
---
base-commit: 088771790e5d121c70c358468abbebb4710eb02f
change-id: 20220908-if-ladder-df33a06d4f4e
Best regards,
--
Lucas De Marchi <lucas.demarchi@intel.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/3] drm/i915: Invert if/else ladder for frequency read
2022-09-13 21:09 [PATCH v2 0/3] drm/i915: A couple of if/else ladder refactors Lucas De Marchi
@ 2022-09-13 21:09 ` Lucas De Marchi
2022-09-13 21:09 ` [PATCH v2 2/3] drm/i915/gt: Extract per-platform function " Lucas De Marchi
2022-09-13 21:09 ` [PATCH v2 3/3] drm/i915: Invert if/else ladder for stolen init Lucas De Marchi
2 siblings, 0 replies; 5+ messages in thread
From: Lucas De Marchi @ 2022-09-13 21:09 UTC (permalink / raw)
To: intel-gfx, Matt Roper, Lucas De Marchi, Ville Syrjälä,
Gustavo Sousa
Cc: dri-devel
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
With the new ranges it's easier to see what platform a branch started to
be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
is also different, but currently there is no such platform in i915.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index d5d1b04dbcad..93608c9349fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
u32 f19_2_mhz = 19200000;
u32 f24_mhz = 24000000;
- if (GRAPHICS_VER(uncore->i915) <= 4) {
- /*
- * PRMs say:
- *
- * "The value in this register increments once every 16
- * hclks." (through the “Clocking Configuration”
- * (“CLKCFG”) MCHBAR register)
- */
- return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
- } else if (GRAPHICS_VER(uncore->i915) <= 8) {
- /*
- * PRMs say:
- *
- * "The PCU TSC counts 10ns increments; this timestamp
- * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
- * rolling over every 1.5 hours).
- */
- return f12_5_mhz;
- } else if (GRAPHICS_VER(uncore->i915) <= 9) {
+ if (GRAPHICS_VER(uncore->i915) >= 11) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
+ /*
+ * First figure out the reference frequency. There are 2 ways
+ * we can compute the frequency, either through the
+ * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
+ * tells us which one we should use.
+ */
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
- freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
+ u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
+
+ if (GRAPHICS_VER(uncore->i915) >= 11)
+ freq = gen11_get_crystal_clock_freq(uncore, c0);
+ else
+ freq = gen9_get_crystal_clock_freq(uncore, c0);
/*
* Now figure out how the command stream's timestamp
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
- CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+ GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
}
return freq;
- } else if (GRAPHICS_VER(uncore->i915) <= 12) {
+ } else if (GRAPHICS_VER(uncore->i915) >= 9) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
- /*
- * First figure out the reference frequency. There are 2 ways
- * we can compute the frequency, either through the
- * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
- * tells us which one we should use.
- */
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
- u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
-
- if (GRAPHICS_VER(uncore->i915) >= 11)
- freq = gen11_get_crystal_clock_freq(uncore, c0);
- else
- freq = gen9_get_crystal_clock_freq(uncore, c0);
+ freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
/*
* Now figure out how the command stream's timestamp
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
- GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
+ CTC_SHIFT_PARAMETER_SHIFT);
}
return freq;
+ } else if (GRAPHICS_VER(uncore->i915) >= 5) {
+ /*
+ * PRMs say:
+ *
+ * "The PCU TSC counts 10ns increments; this timestamp
+ * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
+ * rolling over every 1.5 hours).
+ */
+ return f12_5_mhz;
+ } else {
+ /*
+ * PRMs say:
+ *
+ * "The value in this register increments once every 16
+ * hclks." (through the “Clocking Configuration”
+ * (“CLKCFG”) MCHBAR register)
+ */
+ return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
}
-
- MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
- return 0;
}
void intel_gt_init_clock_frequency(struct intel_gt *gt)
--
b4 0.10.0-dev-bbe61
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/3] drm/i915/gt: Extract per-platform function for frequency read
2022-09-13 21:09 [PATCH v2 0/3] drm/i915: A couple of if/else ladder refactors Lucas De Marchi
2022-09-13 21:09 ` [PATCH v2 1/3] drm/i915: Invert if/else ladder for frequency read Lucas De Marchi
@ 2022-09-13 21:09 ` Lucas De Marchi
2022-09-14 2:19 ` Gustavo Sousa
2022-09-13 21:09 ` [PATCH v2 3/3] drm/i915: Invert if/else ladder for stolen init Lucas De Marchi
2 siblings, 1 reply; 5+ messages in thread
From: Lucas De Marchi @ 2022-09-13 21:09 UTC (permalink / raw)
To: intel-gfx, Matt Roper, Lucas De Marchi, Ville Syrjälä,
Gustavo Sousa
Cc: dri-devel
Instead of calling read_clock_frequency() to walk the if/else ladder
per platform, move the ladder to intel_gt_init_clock_frequency() and
use one function per branch.
With the new logic, it's now clear the call to
gen9_get_crystal_clock_freq() was just dead code, as gen9 is handled by
another function and there is no version 10. Remove that function and
the caller.
v2: Correctly handle intel_gt_check_clock_frequency() that also calls
the function to read clock frequency (Gustavo)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 93608c9349fd..3f656d3dba9a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -26,26 +26,6 @@ static u32 read_reference_ts_freq(struct intel_uncore *uncore)
return base_freq + frac_freq;
}
-static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore,
- u32 rpm_config_reg)
-{
- u32 f19_2_mhz = 19200000;
- u32 f24_mhz = 24000000;
- u32 crystal_clock =
- (rpm_config_reg & GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
- GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
-
- switch (crystal_clock) {
- case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
- return f19_2_mhz;
- case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
- return f24_mhz;
- default:
- MISSING_CASE(crystal_clock);
- return 0;
- }
-}
-
static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
u32 rpm_config_reg)
{
@@ -72,95 +52,106 @@ static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
}
}
-static u32 read_clock_frequency(struct intel_uncore *uncore)
+static u32 gen11_read_clock_frequency(struct intel_uncore *uncore)
{
- u32 f12_5_mhz = 12500000;
- u32 f19_2_mhz = 19200000;
- u32 f24_mhz = 24000000;
+ u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
+ u32 freq = 0;
- if (GRAPHICS_VER(uncore->i915) >= 11) {
- u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
- u32 freq = 0;
+ /*
+ * Note that on gen11+, the clock frequency may be reconfigured.
+ * We do not, and we assume nobody else does.
+ *
+ * First figure out the reference frequency. There are 2 ways
+ * we can compute the frequency, either through the
+ * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
+ * tells us which one we should use.
+ */
+ if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
+ freq = read_reference_ts_freq(uncore);
+ } else {
+ u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
+
+ freq = gen11_get_crystal_clock_freq(uncore, c0);
/*
- * First figure out the reference frequency. There are 2 ways
- * we can compute the frequency, either through the
- * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
- * tells us which one we should use.
- */
- if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
- freq = read_reference_ts_freq(uncore);
- } else {
- u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
-
- if (GRAPHICS_VER(uncore->i915) >= 11)
- freq = gen11_get_crystal_clock_freq(uncore, c0);
- else
- freq = gen9_get_crystal_clock_freq(uncore, c0);
-
- /*
- * Now figure out how the command stream's timestamp
- * register increments from this frequency (it might
- * increment only every few clock cycle).
- */
- freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
- GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
- }
-
- return freq;
- } else if (GRAPHICS_VER(uncore->i915) >= 9) {
- u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
- u32 freq = 0;
-
- if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
- freq = read_reference_ts_freq(uncore);
- } else {
- freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
-
- /*
- * Now figure out how the command stream's timestamp
- * register increments from this frequency (it might
- * increment only every few clock cycle).
- */
- freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
- CTC_SHIFT_PARAMETER_SHIFT);
- }
-
- return freq;
- } else if (GRAPHICS_VER(uncore->i915) >= 5) {
- /*
- * PRMs say:
- *
- * "The PCU TSC counts 10ns increments; this timestamp
- * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
- * rolling over every 1.5 hours).
+ * Now figure out how the command stream's timestamp
+ * register increments from this frequency (it might
+ * increment only every few clock cycle).
*/
- return f12_5_mhz;
+ freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+ GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+ }
+
+ return freq;
+}
+
+static u32 gen9_read_clock_frequency(struct intel_uncore *uncore)
+{
+ u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
+ u32 freq = 0;
+
+ if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
+ freq = read_reference_ts_freq(uncore);
} else {
+ freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000;
+
/*
- * PRMs say:
- *
- * "The value in this register increments once every 16
- * hclks." (through the “Clocking Configuration”
- * (“CLKCFG”) MCHBAR register)
+ * Now figure out how the command stream's timestamp
+ * register increments from this frequency (it might
+ * increment only every few clock cycle).
*/
- return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
+ freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
+ CTC_SHIFT_PARAMETER_SHIFT);
}
+
+ return freq;
}
-void intel_gt_init_clock_frequency(struct intel_gt *gt)
+static u32 gen5_read_clock_frequency(struct intel_uncore *uncore)
{
/*
- * Note that on gen11+, the clock frequency may be reconfigured.
- * We do not, and we assume nobody else does.
+ * PRMs say:
+ *
+ * "The PCU TSC counts 10ns increments; this timestamp
+ * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
+ * rolling over every 1.5 hours).
*/
+ return 12500000;
+}
+
+static u32 gen2_read_clock_frequency(struct intel_uncore *uncore)
+{
+ /*
+ * PRMs say:
+ *
+ * "The value in this register increments once every 16
+ * hclks." (through the “Clocking Configuration”
+ * (“CLKCFG”) MCHBAR register)
+ */
+ return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
+}
+
+static u32 read_clock_frequency(struct intel_uncore *uncore)
+{
+ if (GRAPHICS_VER(uncore->i915) >= 11)
+ return gen11_read_clock_frequency(uncore);
+ else if (GRAPHICS_VER(uncore->i915) >= 9)
+ return gen9_read_clock_frequency(uncore);
+ else if (GRAPHICS_VER(uncore->i915) >= 5)
+ return gen5_read_clock_frequency(uncore);
+ else
+ return gen2_read_clock_frequency(uncore);
+}
+
+void intel_gt_init_clock_frequency(struct intel_gt *gt)
+{
gt->clock_frequency = read_clock_frequency(gt->uncore);
- if (gt->clock_frequency)
- gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1);
/* Icelake appears to use another fixed frequency for CTX_TIMESTAMP */
if (GRAPHICS_VER(gt->i915) == 11)
gt->clock_period_ns = NSEC_PER_SEC / 13750000;
+ else if (gt->clock_frequency)
+ gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1);
GT_TRACE(gt,
"Using clock frequency: %dkHz, period: %dns, wrap: %lldms\n",
--
b4 0.10.0-dev-bbe61
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 3/3] drm/i915: Invert if/else ladder for stolen init
2022-09-13 21:09 [PATCH v2 0/3] drm/i915: A couple of if/else ladder refactors Lucas De Marchi
2022-09-13 21:09 ` [PATCH v2 1/3] drm/i915: Invert if/else ladder for frequency read Lucas De Marchi
2022-09-13 21:09 ` [PATCH v2 2/3] drm/i915/gt: Extract per-platform function " Lucas De Marchi
@ 2022-09-13 21:09 ` Lucas De Marchi
2 siblings, 0 replies; 5+ messages in thread
From: Lucas De Marchi @ 2022-09-13 21:09 UTC (permalink / raw)
To: intel-gfx, Matt Roper, Lucas De Marchi, Ville Syrjälä,
Gustavo Sousa
Cc: dri-devel
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 4f4c9461a23b..acc561c0f0aa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -430,48 +430,29 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
reserved_base = stolen_top;
reserved_size = 0;
- switch (GRAPHICS_VER(i915)) {
- case 2:
- case 3:
- break;
- case 4:
- if (!IS_G4X(i915))
- break;
- fallthrough;
- case 5:
- g4x_get_stolen_reserved(i915, uncore,
+ if (GRAPHICS_VER(i915) >= 11) {
+ icl_get_stolen_reserved(i915, uncore,
&reserved_base, &reserved_size);
- break;
- case 6:
- gen6_get_stolen_reserved(i915, uncore,
- &reserved_base, &reserved_size);
- break;
- case 7:
- if (IS_VALLEYVIEW(i915))
- vlv_get_stolen_reserved(i915, uncore,
- &reserved_base, &reserved_size);
- else
- gen7_get_stolen_reserved(i915, uncore,
- &reserved_base, &reserved_size);
- break;
- case 8:
- case 9:
+ } else if (GRAPHICS_VER(i915) >= 8) {
if (IS_LP(i915))
chv_get_stolen_reserved(i915, uncore,
&reserved_base, &reserved_size);
else
bdw_get_stolen_reserved(i915, uncore,
&reserved_base, &reserved_size);
- break;
- default:
- MISSING_CASE(GRAPHICS_VER(i915));
- fallthrough;
- case 11:
- case 12:
- icl_get_stolen_reserved(i915, uncore,
- &reserved_base,
- &reserved_size);
- break;
+ } else if (GRAPHICS_VER(i915) >= 7) {
+ if (IS_VALLEYVIEW(i915))
+ vlv_get_stolen_reserved(i915, uncore,
+ &reserved_base, &reserved_size);
+ else
+ gen7_get_stolen_reserved(i915, uncore,
+ &reserved_base, &reserved_size);
+ } else if (GRAPHICS_VER(i915) >= 6) {
+ gen6_get_stolen_reserved(i915, uncore,
+ &reserved_base, &reserved_size);
+ } else if (GRAPHICS_VER(i915) >= 5 || IS_G4X(i915)) {
+ g4x_get_stolen_reserved(i915, uncore,
+ &reserved_base, &reserved_size);
}
/*
--
b4 0.10.0-dev-bbe61
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/3] drm/i915/gt: Extract per-platform function for frequency read
2022-09-13 21:09 ` [PATCH v2 2/3] drm/i915/gt: Extract per-platform function " Lucas De Marchi
@ 2022-09-14 2:19 ` Gustavo Sousa
0 siblings, 0 replies; 5+ messages in thread
From: Gustavo Sousa @ 2022-09-14 2:19 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: dri-devel
On Tue, Sep 13, 2022 at 02:09:57PM -0700, Lucas De Marchi wrote:
> Instead of calling read_clock_frequency() to walk the if/else ladder
> per platform, move the ladder to intel_gt_init_clock_frequency() and
> use one function per branch.
>
> With the new logic, it's now clear the call to
> gen9_get_crystal_clock_freq() was just dead code, as gen9 is handled by
> another function and there is no version 10. Remove that function and
> the caller.
>
> v2: Correctly handle intel_gt_check_clock_frequency() that also calls
> the function to read clock frequency (Gustavo)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> index 93608c9349fd..3f656d3dba9a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> @@ -26,26 +26,6 @@ static u32 read_reference_ts_freq(struct intel_uncore *uncore)
> return base_freq + frac_freq;
> }
>
> -static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore,
> - u32 rpm_config_reg)
> -{
> - u32 f19_2_mhz = 19200000;
> - u32 f24_mhz = 24000000;
> - u32 crystal_clock =
> - (rpm_config_reg & GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
> - GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
> -
> - switch (crystal_clock) {
> - case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
> - return f19_2_mhz;
> - case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
> - return f24_mhz;
> - default:
> - MISSING_CASE(crystal_clock);
> - return 0;
> - }
> -}
> -
> static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
> u32 rpm_config_reg)
> {
> @@ -72,95 +52,106 @@ static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
> }
> }
>
> -static u32 read_clock_frequency(struct intel_uncore *uncore)
> +static u32 gen11_read_clock_frequency(struct intel_uncore *uncore)
> {
> - u32 f12_5_mhz = 12500000;
> - u32 f19_2_mhz = 19200000;
> - u32 f24_mhz = 24000000;
> + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> + u32 freq = 0;
>
> - if (GRAPHICS_VER(uncore->i915) >= 11) {
> - u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> - u32 freq = 0;
> + /*
> + * Note that on gen11+, the clock frequency may be reconfigured.
> + * We do not, and we assume nobody else does.
> + *
> + * First figure out the reference frequency. There are 2 ways
> + * we can compute the frequency, either through the
> + * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> + * tells us which one we should use.
> + */
> + if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> + freq = read_reference_ts_freq(uncore);
> + } else {
> + u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> +
> + freq = gen11_get_crystal_clock_freq(uncore, c0);
>
> /*
> - * First figure out the reference frequency. There are 2 ways
> - * we can compute the frequency, either through the
> - * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> - * tells us which one we should use.
> - */
> - if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> - freq = read_reference_ts_freq(uncore);
> - } else {
> - u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> -
> - if (GRAPHICS_VER(uncore->i915) >= 11)
> - freq = gen11_get_crystal_clock_freq(uncore, c0);
> - else
> - freq = gen9_get_crystal_clock_freq(uncore, c0);
> -
> - /*
> - * Now figure out how the command stream's timestamp
> - * register increments from this frequency (it might
> - * increment only every few clock cycle).
> - */
> - freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
> - }
> -
> - return freq;
> - } else if (GRAPHICS_VER(uncore->i915) >= 9) {
> - u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> - u32 freq = 0;
> -
> - if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> - freq = read_reference_ts_freq(uncore);
> - } else {
> - freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
> -
> - /*
> - * Now figure out how the command stream's timestamp
> - * register increments from this frequency (it might
> - * increment only every few clock cycle).
> - */
> - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
> - CTC_SHIFT_PARAMETER_SHIFT);
> - }
> -
> - return freq;
> - } else if (GRAPHICS_VER(uncore->i915) >= 5) {
> - /*
> - * PRMs say:
> - *
> - * "The PCU TSC counts 10ns increments; this timestamp
> - * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
> - * rolling over every 1.5 hours).
> + * Now figure out how the command stream's timestamp
> + * register increments from this frequency (it might
> + * increment only every few clock cycle).
> */
> - return f12_5_mhz;
> + freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
> + }
> +
> + return freq;
> +}
> +
> +static u32 gen9_read_clock_frequency(struct intel_uncore *uncore)
> +{
> + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> + u32 freq = 0;
> +
> + if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> + freq = read_reference_ts_freq(uncore);
> } else {
> + freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000;
> +
> /*
> - * PRMs say:
> - *
> - * "The value in this register increments once every 16
> - * hclks." (through the “Clocking Configuration”
> - * (“CLKCFG”) MCHBAR register)
> + * Now figure out how the command stream's timestamp
> + * register increments from this frequency (it might
> + * increment only every few clock cycle).
> */
> - return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> + freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
> + CTC_SHIFT_PARAMETER_SHIFT);
> }
> +
> + return freq;
> }
>
> -void intel_gt_init_clock_frequency(struct intel_gt *gt)
> +static u32 gen5_read_clock_frequency(struct intel_uncore *uncore)
> {
> /*
> - * Note that on gen11+, the clock frequency may be reconfigured.
> - * We do not, and we assume nobody else does.
> + * PRMs say:
> + *
> + * "The PCU TSC counts 10ns increments; this timestamp
> + * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
> + * rolling over every 1.5 hours).
> */
> + return 12500000;
> +}
> +
> +static u32 gen2_read_clock_frequency(struct intel_uncore *uncore)
> +{
> + /*
> + * PRMs say:
> + *
> + * "The value in this register increments once every 16
> + * hclks." (through the “Clocking Configuration”
> + * (“CLKCFG”) MCHBAR register)
> + */
> + return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> +}
> +
> +static u32 read_clock_frequency(struct intel_uncore *uncore)
> +{
> + if (GRAPHICS_VER(uncore->i915) >= 11)
> + return gen11_read_clock_frequency(uncore);
> + else if (GRAPHICS_VER(uncore->i915) >= 9)
> + return gen9_read_clock_frequency(uncore);
> + else if (GRAPHICS_VER(uncore->i915) >= 5)
> + return gen5_read_clock_frequency(uncore);
> + else
> + return gen2_read_clock_frequency(uncore);
> +}
> +
> +void intel_gt_init_clock_frequency(struct intel_gt *gt)
> +{
> gt->clock_frequency = read_clock_frequency(gt->uncore);
> - if (gt->clock_frequency)
> - gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1);
>
> /* Icelake appears to use another fixed frequency for CTX_TIMESTAMP */
> if (GRAPHICS_VER(gt->i915) == 11)
> gt->clock_period_ns = NSEC_PER_SEC / 13750000;
> + else if (gt->clock_frequency)
> + gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1);
>
> GT_TRACE(gt,
> "Using clock frequency: %dkHz, period: %dns, wrap: %lldms\n",
>
> --
> b4 0.10.0-dev-bbe61
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-09-14 2:19 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-13 21:09 [PATCH v2 0/3] drm/i915: A couple of if/else ladder refactors Lucas De Marchi
2022-09-13 21:09 ` [PATCH v2 1/3] drm/i915: Invert if/else ladder for frequency read Lucas De Marchi
2022-09-13 21:09 ` [PATCH v2 2/3] drm/i915/gt: Extract per-platform function " Lucas De Marchi
2022-09-14 2:19 ` Gustavo Sousa
2022-09-13 21:09 ` [PATCH v2 3/3] drm/i915: Invert if/else ladder for stolen init Lucas De Marchi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).