* [PATCH 0/5] drm/msm: add support for SM8450
@ 2022-09-22 11:30 Dmitry Baryshkov
2022-09-22 11:30 ` [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2022-09-22 11:30 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: David Airlie, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, freedreno
This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform.
Dmitry Baryshkov (5):
drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450
drm/msm/dsi: add support for DSI 2.6.0
drm/msm/dpu: add support for MDP_TOP blackhole
drm/msm/dpu: add support for SM8450
drm/msm: mdss add support for SM8450
drivers/gpu/drm/msm/Kconfig | 6 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 +-
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 +
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 132 ++++++++++-
drivers/gpu/drm/msm/msm_mdss.c | 8 +
11 files changed, 381 insertions(+), 15 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450
2022-09-22 11:30 [PATCH 0/5] drm/msm: add support for SM8450 Dmitry Baryshkov
@ 2022-09-22 11:30 ` Dmitry Baryshkov
2022-11-07 4:27 ` Abhinav Kumar
2022-09-22 11:30 ` [PATCH 2/5] drm/msm/dsi: add support for DSI 2.6.0 Dmitry Baryshkov
` (4 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2022-09-22 11:30 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: David Airlie, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Robert Foss, freedreno
SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.
Co-developed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/Kconfig | 6 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 132 ++++++++++++++++++++--
4 files changed, 131 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 4e0cbd682725..e6c5dfbad009 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY
Choose this option if DSI PHY on SDM845 is used on the platform.
config DRM_MSM_DSI_7NM_PHY
- bool "Enable DSI 7nm PHY driver in MSM DRM"
+ bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
depends on DRM_MSM_DSI
default y
help
- Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
- the platform.
+ Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
+ is used on the platform.
config DRM_MSM_HDMI
bool "Enable HDMI support in MSM DRM driver"
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 7fc0975cb869..97cf6b8b34cc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -567,6 +567,10 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_7nm_8150_cfgs },
{ .compatible = "qcom,sc7280-dsi-phy-7nm",
.data = &dsi_phy_7nm_7280_cfgs },
+ { .compatible = "qcom,dsi-phy-5nm-8350",
+ .data = &dsi_phy_5nm_8350_cfgs },
+ { .compatible = "qcom,dsi-phy-5nm-8450",
+ .data = &dsi_phy_5nm_8450_cfgs },
#endif
{}
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 60a99c6525b2..654cbfa14d6e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -56,6 +56,8 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
struct msm_dsi_dphy_timing {
u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 9e7fa7d88ead..1696ff150b9e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -39,8 +39,14 @@
#define VCO_REF_CLK_RATE 19200000
#define FRAC_BITS 18
+/* Hardware is pre V4.1 */
+#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0)
/* Hardware is V4.1 */
-#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
+#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1)
+/* Hardware is V4.2 */
+#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
+/* Hardware is V4.3 */
+#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
struct dsi_pll_config {
bool enable_ssc;
@@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
dec_multiple = div_u64(pll_freq * multiplier, divider);
dec = div_u64_rem(dec_multiple, multiplier, &frac);
- if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
+ if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
config->pll_clock_inverters = 0x28;
else if (pll_freq <= 1000000000ULL)
config->pll_clock_inverters = 0xa0;
@@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
void __iomem *base = pll->phy->pll_base;
u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
- if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
+ if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
if (pll->vco_current_rate >= 3100000000ULL)
analog_controls_five_1 = 0x03;
+ if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
if (pll->vco_current_rate < 1520000000ULL)
vco_config_1 = 0x08;
else if (pll->vco_current_rate < 2990000000ULL)
vco_config_1 = 0x01;
}
+ if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
+ (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
+ if (pll->vco_current_rate < 1520000000ULL)
+ vco_config_1 = 0x08;
+ else if (pll->vco_current_rate >= 2990000000ULL)
+ vco_config_1 = 0x01;
+ }
+
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
analog_controls_five_1);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
@@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
- pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
+ !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22);
- if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
+ if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) {
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
if (pll->slave)
dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
@@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
const u8 *tx_dctrl = tx_dctrl_0;
void __iomem *lane_base = phy->lane_base;
- if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)
+ if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
tx_dctrl = tx_dctrl_1;
/* Strength ctrl settings */
@@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
if (dsi_phy_hw_v4_0_is_pll_on(phy))
pr_warn("PLL turned on before configuring PHY\n");
+ /* Request for REFGEN READY */
+ if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
+ dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
+ udelay(500);
+ }
+
/* wait for REFGEN READY */
ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS,
status, (status & BIT(0)),
@@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
/* Alter PHY configurations if data rate less than 1.5GHZ*/
less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
- if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
- vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
+ if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
+ if (phy->cphy_mode) {
+ vreg_ctrl_0 = 0x51;
+ glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
+ glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
+ glbl_str_swi_cal_sel_ctrl = 0x00;
+ glbl_hstx_str_ctrl_0 = 0x00;
+ } else {
+ vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
+ glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
+ glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
+ glbl_str_swi_cal_sel_ctrl = 0x00;
+ glbl_hstx_str_ctrl_0 = 0x88;
+ }
+ } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) {
+ if (phy->cphy_mode) {
+ vreg_ctrl_0 = 0x51;
+ glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
+ glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
+ glbl_str_swi_cal_sel_ctrl = 0x00;
+ glbl_hstx_str_ctrl_0 = 0x00;
+ } else {
+ vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
+ glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00;
+ glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
+ glbl_str_swi_cal_sel_ctrl = 0x00;
+ glbl_hstx_str_ctrl_0 = 0x88;
+ }
+ } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
if (phy->cphy_mode) {
+ vreg_ctrl_0 = 0x51;
glbl_rescode_top_ctrl = 0x00;
glbl_rescode_bot_ctrl = 0x3c;
} else {
+ vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
}
glbl_str_swi_cal_sel_ctrl = 0x00;
glbl_hstx_str_ctrl_0 = 0x88;
} else {
- vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
if (phy->cphy_mode) {
+ vreg_ctrl_0 = 0x51;
glbl_str_swi_cal_sel_ctrl = 0x03;
glbl_hstx_str_ctrl_0 = 0x66;
} else {
+ vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
}
@@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
}
if (phy->cphy_mode) {
- vreg_ctrl_0 = 0x51;
vreg_ctrl_1 = 0x55;
glbl_pemph_ctrl_0 = 0x11;
lane_ctrl0 = 0x17;
@@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
pr_warn("Turning OFF PHY while PLL is on\n");
dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
+
+ /* Turn off REFGEN Vote */
+ dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
+ wmb();
+ /* Delay to ensure HW removes vote before PHY shut down */
+ udelay(2);
+
data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
/* disable all lanes */
@@ -1079,6 +1136,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.max_pll_rate = 3500000000UL,
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
+ .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1,
};
const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
@@ -1102,3 +1160,57 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
.num_dsi_phy = 1,
.quirks = DSI_PHY_7NM_QUIRK_V4_1,
};
+
+const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = {
+ .has_phy_lane = true,
+ .reg_cfg = {
+ .num = 1,
+ .regs = {
+ {"vdds", 37550, 0},
+ },
+ },
+ .ops = {
+ .enable = dsi_7nm_phy_enable,
+ .disable = dsi_7nm_phy_disable,
+ .pll_init = dsi_pll_7nm_init,
+ .save_pll_state = dsi_7nm_pll_save_state,
+ .restore_pll_state = dsi_7nm_pll_restore_state,
+ .set_continuous_clock = dsi_7nm_set_continuous_clock,
+ },
+ .min_pll_rate = 600000000UL,
+#ifdef CONFIG_64BIT
+ .max_pll_rate = 5000000000UL,
+#else
+ .max_pll_rate = ULONG_MAX,
+#endif
+ .io_start = { 0xae94400, 0xae96400 },
+ .num_dsi_phy = 2,
+ .quirks = DSI_PHY_7NM_QUIRK_V4_2,
+};
+
+const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
+ .has_phy_lane = true,
+ .reg_cfg = {
+ .num = 1,
+ .regs = {
+ {"vdds", 97800, 0},
+ },
+ },
+ .ops = {
+ .enable = dsi_7nm_phy_enable,
+ .disable = dsi_7nm_phy_disable,
+ .pll_init = dsi_pll_7nm_init,
+ .save_pll_state = dsi_7nm_pll_save_state,
+ .restore_pll_state = dsi_7nm_pll_restore_state,
+ .set_continuous_clock = dsi_7nm_set_continuous_clock,
+ },
+ .min_pll_rate = 600000000UL,
+#ifdef CONFIG_64BIT
+ .max_pll_rate = 5000000000UL,
+#else
+ .max_pll_rate = ULONG_MAX,
+#endif
+ .io_start = { 0xae94400, 0xae96400 },
+ .num_dsi_phy = 2,
+ .quirks = DSI_PHY_7NM_QUIRK_V4_3,
+};
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/5] drm/msm/dsi: add support for DSI 2.6.0
2022-09-22 11:30 [PATCH 0/5] drm/msm: add support for SM8450 Dmitry Baryshkov
2022-09-22 11:30 ` [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov
@ 2022-09-22 11:30 ` Dmitry Baryshkov
2022-09-22 11:30 ` [PATCH 3/5] drm/msm/dpu: add support for MDP_TOP blackhole Dmitry Baryshkov
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2022-09-22 11:30 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: David Airlie, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, freedreno
Add support for DSI 2.6.0 (block used on sm8450).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 7e97c239ed48..59a4cc95a251 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
&sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0,
&sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0,
+ &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
};
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 8f04e685a74e..95957fab499d 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -25,6 +25,7 @@
#define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000
#define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001
#define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000
+#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000
#define MSM_DSI_V2_VER_MINOR_8064 0x0
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/5] drm/msm/dpu: add support for MDP_TOP blackhole
2022-09-22 11:30 [PATCH 0/5] drm/msm: add support for SM8450 Dmitry Baryshkov
2022-09-22 11:30 ` [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov
2022-09-22 11:30 ` [PATCH 2/5] drm/msm/dsi: add support for DSI 2.6.0 Dmitry Baryshkov
@ 2022-09-22 11:30 ` Dmitry Baryshkov
2022-09-22 11:30 ` [PATCH 4/5] drm/msm/dpu: add support for SM8450 Dmitry Baryshkov
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2022-09-22 11:30 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: David Airlie, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, freedreno
On sm8450 a register block was removed from MDP TOP. Accessing it during
snapshotting results in NoC errors / immediate reboot. Skip accessing
these registers during snapshot.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38ab1568..4730f8268f2a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -92,6 +92,7 @@ enum {
DPU_MDP_UBWC_1_0,
DPU_MDP_UBWC_1_5,
DPU_MDP_AUDIO_SELECT,
+ DPU_MDP_PERIPH_0_REMOVED,
DPU_MDP_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 5e6e2626151e..b0bb693c10ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -939,8 +939,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
- msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
- dpu_kms->mmio + cat->mdp[0].base, "top");
+ if (top->caps->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
+ msm_disp_snapshot_add_block(disp_state, 0x380,
+ dpu_kms->mmio + cat->mdp[0].base, "top");
+ msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8,
+ dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2");
+ } else {
+ msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
+ dpu_kms->mmio + cat->mdp[0].base, "top");
+ }
pm_runtime_put_sync(&dpu_kms->pdev->dev);
}
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/5] drm/msm/dpu: add support for SM8450
2022-09-22 11:30 [PATCH 0/5] drm/msm: add support for SM8450 Dmitry Baryshkov
` (2 preceding siblings ...)
2022-09-22 11:30 ` [PATCH 3/5] drm/msm/dpu: add support for MDP_TOP blackhole Dmitry Baryshkov
@ 2022-09-22 11:30 ` Dmitry Baryshkov
2022-09-22 18:08 ` kernel test robot
2022-09-22 11:30 ` [PATCH 5/5] drm/msm: mdss " Dmitry Baryshkov
2022-09-22 11:44 ` [Freedreno] [PATCH 0/5] drm/msm: " Vinod Koul
5 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2022-09-22 11:30 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: David Airlie, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, freedreno
Add definitions for the display hardware used on Qualcomm SM8450
platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 229 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029fdc682..c647ea1207be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -124,6 +124,15 @@
BIT(MDP_AD4_0_INTR) | \
BIT(MDP_AD4_1_INTR))
+#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_7xxx_INTR) | \
+ BIT(MDP_INTF1_7xxx_INTR) | \
+ BIT(MDP_INTF2_7xxx_INTR) | \
+ BIT(MDP_INTF3_7xxx_INTR) | \
+ 0)
+
#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
BIT(DPU_WB_YUV_CONFIG) | \
@@ -364,6 +373,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8450_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sc7280_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
@@ -501,6 +524,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8450_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2B4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2BC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2C4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2B4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2BC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2C4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2BC, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sc7280_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -659,6 +709,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8450_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sc7280_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -877,6 +966,34 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
+static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 =
+ _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 =
+ _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 =
+ _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
+static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 =
+ _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
+
+static const struct dpu_sspp_cfg sm8450_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
+ sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
+ sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
+ SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
+ sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
+ SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
+ sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
+};
+
static const struct dpu_sspp_cfg sc7280_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK,
sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
@@ -1181,6 +1298,34 @@ static struct dpu_pingpong_cfg qcm2290_pp[] = {
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
};
+/* FIXME: interrupts */
+static const struct dpu_pingpong_cfg sm8450_pp[] = {
+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+ PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ -1),
+ PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ -1),
+ PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk,
+ -1,
+ -1),
+ PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk,
+ -1,
+ -1),
+};
+
/*************************************************************
* MERGE_3D sub blocks config
*************************************************************/
@@ -1198,6 +1343,13 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
};
+static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
+ MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
+ MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
+ MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
+ MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
+};
+
static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
@@ -1284,6 +1436,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
};
+static const struct dpu_intf_cfg sm8450_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+};
+
/*************************************************************
* Writeback blocks config
*************************************************************/
@@ -1397,6 +1556,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
};
+static const struct dpu_reg_dma_cfg sm8450_regdma = {
+ .base = 0x0,
+ .version = 0x00020000,
+ .trigger_sel_off = 0x119c,
+ .xin_id = 7,
+ .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
+};
+
/*************************************************************
* PERF data config
*************************************************************/
@@ -1672,6 +1839,36 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
.bw_inefficiency_factor = 120,
};
+static const struct dpu_perf_cfg sm8450_perf_data = {
+ .max_bw_low = 13600000,
+ .max_bw_high = 18200000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 800000,
+ .min_prefill_lines = 35,
+ /* FIXME: lut tables */
+ .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
+ .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
static const struct dpu_perf_cfg sc7280_perf_data = {
.max_bw_low = 4700000,
.max_bw_high = 8800000,
@@ -1876,6 +2073,32 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
.mdss_irqs = IRQ_SM8250_MASK,
};
+static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
+ .caps = &sm8450_dpu_caps,
+ .mdp_count = ARRAY_SIZE(sm8450_mdp),
+ .mdp = sm8450_mdp,
+ .ctl_count = ARRAY_SIZE(sm8450_ctl),
+ .ctl = sm8450_ctl,
+ .sspp_count = ARRAY_SIZE(sm8450_sspp),
+ .sspp = sm8450_sspp,
+ .mixer_count = ARRAY_SIZE(sm8150_lm),
+ .mixer = sm8150_lm,
+ .dspp_count = ARRAY_SIZE(sm8150_dspp),
+ .dspp = sm8150_dspp,
+ .pingpong_count = ARRAY_SIZE(sm8450_pp),
+ .pingpong = sm8450_pp,
+ .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d),
+ .merge_3d = sm8450_merge_3d,
+ .intf_count = ARRAY_SIZE(sm8450_intf),
+ .intf = sm8450_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = &sm8250_regdma,
+ .perf = &sm8450_perf_data,
+ .mdss_irqs = IRQ_SM8450_MASK,
+};
+
static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
.caps = &sc7280_dpu_caps,
.mdp_count = ARRAY_SIZE(sc7280_mdp),
@@ -1934,6 +2157,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
+ { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
};
const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4730f8268f2a..4526ef71c326 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -46,6 +46,7 @@
#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
+#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index d3b0ed0a9c6c..6d8e1bb3b3cc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -195,6 +195,8 @@ enum dpu_pingpong {
PINGPONG_3,
PINGPONG_4,
PINGPONG_5,
+ PINGPONG_6,
+ PINGPONG_7,
PINGPONG_S0,
PINGPONG_MAX
};
@@ -203,6 +205,7 @@ enum dpu_merge_3d {
MERGE_3D_0 = 1,
MERGE_3D_1,
MERGE_3D_2,
+ MERGE_3D_3,
MERGE_3D_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index b0bb693c10ac..4520d6ac8956 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1313,6 +1313,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
+ { .compatible = "qcom,sm8450-dpu", },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 5/5] drm/msm: mdss add support for SM8450
2022-09-22 11:30 [PATCH 0/5] drm/msm: add support for SM8450 Dmitry Baryshkov
` (3 preceding siblings ...)
2022-09-22 11:30 ` [PATCH 4/5] drm/msm/dpu: add support for SM8450 Dmitry Baryshkov
@ 2022-09-22 11:30 ` Dmitry Baryshkov
2022-09-22 11:44 ` [Freedreno] [PATCH 0/5] drm/msm: " Vinod Koul
5 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2022-09-22 11:30 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: David Airlie, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, freedreno
Add support for the MDSS block on SM8450 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e13c5c12b775..9e011762396b 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -219,6 +219,13 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
case DPU_HW_VER_720:
writel_relaxed(0x101e, msm_mdss->mmio + UBWC_STATIC);
break;
+ case DPU_HW_VER_810:
+ /* FIXME: merge with 6.0.0? */
+ /* TODO: 0x102e for LP_DDR4 */
+ writel_relaxed(0x103e, msm_mdss->mmio + UBWC_STATIC);
+ writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
+ writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
+ break;
}
return ret;
@@ -447,6 +454,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8450-mdss" },
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
--
2.35.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Freedreno] [PATCH 0/5] drm/msm: add support for SM8450
2022-09-22 11:30 [PATCH 0/5] drm/msm: add support for SM8450 Dmitry Baryshkov
` (4 preceding siblings ...)
2022-09-22 11:30 ` [PATCH 5/5] drm/msm: mdss " Dmitry Baryshkov
@ 2022-09-22 11:44 ` Vinod Koul
5 siblings, 0 replies; 11+ messages in thread
From: Vinod Koul @ 2022-09-22 11:44 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, David Airlie, linux-arm-msm, Bjorn Andersson,
Abhinav Kumar, dri-devel, Stephen Boyd, Sean Paul
On 22-09-22, 14:30, Dmitry Baryshkov wrote:
> This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform.
Tested this on DM8450-HDK with HDMI and it works for me.
For whole series:
Tested-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
>
> Dmitry Baryshkov (5):
> drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450
> drm/msm/dsi: add support for DSI 2.6.0
> drm/msm/dpu: add support for MDP_TOP blackhole
> drm/msm/dpu: add support for SM8450
> drm/msm: mdss add support for SM8450
>
> drivers/gpu/drm/msm/Kconfig | 6 +-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 +-
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 +
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 132 ++++++++++-
> drivers/gpu/drm/msm/msm_mdss.c | 8 +
> 11 files changed, 381 insertions(+), 15 deletions(-)
>
> --
> 2.35.1
--
~Vinod
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/5] drm/msm/dpu: add support for SM8450
2022-09-22 11:30 ` [PATCH 4/5] drm/msm/dpu: add support for SM8450 Dmitry Baryshkov
@ 2022-09-22 18:08 ` kernel test robot
0 siblings, 0 replies; 11+ messages in thread
From: kernel test robot @ 2022-09-22 18:08 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Abhinav Kumar
Cc: kbuild-all, David Airlie, linux-arm-msm, Bjorn Andersson, llvm,
dri-devel, Stephen Boyd, freedreno
Hi Dmitry,
I love your patch! Perhaps something to improve:
[auto build test WARNING on next-20220921]
[also build test WARNING on linus/master v6.0-rc6]
[cannot apply to drm-misc/drm-misc-next v6.0-rc6 v6.0-rc5 v6.0-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-msm-add-support-for-SM8450/20220922-193223
base: 483fed3b5dc8ce3644c83d24240cf5756fb0993e
config: s390-randconfig-r044-20220922 (https://download.01.org/0day-ci/archive/20220923/202209230114.2apdPcjg-lkp@intel.com/config)
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install s390 cross compiling tool for clang build
# apt-get install binutils-s390x-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/b25f303f8c65c2776a67e8c6ac66c379d74170ce
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Dmitry-Baryshkov/drm-msm-add-support-for-SM8450/20220922-193223
git checkout b25f303f8c65c2776a67e8c6ac66c379d74170ce
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=s390 SHELL=/bin/bash drivers/gpu/drm/msm/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:8:
In file included from include/linux/of_address.h:7:
In file included from include/linux/io.h:13:
In file included from arch/s390/include/asm/io.h:75:
include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __raw_readb(PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
~~~~~~~~~~ ^
include/uapi/linux/byteorder/big_endian.h:37:59: note: expanded from macro '__le16_to_cpu'
#define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x))
^
include/uapi/linux/swab.h:102:54: note: expanded from macro '__swab16'
#define __swab16(x) (__u16)__builtin_bswap16((__u16)(x))
^
In file included from drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:8:
In file included from include/linux/of_address.h:7:
In file included from include/linux/io.h:13:
In file included from arch/s390/include/asm/io.h:75:
include/asm-generic/io.h:573:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
~~~~~~~~~~ ^
include/uapi/linux/byteorder/big_endian.h:35:59: note: expanded from macro '__le32_to_cpu'
#define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x))
^
include/uapi/linux/swab.h:115:54: note: expanded from macro '__swab32'
#define __swab32(x) (__u32)__builtin_bswap32((__u32)(x))
^
In file included from drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:8:
In file included from include/linux/of_address.h:7:
In file included from include/linux/io.h:13:
In file included from arch/s390/include/asm/io.h:75:
include/asm-generic/io.h:584:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writeb(value, PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:594:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:604:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:692:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
readsb(PCI_IOBASE + addr, buffer, count);
~~~~~~~~~~ ^
include/asm-generic/io.h:700:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
readsw(PCI_IOBASE + addr, buffer, count);
~~~~~~~~~~ ^
include/asm-generic/io.h:708:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
readsl(PCI_IOBASE + addr, buffer, count);
~~~~~~~~~~ ^
include/asm-generic/io.h:717:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
writesb(PCI_IOBASE + addr, buffer, count);
~~~~~~~~~~ ^
include/asm-generic/io.h:726:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
writesw(PCI_IOBASE + addr, buffer, count);
~~~~~~~~~~ ^
include/asm-generic/io.h:735:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
writesl(PCI_IOBASE + addr, buffer, count);
~~~~~~~~~~ ^
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:1559:37: warning: unused variable 'sm8450_regdma' [-Wunused-const-variable]
static const struct dpu_reg_dma_cfg sm8450_regdma = {
^
13 warnings generated.
vim +/sm8450_regdma +1559 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
1558
> 1559 static const struct dpu_reg_dma_cfg sm8450_regdma = {
1560 .base = 0x0,
1561 .version = 0x00020000,
1562 .trigger_sel_off = 0x119c,
1563 .xin_id = 7,
1564 .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
1565 };
1566
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450
2022-09-22 11:30 ` [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov
@ 2022-11-07 4:27 ` Abhinav Kumar
2022-11-07 23:02 ` Dmitry Baryshkov
0 siblings, 1 reply; 11+ messages in thread
From: Abhinav Kumar @ 2022-11-07 4:27 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: David Airlie, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Robert Foss, freedreno
On 9/22/2022 4:30 AM, Dmitry Baryshkov wrote:
> SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
> with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
> variants inside the common 5+7nm driver.
I do realize that there is common code across PHYs but i am concerned
about this type of unification of phy drivers.
If we have features which are PHY sequence dependent such as ULPS, this
will just complicate things for us.
Also some PHY registers might get added some might get removed across
chipsets as this is the most frequently changed component.
Even in this patch, I see this added to dsi_7nm_phy_disable()
> + /* Turn off REFGEN Vote */
> + dsi_phy_write(base +
REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
> + wmb();
> + /* Delay to ensure HW removes vote before PHY shut down */
> + udelay(2);
> +
What would be the impact of writing this for the existing 7nm PHY?
I am having some access issues to check the software interface so wanted
to check.
>
> Co-developed-by: Robert Foss <robert.foss@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/Kconfig | 6 +-
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 132 ++++++++++++++++++++--
> 4 files changed, 131 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> index 4e0cbd682725..e6c5dfbad009 100644
> --- a/drivers/gpu/drm/msm/Kconfig
> +++ b/drivers/gpu/drm/msm/Kconfig
> @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY
> Choose this option if DSI PHY on SDM845 is used on the platform.
>
> config DRM_MSM_DSI_7NM_PHY
> - bool "Enable DSI 7nm PHY driver in MSM DRM"
> + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
> depends on DRM_MSM_DSI
> default y
> help
> - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
> - the platform.
> + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
> + is used on the platform.
>
> config DRM_MSM_HDMI
> bool "Enable HDMI support in MSM DRM driver"
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 7fc0975cb869..97cf6b8b34cc 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -567,6 +567,10 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> .data = &dsi_phy_7nm_8150_cfgs },
> { .compatible = "qcom,sc7280-dsi-phy-7nm",
> .data = &dsi_phy_7nm_7280_cfgs },
> + { .compatible = "qcom,dsi-phy-5nm-8350",
> + .data = &dsi_phy_5nm_8350_cfgs },
> + { .compatible = "qcom,dsi-phy-5nm-8450",
> + .data = &dsi_phy_5nm_8450_cfgs },
> #endif
> {}
> };
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 60a99c6525b2..654cbfa14d6e 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -56,6 +56,8 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
>
> struct msm_dsi_dphy_timing {
> u32 clk_zero;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 9e7fa7d88ead..1696ff150b9e 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -39,8 +39,14 @@
> #define VCO_REF_CLK_RATE 19200000
> #define FRAC_BITS 18
>
> +/* Hardware is pre V4.1 */
> +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0)
> /* Hardware is V4.1 */
> -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
> +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1)
> +/* Hardware is V4.2 */
> +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
> +/* Hardware is V4.3 */
> +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
>
> struct dsi_pll_config {
> bool enable_ssc;
> @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
> dec_multiple = div_u64(pll_freq * multiplier, divider);
> dec = div_u64_rem(dec_multiple, multiplier, &frac);
>
> - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
> config->pll_clock_inverters = 0x28;
> else if (pll_freq <= 1000000000ULL)
> config->pll_clock_inverters = 0xa0;
> @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
> void __iomem *base = pll->phy->pll_base;
> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
>
> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
> if (pll->vco_current_rate >= 3100000000ULL)
> analog_controls_five_1 = 0x03;
>
> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> if (pll->vco_current_rate < 1520000000ULL)
> vco_config_1 = 0x08;
> else if (pll->vco_current_rate < 2990000000ULL)
> vco_config_1 = 0x01;
> }
>
> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
> + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
> + if (pll->vco_current_rate < 1520000000ULL)
> + vco_config_1 = 0x08;
> + else if (pll->vco_current_rate >= 2990000000ULL)
> + vco_config_1 = 0x01;
> + }
> +
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
> analog_controls_five_1);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
> @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
> - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
> + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22);
>
> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) {
> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
> if (pll->slave)
> dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
> @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
> const u8 *tx_dctrl = tx_dctrl_0;
> void __iomem *lane_base = phy->lane_base;
>
> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)
> + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
> tx_dctrl = tx_dctrl_1;
>
> /* Strength ctrl settings */
> @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> if (dsi_phy_hw_v4_0_is_pll_on(phy))
> pr_warn("PLL turned on before configuring PHY\n");
>
> + /* Request for REFGEN READY */
> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> + dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
> + udelay(500);
> + }
> +
> /* wait for REFGEN READY */
> ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS,
> status, (status & BIT(0)),
> @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> /* Alter PHY configurations if data rate less than 1.5GHZ*/
> less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
>
> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> + if (phy->cphy_mode) {
> + vreg_ctrl_0 = 0x51;
> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
> + glbl_str_swi_cal_sel_ctrl = 0x00;
> + glbl_hstx_str_ctrl_0 = 0x00;
> + } else {
> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
> + glbl_str_swi_cal_sel_ctrl = 0x00;
> + glbl_hstx_str_ctrl_0 = 0x88;
> + }
> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) {
> + if (phy->cphy_mode) {
> + vreg_ctrl_0 = 0x51;
> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
> + glbl_str_swi_cal_sel_ctrl = 0x00;
> + glbl_hstx_str_ctrl_0 = 0x00;
> + } else {
> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00;
> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
> + glbl_str_swi_cal_sel_ctrl = 0x00;
> + glbl_hstx_str_ctrl_0 = 0x88;
> + }
> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
> if (phy->cphy_mode) {
> + vreg_ctrl_0 = 0x51;
> glbl_rescode_top_ctrl = 0x00;
> glbl_rescode_bot_ctrl = 0x3c;
> } else {
> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
> }
> glbl_str_swi_cal_sel_ctrl = 0x00;
> glbl_hstx_str_ctrl_0 = 0x88;
> } else {
> - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
> if (phy->cphy_mode) {
> + vreg_ctrl_0 = 0x51;
> glbl_str_swi_cal_sel_ctrl = 0x03;
> glbl_hstx_str_ctrl_0 = 0x66;
> } else {
> + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
> glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
> glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
> }
> @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> }
>
> if (phy->cphy_mode) {
> - vreg_ctrl_0 = 0x51;
> vreg_ctrl_1 = 0x55;
> glbl_pemph_ctrl_0 = 0x11;
> lane_ctrl0 = 0x17;
> @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
> pr_warn("Turning OFF PHY while PLL is on\n");
>
> dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
> +
> + /* Turn off REFGEN Vote */
> + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
> + wmb();
> + /* Delay to ensure HW removes vote before PHY shut down */
> + udelay(2);
> +
> data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>
> /* disable all lanes */
> @@ -1079,6 +1136,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
> .max_pll_rate = 3500000000UL,
> .io_start = { 0xae94400, 0xae96400 },
> .num_dsi_phy = 2,
> + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1,
> };
>
> const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
> @@ -1102,3 +1160,57 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
> .num_dsi_phy = 1,
> .quirks = DSI_PHY_7NM_QUIRK_V4_1,
> };
> +
> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = {
> + .has_phy_lane = true,
> + .reg_cfg = {
> + .num = 1,
> + .regs = {
> + {"vdds", 37550, 0},
> + },
> + },
> + .ops = {
> + .enable = dsi_7nm_phy_enable,
> + .disable = dsi_7nm_phy_disable,
> + .pll_init = dsi_pll_7nm_init,
> + .save_pll_state = dsi_7nm_pll_save_state,
> + .restore_pll_state = dsi_7nm_pll_restore_state,
> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
> + },
> + .min_pll_rate = 600000000UL,
> +#ifdef CONFIG_64BIT
> + .max_pll_rate = 5000000000UL,
> +#else
> + .max_pll_rate = ULONG_MAX,
> +#endif
> + .io_start = { 0xae94400, 0xae96400 },
> + .num_dsi_phy = 2,
> + .quirks = DSI_PHY_7NM_QUIRK_V4_2,
> +};
> +
> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
> + .has_phy_lane = true,
> + .reg_cfg = {
> + .num = 1,
> + .regs = {
> + {"vdds", 97800, 0},
> + },
> + },
> + .ops = {
> + .enable = dsi_7nm_phy_enable,
> + .disable = dsi_7nm_phy_disable,
> + .pll_init = dsi_pll_7nm_init,
> + .save_pll_state = dsi_7nm_pll_save_state,
> + .restore_pll_state = dsi_7nm_pll_restore_state,
> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
> + },
> + .min_pll_rate = 600000000UL,
> +#ifdef CONFIG_64BIT
> + .max_pll_rate = 5000000000UL,
> +#else
> + .max_pll_rate = ULONG_MAX,
> +#endif
> + .io_start = { 0xae94400, 0xae96400 },
> + .num_dsi_phy = 2,
> + .quirks = DSI_PHY_7NM_QUIRK_V4_3,
> +};
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450
2022-11-07 4:27 ` Abhinav Kumar
@ 2022-11-07 23:02 ` Dmitry Baryshkov
2022-11-16 7:07 ` Abhinav Kumar
0 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2022-11-07 23:02 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: David Airlie, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Robert Foss, freedreno
On 07/11/2022 07:27, Abhinav Kumar wrote:
>
>
> On 9/22/2022 4:30 AM, Dmitry Baryshkov wrote:
>> SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
>> with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
>> variants inside the common 5+7nm driver.
>
> I do realize that there is common code across PHYs but i am concerned
> about this type of unification of phy drivers.
This more or less follows downstream, which has unifier v4.0 driver.
> If we have features which are PHY sequence dependent such as ULPS, this
> will just complicate things for us.
During development we initially tried to create a separate 5nm driver.
However this resulted in huuuge code duplication. This would be prone to
significant amount of errors if we change one of the drivers at some
point and not another one.
> Also some PHY registers might get added some might get removed across
> chipsets as this is the most frequently changed component.
Yes, I completely agree here. However beforehand we have successfully
managed to have per-generation drivers, handling minor differences with
quirks.
>
> Even in this patch, I see this added to dsi_7nm_phy_disable()
>
> > + /* Turn off REFGEN Vote */
> > + dsi_phy_write(base +
> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
> > + wmb();
> > + /* Delay to ensure HW removes vote before PHY shut down */
> > + udelay(2);
> > +
>
> What would be the impact of writing this for the existing 7nm PHY?
Let's probably guard this with the v4.3 check.
>
> I am having some access issues to check the software interface so wanted
> to check.
I don't remember having any issues on RB5, but I did not run any special
checks.
>
>>
>> Co-developed-by: Robert Foss <robert.foss@linaro.org>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> drivers/gpu/drm/msm/Kconfig | 6 +-
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 132 ++++++++++++++++++++--
>> 4 files changed, 131 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
>> index 4e0cbd682725..e6c5dfbad009 100644
>> --- a/drivers/gpu/drm/msm/Kconfig
>> +++ b/drivers/gpu/drm/msm/Kconfig
>> @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY
>> Choose this option if DSI PHY on SDM845 is used on the platform.
>> config DRM_MSM_DSI_7NM_PHY
>> - bool "Enable DSI 7nm PHY driver in MSM DRM"
>> + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
>> depends on DRM_MSM_DSI
>> default y
>> help
>> - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
>> - the platform.
>> + Choose this option if DSI PHY on
>> SM8150/SM8250/SM8350/SM8450/SC7280
>> + is used on the platform.
>> config DRM_MSM_HDMI
>> bool "Enable HDMI support in MSM DRM driver"
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> index 7fc0975cb869..97cf6b8b34cc 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> @@ -567,6 +567,10 @@ static const struct of_device_id
>> dsi_phy_dt_match[] = {
>> .data = &dsi_phy_7nm_8150_cfgs },
>> { .compatible = "qcom,sc7280-dsi-phy-7nm",
>> .data = &dsi_phy_7nm_7280_cfgs },
>> + { .compatible = "qcom,dsi-phy-5nm-8350",
>> + .data = &dsi_phy_5nm_8350_cfgs },
>> + { .compatible = "qcom,dsi-phy-5nm-8450",
>> + .data = &dsi_phy_5nm_8450_cfgs },
>> #endif
>> {}
>> };
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> index 60a99c6525b2..654cbfa14d6e 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> @@ -56,6 +56,8 @@ extern const struct msm_dsi_phy_cfg
>> dsi_phy_10nm_8998_cfgs;
>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
>> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
>> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
>> struct msm_dsi_dphy_timing {
>> u32 clk_zero;
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index 9e7fa7d88ead..1696ff150b9e 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -39,8 +39,14 @@
>> #define VCO_REF_CLK_RATE 19200000
>> #define FRAC_BITS 18
>> +/* Hardware is pre V4.1 */
>> +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0)
>> /* Hardware is V4.1 */
>> -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
>> +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1)
>> +/* Hardware is V4.2 */
>> +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
>> +/* Hardware is V4.3 */
>> +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
>> struct dsi_pll_config {
>> bool enable_ssc;
>> @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct
>> dsi_pll_7nm *pll, struct dsi_pll_config
>> dec_multiple = div_u64(pll_freq * multiplier, divider);
>> dec = div_u64_rem(dec_multiple, multiplier, &frac);
>> - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
>> config->pll_clock_inverters = 0x28;
>> else if (pll_freq <= 1000000000ULL)
>> config->pll_clock_inverters = 0xa0;
>> @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct
>> dsi_pll_7nm *pll)
>> void __iomem *base = pll->phy->pll_base;
>> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
>> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
>> if (pll->vco_current_rate >= 3100000000ULL)
>> analog_controls_five_1 = 0x03;
>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>> if (pll->vco_current_rate < 1520000000ULL)
>> vco_config_1 = 0x08;
>> else if (pll->vco_current_rate < 2990000000ULL)
>> vco_config_1 = 0x01;
>> }
>> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
>> + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
>> + if (pll->vco_current_rate < 1520000000ULL)
>> + vco_config_1 = 0x08;
>> + else if (pll->vco_current_rate >= 2990000000ULL)
>> + vco_config_1 = 0x01;
>> + }
>> +
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
>> analog_controls_five_1);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1,
>> vco_config_1);
>> @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct
>> dsi_pll_7nm *pll)
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
>> - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
>> + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ?
>> 0x3f : 0x22);
>> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) {
>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
>> if (pll->slave)
>> dsi_phy_write(pll->slave->phy->pll_base +
>> REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
>> @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct
>> msm_dsi_phy *phy)
>> const u8 *tx_dctrl = tx_dctrl_0;
>> void __iomem *lane_base = phy->lane_base;
>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)
>> + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
>> tx_dctrl = tx_dctrl_1;
>> /* Strength ctrl settings */
>> @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy
>> *phy,
>> if (dsi_phy_hw_v4_0_is_pll_on(phy))
>> pr_warn("PLL turned on before configuring PHY\n");
>> + /* Request for REFGEN READY */
>> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
>> + dsi_phy_write(phy->base +
>> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
>> + udelay(500);
>> + }
>> +
>> /* wait for REFGEN READY */
>> ret = readl_poll_timeout_atomic(base +
>> REG_DSI_7nm_PHY_CMN_PHY_STATUS,
>> status, (status & BIT(0)),
>> @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy
>> *phy,
>> /* Alter PHY configurations if data rate less than 1.5GHZ*/
>> less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
>> + if (phy->cphy_mode) {
>> + vreg_ctrl_0 = 0x51;
>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
>> + glbl_str_swi_cal_sel_ctrl = 0x00;
>> + glbl_hstx_str_ctrl_0 = 0x00;
>> + } else {
>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
>> + glbl_str_swi_cal_sel_ctrl = 0x00;
>> + glbl_hstx_str_ctrl_0 = 0x88;
>> + }
>> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) {
>> + if (phy->cphy_mode) {
>> + vreg_ctrl_0 = 0x51;
>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
>> + glbl_str_swi_cal_sel_ctrl = 0x00;
>> + glbl_hstx_str_ctrl_0 = 0x00;
>> + } else {
>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00;
>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
>> + glbl_str_swi_cal_sel_ctrl = 0x00;
>> + glbl_hstx_str_ctrl_0 = 0x88;
>> + }
>> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>> if (phy->cphy_mode) {
>> + vreg_ctrl_0 = 0x51;
>> glbl_rescode_top_ctrl = 0x00;
>> glbl_rescode_bot_ctrl = 0x3c;
>> } else {
>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
>> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
>> }
>> glbl_str_swi_cal_sel_ctrl = 0x00;
>> glbl_hstx_str_ctrl_0 = 0x88;
>> } else {
>> - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
>> if (phy->cphy_mode) {
>> + vreg_ctrl_0 = 0x51;
>> glbl_str_swi_cal_sel_ctrl = 0x03;
>> glbl_hstx_str_ctrl_0 = 0x66;
>> } else {
>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
>> glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 :
>> 0x00;
>> glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
>> }
>> @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy
>> *phy,
>> }
>> if (phy->cphy_mode) {
>> - vreg_ctrl_0 = 0x51;
>> vreg_ctrl_1 = 0x55;
>> glbl_pemph_ctrl_0 = 0x11;
>> lane_ctrl0 = 0x17;
So far this is the largest chunk to handle the difference between
platforms. And I think it was a mess even before we tried adding the
4.2/4.3 versions.
>> @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct
>> msm_dsi_phy *phy)
>> pr_warn("Turning OFF PHY while PLL is on\n");
>> dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
>> +
>> + /* Turn off REFGEN Vote */
>> + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10,
>> 0x0);
>> + wmb();
>> + /* Delay to ensure HW removes vote before PHY shut down */
>> + udelay(2);
>> +
>> data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>> /* disable all lanes */
>> @@ -1079,6 +1136,7 @@ const struct msm_dsi_phy_cfg
>> dsi_phy_7nm_8150_cfgs = {
>> .max_pll_rate = 3500000000UL,
>> .io_start = { 0xae94400, 0xae96400 },
>> .num_dsi_phy = 2,
>> + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1,
>> };
>> const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
>> @@ -1102,3 +1160,57 @@ const struct msm_dsi_phy_cfg
>> dsi_phy_7nm_7280_cfgs = {
>> .num_dsi_phy = 1,
>> .quirks = DSI_PHY_7NM_QUIRK_V4_1,
>> };
>> +
>> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = {
>> + .has_phy_lane = true,
>> + .reg_cfg = {
>> + .num = 1,
>> + .regs = {
>> + {"vdds", 37550, 0},
>> + },
>> + },
>> + .ops = {
>> + .enable = dsi_7nm_phy_enable,
>> + .disable = dsi_7nm_phy_disable,
>> + .pll_init = dsi_pll_7nm_init,
>> + .save_pll_state = dsi_7nm_pll_save_state,
>> + .restore_pll_state = dsi_7nm_pll_restore_state,
>> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
>> + },
>> + .min_pll_rate = 600000000UL,
>> +#ifdef CONFIG_64BIT
>> + .max_pll_rate = 5000000000UL,
>> +#else
>> + .max_pll_rate = ULONG_MAX,
>> +#endif
>> + .io_start = { 0xae94400, 0xae96400 },
>> + .num_dsi_phy = 2,
>> + .quirks = DSI_PHY_7NM_QUIRK_V4_2,
>> +};
>> +
>> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
>> + .has_phy_lane = true,
>> + .reg_cfg = {
>> + .num = 1,
>> + .regs = {
>> + {"vdds", 97800, 0},
>> + },
>> + },
>> + .ops = {
>> + .enable = dsi_7nm_phy_enable,
>> + .disable = dsi_7nm_phy_disable,
>> + .pll_init = dsi_pll_7nm_init,
>> + .save_pll_state = dsi_7nm_pll_save_state,
>> + .restore_pll_state = dsi_7nm_pll_restore_state,
>> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
>> + },
>> + .min_pll_rate = 600000000UL,
>> +#ifdef CONFIG_64BIT
>> + .max_pll_rate = 5000000000UL,
>> +#else
>> + .max_pll_rate = ULONG_MAX,
>> +#endif
>> + .io_start = { 0xae94400, 0xae96400 },
>> + .num_dsi_phy = 2,
>> + .quirks = DSI_PHY_7NM_QUIRK_V4_3,
>> +};
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450
2022-11-07 23:02 ` Dmitry Baryshkov
@ 2022-11-16 7:07 ` Abhinav Kumar
0 siblings, 0 replies; 11+ messages in thread
From: Abhinav Kumar @ 2022-11-16 7:07 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: David Airlie, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Robert Foss, freedreno
On 11/7/2022 3:02 PM, Dmitry Baryshkov wrote:
> On 07/11/2022 07:27, Abhinav Kumar wrote:
>>
>>
>> On 9/22/2022 4:30 AM, Dmitry Baryshkov wrote:
>>> SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
>>> with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
>>> variants inside the common 5+7nm driver.
>>
>> I do realize that there is common code across PHYs but i am concerned
>> about this type of unification of phy drivers.
>
> This more or less follows downstream, which has unifier v4.0 driver.
>
Ack, I just observed the same. Thanks for the pointer.
Its still prone to sequencing issues though. But for now, this is okay.
>> If we have features which are PHY sequence dependent such as ULPS,
>> this will just complicate things for us.
>
> During development we initially tried to create a separate 5nm driver.
> However this resulted in huuuge code duplication. This would be prone to
> significant amount of errors if we change one of the drivers at some
> point and not another one.
>
>> Also some PHY registers might get added some might get removed across
>> chipsets as this is the most frequently changed component.
>
> Yes, I completely agree here. However beforehand we have successfully
> managed to have per-generation drivers, handling minor differences with
> quirks.
>
I kind of agree with Konrad's earlier comment that "QUIRK" is really not
the right naming for this. Its actually different phy sub-versions.
A cleanup is needed to change or move away from quirk terminology for this.
>>
>> Even in this patch, I see this added to dsi_7nm_phy_disable()
>>
>> > + /* Turn off REFGEN Vote */
>> > + dsi_phy_write(base +
>> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
>> > + wmb();
>> > + /* Delay to ensure HW removes vote before PHY shut down */
>> > + udelay(2);
>> > +
>>
>> What would be the impact of writing this for the existing 7nm PHY?
>
> Let's probably guard this with the v4.3 check.
hmmm, i see that in downstream also we are doing this for 7nm and 5nm
PHYs. I am now wondering whether a write to 0 along with the 2 microsec
delay was just missed out while writing the 7nm PHY. If so, can you move
that to a separate patch instead of this one as a "fix". Adding it to
this patch creates an impression that this is specific to the 5nm
changes but seems like they arent.
>
>>
>> I am having some access issues to check the software interface so
>> wanted to check.
>
> I don't remember having any issues on RB5, but I did not run any special
> checks.
When I meant access issues, I meant some permissions issue internally
for accessing software register documentation not register access issues
on the device :)
>
>>
>>>
>>> Co-developed-by: Robert Foss <robert.foss@linaro.org>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/Kconfig | 6 +-
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +
>>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 132 ++++++++++++++++++++--
>>> 4 files changed, 131 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
>>> index 4e0cbd682725..e6c5dfbad009 100644
>>> --- a/drivers/gpu/drm/msm/Kconfig
>>> +++ b/drivers/gpu/drm/msm/Kconfig
>>> @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY
>>> Choose this option if DSI PHY on SDM845 is used on the platform.
>>> config DRM_MSM_DSI_7NM_PHY
>>> - bool "Enable DSI 7nm PHY driver in MSM DRM"
>>> + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
>>> depends on DRM_MSM_DSI
>>> default y
>>> help
>>> - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
>>> - the platform.
>>> + Choose this option if DSI PHY on
>>> SM8150/SM8250/SM8350/SM8450/SC7280
>>> + is used on the platform.
>>> config DRM_MSM_HDMI
>>> bool "Enable HDMI support in MSM DRM driver"
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>>> index 7fc0975cb869..97cf6b8b34cc 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>>> @@ -567,6 +567,10 @@ static const struct of_device_id
>>> dsi_phy_dt_match[] = {
>>> .data = &dsi_phy_7nm_8150_cfgs },
>>> { .compatible = "qcom,sc7280-dsi-phy-7nm",
>>> .data = &dsi_phy_7nm_7280_cfgs },
>>> + { .compatible = "qcom,dsi-phy-5nm-8350",
>>> + .data = &dsi_phy_5nm_8350_cfgs },
>>> + { .compatible = "qcom,dsi-phy-5nm-8450",
>>> + .data = &dsi_phy_5nm_8450_cfgs },
>>> #endif
>>> {}
>>> };
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>>> index 60a99c6525b2..654cbfa14d6e 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>>> @@ -56,6 +56,8 @@ extern const struct msm_dsi_phy_cfg
>>> dsi_phy_10nm_8998_cfgs;
>>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
>>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
>>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
>>> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
>>> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
>>> struct msm_dsi_dphy_timing {
>>> u32 clk_zero;
>>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> index 9e7fa7d88ead..1696ff150b9e 100644
>>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>>> @@ -39,8 +39,14 @@
>>> #define VCO_REF_CLK_RATE 19200000
>>> #define FRAC_BITS 18
>>> +/* Hardware is pre V4.1 */
>>> +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0)
>>> /* Hardware is V4.1 */
>>> -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
>>> +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1)
>>> +/* Hardware is V4.2 */
>>> +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
>>> +/* Hardware is V4.3 */
>>> +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
>>> struct dsi_pll_config {
>>> bool enable_ssc;
>>> @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct
>>> dsi_pll_7nm *pll, struct dsi_pll_config
>>> dec_multiple = div_u64(pll_freq * multiplier, divider);
>>> dec = div_u64_rem(dec_multiple, multiplier, &frac);
>>> - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
>>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
>>> config->pll_clock_inverters = 0x28;
>>> else if (pll_freq <= 1000000000ULL)
>>> config->pll_clock_inverters = 0xa0;
>>> @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct
>>> dsi_pll_7nm *pll)
>>> void __iomem *base = pll->phy->pll_base;
>>> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
>>> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>>> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
>>> if (pll->vco_current_rate >= 3100000000ULL)
>>> analog_controls_five_1 = 0x03;
>>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>>> if (pll->vco_current_rate < 1520000000ULL)
>>> vco_config_1 = 0x08;
>>> else if (pll->vco_current_rate < 2990000000ULL)
>>> vco_config_1 = 0x01;
>>> }
>>> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
>>> + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
>>> + if (pll->vco_current_rate < 1520000000ULL)
>>> + vco_config_1 = 0x08;
>>> + else if (pll->vco_current_rate >= 2990000000ULL)
>>> + vco_config_1 = 0x01;
>>> + }
>>> +
>>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
>>> analog_controls_five_1);
>>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1,
>>> vco_config_1);
>>> @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct
>>> dsi_pll_7nm *pll)
>>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
>>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
>>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
>>> - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f :
>>> 0x22);
>>> + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ?
>>> 0x3f : 0x22);
>>> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>>> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) {
>>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
>>> if (pll->slave)
>>> dsi_phy_write(pll->slave->phy->pll_base +
>>> REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
>>> @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct
>>> msm_dsi_phy *phy)
>>> const u8 *tx_dctrl = tx_dctrl_0;
>>> void __iomem *lane_base = phy->lane_base;
>>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)
>>> + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
>>> tx_dctrl = tx_dctrl_1;
>>> /* Strength ctrl settings */
>>> @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy
>>> *phy,
>>> if (dsi_phy_hw_v4_0_is_pll_on(phy))
>>> pr_warn("PLL turned on before configuring PHY\n");
>>> + /* Request for REFGEN READY */
>>> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
>>> + dsi_phy_write(phy->base +
>>> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
>>> + udelay(500);
>>> + }
>>> +
>>> /* wait for REFGEN READY */
>>> ret = readl_poll_timeout_atomic(base +
>>> REG_DSI_7nm_PHY_CMN_PHY_STATUS,
>>> status, (status & BIT(0)),
>>> @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct
>>> msm_dsi_phy *phy,
>>> /* Alter PHY configurations if data rate less than 1.5GHZ*/
>>> less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
>>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>>> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>>> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
>>> + if (phy->cphy_mode) {
>>> + vreg_ctrl_0 = 0x51;
>>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
>>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
>>> + glbl_str_swi_cal_sel_ctrl = 0x00;
>>> + glbl_hstx_str_ctrl_0 = 0x00;
>>> + } else {
>>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
>>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
>>> + glbl_str_swi_cal_sel_ctrl = 0x00;
>>> + glbl_hstx_str_ctrl_0 = 0x88;
>>> + }
>>> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) {
>>> + if (phy->cphy_mode) {
>>> + vreg_ctrl_0 = 0x51;
>>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
>>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
>>> + glbl_str_swi_cal_sel_ctrl = 0x00;
>>> + glbl_hstx_str_ctrl_0 = 0x00;
>>> + } else {
>>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00;
>>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39;
>>> + glbl_str_swi_cal_sel_ctrl = 0x00;
>>> + glbl_hstx_str_ctrl_0 = 0x88;
>>> + }
>>> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
>>> if (phy->cphy_mode) {
>>> + vreg_ctrl_0 = 0x51;
>>> glbl_rescode_top_ctrl = 0x00;
>>> glbl_rescode_bot_ctrl = 0x3c;
>>> } else {
>>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
>>> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
>>> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
>>> }
>>> glbl_str_swi_cal_sel_ctrl = 0x00;
>>> glbl_hstx_str_ctrl_0 = 0x88;
>>> } else {
>>> - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
>>> if (phy->cphy_mode) {
>>> + vreg_ctrl_0 = 0x51;
>>> glbl_str_swi_cal_sel_ctrl = 0x03;
>>> glbl_hstx_str_ctrl_0 = 0x66;
>>> } else {
>>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
>>> glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 :
>>> 0x00;
>>> glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
>>> }
>>> @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy
>>> *phy,
>>> }
>>> if (phy->cphy_mode) {
>>> - vreg_ctrl_0 = 0x51;
>>> vreg_ctrl_1 = 0x55;
>>> glbl_pemph_ctrl_0 = 0x11;
>>> lane_ctrl0 = 0x17;
>
> So far this is the largest chunk to handle the difference between
> platforms. And I think it was a mess even before we tried adding the
> 4.2/4.3 versions.
A cleaner way to handle this would be to have separate _phy_enable()
calls for DPHY and CPHY to clear out this mess.
Add a "phy_type" to the phy_cfg which shall decide which phy call gets
executed (an idea derived from the downstream phy).
I am not sure if you want to absorb that change in this series but if
you do it will be a welcome cleanup otherwise we will keep compounding
the mess.
>
>>> @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct
>>> msm_dsi_phy *phy)
>>> pr_warn("Turning OFF PHY while PLL is on\n");
>>> dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
>>> +
>>> + /* Turn off REFGEN Vote */
>>> + dsi_phy_write(base +
>>> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
>>> + wmb();
>>> + /* Delay to ensure HW removes vote before PHY shut down */
>>> + udelay(2);
>>> +
>>> data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
>>> /* disable all lanes */
>>> @@ -1079,6 +1136,7 @@ const struct msm_dsi_phy_cfg
>>> dsi_phy_7nm_8150_cfgs = {
>>> .max_pll_rate = 3500000000UL,
>>> .io_start = { 0xae94400, 0xae96400 },
>>> .num_dsi_phy = 2,
>>> + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1,
>>> };
>>> const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
>>> @@ -1102,3 +1160,57 @@ const struct msm_dsi_phy_cfg
>>> dsi_phy_7nm_7280_cfgs = {
>>> .num_dsi_phy = 1,
>>> .quirks = DSI_PHY_7NM_QUIRK_V4_1,
>>> };
>>> +
>>> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = {
>>> + .has_phy_lane = true,
>>> + .reg_cfg = {
>>> + .num = 1,
>>> + .regs = {
>>> + {"vdds", 37550, 0},
>>> + },
>>> + },
>>> + .ops = {
>>> + .enable = dsi_7nm_phy_enable,
>>> + .disable = dsi_7nm_phy_disable,
>>> + .pll_init = dsi_pll_7nm_init,
>>> + .save_pll_state = dsi_7nm_pll_save_state,
>>> + .restore_pll_state = dsi_7nm_pll_restore_state,
>>> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
>>> + },
>>> + .min_pll_rate = 600000000UL,
>>> +#ifdef CONFIG_64BIT
>>> + .max_pll_rate = 5000000000UL,
>>> +#else
>>> + .max_pll_rate = ULONG_MAX,
>>> +#endif
>>> + .io_start = { 0xae94400, 0xae96400 },
>>> + .num_dsi_phy = 2,
>>> + .quirks = DSI_PHY_7NM_QUIRK_V4_2,
>>> +};
>>> +
>>> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
>>> + .has_phy_lane = true,
>>> + .reg_cfg = {
>>> + .num = 1,
>>> + .regs = {
>>> + {"vdds", 97800, 0},
>>> + },
>>> + },
>>> + .ops = {
>>> + .enable = dsi_7nm_phy_enable,
>>> + .disable = dsi_7nm_phy_disable,
>>> + .pll_init = dsi_pll_7nm_init,
>>> + .save_pll_state = dsi_7nm_pll_save_state,
>>> + .restore_pll_state = dsi_7nm_pll_restore_state,
>>> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
>>> + },
>>> + .min_pll_rate = 600000000UL,
>>> +#ifdef CONFIG_64BIT
>>> + .max_pll_rate = 5000000000UL,
>>> +#else
>>> + .max_pll_rate = ULONG_MAX,
>>> +#endif
>>> + .io_start = { 0xae94400, 0xae96400 },
>>> + .num_dsi_phy = 2,
>>> + .quirks = DSI_PHY_7NM_QUIRK_V4_3,
>>> +};
>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-11-16 7:08 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-22 11:30 [PATCH 0/5] drm/msm: add support for SM8450 Dmitry Baryshkov
2022-09-22 11:30 ` [PATCH 1/5] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov
2022-11-07 4:27 ` Abhinav Kumar
2022-11-07 23:02 ` Dmitry Baryshkov
2022-11-16 7:07 ` Abhinav Kumar
2022-09-22 11:30 ` [PATCH 2/5] drm/msm/dsi: add support for DSI 2.6.0 Dmitry Baryshkov
2022-09-22 11:30 ` [PATCH 3/5] drm/msm/dpu: add support for MDP_TOP blackhole Dmitry Baryshkov
2022-09-22 11:30 ` [PATCH 4/5] drm/msm/dpu: add support for SM8450 Dmitry Baryshkov
2022-09-22 18:08 ` kernel test robot
2022-09-22 11:30 ` [PATCH 5/5] drm/msm: mdss " Dmitry Baryshkov
2022-09-22 11:44 ` [Freedreno] [PATCH 0/5] drm/msm: " Vinod Koul
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