* [PATCH 0/5] i915: CAGF and RC6 changes for MTL
@ 2022-10-19 23:37 Ashutosh Dixit
2022-10-19 23:37 ` [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf Ashutosh Dixit
` (4 more replies)
0 siblings, 5 replies; 17+ messages in thread
From: Ashutosh Dixit @ 2022-10-19 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6 residency functions to accept register
ID's" based on code review feedback
v6:
- Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
functions to accept register ID's"
- Re-add "drm/i915: Use GEN12_RPSTAT register for GT freq" to this series
v7: Rebuild, identical to v6
v8:
- Add "drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf" to the series
(based on Rodrigo's review) to consistently use REG_FIELD_GET
- Minor changes to other patches, please see individual patches for changelogs
Ashutosh Dixit (2):
drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
drm/i915/gt: Use RC6 residency types as arguments to residency
functions
Badal Nilawar (2):
drm/i915/mtl: Modify CAGF functions for MTL
drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Don Hiatt (1):
drm/i915: Use GEN12_RPSTAT register for GT freq
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 87 ++++++++++++++-----
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 22 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 +--
drivers/gpu/drm/i915/gt/intel_rc6.c | 64 +++++++++-----
drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++-
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 51 ++++++++---
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 9 +-
10 files changed, 197 insertions(+), 82 deletions(-)
--
2.38.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
2022-10-19 23:37 [PATCH 0/5] i915: CAGF and RC6 changes for MTL Ashutosh Dixit
@ 2022-10-19 23:37 ` Ashutosh Dixit
2022-10-21 16:11 ` Rodrigo Vivi
2022-10-19 23:37 ` [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq Ashutosh Dixit
` (3 subsequent siblings)
4 siblings, 1 reply; 17+ messages in thread
From: Ashutosh Dixit @ 2022-10-19 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi
Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
extract reg fields. This allows future patches touching this code to also
consistently use REG_FIELD_GET and friends.
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 12 ++++--------
drivers/gpu/drm/i915/gt/intel_rps.c | 11 +++++------
3 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 40d0a3be42acf..979e602946549 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -307,7 +307,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
MEMSTAT_VID_SHIFT);
drm_printf(p, "Current P-state: %d\n",
- (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
+ REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat));
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
u32 rpmodectl, freq_sts;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c0..35c039573294c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -794,12 +794,9 @@
#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010)
#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014)
#define GEN6_RPSTAT1 _MMIO(0xa01c)
-#define GEN6_CAGF_SHIFT 8
-#define HSW_CAGF_SHIFT 7
-#define GEN9_CAGF_SHIFT 23
-#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
-#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
-#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
+#define GEN6_CAGF_MASK REG_GENMASK(14, 8)
+#define HSW_CAGF_MASK REG_GENMASK(13, 7)
+#define GEN9_CAGF_MASK REG_GENMASK(31, 23)
#define GEN6_RP_CONTROL _MMIO(0xa024)
#define GEN6_RP_MEDIA_TURBO (1 << 11)
#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
@@ -1370,8 +1367,7 @@
#define MEMSTAT_ILK _MMIO(0x111f8)
#define MEMSTAT_VID_MASK 0x7f00
#define MEMSTAT_VID_SHIFT 8
-#define MEMSTAT_PSTATE_MASK 0x00f8
-#define MEMSTAT_PSTATE_SHIFT 3
+#define MEMSTAT_PSTATE_MASK REG_GENMASK(7, 3)
#define MEMSTAT_MON_ACTV (1 << 2)
#define MEMSTAT_SRC_CTL_MASK 0x0003
#define MEMSTAT_SRC_CTL_CORE 0
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index fc23c562d9b2a..5bd6671554a6e 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2074,16 +2074,15 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
u32 cagf;
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- cagf = (rpstat >> 8) & 0xff;
+ cagf = REG_FIELD_GET(RPE_MASK, rpstat);
else if (GRAPHICS_VER(i915) >= 9)
- cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+ cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
- cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
+ cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat);
else if (GRAPHICS_VER(i915) >= 6)
- cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
+ cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat);
else
- cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
- MEMSTAT_PSTATE_SHIFT);
+ cagf = gen5_invert_freq(rps, REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rpstat));
return cagf;
}
--
2.38.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq
2022-10-19 23:37 [PATCH 0/5] i915: CAGF and RC6 changes for MTL Ashutosh Dixit
2022-10-19 23:37 ` [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf Ashutosh Dixit
@ 2022-10-19 23:37 ` Ashutosh Dixit
2022-10-21 16:12 ` [Intel-gfx] " Rodrigo Vivi
2022-10-19 23:37 ` [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL Ashutosh Dixit
` (2 subsequent siblings)
4 siblings, 1 reply; 17+ messages in thread
From: Ashutosh Dixit @ 2022-10-19 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi
From: Don Hiatt <don.hiatt@intel.com>
On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
GT is in RC6.
v2:
- Fixed review comments(Ashutosh)
- Added function intel_rps_read_rpstat_fw to read RPSTAT without
forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko)
v3:
- Updated commit title and message for more clarity (Ashutosh)
- Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in
read_cagf (Ashutosh)
v4: Remove GEN12_CAGF_SHIFT and use REG_FIELD_GET (Rodrigo)
Cc: Don Hiatt <donhiatt@gmail.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Don Hiatt <don.hiatt@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++----
drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
drivers/gpu/drm/i915/i915_pmu.c | 3 +--
4 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 35c039573294c..f8c4f758ac0b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1539,6 +1539,7 @@
#define GEN12_RPSTAT1 _MMIO(0x1381b4)
#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
+#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 5bd6671554a6e..da6b969f554b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps)
rps_disable_interrupts(rps);
}
+u32 intel_rps_read_rpstat_fw(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ i915_reg_t rpstat;
+
+ rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+ return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat);
+}
+
+u32 intel_rps_read_rpstat(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ i915_reg_t rpstat;
+
+ rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+ return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
+}
+
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 cagf;
- if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ if (GRAPHICS_VER(i915) >= 12)
+ cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = REG_FIELD_GET(RPE_MASK, rpstat);
else if (GRAPHICS_VER(i915) >= 9)
cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
@@ -2093,7 +2115,9 @@ static u32 read_cagf(struct intel_rps *rps)
struct intel_uncore *uncore = rps_to_uncore(rps);
u32 freq;
- if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ if (GRAPHICS_VER(i915) >= 12) {
+ freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
+ } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
vlv_punit_get(i915);
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
@@ -2259,7 +2283,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
- rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ rpstat = intel_rps_read_rpstat(rps);
rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
@@ -2394,7 +2418,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
rps->pm_intrmsk_mbz);
- drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
+ drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps));
drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
intel_gpu_freq(rps, caps.min_freq));
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 110300dfd4383..9e1cad9ba0e9c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
u32 intel_rps_read_punit_req(struct intel_rps *rps);
u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_rpstat(struct intel_rps *rps);
+u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
void intel_rps_raise_unslice(struct intel_rps *rps);
void intel_rps_lower_unslice(struct intel_rps *rps);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 958b37123bf12..67140a87182f8 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -371,7 +371,6 @@ static void
frequency_sample(struct intel_gt *gt, unsigned int period_ns)
{
struct drm_i915_private *i915 = gt->i915;
- struct intel_uncore *uncore = gt->uncore;
struct i915_pmu *pmu = &i915->pmu;
struct intel_rps *rps = >->rps;
@@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
* case we assume the system is running at the intended
* frequency. Fortunately, the read should rarely fail!
*/
- val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
+ val = intel_rps_read_rpstat_fw(rps);
if (val)
val = intel_rps_get_cagf(rps, val);
else
--
2.38.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL
2022-10-19 23:37 [PATCH 0/5] i915: CAGF and RC6 changes for MTL Ashutosh Dixit
2022-10-19 23:37 ` [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf Ashutosh Dixit
2022-10-19 23:37 ` [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq Ashutosh Dixit
@ 2022-10-19 23:37 ` Ashutosh Dixit
2022-10-21 16:02 ` [Intel-gfx] " Dixit, Ashutosh
2022-10-19 23:37 ` [PATCH 4/5] drm/i915/gt: Use RC6 residency types as arguments to residency functions Ashutosh Dixit
2022-10-19 23:37 ` [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia Ashutosh Dixit
4 siblings, 1 reply; 17+ messages in thread
From: Ashutosh Dixit @ 2022-10-19 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi
From: Badal Nilawar <badal.nilawar@intel.com>
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
v3: Added comment about registers not needing forcewake for Gen12+ and
returning 0 freq in RC6
v4: Use REG_FIELD_GET and uncore (Rodrigo)
Bspec: 66300
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++
drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++++++++++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f8c4f758ac0b1..d8dbd0ac3b064 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -21,6 +21,10 @@
*/
#define PERF_REG(offset) _MMIO(offset)
+/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
+#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
+#define MTL_CAGF_MASK REG_GENMASK(8, 0)
+
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index da6b969f554b6..63cc7c538401e 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 cagf;
- if (GRAPHICS_VER(i915) >= 12)
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
+ else if (GRAPHICS_VER(i915) >= 12)
cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = REG_FIELD_GET(RPE_MASK, rpstat);
@@ -2115,7 +2117,13 @@ static u32 read_cagf(struct intel_rps *rps)
struct intel_uncore *uncore = rps_to_uncore(rps);
u32 freq;
- if (GRAPHICS_VER(i915) >= 12) {
+ /*
+ * For Gen12+ reading freq from HW does not need a forcewake and
+ * registers will return 0 freq when GT is in RC6
+ */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
+ freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+ } else if (GRAPHICS_VER(i915) >= 12) {
freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
vlv_punit_get(i915);
--
2.38.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/5] drm/i915/gt: Use RC6 residency types as arguments to residency functions
2022-10-19 23:37 [PATCH 0/5] i915: CAGF and RC6 changes for MTL Ashutosh Dixit
` (2 preceding siblings ...)
2022-10-19 23:37 ` [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL Ashutosh Dixit
@ 2022-10-19 23:37 ` Ashutosh Dixit
2022-10-21 16:15 ` Rodrigo Vivi
2022-10-19 23:37 ` [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia Ashutosh Dixit
4 siblings, 1 reply; 17+ messages in thread
From: Ashutosh Dixit @ 2022-10-19 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi
Previously RC6 residency functions directly accepted RC6 residency register
MMIO offsets (there are four RC6 residency registers). This worked but
required an assumption on the residency register layout so was not future
proof.
Therefore change RC6 residency functions to accept RC6 residency types
instead of register MMIO offsets. The knowledge of register offsets as well
as ID to offset mapping is now maintained solely in intel_rc6 and can be
tailored for different platforms and different register layouts as need
arises.
v2: Address review comments by Jani N
- Change residency functions to accept RC6 residency types instead of
register ID's
- s/intel_rc6_print_rc5_res/intel_rc6_print_residency/
- Remove "const enum" in function arguments
- Naming: intel_rc6_* for enum
- Use INTEL_RC6_RES_MAX and other minor changes
v3: Don't include intel_rc6_types.h in intel_rc6.h (Jani)
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Reported-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++------
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_rc6.c | 55 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++--
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 ++++-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 6 +-
7 files changed, 72 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 979e602946549..5d6b346831393 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -83,19 +83,6 @@ static int fw_domains_show(struct seq_file *m, void *data)
}
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains);
-static void print_rc6_res(struct seq_file *m,
- const char *title,
- const i915_reg_t reg)
-{
- struct intel_gt *gt = m->private;
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- seq_printf(m, "%s %u (%llu us)\n", title,
- intel_uncore_read(gt->uncore, reg),
- intel_rc6_residency_us(>->rc6, reg));
-}
-
static int vlv_drpc(struct seq_file *m)
{
struct intel_gt *gt = m->private;
@@ -115,8 +102,8 @@ static int vlv_drpc(struct seq_file *m)
seq_printf(m, "Media Power Well: %s\n",
(pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
- print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6);
- print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
+ intel_rc6_print_residency(m, "Render RC6 residency since boot:", INTEL_RC6_RES_RC6);
+ intel_rc6_print_residency(m, "Media RC6 residency since boot:", INTEL_RC6_RES_VLV_MEDIA);
return fw_domains_show(m, NULL);
}
@@ -192,11 +179,11 @@ static int gen6_drpc(struct seq_file *m)
}
/* Not exactly sure what this is */
- print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
- GEN6_GT_GFX_RC6_LOCKED);
- print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
- print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
- print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
+ intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since boot:",
+ INTEL_RC6_RES_RC6_LOCKED);
+ intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
+ intel_rc6_print_residency(m, "RC6+ residency since boot:", INTEL_RC6_RES_RC6p);
+ intel_rc6_print_residency(m, "RC6++ residency since boot:", INTEL_RC6_RES_RC6pp);
if (GRAPHICS_VER(i915) <= 7) {
seq_printf(m, "RC6 voltage: %dmV\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 9041609523697..19a60000e052c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -93,13 +93,13 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
#ifdef CONFIG_PM
-static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
+static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
{
intel_wakeref_t wakeref;
u64 res = 0;
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- res = intel_rc6_residency_us(>->rc6, reg);
+ res = intel_rc6_residency_us(>->rc6, id);
return DIV_ROUND_CLOSEST_ULL(res, 1000);
}
@@ -123,7 +123,7 @@ static ssize_t rc6_enable_show(struct device *dev,
static u32 __rc6_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6);
+ return get_residency(gt, INTEL_RC6_RES_RC6);
}
static ssize_t rc6_residency_ms_show(struct device *dev,
@@ -138,7 +138,7 @@ static ssize_t rc6_residency_ms_show(struct device *dev,
static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6p);
+ return get_residency(gt, INTEL_RC6_RES_RC6p);
}
static ssize_t rc6p_residency_ms_show(struct device *dev,
@@ -153,7 +153,7 @@ static ssize_t rc6p_residency_ms_show(struct device *dev,
static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6pp);
+ return get_residency(gt, INTEL_RC6_RES_RC6pp);
}
static ssize_t rc6pp_residency_ms_show(struct device *dev,
@@ -168,7 +168,7 @@ static ssize_t rc6pp_residency_ms_show(struct device *dev,
static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, VLV_GT_MEDIA_RC6);
+ return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
}
static ssize_t media_rc6_residency_ms_show(struct device *dev,
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index f8d0523f4c18e..6db4e60d5fba5 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -551,6 +551,14 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
}
+static void rc6_res_reg_init(struct intel_rc6 *rc6)
+{
+ rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
+ rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
+ rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
+ rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+}
+
void intel_rc6_init(struct intel_rc6 *rc6)
{
struct drm_i915_private *i915 = rc6_to_i915(rc6);
@@ -562,6 +570,8 @@ void intel_rc6_init(struct intel_rc6 *rc6)
if (!rc6_supported(rc6))
return;
+ rc6_res_reg_init(rc6);
+
if (IS_CHERRYVIEW(i915))
err = chv_rc6_init(rc6);
else if (IS_VALLEYVIEW(i915))
@@ -736,31 +746,19 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
return lower | (u64)upper << 8;
}
-u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
+u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
{
struct drm_i915_private *i915 = rc6_to_i915(rc6);
struct intel_uncore *uncore = rc6_to_uncore(rc6);
u64 time_hw, prev_hw, overflow_hw;
+ i915_reg_t reg = rc6->res_reg[id];
unsigned int fw_domains;
unsigned long flags;
- unsigned int i;
u32 mul, div;
if (!rc6->supported)
return 0;
- /*
- * Store previous hw counter values for counter wrap-around handling.
- *
- * There are only four interesting registers and they live next to each
- * other so we can use the relative address, compared to the smallest
- * one as the index into driver storage.
- */
- i = (i915_mmio_reg_offset(reg) -
- i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
- if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))
- return 0;
-
fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
spin_lock_irqsave(&uncore->lock, flags);
@@ -789,11 +787,11 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
/*
* Counter wrap handling.
*
- * But relying on a sufficient frequency of queries otherwise counters
- * can still wrap.
+ * Store previous hw counter values for counter wrap-around handling. But
+ * relying on a sufficient frequency of queries otherwise counters can still wrap.
*/
- prev_hw = rc6->prev_hw_residency[i];
- rc6->prev_hw_residency[i] = time_hw;
+ prev_hw = rc6->prev_hw_residency[id];
+ rc6->prev_hw_residency[id] = time_hw;
/* RC6 delta from last sample. */
if (time_hw >= prev_hw)
@@ -802,8 +800,8 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
time_hw += overflow_hw - prev_hw;
/* Add delta to RC6 extended raw driver copy. */
- time_hw += rc6->cur_residency[i];
- rc6->cur_residency[i] = time_hw;
+ time_hw += rc6->cur_residency[id];
+ rc6->cur_residency[id] = time_hw;
intel_uncore_forcewake_put__locked(uncore, fw_domains);
spin_unlock_irqrestore(&uncore->lock, flags);
@@ -811,9 +809,22 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
return mul_u64_u32_div(time_hw, mul, div);
}
-u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
+u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
+{
+ return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000);
+}
+
+void intel_rc6_print_residency(struct seq_file *m, const char *title,
+ enum intel_rc6_res_type id)
{
- return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
+ struct intel_gt *gt = m->private;
+ i915_reg_t reg = gt->rc6.res_reg[id];
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ seq_printf(m, "%s %u (%llu us)\n", title,
+ intel_uncore_read(gt->uncore, reg),
+ intel_rc6_residency_us(>->rc6, id));
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h
index b6fea71afc223..456fa668a2769 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.h
@@ -6,10 +6,11 @@
#ifndef INTEL_RC6_H
#define INTEL_RC6_H
-#include "i915_reg_defs.h"
+#include <linux/types.h>
-struct intel_engine_cs;
+enum intel_rc6_res_type;
struct intel_rc6;
+struct seq_file;
void intel_rc6_init(struct intel_rc6 *rc6);
void intel_rc6_fini(struct intel_rc6 *rc6);
@@ -21,7 +22,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6);
void intel_rc6_enable(struct intel_rc6 *rc6);
void intel_rc6_disable(struct intel_rc6 *rc6);
-u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg);
-u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg);
+u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
+u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
+void intel_rc6_print_residency(struct seq_file *m, const char *title,
+ enum intel_rc6_res_type id);
#endif /* INTEL_RC6_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
index e747492b2f46e..fa23c4dce00b4 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
@@ -13,9 +13,20 @@
struct drm_i915_gem_object;
+/* RC6 residency types */
+enum intel_rc6_res_type {
+ INTEL_RC6_RES_RC6_LOCKED,
+ INTEL_RC6_RES_RC6,
+ INTEL_RC6_RES_RC6p,
+ INTEL_RC6_RES_RC6pp,
+ INTEL_RC6_RES_MAX,
+ INTEL_RC6_RES_VLV_MEDIA = INTEL_RC6_RES_RC6p,
+};
+
struct intel_rc6 {
- u64 prev_hw_residency[4];
- u64 cur_residency[4];
+ i915_reg_t res_reg[INTEL_RC6_RES_MAX];
+ u64 prev_hw_residency[INTEL_RC6_RES_MAX];
+ u64 cur_residency[INTEL_RC6_RES_MAX];
u32 ctl_enable;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 8c70b7e120749..2ceeadecc639c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -19,11 +19,11 @@ static u64 rc6_residency(struct intel_rc6 *rc6)
/* XXX VLV_GT_MEDIA_RC6? */
- result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
+ result = intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6);
if (HAS_RC6p(rc6_to_i915(rc6)))
- result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p);
+ result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6p);
if (HAS_RC6pp(rc6_to_i915(rc6)))
- result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6pp);
+ result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6pp);
return result;
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 67140a87182f8..52531ab28c5f5 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -148,13 +148,13 @@ static u64 __get_rc6(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
u64 val;
- val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6);
+ val = intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6);
if (HAS_RC6p(i915))
- val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p);
+ val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6p);
if (HAS_RC6pp(i915))
- val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6pp);
+ val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6pp);
return val;
}
--
2.38.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia
2022-10-19 23:37 [PATCH 0/5] i915: CAGF and RC6 changes for MTL Ashutosh Dixit
` (3 preceding siblings ...)
2022-10-19 23:37 ` [PATCH 4/5] drm/i915/gt: Use RC6 residency types as arguments to residency functions Ashutosh Dixit
@ 2022-10-19 23:37 ` Ashutosh Dixit
2022-10-21 16:35 ` Rodrigo Vivi
4 siblings, 1 reply; 17+ messages in thread
From: Ashutosh Dixit @ 2022-10-19 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi
From: Badal Nilawar <badal.nilawar@intel.com>
Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.
v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code refactor (Jani N)
v4: Move MTL branch to top in drpc_show
v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_rc6.c | 17 ++++--
3 files changed, 75 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 5d6b346831393..f15a7486a9866 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -256,6 +256,60 @@ static int ilk_drpc(struct seq_file *m)
return 0;
}
+static int mtl_drpc(struct seq_file *m)
+{
+ struct intel_gt *gt = m->private;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 gt_core_status, rcctl1, mt_fwake_req;
+ u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
+
+ mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
+ gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+
+ rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+ mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
+ mtl_powergate_status = intel_uncore_read(uncore,
+ GEN9_PWRGT_DOMAIN_STATUS);
+
+ seq_printf(m, "RC6 Enabled: %s\n",
+ str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (gt->type == GT_MEDIA) {
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE));
+ } else {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE));
+ }
+
+ seq_puts(m, "Current RC state: ");
+ switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {
+ case MTL_CC0:
+ seq_puts(m, "on\n");
+ break;
+ case MTL_CC6:
+ seq_puts(m, "RC6\n");
+ break;
+ default:
+ seq_puts(m, "Unknown\n");
+ break;
+ }
+
+ seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
+ if (gt->type == GT_MEDIA)
+ seq_printf(m, "Media Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ else
+ seq_printf(m, "Render Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+
+ /* Works for both render and media gt's */
+ intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
+
+ return fw_domains_show(m, NULL);
+}
+
static int drpc_show(struct seq_file *m, void *unused)
{
struct intel_gt *gt = m->private;
@@ -264,7 +318,9 @@ static int drpc_show(struct seq_file *m, void *unused)
int err = -ENODEV;
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
- if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ err = mtl_drpc(m);
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d8dbd0ac3b064..a0ddaf243593c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -24,6 +24,9 @@
/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
#define MTL_CAGF_MASK REG_GENMASK(8, 0)
+#define MTL_CC0 0x0
+#define MTL_CC6 0x3
+#define MTL_CC_MASK REG_GENMASK(12, 9)
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
@@ -1512,6 +1515,8 @@
#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
+#define MTL_MEDIA_MC6 _MMIO(0x138048)
+
#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 6db4e60d5fba5..2ee4051e4d961 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -553,10 +553,19 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
static void rc6_res_reg_init(struct intel_rc6 *rc6)
{
- rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
- rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
- rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
- rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+ memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
+
+ switch (rc6_to_gt(rc6)->type) {
+ case GT_MEDIA:
+ rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
+ break;
+ default:
+ rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
+ rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
+ rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
+ rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+ break;
+ }
}
void intel_rc6_init(struct intel_rc6 *rc6)
--
2.38.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL
2022-10-19 23:37 ` [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL Ashutosh Dixit
@ 2022-10-21 16:02 ` Dixit, Ashutosh
2022-10-21 16:12 ` Rodrigo Vivi
0 siblings, 1 reply; 17+ messages in thread
From: Dixit, Ashutosh @ 2022-10-21 16:02 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
On Wed, 19 Oct 2022 16:37:19 -0700, Ashutosh Dixit wrote:
>
> From: Badal Nilawar <badal.nilawar@intel.com>
>
> Update CAGF functions for MTL to get actual resolved frequency of 3D and
> SAMedia.
>
> v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
> Move MTL branches in cagf functions to top (MattR)
> Fix commit message (Andi)
> v3: Added comment about registers not needing forcewake for Gen12+ and
> returning 0 freq in RC6
> v4: Use REG_FIELD_GET and uncore (Rodrigo)
>
> Bspec: 66300
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++
> drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++++++++++--
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index f8c4f758ac0b1..d8dbd0ac3b064 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -21,6 +21,10 @@
> */
> #define PERF_REG(offset) _MMIO(offset)
>
> +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
> +#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
> +#define MTL_CAGF_MASK REG_GENMASK(8, 0)
> +
> /* RPM unit config (Gen8+) */
> #define RPM_CONFIG0 _MMIO(0xd00)
> #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index da6b969f554b6..63cc7c538401e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> struct drm_i915_private *i915 = rps_to_i915(rps);
> u32 cagf;
>
> - if (GRAPHICS_VER(i915) >= 12)
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> + cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
> + else if (GRAPHICS_VER(i915) >= 12)
> cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
> else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> cagf = REG_FIELD_GET(RPE_MASK, rpstat);
> @@ -2115,7 +2117,13 @@ static u32 read_cagf(struct intel_rps *rps)
> struct intel_uncore *uncore = rps_to_uncore(rps);
> u32 freq;
>
> - if (GRAPHICS_VER(i915) >= 12) {
> + /*
> + * For Gen12+ reading freq from HW does not need a forcewake and
> + * registers will return 0 freq when GT is in RC6
> + */
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> + freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
> + } else if (GRAPHICS_VER(i915) >= 12) {
> freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
> } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> vlv_punit_get(i915);
> --
> 2.38.0
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
2022-10-19 23:37 ` [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf Ashutosh Dixit
@ 2022-10-21 16:11 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2022-10-21 16:11 UTC (permalink / raw)
To: Ashutosh Dixit; +Cc: Anshuman Gupta, intel-gfx, dri-devel, Badal Nilawar
On Wed, Oct 19, 2022 at 04:37:17PM -0700, Ashutosh Dixit wrote:
> Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
> extract reg fields. This allows future patches touching this code to also
> consistently use REG_FIELD_GET and friends.
>
> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 12 ++++--------
> drivers/gpu/drm/i915/gt/intel_rps.c | 11 +++++------
> 3 files changed, 10 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 40d0a3be42acf..979e602946549 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -307,7 +307,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
> drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
> MEMSTAT_VID_SHIFT);
> drm_printf(p, "Current P-state: %d\n",
> - (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
> + REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat));
> } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> u32 rpmodectl, freq_sts;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 36d95b79022c0..35c039573294c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -794,12 +794,9 @@
> #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010)
> #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014)
> #define GEN6_RPSTAT1 _MMIO(0xa01c)
> -#define GEN6_CAGF_SHIFT 8
> -#define HSW_CAGF_SHIFT 7
> -#define GEN9_CAGF_SHIFT 23
> -#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
> -#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
> -#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
> +#define GEN6_CAGF_MASK REG_GENMASK(14, 8)
> +#define HSW_CAGF_MASK REG_GENMASK(13, 7)
> +#define GEN9_CAGF_MASK REG_GENMASK(31, 23)
> #define GEN6_RP_CONTROL _MMIO(0xa024)
> #define GEN6_RP_MEDIA_TURBO (1 << 11)
> #define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
> @@ -1370,8 +1367,7 @@
> #define MEMSTAT_ILK _MMIO(0x111f8)
> #define MEMSTAT_VID_MASK 0x7f00
> #define MEMSTAT_VID_SHIFT 8
> -#define MEMSTAT_PSTATE_MASK 0x00f8
> -#define MEMSTAT_PSTATE_SHIFT 3
> +#define MEMSTAT_PSTATE_MASK REG_GENMASK(7, 3)
> #define MEMSTAT_MON_ACTV (1 << 2)
> #define MEMSTAT_SRC_CTL_MASK 0x0003
> #define MEMSTAT_SRC_CTL_CORE 0
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index fc23c562d9b2a..5bd6671554a6e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2074,16 +2074,15 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> u32 cagf;
>
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> - cagf = (rpstat >> 8) & 0xff;
> + cagf = REG_FIELD_GET(RPE_MASK, rpstat);
> else if (GRAPHICS_VER(i915) >= 9)
> - cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> + cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> - cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> + cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat);
> else if (GRAPHICS_VER(i915) >= 6)
> - cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
> + cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat);
> else
> - cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
> - MEMSTAT_PSTATE_SHIFT);
> + cagf = gen5_invert_freq(rps, REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rpstat));
>
> return cagf;
> }
> --
> 2.38.0
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq
2022-10-19 23:37 ` [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq Ashutosh Dixit
@ 2022-10-21 16:12 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2022-10-21 16:12 UTC (permalink / raw)
To: Ashutosh Dixit; +Cc: intel-gfx, dri-devel
On Wed, Oct 19, 2022 at 04:37:18PM -0700, Ashutosh Dixit wrote:
> From: Don Hiatt <don.hiatt@intel.com>
>
> On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
> freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
> GT is in RC6.
>
> v2:
> - Fixed review comments(Ashutosh)
> - Added function intel_rps_read_rpstat_fw to read RPSTAT without
> forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko)
> v3:
> - Updated commit title and message for more clarity (Ashutosh)
> - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in
> read_cagf (Ashutosh)
> v4: Remove GEN12_CAGF_SHIFT and use REG_FIELD_GET (Rodrigo)
>
> Cc: Don Hiatt <donhiatt@gmail.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Signed-off-by: Don Hiatt <don.hiatt@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
> drivers/gpu/drm/i915/i915_pmu.c | 3 +--
> 4 files changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 35c039573294c..f8c4f758ac0b1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1539,6 +1539,7 @@
>
> #define GEN12_RPSTAT1 _MMIO(0x1381b4)
> #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
> +#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
>
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> #define GEN11_CSME (31)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 5bd6671554a6e..da6b969f554b6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps)
> rps_disable_interrupts(rps);
> }
>
> +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps)
> +{
> + struct drm_i915_private *i915 = rps_to_i915(rps);
> + i915_reg_t rpstat;
> +
> + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
> +
> + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat);
> +}
> +
> +u32 intel_rps_read_rpstat(struct intel_rps *rps)
> +{
> + struct drm_i915_private *i915 = rps_to_i915(rps);
> + i915_reg_t rpstat;
> +
> + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
> +
> + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
> +}
> +
> u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
> u32 cagf;
>
> - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + if (GRAPHICS_VER(i915) >= 12)
> + cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
> + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> cagf = REG_FIELD_GET(RPE_MASK, rpstat);
> else if (GRAPHICS_VER(i915) >= 9)
> cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
> @@ -2093,7 +2115,9 @@ static u32 read_cagf(struct intel_rps *rps)
> struct intel_uncore *uncore = rps_to_uncore(rps);
> u32 freq;
>
> - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> + if (GRAPHICS_VER(i915) >= 12) {
> + freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
> + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> vlv_punit_get(i915);
> freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> vlv_punit_put(i915);
> @@ -2259,7 +2283,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
>
> - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
> + rpstat = intel_rps_read_rpstat(rps);
> rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
> rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
> rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
> @@ -2394,7 +2418,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
> drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
> drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
> rps->pm_intrmsk_mbz);
> - drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
> + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps));
> drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
> drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
> intel_gpu_freq(rps, caps.min_freq));
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
> index 110300dfd4383..9e1cad9ba0e9c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
> @@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
> u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
> u32 intel_rps_read_punit_req(struct intel_rps *rps);
> u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
> +u32 intel_rps_read_rpstat(struct intel_rps *rps);
> +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
> void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
> void intel_rps_raise_unslice(struct intel_rps *rps);
> void intel_rps_lower_unslice(struct intel_rps *rps);
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 958b37123bf12..67140a87182f8 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -371,7 +371,6 @@ static void
> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> {
> struct drm_i915_private *i915 = gt->i915;
> - struct intel_uncore *uncore = gt->uncore;
> struct i915_pmu *pmu = &i915->pmu;
> struct intel_rps *rps = >->rps;
>
> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> * case we assume the system is running at the intended
> * frequency. Fortunately, the read should rarely fail!
> */
> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
> + val = intel_rps_read_rpstat_fw(rps);
> if (val)
> val = intel_rps_get_cagf(rps, val);
> else
> --
> 2.38.0
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL
2022-10-21 16:02 ` [Intel-gfx] " Dixit, Ashutosh
@ 2022-10-21 16:12 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2022-10-21 16:12 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: intel-gfx, dri-devel
On Fri, Oct 21, 2022 at 09:02:03AM -0700, Dixit, Ashutosh wrote:
> On Wed, 19 Oct 2022 16:37:19 -0700, Ashutosh Dixit wrote:
> >
> > From: Badal Nilawar <badal.nilawar@intel.com>
> >
> > Update CAGF functions for MTL to get actual resolved frequency of 3D and
> > SAMedia.
> >
> > v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
> > Move MTL branches in cagf functions to top (MattR)
> > Fix commit message (Andi)
> > v3: Added comment about registers not needing forcewake for Gen12+ and
> > returning 0 freq in RC6
> > v4: Use REG_FIELD_GET and uncore (Rodrigo)
> >
> > Bspec: 66300
>
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++
> > drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++++++++++--
> > 2 files changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index f8c4f758ac0b1..d8dbd0ac3b064 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -21,6 +21,10 @@
> > */
> > #define PERF_REG(offset) _MMIO(offset)
> >
> > +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
> > +#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
> > +#define MTL_CAGF_MASK REG_GENMASK(8, 0)
> > +
> > /* RPM unit config (Gen8+) */
> > #define RPM_CONFIG0 _MMIO(0xd00)
> > #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index da6b969f554b6..63cc7c538401e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> > struct drm_i915_private *i915 = rps_to_i915(rps);
> > u32 cagf;
> >
> > - if (GRAPHICS_VER(i915) >= 12)
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > + cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
> > + else if (GRAPHICS_VER(i915) >= 12)
> > cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
> > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > cagf = REG_FIELD_GET(RPE_MASK, rpstat);
> > @@ -2115,7 +2117,13 @@ static u32 read_cagf(struct intel_rps *rps)
> > struct intel_uncore *uncore = rps_to_uncore(rps);
> > u32 freq;
> >
> > - if (GRAPHICS_VER(i915) >= 12) {
> > + /*
> > + * For Gen12+ reading freq from HW does not need a forcewake and
> > + * registers will return 0 freq when GT is in RC6
> > + */
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> > + freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
> > + } else if (GRAPHICS_VER(i915) >= 12) {
> > freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
> > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> > vlv_punit_get(i915);
> > --
> > 2.38.0
> >
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/5] drm/i915/gt: Use RC6 residency types as arguments to residency functions
2022-10-19 23:37 ` [PATCH 4/5] drm/i915/gt: Use RC6 residency types as arguments to residency functions Ashutosh Dixit
@ 2022-10-21 16:15 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2022-10-21 16:15 UTC (permalink / raw)
To: Ashutosh Dixit; +Cc: Anshuman Gupta, intel-gfx, dri-devel, Badal Nilawar
On Wed, Oct 19, 2022 at 04:37:20PM -0700, Ashutosh Dixit wrote:
> Previously RC6 residency functions directly accepted RC6 residency register
> MMIO offsets (there are four RC6 residency registers). This worked but
> required an assumption on the residency register layout so was not future
> proof.
>
> Therefore change RC6 residency functions to accept RC6 residency types
> instead of register MMIO offsets. The knowledge of register offsets as well
> as ID to offset mapping is now maintained solely in intel_rc6 and can be
> tailored for different platforms and different register layouts as need
> arises.
>
> v2: Address review comments by Jani N
> - Change residency functions to accept RC6 residency types instead of
> register ID's
> - s/intel_rc6_print_rc5_res/intel_rc6_print_residency/
> - Remove "const enum" in function arguments
> - Naming: intel_rc6_* for enum
> - Use INTEL_RC6_RES_MAX and other minor changes
> v3: Don't include intel_rc6_types.h in intel_rc6.h (Jani)
>
> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
> Reported-by: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++------
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++--
> drivers/gpu/drm/i915/gt/intel_rc6.c | 55 +++++++++++--------
> drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++--
> drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 ++++-
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
> drivers/gpu/drm/i915/i915_pmu.c | 6 +-
> 7 files changed, 72 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 979e602946549..5d6b346831393 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -83,19 +83,6 @@ static int fw_domains_show(struct seq_file *m, void *data)
> }
> DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains);
>
> -static void print_rc6_res(struct seq_file *m,
> - const char *title,
> - const i915_reg_t reg)
> -{
> - struct intel_gt *gt = m->private;
> - intel_wakeref_t wakeref;
> -
> - with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> - seq_printf(m, "%s %u (%llu us)\n", title,
> - intel_uncore_read(gt->uncore, reg),
> - intel_rc6_residency_us(>->rc6, reg));
> -}
> -
> static int vlv_drpc(struct seq_file *m)
> {
> struct intel_gt *gt = m->private;
> @@ -115,8 +102,8 @@ static int vlv_drpc(struct seq_file *m)
> seq_printf(m, "Media Power Well: %s\n",
> (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
>
> - print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6);
> - print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
> + intel_rc6_print_residency(m, "Render RC6 residency since boot:", INTEL_RC6_RES_RC6);
> + intel_rc6_print_residency(m, "Media RC6 residency since boot:", INTEL_RC6_RES_VLV_MEDIA);
>
> return fw_domains_show(m, NULL);
> }
> @@ -192,11 +179,11 @@ static int gen6_drpc(struct seq_file *m)
> }
>
> /* Not exactly sure what this is */
> - print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
> - GEN6_GT_GFX_RC6_LOCKED);
> - print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
> - print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
> - print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
> + intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since boot:",
> + INTEL_RC6_RES_RC6_LOCKED);
> + intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
> + intel_rc6_print_residency(m, "RC6+ residency since boot:", INTEL_RC6_RES_RC6p);
> + intel_rc6_print_residency(m, "RC6++ residency since boot:", INTEL_RC6_RES_RC6pp);
>
> if (GRAPHICS_VER(i915) <= 7) {
> seq_printf(m, "RC6 voltage: %dmV\n",
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index 9041609523697..19a60000e052c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -93,13 +93,13 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
> sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
>
> #ifdef CONFIG_PM
> -static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
> +static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
> {
> intel_wakeref_t wakeref;
> u64 res = 0;
>
> with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> - res = intel_rc6_residency_us(>->rc6, reg);
> + res = intel_rc6_residency_us(>->rc6, id);
>
> return DIV_ROUND_CLOSEST_ULL(res, 1000);
> }
> @@ -123,7 +123,7 @@ static ssize_t rc6_enable_show(struct device *dev,
>
> static u32 __rc6_residency_ms_show(struct intel_gt *gt)
> {
> - return get_residency(gt, GEN6_GT_GFX_RC6);
> + return get_residency(gt, INTEL_RC6_RES_RC6);
> }
>
> static ssize_t rc6_residency_ms_show(struct device *dev,
> @@ -138,7 +138,7 @@ static ssize_t rc6_residency_ms_show(struct device *dev,
>
> static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
> {
> - return get_residency(gt, GEN6_GT_GFX_RC6p);
> + return get_residency(gt, INTEL_RC6_RES_RC6p);
> }
>
> static ssize_t rc6p_residency_ms_show(struct device *dev,
> @@ -153,7 +153,7 @@ static ssize_t rc6p_residency_ms_show(struct device *dev,
>
> static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
> {
> - return get_residency(gt, GEN6_GT_GFX_RC6pp);
> + return get_residency(gt, INTEL_RC6_RES_RC6pp);
> }
>
> static ssize_t rc6pp_residency_ms_show(struct device *dev,
> @@ -168,7 +168,7 @@ static ssize_t rc6pp_residency_ms_show(struct device *dev,
>
> static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
> {
> - return get_residency(gt, VLV_GT_MEDIA_RC6);
> + return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
> }
>
> static ssize_t media_rc6_residency_ms_show(struct device *dev,
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index f8d0523f4c18e..6db4e60d5fba5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -551,6 +551,14 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
> intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> }
>
> +static void rc6_res_reg_init(struct intel_rc6 *rc6)
> +{
> + rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
> + rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
> + rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
> + rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
> +}
> +
> void intel_rc6_init(struct intel_rc6 *rc6)
> {
> struct drm_i915_private *i915 = rc6_to_i915(rc6);
> @@ -562,6 +570,8 @@ void intel_rc6_init(struct intel_rc6 *rc6)
> if (!rc6_supported(rc6))
> return;
>
> + rc6_res_reg_init(rc6);
> +
> if (IS_CHERRYVIEW(i915))
> err = chv_rc6_init(rc6);
> else if (IS_VALLEYVIEW(i915))
> @@ -736,31 +746,19 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
> return lower | (u64)upper << 8;
> }
>
> -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
> +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
> {
> struct drm_i915_private *i915 = rc6_to_i915(rc6);
> struct intel_uncore *uncore = rc6_to_uncore(rc6);
> u64 time_hw, prev_hw, overflow_hw;
> + i915_reg_t reg = rc6->res_reg[id];
> unsigned int fw_domains;
> unsigned long flags;
> - unsigned int i;
> u32 mul, div;
>
> if (!rc6->supported)
> return 0;
>
> - /*
> - * Store previous hw counter values for counter wrap-around handling.
> - *
> - * There are only four interesting registers and they live next to each
> - * other so we can use the relative address, compared to the smallest
> - * one as the index into driver storage.
> - */
> - i = (i915_mmio_reg_offset(reg) -
> - i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
> - if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))
> - return 0;
> -
> fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
>
> spin_lock_irqsave(&uncore->lock, flags);
> @@ -789,11 +787,11 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
> /*
> * Counter wrap handling.
> *
> - * But relying on a sufficient frequency of queries otherwise counters
> - * can still wrap.
> + * Store previous hw counter values for counter wrap-around handling. But
> + * relying on a sufficient frequency of queries otherwise counters can still wrap.
> */
> - prev_hw = rc6->prev_hw_residency[i];
> - rc6->prev_hw_residency[i] = time_hw;
> + prev_hw = rc6->prev_hw_residency[id];
> + rc6->prev_hw_residency[id] = time_hw;
>
> /* RC6 delta from last sample. */
> if (time_hw >= prev_hw)
> @@ -802,8 +800,8 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
> time_hw += overflow_hw - prev_hw;
>
> /* Add delta to RC6 extended raw driver copy. */
> - time_hw += rc6->cur_residency[i];
> - rc6->cur_residency[i] = time_hw;
> + time_hw += rc6->cur_residency[id];
> + rc6->cur_residency[id] = time_hw;
>
> intel_uncore_forcewake_put__locked(uncore, fw_domains);
> spin_unlock_irqrestore(&uncore->lock, flags);
> @@ -811,9 +809,22 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
> return mul_u64_u32_div(time_hw, mul, div);
> }
>
> -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
> +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
> +{
> + return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000);
> +}
> +
> +void intel_rc6_print_residency(struct seq_file *m, const char *title,
> + enum intel_rc6_res_type id)
> {
> - return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
> + struct intel_gt *gt = m->private;
> + i915_reg_t reg = gt->rc6.res_reg[id];
> + intel_wakeref_t wakeref;
> +
> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> + seq_printf(m, "%s %u (%llu us)\n", title,
> + intel_uncore_read(gt->uncore, reg),
> + intel_rc6_residency_us(>->rc6, id));
> }
>
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h
> index b6fea71afc223..456fa668a2769 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h
> @@ -6,10 +6,11 @@
> #ifndef INTEL_RC6_H
> #define INTEL_RC6_H
>
> -#include "i915_reg_defs.h"
> +#include <linux/types.h>
>
> -struct intel_engine_cs;
> +enum intel_rc6_res_type;
> struct intel_rc6;
> +struct seq_file;
>
> void intel_rc6_init(struct intel_rc6 *rc6);
> void intel_rc6_fini(struct intel_rc6 *rc6);
> @@ -21,7 +22,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6);
> void intel_rc6_enable(struct intel_rc6 *rc6);
> void intel_rc6_disable(struct intel_rc6 *rc6);
>
> -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg);
> -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg);
> +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
> +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
> +void intel_rc6_print_residency(struct seq_file *m, const char *title,
> + enum intel_rc6_res_type id);
>
> #endif /* INTEL_RC6_H */
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
> index e747492b2f46e..fa23c4dce00b4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
> @@ -13,9 +13,20 @@
>
> struct drm_i915_gem_object;
>
> +/* RC6 residency types */
> +enum intel_rc6_res_type {
> + INTEL_RC6_RES_RC6_LOCKED,
> + INTEL_RC6_RES_RC6,
> + INTEL_RC6_RES_RC6p,
> + INTEL_RC6_RES_RC6pp,
> + INTEL_RC6_RES_MAX,
> + INTEL_RC6_RES_VLV_MEDIA = INTEL_RC6_RES_RC6p,
> +};
> +
> struct intel_rc6 {
> - u64 prev_hw_residency[4];
> - u64 cur_residency[4];
> + i915_reg_t res_reg[INTEL_RC6_RES_MAX];
> + u64 prev_hw_residency[INTEL_RC6_RES_MAX];
> + u64 cur_residency[INTEL_RC6_RES_MAX];
>
> u32 ctl_enable;
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 8c70b7e120749..2ceeadecc639c 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -19,11 +19,11 @@ static u64 rc6_residency(struct intel_rc6 *rc6)
>
> /* XXX VLV_GT_MEDIA_RC6? */
>
> - result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
> + result = intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6);
> if (HAS_RC6p(rc6_to_i915(rc6)))
> - result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p);
> + result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6p);
> if (HAS_RC6pp(rc6_to_i915(rc6)))
> - result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6pp);
> + result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6pp);
>
> return result;
> }
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 67140a87182f8..52531ab28c5f5 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -148,13 +148,13 @@ static u64 __get_rc6(struct intel_gt *gt)
> struct drm_i915_private *i915 = gt->i915;
> u64 val;
>
> - val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6);
> + val = intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6);
>
> if (HAS_RC6p(i915))
> - val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p);
> + val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6p);
>
> if (HAS_RC6pp(i915))
> - val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6pp);
> + val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6pp);
>
> return val;
> }
> --
> 2.38.0
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia
2022-10-19 23:37 ` [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia Ashutosh Dixit
@ 2022-10-21 16:35 ` Rodrigo Vivi
2022-10-24 19:16 ` Dixit, Ashutosh
0 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Vivi @ 2022-10-21 16:35 UTC (permalink / raw)
To: Ashutosh Dixit; +Cc: Anshuman Gupta, intel-gfx, dri-devel, Badal Nilawar
On Wed, Oct 19, 2022 at 04:37:21PM -0700, Ashutosh Dixit wrote:
> From: Badal Nilawar <badal.nilawar@intel.com>
>
> Add support for C6 residency and C state type for MTL SAMedia. Also add
> mtl_drpc.
I believe this patch deserves a slip between the actual support and
the debugfs, but I'm late to the review, so feel free to ignore this
comment...
but I do have more dummy doubts below:
>
> v2: Fixed review comments (Ashutosh)
> v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
> Remove MTL_CC_SHIFT (Ashutosh)
> Adapt to RC6 residency register code refactor (Jani N)
> v4: Move MTL branch to top in drpc_show
> v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh)
>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
> drivers/gpu/drm/i915/gt/intel_rc6.c | 17 ++++--
> 3 files changed, 75 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 5d6b346831393..f15a7486a9866 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -256,6 +256,60 @@ static int ilk_drpc(struct seq_file *m)
> return 0;
> }
>
> +static int mtl_drpc(struct seq_file *m)
> +{
> + struct intel_gt *gt = m->private;
> + struct intel_uncore *uncore = gt->uncore;
> + u32 gt_core_status, rcctl1, mt_fwake_req;
> + u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
> +
> + mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
> + gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
> +
> + rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> + mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
> + mtl_powergate_status = intel_uncore_read(uncore,
> + GEN9_PWRGT_DOMAIN_STATUS);
> +
> + seq_printf(m, "RC6 Enabled: %s\n",
> + str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> + if (gt->type == GT_MEDIA) {
> + seq_printf(m, "Media Well Gating Enabled: %s\n",
> + str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE));
> + } else {
> + seq_printf(m, "Render Well Gating Enabled: %s\n",
> + str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE));
> + }
> +
> + seq_puts(m, "Current RC state: ");
(Just a "loud" thought here in this chunck, but no actual action requested)
should we really use "R" (Render) for this Media C state?
But well, MC6 seems to be a totally different thing and CC6 is
really strange because the C stands for Core and this can get
very confusing with the SoC or CPU C states... :(
At least with the Render we know which level of the IP we
are looking at when looking at media...
> + switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {
> + case MTL_CC0:
> + seq_puts(m, "on\n");
maybe "*C0" instead of "on"?
> + break;
> + case MTL_CC6:
> + seq_puts(m, "RC6\n");
> + break;
> + default:
> + seq_puts(m, "Unknown\n");
maybe use a MISSING_CASE() here?
or raise a WARN?
> + break;
> + }
> +
> + seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
> + if (gt->type == GT_MEDIA)
> + seq_printf(m, "Media Power Well: %s\n",
> + (mtl_powergate_status &
> + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
gate is up and power is down or gate is down and power is up?
> + else
> + seq_printf(m, "Render Power Well: %s\n",
> + (mtl_powergate_status &
> + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> +
> + /* Works for both render and media gt's */
> + intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
> +
> + return fw_domains_show(m, NULL);
> +}
> +
> static int drpc_show(struct seq_file *m, void *unused)
> {
> struct intel_gt *gt = m->private;
> @@ -264,7 +318,9 @@ static int drpc_show(struct seq_file *m, void *unused)
> int err = -ENODEV;
>
> with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> + err = mtl_drpc(m);
> + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> err = vlv_drpc(m);
> else if (GRAPHICS_VER(i915) >= 6)
> err = gen6_drpc(m);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index d8dbd0ac3b064..a0ddaf243593c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -24,6 +24,9 @@
> /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
> #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
> #define MTL_CAGF_MASK REG_GENMASK(8, 0)
> +#define MTL_CC0 0x0
> +#define MTL_CC6 0x3
> +#define MTL_CC_MASK REG_GENMASK(12, 9)
>
> /* RPM unit config (Gen8+) */
> #define RPM_CONFIG0 _MMIO(0xd00)
> @@ -1512,6 +1515,8 @@
> #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
> #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
>
> +#define MTL_MEDIA_MC6 _MMIO(0x138048)
> +
> #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
> #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 6db4e60d5fba5..2ee4051e4d961 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -553,10 +553,19 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
>
> static void rc6_res_reg_init(struct intel_rc6 *rc6)
> {
> - rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
> - rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
> - rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
> - rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
> + memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
> +
> + switch (rc6_to_gt(rc6)->type) {
> + case GT_MEDIA:
> + rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
> + break;
> + default:
> + rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
> + rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
> + rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
> + rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
> + break;
> + }
> }
>
> void intel_rc6_init(struct intel_rc6 *rc6)
> --
> 2.38.0
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia
2022-10-21 16:35 ` Rodrigo Vivi
@ 2022-10-24 19:16 ` Dixit, Ashutosh
2022-10-24 19:49 ` Rodrigo Vivi
0 siblings, 1 reply; 17+ messages in thread
From: Dixit, Ashutosh @ 2022-10-24 19:16 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Anshuman Gupta, intel-gfx, dri-devel, Badal Nilawar
On Fri, 21 Oct 2022 09:35:32 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Wed, Oct 19, 2022 at 04:37:21PM -0700, Ashutosh Dixit wrote:
> > From: Badal Nilawar <badal.nilawar@intel.com>
> >
> > Add support for C6 residency and C state type for MTL SAMedia. Also add
> > mtl_drpc.
>
> I believe this patch deserves a slip between the actual support and
> the debugfs, but I'm late to the review, so feel free to ignore this
> comment...
Sorry didn't understand what you mean by "slip", you mean the patch should
be split in two?
> but I do have more dummy doubts below:
>
> >
> > v2: Fixed review comments (Ashutosh)
> > v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
> > Remove MTL_CC_SHIFT (Ashutosh)
> > Adapt to RC6 residency register code refactor (Jani N)
> > v4: Move MTL branch to top in drpc_show
> > v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh)
> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++++++++++++++++++-
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
> > drivers/gpu/drm/i915/gt/intel_rc6.c | 17 ++++--
> > 3 files changed, 75 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > index 5d6b346831393..f15a7486a9866 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > @@ -256,6 +256,60 @@ static int ilk_drpc(struct seq_file *m)
> > return 0;
> > }
> >
> > +static int mtl_drpc(struct seq_file *m)
> > +{
> > + struct intel_gt *gt = m->private;
> > + struct intel_uncore *uncore = gt->uncore;
> > + u32 gt_core_status, rcctl1, mt_fwake_req;
> > + u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
> > +
> > + mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
> > + gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
> > +
> > + rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> > + mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
> > + mtl_powergate_status = intel_uncore_read(uncore,
> > + GEN9_PWRGT_DOMAIN_STATUS);
> > +
> > + seq_printf(m, "RC6 Enabled: %s\n",
> > + str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> > + if (gt->type == GT_MEDIA) {
> > + seq_printf(m, "Media Well Gating Enabled: %s\n",
> > + str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE));
> > + } else {
> > + seq_printf(m, "Render Well Gating Enabled: %s\n",
> > + str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE));
> > + }
> > +
> > + seq_puts(m, "Current RC state: ");
>
> (Just a "loud" thought here in this chunck, but no actual action requested)
>
> should we really use "R" (Render) for this Media C state?
This function is called for both render and media gt's. But let's think
about this. We can call easily call them e.g. RC6 for render and MC6 for
media too if that is more accurate and descriptive. On the other hand, do
we really need to introduce a new term like MC6? Maybe we just stick to
RC/RC6 terminology for anything on the GPU?
> But well, MC6 seems to be a totally different thing and CC6
MC6 is not the same as RC6 for the media tile?
> and CC6 is really strange because the C stands for Core and this can get
> very confusing with the SoC or CPU C states... :(
Yes Bspec 66300 refers to these as core C states but refers to GT and
IA. So it's confusing.
> At least with the Render we know which level of the IP we
> are looking at when looking at media...
Yup that's why I've left this as RC/RC6 in Patch v6.
>
> > + switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {
> > + case MTL_CC0:
> > + seq_puts(m, "on\n");
>
> maybe "*C0" instead of "on"?
Done in v6. Though this string is "on" also in the previous function
gen6_drpc. Also, if we are calling this C0 we could call the C6 state as
just C6 (which would mean RC6 for render and MC6 for media). But I thought
RC6 is better for both render and media.
>
> > + break;
> > + case MTL_CC6:
> > + seq_puts(m, "RC6\n");
> > + break;
> > + default:
> > + seq_puts(m, "Unknown\n");
>
> maybe use a MISSING_CASE() here?
> or raise a WARN?
Done in v6.
>
> > + break;
> > + }
> > +
> > + seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
> > + if (gt->type == GT_MEDIA)
> > + seq_printf(m, "Media Power Well: %s\n",
> > + (mtl_powergate_status &
> > + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
>
> gate is up and power is down or gate is down and power is up?
Yes name is confusing but is the same as Bspec and also gen6_drpc. So the
prints "Media Power Well: Up" or "Media Power Well: Down" are correct (0 is
down, 1 is up). Similarly for Render below.
Thanks.
--
Ashutosh
>
> > + else
> > + seq_printf(m, "Render Power Well: %s\n",
> > + (mtl_powergate_status &
> > + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> > +
> > + /* Works for both render and media gt's */
> > + intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
> > +
> > + return fw_domains_show(m, NULL);
> > +}
> > +
> > static int drpc_show(struct seq_file *m, void *unused)
> > {
> > struct intel_gt *gt = m->private;
> > @@ -264,7 +318,9 @@ static int drpc_show(struct seq_file *m, void *unused)
> > int err = -ENODEV;
> >
> > with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > + err = mtl_drpc(m);
> > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > err = vlv_drpc(m);
> > else if (GRAPHICS_VER(i915) >= 6)
> > err = gen6_drpc(m);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index d8dbd0ac3b064..a0ddaf243593c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -24,6 +24,9 @@
> > /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
> > #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
> > #define MTL_CAGF_MASK REG_GENMASK(8, 0)
> > +#define MTL_CC0 0x0
> > +#define MTL_CC6 0x3
> > +#define MTL_CC_MASK REG_GENMASK(12, 9)
> >
> > /* RPM unit config (Gen8+) */
> > #define RPM_CONFIG0 _MMIO(0xd00)
> > @@ -1512,6 +1515,8 @@
> > #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
> > #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
> >
> > +#define MTL_MEDIA_MC6 _MMIO(0x138048)
> > +
> > #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
> > #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > index 6db4e60d5fba5..2ee4051e4d961 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > @@ -553,10 +553,19 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
> >
> > static void rc6_res_reg_init(struct intel_rc6 *rc6)
> > {
> > - rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
> > - rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
> > - rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
> > - rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
> > + memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
> > +
> > + switch (rc6_to_gt(rc6)->type) {
> > + case GT_MEDIA:
> > + rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
> > + break;
> > + default:
> > + rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
> > + rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
> > + rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
> > + rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
> > + break;
> > + }
> > }
> >
> > void intel_rc6_init(struct intel_rc6 *rc6)
> > --
> > 2.38.0
> >
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia
2022-10-24 19:16 ` Dixit, Ashutosh
@ 2022-10-24 19:49 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2022-10-24 19:49 UTC (permalink / raw)
To: Dixit, Ashutosh; +Cc: Anshuman Gupta, intel-gfx, dri-devel, Badal Nilawar
On Mon, Oct 24, 2022 at 12:16:28PM -0700, Dixit, Ashutosh wrote:
> On Fri, 21 Oct 2022 09:35:32 -0700, Rodrigo Vivi wrote:
> >
>
> Hi Rodrigo,
>
> > On Wed, Oct 19, 2022 at 04:37:21PM -0700, Ashutosh Dixit wrote:
> > > From: Badal Nilawar <badal.nilawar@intel.com>
> > >
> > > Add support for C6 residency and C state type for MTL SAMedia. Also add
> > > mtl_drpc.
> >
> > I believe this patch deserves a slip between the actual support and
> > the debugfs, but I'm late to the review, so feel free to ignore this
> > comment...
>
> Sorry didn't understand what you mean by "slip", you mean the patch should
> be split in two?
yeap, I meant split.. sorry for the typo...
>
> > but I do have more dummy doubts below:
> >
> > >
> > > v2: Fixed review comments (Ashutosh)
> > > v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
> > > Remove MTL_CC_SHIFT (Ashutosh)
> > > Adapt to RC6 residency register code refactor (Jani N)
> > > v4: Move MTL branch to top in drpc_show
> > > v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh)
> > >
> > > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++++++++++++++++++-
> > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
> > > drivers/gpu/drm/i915/gt/intel_rc6.c | 17 ++++--
> > > 3 files changed, 75 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > > index 5d6b346831393..f15a7486a9866 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > > @@ -256,6 +256,60 @@ static int ilk_drpc(struct seq_file *m)
> > > return 0;
> > > }
> > >
> > > +static int mtl_drpc(struct seq_file *m)
> > > +{
> > > + struct intel_gt *gt = m->private;
> > > + struct intel_uncore *uncore = gt->uncore;
> > > + u32 gt_core_status, rcctl1, mt_fwake_req;
> > > + u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
> > > +
> > > + mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
> > > + gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
> > > +
> > > + rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> > > + mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
> > > + mtl_powergate_status = intel_uncore_read(uncore,
> > > + GEN9_PWRGT_DOMAIN_STATUS);
> > > +
> > > + seq_printf(m, "RC6 Enabled: %s\n",
> > > + str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> > > + if (gt->type == GT_MEDIA) {
> > > + seq_printf(m, "Media Well Gating Enabled: %s\n",
> > > + str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE));
> > > + } else {
> > > + seq_printf(m, "Render Well Gating Enabled: %s\n",
> > > + str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE));
> > > + }
> > > +
> > > + seq_puts(m, "Current RC state: ");
> >
> > (Just a "loud" thought here in this chunck, but no actual action requested)
> >
> > should we really use "R" (Render) for this Media C state?
>
> This function is called for both render and media gt's. But let's think
> about this. We can call easily call them e.g. RC6 for render and MC6 for
> media too if that is more accurate and descriptive. On the other hand, do
> we really need to introduce a new term like MC6? Maybe we just stick to
> RC/RC6 terminology for anything on the GPU?
>
> > But well, MC6 seems to be a totally different thing and CC6
>
> MC6 is not the same as RC6 for the media tile?
I saw people using this in some bug, but I thought this was for the package
since they were refering to the rc6 as well...
so you can see how confusing this bad naming is by itself... not a single
document or bspec page that put a good name we can use... so let's not
invent it here and move with the RC6.
>
> > and CC6 is really strange because the C stands for Core and this can get
> > very confusing with the SoC or CPU C states... :(
>
> Yes Bspec 66300 refers to these as core C states but refers to GT and
> IA. So it's confusing.
>
> > At least with the Render we know which level of the IP we
> > are looking at when looking at media...
>
> Yup that's why I've left this as RC/RC6 in Patch v6.
ack
>
> >
> > > + switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {
> > > + case MTL_CC0:
> > > + seq_puts(m, "on\n");
> >
> > maybe "*C0" instead of "on"?
>
> Done in v6. Though this string is "on" also in the previous function
> gen6_drpc. Also, if we are calling this C0 we could call the C6 state as
> just C6 (which would mean RC6 for render and MC6 for media). But I thought
> RC6 is better for both render and media.
oh, now that we agreed on staying with the RC I believe RC0 is better.
>
> >
> > > + break;
> > > + case MTL_CC6:
> > > + seq_puts(m, "RC6\n");
> > > + break;
> > > + default:
> > > + seq_puts(m, "Unknown\n");
> >
> > maybe use a MISSING_CASE() here?
> > or raise a WARN?
>
> Done in v6.
>
> >
> > > + break;
> > > + }
> > > +
> > > + seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
> > > + if (gt->type == GT_MEDIA)
> > > + seq_printf(m, "Media Power Well: %s\n",
> > > + (mtl_powergate_status &
> > > + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
> >
> > gate is up and power is down or gate is down and power is up?
>
> Yes name is confusing but is the same as Bspec and also gen6_drpc. So the
> prints "Media Power Well: Up" or "Media Power Well: Down" are correct (0 is
> down, 1 is up). Similarly for Render below.
:( oh, indeed!
Let's stay with it.
>
> Thanks.
> --
> Ashutosh
>
> >
> > > + else
> > > + seq_printf(m, "Render Power Well: %s\n",
> > > + (mtl_powergate_status &
> > > + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> > > +
> > > + /* Works for both render and media gt's */
> > > + intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
> > > +
> > > + return fw_domains_show(m, NULL);
> > > +}
> > > +
> > > static int drpc_show(struct seq_file *m, void *unused)
> > > {
> > > struct intel_gt *gt = m->private;
> > > @@ -264,7 +318,9 @@ static int drpc_show(struct seq_file *m, void *unused)
> > > int err = -ENODEV;
> > >
> > > with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
> > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > > + err = mtl_drpc(m);
> > > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > > err = vlv_drpc(m);
> > > else if (GRAPHICS_VER(i915) >= 6)
> > > err = gen6_drpc(m);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > index d8dbd0ac3b064..a0ddaf243593c 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > > @@ -24,6 +24,9 @@
> > > /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
> > > #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
> > > #define MTL_CAGF_MASK REG_GENMASK(8, 0)
> > > +#define MTL_CC0 0x0
> > > +#define MTL_CC6 0x3
> > > +#define MTL_CC_MASK REG_GENMASK(12, 9)
> > >
> > > /* RPM unit config (Gen8+) */
> > > #define RPM_CONFIG0 _MMIO(0xd00)
> > > @@ -1512,6 +1515,8 @@
> > > #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
> > > #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
> > >
> > > +#define MTL_MEDIA_MC6 _MMIO(0x138048)
> > > +
> > > #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
> > > #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > > index 6db4e60d5fba5..2ee4051e4d961 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > > @@ -553,10 +553,19 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
> > >
> > > static void rc6_res_reg_init(struct intel_rc6 *rc6)
> > > {
> > > - rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
> > > - rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
> > > - rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
> > > - rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
> > > + memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
> > > +
> > > + switch (rc6_to_gt(rc6)->type) {
> > > + case GT_MEDIA:
> > > + rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
> > > + break;
> > > + default:
> > > + rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
> > > + rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
> > > + rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
> > > + rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
> > > + break;
> > > + }
> > > }
> > >
> > > void intel_rc6_init(struct intel_rc6 *rc6)
> > > --
> > > 2.38.0
> > >
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/5] i915: CAGF and RC6 changes for MTL
@ 2022-11-14 12:33 Badal Nilawar
0 siblings, 0 replies; 17+ messages in thread
From: Badal Nilawar @ 2022-11-14 12:33 UTC (permalink / raw)
To: intel-gfx; +Cc: ashutosh.dixit, dri-devel, rodrigo.vivi
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6 residency functions to accept register
ID's" based on code review feedback
v6:
- Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
functions to accept register ID's"
- Re-add "drm/i915: Use GEN12_RPSTAT register for GT freq" to this series
v7: Rebuild, identical to v6
v8:
- Add "drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf" to the series
(based on Rodrigo's review) to consistently use REG_FIELD_GET
- Minor changes to other patches, please see individual patches for changelogs
v9: Rebuild, identical to v8
v10: Address review comments from Rodrigo on Patch 5
v11: Change state name for MTL_CC0 to RC0 in Patch 5
v12: Rebased to latest upstream. Identical to v11.
Ashutosh Dixit (2):
drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
drm/i915/gt: Use RC6 residency types as arguments to residency
functions
Badal Nilawar (2):
drm/i915/mtl: Modify CAGF functions for MTL
drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Don Hiatt (1):
drm/i915: Use GEN12_RPSTAT register for GT freq
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 88 ++++++++++++++-----
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 22 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 +--
drivers/gpu/drm/i915/gt/intel_rc6.c | 64 +++++++++-----
drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++-
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 51 ++++++++---
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 9 +-
10 files changed, 198 insertions(+), 82 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/5] i915: CAGF and RC6 changes for MTL
@ 2022-10-24 20:24 Ashutosh Dixit
0 siblings, 0 replies; 17+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Badal Nilawar, dri-devel, Rodrigo Vivi
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6 residency functions to accept register
ID's" based on code review feedback
v6:
- Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
functions to accept register ID's"
- Re-add "drm/i915: Use GEN12_RPSTAT register for GT freq" to this series
v7: Rebuild, identical to v6
v8:
- Add "drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf" to the series
(based on Rodrigo's review) to consistently use REG_FIELD_GET
- Minor changes to other patches, please see individual patches for changelogs
v9: Rebuild, identical to v8
v10: Address review comments from Rodrigo on Patch 5
v11: Change state name for MTL_CC0 to RC0 in Patch 5
Ashutosh Dixit (2):
drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
drm/i915/gt: Use RC6 residency types as arguments to residency
functions
Badal Nilawar (2):
drm/i915/mtl: Modify CAGF functions for MTL
drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Don Hiatt (1):
drm/i915: Use GEN12_RPSTAT register for GT freq
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 88 ++++++++++++++-----
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 22 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 +--
drivers/gpu/drm/i915/gt/intel_rc6.c | 64 +++++++++-----
drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++-
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 51 ++++++++---
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 9 +-
10 files changed, 198 insertions(+), 82 deletions(-)
--
2.38.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/5] i915: CAGF and RC6 changes for MTL
@ 2022-10-24 19:13 Ashutosh Dixit
0 siblings, 0 replies; 17+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 19:13 UTC (permalink / raw)
To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6 residency functions to accept register
ID's" based on code review feedback
v6:
- Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
functions to accept register ID's"
- Re-add "drm/i915: Use GEN12_RPSTAT register for GT freq" to this series
v7: Rebuild, identical to v6
v8:
- Add "drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf" to the series
(based on Rodrigo's review) to consistently use REG_FIELD_GET
- Minor changes to other patches, please see individual patches for changelogs
v9: Rebuild, identical to v8
v10: Address review comments from Rodrigo on Patch 5
Ashutosh Dixit (2):
drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
drm/i915/gt: Use RC6 residency types as arguments to residency
functions
Badal Nilawar (2):
drm/i915/mtl: Modify CAGF functions for MTL
drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Don Hiatt (1):
drm/i915: Use GEN12_RPSTAT register for GT freq
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 88 ++++++++++++++-----
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 22 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 +--
drivers/gpu/drm/i915/gt/intel_rc6.c | 64 +++++++++-----
drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++-
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 51 ++++++++---
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 9 +-
10 files changed, 198 insertions(+), 82 deletions(-)
--
2.38.0
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-11-14 12:30 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-19 23:37 [PATCH 0/5] i915: CAGF and RC6 changes for MTL Ashutosh Dixit
2022-10-19 23:37 ` [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf Ashutosh Dixit
2022-10-21 16:11 ` Rodrigo Vivi
2022-10-19 23:37 ` [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq Ashutosh Dixit
2022-10-21 16:12 ` [Intel-gfx] " Rodrigo Vivi
2022-10-19 23:37 ` [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL Ashutosh Dixit
2022-10-21 16:02 ` [Intel-gfx] " Dixit, Ashutosh
2022-10-21 16:12 ` Rodrigo Vivi
2022-10-19 23:37 ` [PATCH 4/5] drm/i915/gt: Use RC6 residency types as arguments to residency functions Ashutosh Dixit
2022-10-21 16:15 ` Rodrigo Vivi
2022-10-19 23:37 ` [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia Ashutosh Dixit
2022-10-21 16:35 ` Rodrigo Vivi
2022-10-24 19:16 ` Dixit, Ashutosh
2022-10-24 19:49 ` Rodrigo Vivi
2022-10-24 19:13 [PATCH 0/5] i915: CAGF and RC6 changes for MTL Ashutosh Dixit
2022-10-24 20:24 Ashutosh Dixit
2022-11-14 12:33 Badal Nilawar
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