* [PATCH v1 0/9] Enable Display for SM8350
@ 2022-10-28 12:08 Robert Foss
2022-10-28 12:08 ` [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display Robert Foss
` (8 more replies)
0 siblings, 9 replies; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
This series implements display support for SM8350 and
enables HDMI output for the SM8350-HDK platform.
Robert Foss (9):
drm/msm: Add compatibles for SM8350 display
drm/msm/dpu: Refactor sc7280_pp location
drm/msm/dpu: Add SM8350 to hw catalog
arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
arm64: dts: qcom: sm8350: Use 2 interconnect cells
arm64: dts: qcom: sm8350: Add display system nodes
arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 333 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 217 +++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 227 +++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_mdss.c | 1 +
6 files changed, 760 insertions(+), 20 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
@ 2022-10-28 12:08 ` Robert Foss
2022-10-28 12:13 ` Dmitry Baryshkov
2022-10-28 12:19 ` Dmitry Baryshkov
2022-10-28 12:08 ` [PATCH v1 2/9] drm/msm/dpu: Refactor sc7280_pp location Robert Foss
` (7 subsequent siblings)
8 siblings, 2 replies; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
Add compatible string for "qcom,sm8350-dpu" and
"qcom,sm8350-mdss".
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_mdss.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 008e1420e6e5..70683dbc6b32 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1315,6 +1315,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
+ { .compatible = "qcom,sm8350-dpu", },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e13c5c12b775..fd5a95cace16 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -447,6 +447,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8350-mdss" },
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v1 2/9] drm/msm/dpu: Refactor sc7280_pp location
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
2022-10-28 12:08 ` [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display Robert Foss
@ 2022-10-28 12:08 ` Robert Foss
2022-10-28 12:14 ` Dmitry Baryshkov
2022-10-28 12:08 ` [PATCH v1 3/9] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
` (6 subsequent siblings)
8 siblings, 1 reply; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
The sc7280_pp declaration is not located by the other _pp
declarations, but rather hidden around the _merge_3d
declarations. Let's fix this to avoid confusion.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 0239a811d5ec..d0ce7612fee8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1175,6 +1175,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
};
+static const struct dpu_pingpong_cfg sc7280_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
+};
+
static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1198,13 +1205,6 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
};
-static const struct dpu_pingpong_cfg sc7280_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
-};
-
/*************************************************************
* DSC sub blocks config
*************************************************************/
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v1 3/9] drm/msm/dpu: Add SM8350 to hw catalog
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
2022-10-28 12:08 ` [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display Robert Foss
2022-10-28 12:08 ` [PATCH v1 2/9] drm/msm/dpu: Refactor sc7280_pp location Robert Foss
@ 2022-10-28 12:08 ` Robert Foss
2022-10-28 12:26 ` Dmitry Baryshkov
2022-10-28 12:08 ` [PATCH v1 4/9] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names Robert Foss
` (5 subsequent siblings)
8 siblings, 1 reply; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 217 ++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
2 files changed, 218 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d0ce7612fee8..bc829d7bdd6e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_7xxx_INTR) | \
+ BIT(MDP_INTF1_7xxx_INTR) | \
+ BIT(MDP_INTF2_7xxx_INTR) | \
+ BIT(MDP_INTF3_7xxx_INTR) | \
+ 0)
+
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -364,6 +373,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sc7280_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
@@ -501,6 +524,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2B4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2BC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2C4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2B4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2BC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2C4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2BC, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sc7280_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -659,6 +709,66 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) |
+ BIT(DPU_CTL_PINGPONG_SPLIT) |
+ BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) |
+ BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sc7280_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1182,6 +1292,27 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
};
+static const struct dpu_pingpong_cfg sm8350_pp[] = {
+ PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+ PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+ PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ -1),
+ PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ -1),
+};
+
static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1205,6 +1336,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
};
+static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
+ MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
+ MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
+ MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
+};
+
/*************************************************************
* DSC sub blocks config
*************************************************************/
@@ -1222,6 +1359,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = {
DSC_BLK("dsc_3", DSC_3, 0x80c00),
};
+static struct dpu_dsc_cfg sm8350_dsc[] = {
+ DSC_BLK("dsc_0", DSC_0, 0x80000),
+ DSC_BLK("dsc_1", DSC_1, 0x81000),
+ DSC_BLK("dsc_2", DSC_2, 0x82000),
+};
+
/*************************************************************
* INTF sub blocks config
*************************************************************/
@@ -1269,6 +1412,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
};
+static const struct dpu_intf_cfg sm8350_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+};
+
static const struct dpu_intf_cfg sc8180x_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
@@ -1397,6 +1547,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
};
+static const struct dpu_reg_dma_cfg sm8350_regdma = {
+ .base = 0x0,
+ .version = 0x00020000,
+ .trigger_sel_off = 0x119c,
+ .xin_id = 7,
+ .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
+};
+
/*************************************************************
* PERF data config
*************************************************************/
@@ -1700,6 +1858,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
.bw_inefficiency_factor = 120,
};
+static const struct dpu_perf_cfg sm8350_perf_data = {
+ .max_bw_low = 11800000,
+ .max_bw_high = 18200000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 800000,
+ .min_prefill_lines = 40,
+ /* FIXME: lut tables */
+ .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
+ .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
static const struct dpu_perf_cfg qcm2290_perf_data = {
.max_bw_low = 2700000,
.max_bw_high = 2700000,
@@ -1876,6 +2064,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
.mdss_irqs = IRQ_SM8250_MASK,
};
+static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
+ .caps = &sm8350_dpu_caps,
+ .mdp_count = ARRAY_SIZE(sm8350_mdp),
+ .mdp = sm8350_mdp,
+ .ctl_count = ARRAY_SIZE(sm8350_ctl),
+ .ctl = sm8350_ctl,
+ .sspp_count = ARRAY_SIZE(sm8250_sspp),
+ .sspp = sm8250_sspp,
+ .mixer_count = ARRAY_SIZE(sm8150_lm),
+ .mixer = sm8150_lm,
+ .dspp_count = ARRAY_SIZE(sm8150_dspp),
+ .dspp = sm8150_dspp,
+ .pingpong_count = ARRAY_SIZE(sm8350_pp),
+ .pingpong = sm8350_pp,
+ .dsc_count = ARRAY_SIZE(sm8350_dsc),
+ .dsc = sm8350_dsc,
+ .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
+ .merge_3d = sm8350_merge_3d,
+ .intf_count = ARRAY_SIZE(sm8350_intf),
+ .intf = sm8350_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .reg_dma_count = 1,
+ .dma_cfg = &sm8250_regdma,
+ .perf = &sm8350_perf_data,
+ .mdss_irqs = IRQ_SM8350_MASK,
+};
+
static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
.caps = &sc7280_dpu_caps,
.mdp_count = ARRAY_SIZE(sc7280_mdp),
@@ -1933,6 +2149,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
+ { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 71fe4c505f5b..e59630e06110 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -45,6 +45,7 @@
#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
+#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v1 4/9] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
` (2 preceding siblings ...)
2022-10-28 12:08 ` [PATCH v1 3/9] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
@ 2022-10-28 12:08 ` Robert Foss
2022-10-28 12:08 ` [PATCH v1 5/9] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name Robert Foss
` (4 subsequent siblings)
8 siblings, 0 replies; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
Add GPIO line names as described by the sm8350-hdk schematic.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205 ++++++++++++++++++++++++
1 file changed, 205 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0fcf5bd88fc7..e6deb08c6da0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -233,6 +233,211 @@ &slpi {
&tlmm {
gpio-reserved-ranges = <52 8>;
+
+ gpio-line-names =
+ "APPS_I2C_SDA", /* GPIO_0 */
+ "APPS_I2C_SCL",
+ "FSA_INT_N",
+ "USER_LED3_EN",
+ "SMBUS_SDA_1P8",
+ "SMBUS_SCL_1P8",
+ "2M2_3P3_EN",
+ "ALERT_DUAL_M2_N",
+ "EXP_UART_CTS",
+ "EXP_UART_RFR",
+ "EXP_UART_TX", /* GPIO_10 */
+ "EXP_UART_RX",
+ "NC",
+ "NC",
+ "RCM_MARKER1",
+ "WSA0_EN",
+ "CAM1_RESET_N",
+ "CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "TS_I2C_SDA", /* GPIO_20 */
+ "TS_I2C_SCL",
+ "TS_RESET_N",
+ "TS_INT_N",
+ "DISP0_RESET_N",
+ "DISP1_RESET_N",
+ "ETH_RESET",
+ "RCM_MARKER2",
+ "CAM_DC_MIPI_MUX_EN",
+ "CAM_DC_MIPI_MUX_SEL",
+ "AFC_PHY_TA_D_PLUS", /* GPIO_30 */
+ "AFC_PHY_TA_D_MINUS",
+ "PM8008_1_IRQ",
+ "PM8008_1_RESET_N",
+ "PM8008_2_IRQ",
+ "PM8008_2_RESET_N",
+ "CAM_DC_I3C_SDA",
+ "CAM_DC_I3C_SCL",
+ "FP_INT_N",
+ "FP_WUHB_INT_N",
+ "SMB_SPMI_DATA", /* GPIO_40 */
+ "SMB_SPMI_CLK",
+ "USB_HUB_RESET",
+ "FORCE_USB_BOOT",
+ "LRF_IRQ",
+ "NC",
+ "IMU2_INT",
+ "HDMI_3P3_EN",
+ "HDMI_RSTN",
+ "HDMI_1P2_EN",
+ "HDMI_INT", /* GPIO_50 */
+ "USB1_ID",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "NFC_I2C_SDA", /* GPIO_60 */
+ "NFC_I2C_SCLC",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "HST_WLAN_EN",
+ "HST_BT_EN",
+ "HST_SW_CTRL",
+ "NC",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX", /* GPIO_70 */
+ "HST_BT_UART_RX",
+ "CAM_DC_SPI0_MISO",
+ "CAM_DC_SPI0_MOSI",
+ "CAM_DC_SPI0_CLK",
+ "CAM_DC_SPI0_CS_N",
+ "CAM_DC_SPI1_MISO",
+ "CAM_DC_SPI1_MOSI",
+ "CAM_DC_SPI1_CLK",
+ "CAM_DC_SPI1_CS_N",
+ "HALL_INT_N", /* GPIO_80 */
+ "USB_PHY_PS",
+ "MDP_VSYNC_P",
+ "MDP_VSYNC_S",
+ "ETH_3P3_EN",
+ "RADAR_INT",
+ "NFC_DWL_REQ",
+ "SM_GPIO_87",
+ "WCD_RESET_N",
+ "ALSP_INT_N",
+ "PRESS_INT", /* GPIO_90 */
+ "SAR_INT_N",
+ "SD_CARD_DET_N",
+ "NC",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "PCIE1_RESET_N",
+ "PCIE1_CLK_REQ_N",
+ "PCIE1_WAKE_N",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2",
+ "CAM_MCLK3",
+ "CAM_MCLK4",
+ "CAM_MCLK5",
+ "CAM2_RESET_N",
+ "CCI_I2C0_SDA",
+ "CCI_I2C0_SCL",
+ "CCI_I2C1_SDA",
+ "CCI_I2C1_SCL", /* GPIO_110 */
+ "CCI_I2C2_SDA",
+ "CCI_I2C2_SCL",
+ "CCI_I2C3_SDA",
+ "CCI_I2C3_SCL",
+ "CAM5_RESET_N",
+ "CAM4_RESET_N",
+ "CAM3_RESET_N",
+ "IMU1_INT",
+ "MAG_INT_N",
+ "MI2S2_I2S_SCK", /* GPIO_120 */
+ "MI2S2_I2S_DAT0",
+ "MI2S2_I2S_WS",
+ "HIFI_DAC_I2S_MCLK",
+ "MI2S2_I2S_DAT1",
+ "HIFI_DAC_I2S_SCK",
+ "HIFI_DAC_I2S_DAT0",
+ "NC",
+ "HIFI_DAC_I2S_WS",
+ "HST_BT_WLAN_SLIMBUS_CLK",
+ "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */
+ "BT_LED_EN",
+ "WLAN_LED_EN",
+ "NC",
+ "NC",
+ "NC",
+ "UIM2_PRESENT",
+ "NC",
+ "NC",
+ "NC",
+ "UIM1_PRESENT", /* GPIO_140 */
+ "NC",
+ "SM_RFFE0_DATA",
+ "NC",
+ "SM_RFFE1_DATA",
+ "SM_MSS_GRFC4",
+ "SM_MSS_GRFC5",
+ "SM_MSS_GRFC6",
+ "SM_MSS_GRFC7",
+ "SM_RFFE4_CLK",
+ "SM_RFFE4_DATA", /* GPIO_150 */
+ "WLAN_COEX_UART1_RX",
+ "WLAN_COEX_UART1_TX",
+ "HST_SW_CTRL",
+ "DSI0_STATUS",
+ "DSI1_STATUS",
+ "APPS_PBL_BOOT_SPEED_1",
+ "APPS_BOOT_FROM_ROM",
+ "APPS_PBL_BOOT_SPEED_0",
+ "QLINK0_REQ",
+ "QLINK0_EN", /* GPIO_160 */
+ "QLINK0_WMSS_RESET_N",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "WCD_SWR_TX_CLK",
+ "WCD_SWR_TX_DATA0",
+ "WCD_SWR_TX_DATA1", /* GPIO_170 */
+ "WCD_SWR_RX_CLK",
+ "WCD_SWR_RX_DATA0",
+ "WCD_SWR_RX_DATA1",
+ "DMIC01_CLK",
+ "DMIC01_DATA",
+ "DMIC23_CLK",
+ "DMIC23_DATA",
+ "WSA_SWR_CLK",
+ "WSA_SWR_DATA",
+ "DMIC45_CLK", /* GPIO_180 */
+ "DMIC45_DATA",
+ "WCD_SWR_TX_DATA2",
+ "SENSOR_I3C_SDA",
+ "SENSOR_I3C_SCL",
+ "CAM_OIS0_I3C_SDA",
+ "CAM_OIS0_I3C_SCL",
+ "IMU_SPI_MISO",
+ "IMU_SPI_MOSI",
+ "IMU_SPI_CLK",
+ "IMU_SPI_CS_N", /* GPIO_190 */
+ "MAG_I2C_SDA",
+ "MAG_I2C_SCL",
+ "SENSOR_I2C_SDA",
+ "SENSOR_I2C_SCL",
+ "RADAR_SPI_MISO",
+ "RADAR_SPI_MOSI",
+ "RADAR_SPI_CLK",
+ "RADAR_SPI_CS_N",
+ "HST_BLE_UART_TX",
+ "HST_BLE_UART_RX", /* GPIO_200 */
+ "HST_WLAN_UART_TX",
+ "HST_WLAN_UART_RX";
};
&uart2 {
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v1 5/9] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
` (3 preceding siblings ...)
2022-10-28 12:08 ` [PATCH v1 4/9] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names Robert Foss
@ 2022-10-28 12:08 ` Robert Foss
2022-10-28 12:08 ` [PATCH v1 6/9] arm64: dts: qcom: sm8350: Use 2 interconnect cells Robert Foss
` (3 subsequent siblings)
8 siblings, 0 replies; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
The mmxc power-domain-name is not required, and is not
used by either earlier or later SoC versions (sm8250 / sm8450).
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e72a04411888..606fab087945 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2557,7 +2557,6 @@ dispcc: clock-controller@af00000 {
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8350_MMCX>;
- power-domain-names = "mmcx";
};
adsp: remoteproc@17300000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v1 6/9] arm64: dts: qcom: sm8350: Use 2 interconnect cells
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
` (4 preceding siblings ...)
2022-10-28 12:08 ` [PATCH v1 5/9] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name Robert Foss
@ 2022-10-28 12:08 ` Robert Foss
2022-10-28 13:44 ` Bjorn Andersson
2022-10-28 12:08 ` [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
` (2 subsequent siblings)
8 siblings, 1 reply; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
Use two interconnect cells in order to optionally
support a path tag.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 606fab087945..b6e44cd3b394 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 {
config_noc: interconnect@1500000 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x01500000 0 0xa580>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@1580000 {
compatible = "qcom,sm8350-mc-virt";
reg = <0 0x01580000 0 0x1000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1680000 {
compatible = "qcom,sm8350-system-noc";
reg = <0 0x01680000 0 0x1c200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8350-aggre1-noc";
reg = <0 0x016e0000 0 0x1f180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sm8350-aggre2-noc";
reg = <0 0x01700000 0 0x33000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sm8350-mmss-noc";
reg = <0 0x01740000 0 0x1f080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@3c40000 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c40000 0 0xf080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
compute_noc: interconnect@a0c0000{
compatible = "qcom,sm8350-compute-noc";
reg = <0 0x0a0c0000 0 0xa180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
@@ -2420,14 +2420,14 @@ usb_2_ssphy: phy@88ebe00 {
dc_noc: interconnect@90c0000 {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c0000 0 0x4200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@9100000 {
compatible = "qcom,sm8350-gem-noc";
reg = <0 0x09100000 0 0xb4000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
` (5 preceding siblings ...)
2022-10-28 12:08 ` [PATCH v1 6/9] arm64: dts: qcom: sm8350: Use 2 interconnect cells Robert Foss
@ 2022-10-28 12:08 ` Robert Foss
2022-10-28 13:50 ` Bjorn Andersson
2022-10-28 22:01 ` Krzysztof Kozlowski
2022-10-28 12:08 ` [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Robert Foss
2022-10-28 12:08 ` [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
8 siblings, 2 replies; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++++++++++++++++++++++++++-
1 file changed, 192 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index b6e44cd3b394..eaa3cdee1860 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
@@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a800000 {
};
};
+ mdss: mdss@ae00000 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ status = "ok";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp", "vbif";
+ iommus = <&apps_smmu 0x820 0x402>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ status = "ok";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: mdp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>,
+ <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-5nm-8350";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+
+ dsi_opp_table: dsi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,sm8350-dispcc";
reg = <0 0x0af00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&dsi0_phy 0>, <&dsi0_phy 1>,
+ <0>, <0>,
<0>,
<0>;
clock-names = "bi_tcxo",
@@ -2557,6 +2744,7 @@ dispcc: clock-controller@af00000 {
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8350_MMCX>;
+ required-opps = <&rpmhpd_opp_turbo>;
};
adsp: remoteproc@17300000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
` (6 preceding siblings ...)
2022-10-28 12:08 ` [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
@ 2022-10-28 12:08 ` Robert Foss
2022-10-28 13:51 ` Bjorn Andersson
2022-10-28 22:03 ` Krzysztof Kozlowski
2022-10-28 12:08 ` [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
8 siblings, 2 replies; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
Enable the display subsystem and the dsi0 output for
the sm8350-hdk board.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e6deb08c6da0..6e07feb4b3b2 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -213,10 +213,32 @@ &cdsp {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
+&dispcc {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "okay";
+ vdda-supply = <&vreg_l6b_1p2>;
+};
+
+&dsi0_phy {
+ status = "okay";
+ vdds-supply = <&vreg_l5b_0p88>;
+};
+
&gpi_dma1 {
status = "okay";
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
&mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
` (7 preceding siblings ...)
2022-10-28 12:08 ` [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Robert Foss
@ 2022-10-28 12:08 ` Robert Foss
2022-10-28 13:56 ` Dmitry Baryshkov
` (2 more replies)
8 siblings, 3 replies; 30+ messages in thread
From: Robert Foss @ 2022-10-28 12:08 UTC (permalink / raw)
To: agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
robert.foss, angelogioacchino.delregno, loic.poulain,
quic_vpolimer, vkoul, dianders, linux-arm-msm, devicetree,
linux-kernel, dri-devel, freedreno, Jonathan Marek, vinod.koul,
quic_jesszhan
The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
In order to toggle the board to enable the HDMI output,
switch #7 & #8 on the rightmost multi-switch package have
to be toggled to On.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 106 ++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 6e07feb4b3b2..6666b38b58f8 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -20,6 +20,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -29,6 +40,32 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+ lt9611_1v2: lt9611-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ vin-supply = <&vph_pwr>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lt9611_3v3: lt9611-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ vin-supply = <&vreg_bob>;
+ gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&adsp {
@@ -220,6 +257,15 @@ &dispcc {
&dsi0 {
status = "okay";
vdda-supply = <&vreg_l6b_1p2>;
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
};
&dsi0_phy {
@@ -231,6 +277,48 @@ &gpi_dma1 {
status = "okay";
};
+&i2c15 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+ status = "okay";
+
+ interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+
+ };
+ };
+};
+
&mdss {
status = "okay";
};
@@ -248,6 +336,10 @@ &qupv3_id_0 {
status = "okay";
};
+&qupv3_id_2 {
+ status = "okay";
+};
+
&slpi {
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
@@ -544,4 +636,18 @@ usb_hub_enabled_state: usb-hub-enabled-state {
drive-strength = <2>;
output-low;
};
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio48";
+ function = "normal";
+
+ output-high;
+ input-disable;
+ };
+
+ lt9611_irq_pin: lt9611-irq {
+ pins = "gpio50";
+ function = "gpio";
+ bias-disable;
+ };
};
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display
2022-10-28 12:08 ` [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display Robert Foss
@ 2022-10-28 12:13 ` Dmitry Baryshkov
2022-10-28 12:19 ` Dmitry Baryshkov
1 sibling, 0 replies; 30+ messages in thread
From: Dmitry Baryshkov @ 2022-10-28 12:13 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk, sean, airlied,
daniel, quic_kalyant, swboyd, angelogioacchino.delregno,
loic.poulain, quic_vpolimer, vkoul, dianders, linux-arm-msm,
devicetree, linux-kernel, dri-devel, freedreno, Jonathan Marek,
vinod.koul, quic_jesszhan
On 28/10/2022 15:08, Robert Foss wrote:
> Add compatible string for "qcom,sm8350-dpu" and
> "qcom,sm8350-mdss".
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> drivers/gpu/drm/msm/msm_mdss.c | 1 +
> 2 files changed, 2 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 2/9] drm/msm/dpu: Refactor sc7280_pp location
2022-10-28 12:08 ` [PATCH v1 2/9] drm/msm/dpu: Refactor sc7280_pp location Robert Foss
@ 2022-10-28 12:14 ` Dmitry Baryshkov
0 siblings, 0 replies; 30+ messages in thread
From: Dmitry Baryshkov @ 2022-10-28 12:14 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk, sean, airlied,
daniel, quic_kalyant, swboyd, angelogioacchino.delregno,
loic.poulain, quic_vpolimer, vkoul, dianders, linux-arm-msm,
devicetree, linux-kernel, dri-devel, freedreno, Jonathan Marek,
vinod.koul, quic_jesszhan
On 28/10/2022 15:08, Robert Foss wrote:
> The sc7280_pp declaration is not located by the other _pp
> declarations, but rather hidden around the _merge_3d
> declarations. Let's fix this to avoid confusion.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display
2022-10-28 12:08 ` [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display Robert Foss
2022-10-28 12:13 ` Dmitry Baryshkov
@ 2022-10-28 12:19 ` Dmitry Baryshkov
2022-10-28 12:29 ` Dmitry Baryshkov
1 sibling, 1 reply; 30+ messages in thread
From: Dmitry Baryshkov @ 2022-10-28 12:19 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk, sean, airlied,
daniel, quic_kalyant, swboyd, angelogioacchino.delregno,
loic.poulain, quic_vpolimer, vkoul, dianders, linux-arm-msm,
devicetree, linux-kernel, dri-devel, freedreno, Jonathan Marek,
vinod.koul, quic_jesszhan
On 28/10/2022 15:08, Robert Foss wrote:
> Add compatible string for "qcom,sm8350-dpu" and
> "qcom,sm8350-mdss".
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> drivers/gpu/drm/msm/msm_mdss.c | 1 +
> 2 files changed, 2 insertions(+)
[skipped]
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index e13c5c12b775..fd5a95cace16 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -447,6 +447,7 @@ static const struct of_device_id mdss_dt_match[] = {
> { .compatible = "qcom,sc8180x-mdss" },
> { .compatible = "qcom,sm8150-mdss" },
> { .compatible = "qcom,sm8250-mdss" },
> + { .compatible = "qcom,sm8350-mdss" },
> {}
> };
> MODULE_DEVICE_TABLE(of, mdss_dt_match);
BTW: you probably also have to update the msm_mdss_enable() function
with the 8350-specific code.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 3/9] drm/msm/dpu: Add SM8350 to hw catalog
2022-10-28 12:08 ` [PATCH v1 3/9] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
@ 2022-10-28 12:26 ` Dmitry Baryshkov
2022-11-11 12:39 ` Robert Foss
0 siblings, 1 reply; 30+ messages in thread
From: Dmitry Baryshkov @ 2022-10-28 12:26 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk, sean, airlied,
daniel, quic_kalyant, swboyd, angelogioacchino.delregno,
loic.poulain, quic_vpolimer, vkoul, dianders, linux-arm-msm,
devicetree, linux-kernel, dri-devel, freedreno, Jonathan Marek,
vinod.koul, quic_jesszhan
On 28/10/2022 15:08, Robert Foss wrote:
> Add compatibility for SM8350 display subsystem, including
> required entries in DPU hw catalog.
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 217 ++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> 2 files changed, 218 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index d0ce7612fee8..bc829d7bdd6e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -112,6 +112,15 @@
> BIT(MDP_INTF3_INTR) | \
> BIT(MDP_INTF4_INTR))
>
> +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_7xxx_INTR) | \
> + BIT(MDP_INTF1_7xxx_INTR) | \
> + BIT(MDP_INTF2_7xxx_INTR) | \
> + BIT(MDP_INTF3_7xxx_INTR) | \
> + 0)
> +
> #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> BIT(MDP_SSPP_TOP0_INTR2) | \
> BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> @@ -364,6 +373,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> };
>
> +static const struct dpu_caps sm8350_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0xb,
> + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> + .ubwc_version = DPU_HW_UBWC_VER_40,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .has_3d_merge = true,
> + .max_linewidth = 4096,
Is it 4096 or 5120?
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> static const struct dpu_caps sc7280_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0x7,
> @@ -501,6 +524,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> },
> };
>
> +static const struct dpu_mdp_cfg sm8350_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + .base = 0x0, .len = 0x494,
> + .features = 0,
> + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> + .reg_off = 0x2AC, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> + .reg_off = 0x2B4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> + .reg_off = 0x2BC, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> + .reg_off = 0x2C4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> + .reg_off = 0x2AC, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> + .reg_off = 0x2B4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> + .reg_off = 0x2BC, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> + .reg_off = 0x2C4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> + .reg_off = 0x2BC, .bit_off = 20},
> + },
> +};
> +
> static const struct dpu_mdp_cfg sc7280_mdp[] = {
> {
> .name = "top_0", .id = MDP_TOP,
> @@ -659,6 +709,66 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> },
> };
>
> +static const struct dpu_ctl_cfg sm8350_ctl[] = {
> + {
> + .name = "ctl_0", .id = CTL_0,
> + .base = 0x15000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) |
> + BIT(DPU_CTL_PINGPONG_SPLIT) |
> + BIT(DPU_CTL_ACTIVE_CFG) |
> + BIT(DPU_CTL_FETCH_ACTIVE) |
> + BIT(DPU_CTL_VM_CFG) |
> + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> + },
> + {
> + .name = "ctl_1", .id = CTL_1,
> + .base = 0x16000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) |
> + BIT(DPU_CTL_ACTIVE_CFG) |
> + BIT(DPU_CTL_FETCH_ACTIVE) |
> + BIT(DPU_CTL_VM_CFG) |
> + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
The UNIFIED_DSPP_FLUSH is not merged. Could you please change this to
BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK (for first two CTLs) and
just CTL_SC7280_MASK for the rest of them?
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> + },
> + {
> + .name = "ctl_2", .id = CTL_2,
> + .base = 0x17000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) |
> + BIT(DPU_CTL_FETCH_ACTIVE) |
> + BIT(DPU_CTL_VM_CFG) |
> + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> + },
> + {
> + .name = "ctl_3", .id = CTL_3,
> + .base = 0x18000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) |
> + BIT(DPU_CTL_FETCH_ACTIVE) |
> + BIT(DPU_CTL_VM_CFG) |
> + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> + },
> + {
> + .name = "ctl_4", .id = CTL_4,
> + .base = 0x19000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) |
> + BIT(DPU_CTL_FETCH_ACTIVE) |
> + BIT(DPU_CTL_VM_CFG) |
> + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> + },
> + {
> + .name = "ctl_5", .id = CTL_5,
> + .base = 0x1a000, .len = 0x1e8,
> + .features = BIT(DPU_CTL_ACTIVE_CFG) |
> + BIT(DPU_CTL_FETCH_ACTIVE) |
> + BIT(DPU_CTL_VM_CFG) |
> + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> + },
> +};
> +
> static const struct dpu_ctl_cfg sc7280_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> @@ -1182,6 +1292,27 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
> PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
> };
>
> +static const struct dpu_pingpong_cfg sm8350_pp[] = {
> + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + -1),
> + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
> + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + -1),
> +};
> +
> static struct dpu_pingpong_cfg qcm2290_pp[] = {
> PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> @@ -1205,6 +1336,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
> MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
> };
>
> +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
> + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> +};
> +
> /*************************************************************
> * DSC sub blocks config
> *************************************************************/
> @@ -1222,6 +1359,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = {
> DSC_BLK("dsc_3", DSC_3, 0x80c00),
> };
>
> +static struct dpu_dsc_cfg sm8350_dsc[] = {
> + DSC_BLK("dsc_0", DSC_0, 0x80000),
> + DSC_BLK("dsc_1", DSC_1, 0x81000),
> + DSC_BLK("dsc_2", DSC_2, 0x82000),
> +};
> +
> /*************************************************************
> * INTF sub blocks config
> *************************************************************/
> @@ -1269,6 +1412,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> };
>
> +static const struct dpu_intf_cfg sm8350_intf[] = {
> + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> +};
> +
> static const struct dpu_intf_cfg sc8180x_intf[] = {
> INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> @@ -1397,6 +1547,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
> .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> };
>
> +static const struct dpu_reg_dma_cfg sm8350_regdma = {
> + .base = 0x0,
> + .version = 0x00020000,
> + .trigger_sel_off = 0x119c,
> + .xin_id = 7,
> + .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> +};
> +
> /*************************************************************
> * PERF data config
> *************************************************************/
> @@ -1700,6 +1858,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
> .bw_inefficiency_factor = 120,
> };
>
> +static const struct dpu_perf_cfg sm8350_perf_data = {
> + .max_bw_low = 11800000,
> + .max_bw_high = 18200000,
> + .min_core_ib = 2500000,
> + .min_llcc_ib = 0,
> + .min_dram_ib = 800000,
> + .min_prefill_lines = 40,
> + /* FIXME: lut tables */
> + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
> + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
> + .qos_lut_tbl = {
> + {.nentry = ARRAY_SIZE(sc7180_qos_linear),
> + .entries = sc7180_qos_linear
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> + .entries = sc7180_qos_macrotile
> + },
> + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> + .entries = sc7180_qos_nrt
> + },
> + /* TODO: macrotile-qseed is different from macrotile */
> + },
> + .cdp_cfg = {
> + {.rd_enable = 1, .wr_enable = 1},
> + {.rd_enable = 1, .wr_enable = 0}
> + },
> + .clk_inefficiency_factor = 105,
> + .bw_inefficiency_factor = 120,
> +};
> +
> static const struct dpu_perf_cfg qcm2290_perf_data = {
> .max_bw_low = 2700000,
> .max_bw_high = 2700000,
> @@ -1876,6 +2064,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
> .mdss_irqs = IRQ_SM8250_MASK,
> };
>
> +static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
> + .caps = &sm8350_dpu_caps,
> + .mdp_count = ARRAY_SIZE(sm8350_mdp),
> + .mdp = sm8350_mdp,
> + .ctl_count = ARRAY_SIZE(sm8350_ctl),
> + .ctl = sm8350_ctl,
> + .sspp_count = ARRAY_SIZE(sm8250_sspp),
> + .sspp = sm8250_sspp,
> + .mixer_count = ARRAY_SIZE(sm8150_lm),
> + .mixer = sm8150_lm,
> + .dspp_count = ARRAY_SIZE(sm8150_dspp),
> + .dspp = sm8150_dspp,
> + .pingpong_count = ARRAY_SIZE(sm8350_pp),
> + .pingpong = sm8350_pp,
> + .dsc_count = ARRAY_SIZE(sm8350_dsc),
> + .dsc = sm8350_dsc,
> + .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
> + .merge_3d = sm8350_merge_3d,
> + .intf_count = ARRAY_SIZE(sm8350_intf),
> + .intf = sm8350_intf,
> + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> + .vbif = sdm845_vbif,
> + .reg_dma_count = 1,
> + .dma_cfg = &sm8250_regdma,
> + .perf = &sm8350_perf_data,
> + .mdss_irqs = IRQ_SM8350_MASK,
> +};
> +
> static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
> .caps = &sc7280_dpu_caps,
> .mdp_count = ARRAY_SIZE(sc7280_mdp),
> @@ -1933,6 +2149,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
> { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
> { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
> { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
> + { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
> { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 71fe4c505f5b..e59630e06110 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -45,6 +45,7 @@
> #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
> #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
> #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
> +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
> #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
>
> #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display
2022-10-28 12:19 ` Dmitry Baryshkov
@ 2022-10-28 12:29 ` Dmitry Baryshkov
0 siblings, 0 replies; 30+ messages in thread
From: Dmitry Baryshkov @ 2022-10-28 12:29 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk, sean, airlied,
daniel, quic_kalyant, swboyd, angelogioacchino.delregno,
loic.poulain, quic_vpolimer, vkoul, dianders, linux-arm-msm,
devicetree, linux-kernel, dri-devel, freedreno, Jonathan Marek,
vinod.koul, quic_jesszhan
On 28/10/2022 15:19, Dmitry Baryshkov wrote:
> On 28/10/2022 15:08, Robert Foss wrote:
>> Add compatible string for "qcom,sm8350-dpu" and
>> "qcom,sm8350-mdss".
>>
>> Signed-off-by: Robert Foss <robert.foss@linaro.org>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
>> drivers/gpu/drm/msm/msm_mdss.c | 1 +
>> 2 files changed, 2 insertions(+)
>
> [skipped]
>
>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c
>> b/drivers/gpu/drm/msm/msm_mdss.c
>> index e13c5c12b775..fd5a95cace16 100644
>> --- a/drivers/gpu/drm/msm/msm_mdss.c
>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
>> @@ -447,6 +447,7 @@ static const struct of_device_id mdss_dt_match[] = {
>> { .compatible = "qcom,sc8180x-mdss" },
>> { .compatible = "qcom,sm8150-mdss" },
>> { .compatible = "qcom,sm8250-mdss" },
>> + { .compatible = "qcom,sm8350-mdss" },
>> {}
>> };
>> MODULE_DEVICE_TABLE(of, mdss_dt_match);
>
>
> BTW: you probably also have to update the msm_mdss_enable() function
> with the 8350-specific code.
>
For mdss changes you can depend on [1], I plan to merge this patch in
this window.
[1] https://patchwork.freedesktop.org/patch/489578/?series=105162&rev=1
Also with the mdss changes, it would be good to split this patch into
dpu and mdss parts.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 6/9] arm64: dts: qcom: sm8350: Use 2 interconnect cells
2022-10-28 12:08 ` [PATCH v1 6/9] arm64: dts: qcom: sm8350: Use 2 interconnect cells Robert Foss
@ 2022-10-28 13:44 ` Bjorn Andersson
2022-11-11 13:52 ` Robert Foss
0 siblings, 1 reply; 30+ messages in thread
From: Bjorn Andersson @ 2022-10-28 13:44 UTC (permalink / raw)
To: Robert Foss
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
dmitry.baryshkov, freedreno
On Fri, Oct 28, 2022 at 02:08:09PM +0200, Robert Foss wrote:
> Use two interconnect cells in order to optionally
> support a path tag.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 606fab087945..b6e44cd3b394 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 {
> config_noc: interconnect@1500000 {
> compatible = "qcom,sm8350-config-noc";
> reg = <0 0x01500000 0 0xa580>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
You also need amend all the interconnects references with the additional
tag cell.
Regards,
Bjorn
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> mc_virt: interconnect@1580000 {
> compatible = "qcom,sm8350-mc-virt";
> reg = <0 0x01580000 0 0x1000>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> system_noc: interconnect@1680000 {
> compatible = "qcom,sm8350-system-noc";
> reg = <0 0x01680000 0 0x1c200>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> aggre1_noc: interconnect@16e0000 {
> compatible = "qcom,sm8350-aggre1-noc";
> reg = <0 0x016e0000 0 0x1f180>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> aggre2_noc: interconnect@1700000 {
> compatible = "qcom,sm8350-aggre2-noc";
> reg = <0 0x01700000 0 0x33000>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> mmss_noc: interconnect@1740000 {
> compatible = "qcom,sm8350-mmss-noc";
> reg = <0 0x01740000 0 0x1f080>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> lpass_ag_noc: interconnect@3c40000 {
> compatible = "qcom,sm8350-lpass-ag-noc";
> reg = <0 0x03c40000 0 0xf080>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> compute_noc: interconnect@a0c0000{
> compatible = "qcom,sm8350-compute-noc";
> reg = <0 0x0a0c0000 0 0xa180>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> @@ -2420,14 +2420,14 @@ usb_2_ssphy: phy@88ebe00 {
> dc_noc: interconnect@90c0000 {
> compatible = "qcom,sm8350-dc-noc";
> reg = <0 0x090c0000 0 0x4200>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> gem_noc: interconnect@9100000 {
> compatible = "qcom,sm8350-gem-noc";
> reg = <0 0x09100000 0 0xb4000>;
> - #interconnect-cells = <1>;
> + #interconnect-cells = <2>;
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes
2022-10-28 12:08 ` [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
@ 2022-10-28 13:50 ` Bjorn Andersson
2022-10-28 22:01 ` Krzysztof Kozlowski
1 sibling, 0 replies; 30+ messages in thread
From: Bjorn Andersson @ 2022-10-28 13:50 UTC (permalink / raw)
To: Robert Foss
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
dmitry.baryshkov, freedreno
On Fri, Oct 28, 2022 at 02:08:10PM +0200, Robert Foss wrote:
> Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
> nodes the display subsystem is configured to support
> one DSI output.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++++++++++++++++++++++++++-
> 1 file changed, 192 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index b6e44cd3b394..eaa3cdee1860 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2020, Linaro Limited
> */
>
> +#include <dt-bindings/interconnect/qcom,sm8350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> @@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a800000 {
> };
> };
>
> + mdss: mdss@ae00000 {
display-subsystem@ae00000 please.
> + compatible = "qcom,sm8350-mdss";
> + reg = <0 0x0ae00000 0 0x1000>;
> + reg-names = "mdss";
> +
> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + power-domains = <&dispcc MDSS_GDSC>;
> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "nrt_bus", "core";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + status = "ok";
You want "disabled" here, and then "okay" in the .dts.
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss_mdp: mdp@ae01000 {
display-controller@ae01000 please.
> + compatible = "qcom,sm8350-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> + iommus = <&apps_smmu 0x820 0x402>;
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + status = "ok";
"okay", but this is the default, so you can skip it in the .dtsi
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> +
> + mdp_opp_table: mdp-opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-345000000 {
> + opp-hz = /bits/ 64 <345000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-460000000 {
> + opp-hz = /bits/ 64 <460000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&dsi0_phy 0>,
> + <&dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + phys = <&dsi0_phy>;
> + phy-names = "dsi";
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi0_phy: dsi-phy@ae94400 {
> + compatible = "qcom,dsi-phy-5nm-8350";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x260>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> +
> + dsi_opp_table: dsi-opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-187500000 {
> + opp-hz = /bits/ 64 <187500000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-358000000 {
> + opp-hz = /bits/ 64 <358000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> + };
> + };
> + };
> +
> dispcc: clock-controller@af00000 {
> compatible = "qcom,sm8350-dispcc";
> reg = <0 0x0af00000 0 0x10000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> + <&dsi0_phy 0>, <&dsi0_phy 1>,
> + <0>, <0>,
> <0>,
> <0>;
> clock-names = "bi_tcxo",
> @@ -2557,6 +2744,7 @@ dispcc: clock-controller@af00000 {
> #power-domain-cells = <1>;
>
> power-domains = <&rpmhpd SM8350_MMCX>;
> + required-opps = <&rpmhpd_opp_turbo>;
That seems a little bit aggressive, is the opp-based voting from within
the mdss/dpu not sufficient?
Regards,
Bjorn
> };
>
> adsp: remoteproc@17300000 {
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
2022-10-28 12:08 ` [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Robert Foss
@ 2022-10-28 13:51 ` Bjorn Andersson
2022-10-28 22:03 ` Krzysztof Kozlowski
1 sibling, 0 replies; 30+ messages in thread
From: Bjorn Andersson @ 2022-10-28 13:51 UTC (permalink / raw)
To: Robert Foss
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
dmitry.baryshkov, freedreno
On Fri, Oct 28, 2022 at 02:08:11PM +0200, Robert Foss wrote:
> Enable the display subsystem and the dsi0 output for
> the sm8350-hdk board.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> index e6deb08c6da0..6e07feb4b3b2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> @@ -213,10 +213,32 @@ &cdsp {
> firmware-name = "qcom/sm8350/cdsp.mbn";
> };
>
> +&dispcc {
> + status = "okay";
> +};
> +
> +&dsi0 {
If you prefix the label for the dsi controller and phy with mdss_ they
sort nicely together with the other display nodes.
Regards,
Bjorn
> + status = "okay";
> + vdda-supply = <&vreg_l6b_1p2>;
> +};
> +
> +&dsi0_phy {
> + status = "okay";
> + vdds-supply = <&vreg_l5b_0p88>;
> +};
> +
> &gpi_dma1 {
> status = "okay";
> };
>
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_mdp {
> + status = "okay";
> +};
> +
> &mpss {
> status = "okay";
> firmware-name = "qcom/sm8350/modem.mbn";
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-10-28 12:08 ` [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
@ 2022-10-28 13:56 ` Dmitry Baryshkov
2022-11-03 14:19 ` Dmitry Baryshkov
2022-10-28 13:57 ` Bjorn Andersson
2022-10-28 22:05 ` Krzysztof Kozlowski
2 siblings, 1 reply; 30+ messages in thread
From: Dmitry Baryshkov @ 2022-10-28 13:56 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk, sean, airlied,
daniel, quic_kalyant, swboyd, angelogioacchino.delregno,
loic.poulain, quic_vpolimer, vkoul, dianders, linux-arm-msm,
devicetree, linux-kernel, dri-devel, freedreno, Jonathan Marek,
vinod.koul, quic_jesszhan
On 28/10/2022 15:08, Robert Foss wrote:
> The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
>
> In order to toggle the board to enable the HDMI output,
> switch #7 & #8 on the rightmost multi-switch package have
> to be toggled to On.
Since this doesn't look like a default setup, it would probably make
sense to move this to new sm8350-hdk-hdmi.dts with the comment regarding
necessary switch changes at the top of the file.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 106 ++++++++++++++++++++++++
> 1 file changed, 106 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> index 6e07feb4b3b2..6666b38b58f8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> @@ -20,6 +20,17 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
> + hdmi-out {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con: endpoint {
> + remote-endpoint = <<9611_out>;
> + };
> + };
> + };
> +
> vph_pwr: vph-pwr-regulator {
> compatible = "regulator-fixed";
> regulator-name = "vph_pwr";
> @@ -29,6 +40,32 @@ vph_pwr: vph-pwr-regulator {
> regulator-always-on;
> regulator-boot-on;
> };
> +
> + lt9611_1v2: lt9611-1v2 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT9611_1V2";
> +
> + vin-supply = <&vph_pwr>;
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + lt9611_3v3: lt9611-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT9611_3V3";
> +
> + vin-supply = <&vreg_bob>;
> + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> };
>
> &adsp {
> @@ -220,6 +257,15 @@ &dispcc {
> &dsi0 {
> status = "okay";
> vdda-supply = <&vreg_l6b_1p2>;
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <<9611_a>;
> + data-lanes = <0 1 2 3>;
> + };
> + };
> + };
> };
>
> &dsi0_phy {
> @@ -231,6 +277,48 @@ &gpi_dma1 {
> status = "okay";
> };
>
> +&i2c15 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + lt9611_codec: hdmi-bridge@2b {
> + compatible = "lontium,lt9611uxc";
> + reg = <0x2b>;
> + status = "okay";
> +
> + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
> +
> + vdd-supply = <<9611_1v2>;
> + vcc-supply = <<9611_3v3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lt9611_a: endpoint {
> + remote-endpoint = <&dsi0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + lt9611_out: endpoint {
> + remote-endpoint = <&hdmi_con>;
> + };
> + };
> +
> + };
> + };
> +};
> +
> &mdss {
> status = "okay";
> };
> @@ -248,6 +336,10 @@ &qupv3_id_0 {
> status = "okay";
> };
>
> +&qupv3_id_2 {
> + status = "okay";
> +};
> +
> &slpi {
> status = "okay";
> firmware-name = "qcom/sm8350/slpi.mbn";
> @@ -544,4 +636,18 @@ usb_hub_enabled_state: usb-hub-enabled-state {
> drive-strength = <2>;
> output-low;
> };
> +
> + lt9611_rst_pin: lt9611-rst-state {
> + pins = "gpio48";
> + function = "normal";
> +
> + output-high;
> + input-disable;
> + };
> +
> + lt9611_irq_pin: lt9611-irq {
> + pins = "gpio50";
> + function = "gpio";
> + bias-disable;
> + };
> };
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-10-28 12:08 ` [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
2022-10-28 13:56 ` Dmitry Baryshkov
@ 2022-10-28 13:57 ` Bjorn Andersson
2022-11-11 15:18 ` Robert Foss
2022-10-28 22:05 ` Krzysztof Kozlowski
2 siblings, 1 reply; 30+ messages in thread
From: Bjorn Andersson @ 2022-10-28 13:57 UTC (permalink / raw)
To: Robert Foss
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
dmitry.baryshkov, freedreno
On Fri, Oct 28, 2022 at 02:08:12PM +0200, Robert Foss wrote:
> The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
>
> In order to toggle the board to enable the HDMI output,
> switch #7 & #8 on the rightmost multi-switch package have
> to be toggled to On.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 106 ++++++++++++++++++++++++
> 1 file changed, 106 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> index 6e07feb4b3b2..6666b38b58f8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> @@ -20,6 +20,17 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
> + hdmi-out {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con: endpoint {
> + remote-endpoint = <<9611_out>;
> + };
> + };
> + };
> +
> vph_pwr: vph-pwr-regulator {
> compatible = "regulator-fixed";
> regulator-name = "vph_pwr";
> @@ -29,6 +40,32 @@ vph_pwr: vph-pwr-regulator {
> regulator-always-on;
> regulator-boot-on;
> };
> +
> + lt9611_1v2: lt9611-1v2 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT9611_1V2";
> +
> + vin-supply = <&vph_pwr>;
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-boot-on;
> + regulator-always-on;
Why is this always-on?
> + };
> +
> + lt9611_3v3: lt9611-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT9611_3V3";
> +
> + vin-supply = <&vreg_bob>;
> + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> };
>
> &adsp {
> @@ -220,6 +257,15 @@ &dispcc {
> &dsi0 {
> status = "okay";
> vdda-supply = <&vreg_l6b_1p2>;
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <<9611_a>;
> + data-lanes = <0 1 2 3>;
> + };
> + };
> + };
> };
>
> &dsi0_phy {
> @@ -231,6 +277,48 @@ &gpi_dma1 {
> status = "okay";
> };
>
> +&i2c15 {
> + status = "okay";
Please keep status last. (Yes I see that it goes against the convention
in this file, so let's update that at some point as well)
> + clock-frequency = <400000>;
> +
> + lt9611_codec: hdmi-bridge@2b {
> + compatible = "lontium,lt9611uxc";
> + reg = <0x2b>;
> + status = "okay";
This is the default, you can omit it.
> +
> + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
> +
> + vdd-supply = <<9611_1v2>;
> + vcc-supply = <<9611_3v3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lt9611_a: endpoint {
> + remote-endpoint = <&dsi0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + lt9611_out: endpoint {
> + remote-endpoint = <&hdmi_con>;
> + };
> + };
> +
> + };
> + };
> +};
> +
> &mdss {
> status = "okay";
> };
> @@ -248,6 +336,10 @@ &qupv3_id_0 {
> status = "okay";
> };
>
> +&qupv3_id_2 {
> + status = "okay";
> +};
> +
> &slpi {
> status = "okay";
> firmware-name = "qcom/sm8350/slpi.mbn";
> @@ -544,4 +636,18 @@ usb_hub_enabled_state: usb-hub-enabled-state {
> drive-strength = <2>;
> output-low;
> };
> +
> + lt9611_rst_pin: lt9611-rst-state {
> + pins = "gpio48";
> + function = "normal";
> +
> + output-high;
> + input-disable;
> + };
> +
> + lt9611_irq_pin: lt9611-irq {
pinctrl state nodes should be suffixed with "-state".
And you can lump the two pins into a single -state, with rst-pins and
irq-pins as subnodes, defining the two pins.
Regards,
Bjorn
> + pins = "gpio50";
> + function = "gpio";
> + bias-disable;
> + };
> };
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes
2022-10-28 12:08 ` [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
2022-10-28 13:50 ` Bjorn Andersson
@ 2022-10-28 22:01 ` Krzysztof Kozlowski
2022-11-11 15:16 ` Robert Foss
1 sibling, 1 reply; 30+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-28 22:01 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
angelogioacchino.delregno, loic.poulain, quic_vpolimer, vkoul,
dianders, linux-arm-msm, devicetree, linux-kernel, dri-devel,
freedreno, Jonathan Marek, vinod.koul, quic_jesszhan,
Dmitry Baryshkov
On 28/10/2022 08:08, Robert Foss wrote:
> Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
> nodes the display subsystem is configured to support
> one DSI output.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++++++++++++++++++++++++++-
> 1 file changed, 192 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index b6e44cd3b394..eaa3cdee1860 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2020, Linaro Limited
> */
>
> +#include <dt-bindings/interconnect/qcom,sm8350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> @@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a800000 {
> };
> };
>
> + mdss: mdss@ae00000 {
> + compatible = "qcom,sm8350-mdss";
> + reg = <0 0x0ae00000 0 0x1000>;
> + reg-names = "mdss";
> +
> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + power-domains = <&dispcc MDSS_GDSC>;
> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "nrt_bus", "core";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + status = "ok";
No need for this.
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss_mdp: mdp@ae01000 {
Node name: display-controller
> + compatible = "qcom,sm8350-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> + iommus = <&apps_smmu 0x820 0x402>;
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&gcc GCC_DISP_SF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + status = "ok";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> +
> + mdp_opp_table: mdp-opp-table {
I have doubts that it passes dtbs_checks... opp-table
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-345000000 {
> + opp-hz = /bits/ 64 <345000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-460000000 {
> + opp-hz = /bits/ 64 <460000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&dsi0_phy 0>,
> + <&dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + phys = <&dsi0_phy>;
> + phy-names = "dsi";
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + dsi0_phy: dsi-phy@ae94400 {
Just "phy". I think Dmitry was renaming all of these.
> + compatible = "qcom,dsi-phy-5nm-8350";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x260>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> +
> + dsi_opp_table: dsi-opp-table {
opp-table
Run `make dtbs_check`
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
2022-10-28 12:08 ` [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Robert Foss
2022-10-28 13:51 ` Bjorn Andersson
@ 2022-10-28 22:03 ` Krzysztof Kozlowski
2022-11-11 15:17 ` Robert Foss
1 sibling, 1 reply; 30+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-28 22:03 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
angelogioacchino.delregno, loic.poulain, quic_vpolimer, vkoul,
dianders, linux-arm-msm, devicetree, linux-kernel, dri-devel,
freedreno, Jonathan Marek, vinod.koul, quic_jesszhan
On 28/10/2022 08:08, Robert Foss wrote:
> Enable the display subsystem and the dsi0 output for
> the sm8350-hdk board.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> index e6deb08c6da0..6e07feb4b3b2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> @@ -213,10 +213,32 @@ &cdsp {
> firmware-name = "qcom/sm8350/cdsp.mbn";
> };
>
> +&dispcc {
> + status = "okay";
> +};
> +
> +&dsi0 {
> + status = "okay";
Status is the last property.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-10-28 12:08 ` [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
2022-10-28 13:56 ` Dmitry Baryshkov
2022-10-28 13:57 ` Bjorn Andersson
@ 2022-10-28 22:05 ` Krzysztof Kozlowski
2022-11-11 15:20 ` Robert Foss
2 siblings, 1 reply; 30+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-28 22:05 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk,
dmitry.baryshkov, sean, airlied, daniel, quic_kalyant, swboyd,
angelogioacchino.delregno, loic.poulain, quic_vpolimer, vkoul,
dianders, linux-arm-msm, devicetree, linux-kernel, dri-devel,
freedreno, Jonathan Marek, vinod.koul, quic_jesszhan
On 28/10/2022 08:08, Robert Foss wrote:
> The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
>
> In order to toggle the board to enable the HDMI output,
> switch #7 & #8 on the rightmost multi-switch package have
> to be toggled to On.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 106 ++++++++++++++++++++++++
> 1 file changed, 106 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> index 6e07feb4b3b2..6666b38b58f8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> @@ -20,6 +20,17 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
> + hdmi-out {
Generic node names, so hdmi-connector or just connector.
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con: endpoint {
> + remote-endpoint = <<9611_out>;
> + };
> + };
> + };
> +
> vph_pwr: vph-pwr-regulator {
> compatible = "regulator-fixed";
> regulator-name = "vph_pwr";
> @@ -29,6 +40,32 @@ vph_pwr: vph-pwr-regulator {
> regulator-always-on;
> regulator-boot-on;
> };
> +
> + lt9611_1v2: lt9611-1v2 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "regulator-fixed";
> + regulator-name = "LT9611_1V2";
> +
> + vin-supply = <&vph_pwr>;
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + lt9611_3v3: lt9611-3v3 {
Ditto
> + compatible = "regulator-fixed";
> + regulator-name = "LT9611_3V3";
> +
> + vin-supply = <&vreg_bob>;
> + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> };
>
> &adsp {
> @@ -220,6 +257,15 @@ &dispcc {
> &dsi0 {
> status = "okay";
> vdda-supply = <&vreg_l6b_1p2>;
> +
> + ports {
> + port@1 {
> + endpoint {
> + remote-endpoint = <<9611_a>;
> + data-lanes = <0 1 2 3>;
> + };
> + };
> + };
> };
>
> &dsi0_phy {
> @@ -231,6 +277,48 @@ &gpi_dma1 {
> status = "okay";
> };
>
> +&i2c15 {
> + status = "okay";
status is the last property
> + clock-frequency = <400000>;
> +
> + lt9611_codec: hdmi-bridge@2b {
> + compatible = "lontium,lt9611uxc";
> + reg = <0x2b>;
> + status = "okay";
Why status?
> +
> + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
> +
> + vdd-supply = <<9611_1v2>;
> + vcc-supply = <<9611_3v3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lt9611_a: endpoint {
> + remote-endpoint = <&dsi0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + lt9611_out: endpoint {
> + remote-endpoint = <&hdmi_con>;
> + };
> + };
> +
No need for blank line
> + };
> + };
> +};
> +
> &mdss {
> status = "okay";
> };
> @@ -248,6 +336,10 @@ &qupv3_id_0 {
> status = "okay";
> };
>
> +&qupv3_id_2 {
> + status = "okay";
> +};
> +
> &slpi {
> status = "okay";
> firmware-name = "qcom/sm8350/slpi.mbn";
> @@ -544,4 +636,18 @@ usb_hub_enabled_state: usb-hub-enabled-state {
> drive-strength = <2>;
> output-low;
> };
> +
> + lt9611_rst_pin: lt9611-rst-state {
> + pins = "gpio48";
> + function = "normal";
> +
> + output-high;
> + input-disable;
> + };
> +
> + lt9611_irq_pin: lt9611-irq {
Missing suffix 'state'.
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
Rebase your changes on last linux-next.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-10-28 13:56 ` Dmitry Baryshkov
@ 2022-11-03 14:19 ` Dmitry Baryshkov
0 siblings, 0 replies; 30+ messages in thread
From: Dmitry Baryshkov @ 2022-11-03 14:19 UTC (permalink / raw)
To: Robert Foss, agross, bjorn.andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, robdclark, quic_abhinavk, sean, airlied,
daniel, quic_kalyant, swboyd, angelogioacchino.delregno,
loic.poulain, quic_vpolimer, vkoul, dianders, linux-arm-msm,
devicetree, linux-kernel, dri-devel, freedreno, Jonathan Marek,
vinod.koul, quic_jesszhan
On 28/10/2022 16:56, Dmitry Baryshkov wrote:
> On 28/10/2022 15:08, Robert Foss wrote:
>> The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
>>
>> In order to toggle the board to enable the HDMI output,
>> switch #7 & #8 on the rightmost multi-switch package have
>> to be toggled to On.
>
> Since this doesn't look like a default setup, it would probably make
> sense to move this to new sm8350-hdk-hdmi.dts with the comment regarding
> necessary switch changes at the top of the file.
>
Please excuse me here. I checked the Lantronix site. It clearly names
'Optional Display/Expansion board mates to DSI connectors'. So, you were
correct, the HDMI should be in the base setup, while DSI panel should
come as the extending DT file.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 3/9] drm/msm/dpu: Add SM8350 to hw catalog
2022-10-28 12:26 ` Dmitry Baryshkov
@ 2022-11-11 12:39 ` Robert Foss
0 siblings, 0 replies; 30+ messages in thread
From: Robert Foss @ 2022-11-11 12:39 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
freedreno
On Fri, 28 Oct 2022 at 14:27, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 28/10/2022 15:08, Robert Foss wrote:
> > Add compatibility for SM8350 display subsystem, including
> > required entries in DPU hw catalog.
> > ---
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 217 ++++++++++++++++++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> > 2 files changed, 218 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index d0ce7612fee8..bc829d7bdd6e 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -112,6 +112,15 @@
> > BIT(MDP_INTF3_INTR) | \
> > BIT(MDP_INTF4_INTR))
> >
> > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_7xxx_INTR) | \
> > + BIT(MDP_INTF1_7xxx_INTR) | \
> > + BIT(MDP_INTF2_7xxx_INTR) | \
> > + BIT(MDP_INTF3_7xxx_INTR) | \
> > + 0)
> > +
> > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > BIT(MDP_SSPP_TOP0_INTR2) | \
> > BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > @@ -364,6 +373,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
> > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > };
> >
> > +static const struct dpu_caps sm8350_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0xb,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> > + .ubwc_version = DPU_HW_UBWC_VER_40,
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .has_3d_merge = true,
> > + .max_linewidth = 4096,
>
> Is it 4096 or 5120?
4096 is what I'm seeing in the downstream dts, except for the
wb-linewidth-linear property which is 5120.
So I would think 4096 is the correct value, what do you think?
>
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > +};
> > +
> > static const struct dpu_caps sc7280_dpu_caps = {
> > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > .max_mixer_blendstages = 0x7,
> > @@ -501,6 +524,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> > },
> > };
> >
> > +static const struct dpu_mdp_cfg sm8350_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x494,
> > + .features = 0,
> > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> > + .reg_off = 0x2AC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> > + .reg_off = 0x2B4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> > + .reg_off = 0x2BC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> > + .reg_off = 0x2C4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> > + .reg_off = 0x2AC, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> > + .reg_off = 0x2B4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> > + .reg_off = 0x2BC, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> > + .reg_off = 0x2C4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> > + .reg_off = 0x2BC, .bit_off = 20},
> > + },
> > +};
> > +
> > static const struct dpu_mdp_cfg sc7280_mdp[] = {
> > {
> > .name = "top_0", .id = MDP_TOP,
> > @@ -659,6 +709,66 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> > },
> > };
> >
> > +static const struct dpu_ctl_cfg sm8350_ctl[] = {
> > + {
> > + .name = "ctl_0", .id = CTL_0,
> > + .base = 0x15000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) |
> > + BIT(DPU_CTL_PINGPONG_SPLIT) |
> > + BIT(DPU_CTL_ACTIVE_CFG) |
> > + BIT(DPU_CTL_FETCH_ACTIVE) |
> > + BIT(DPU_CTL_VM_CFG) |
> > + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> > + },
> > + {
> > + .name = "ctl_1", .id = CTL_1,
> > + .base = 0x16000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) |
> > + BIT(DPU_CTL_ACTIVE_CFG) |
> > + BIT(DPU_CTL_FETCH_ACTIVE) |
> > + BIT(DPU_CTL_VM_CFG) |
> > + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
>
> The UNIFIED_DSPP_FLUSH is not merged. Could you please change this to
> BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK (for first two CTLs) and
> just CTL_SC7280_MASK for the rest of them?
Ack.
>
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> > + },
> > + {
> > + .name = "ctl_2", .id = CTL_2,
> > + .base = 0x17000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG) |
> > + BIT(DPU_CTL_FETCH_ACTIVE) |
> > + BIT(DPU_CTL_VM_CFG) |
> > + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> > + },
> > + {
> > + .name = "ctl_3", .id = CTL_3,
> > + .base = 0x18000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG) |
> > + BIT(DPU_CTL_FETCH_ACTIVE) |
> > + BIT(DPU_CTL_VM_CFG) |
> > + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> > + },
> > + {
> > + .name = "ctl_4", .id = CTL_4,
> > + .base = 0x19000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG) |
> > + BIT(DPU_CTL_FETCH_ACTIVE) |
> > + BIT(DPU_CTL_VM_CFG) |
> > + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> > + },
> > + {
> > + .name = "ctl_5", .id = CTL_5,
> > + .base = 0x1a000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_ACTIVE_CFG) |
> > + BIT(DPU_CTL_FETCH_ACTIVE) |
> > + BIT(DPU_CTL_VM_CFG) |
> > + BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> > + },
> > +};
> > +
> > static const struct dpu_ctl_cfg sc7280_ctl[] = {
> > {
> > .name = "ctl_0", .id = CTL_0,
> > @@ -1182,6 +1292,27 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
> > PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
> > };
> >
> > +static const struct dpu_pingpong_cfg sm8350_pp[] = {
> > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> > + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> > + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> > + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> > + -1),
> > + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
> > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> > + -1),
> > +};
> > +
> > static struct dpu_pingpong_cfg qcm2290_pp[] = {
> > PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
> > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> > @@ -1205,6 +1336,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
> > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
> > };
> >
> > +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
> > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> > +};
> > +
> > /*************************************************************
> > * DSC sub blocks config
> > *************************************************************/
> > @@ -1222,6 +1359,12 @@ static struct dpu_dsc_cfg sdm845_dsc[] = {
> > DSC_BLK("dsc_3", DSC_3, 0x80c00),
> > };
> >
> > +static struct dpu_dsc_cfg sm8350_dsc[] = {
> > + DSC_BLK("dsc_0", DSC_0, 0x80000),
> > + DSC_BLK("dsc_1", DSC_1, 0x81000),
> > + DSC_BLK("dsc_2", DSC_2, 0x82000),
> > +};
> > +
> > /*************************************************************
> > * INTF sub blocks config
> > *************************************************************/
> > @@ -1269,6 +1412,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> > INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> > };
> >
> > +static const struct dpu_intf_cfg sm8350_intf[] = {
> > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
> > +};
> > +
> > static const struct dpu_intf_cfg sc8180x_intf[] = {
> > INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> > @@ -1397,6 +1547,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
> > .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> > };
> >
> > +static const struct dpu_reg_dma_cfg sm8350_regdma = {
> > + .base = 0x0,
> > + .version = 0x00020000,
> > + .trigger_sel_off = 0x119c,
> > + .xin_id = 7,
> > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
> > +};
> > +
> > /*************************************************************
> > * PERF data config
> > *************************************************************/
> > @@ -1700,6 +1858,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
> > .bw_inefficiency_factor = 120,
> > };
> >
> > +static const struct dpu_perf_cfg sm8350_perf_data = {
> > + .max_bw_low = 11800000,
> > + .max_bw_high = 18200000,
> > + .min_core_ib = 2500000,
> > + .min_llcc_ib = 0,
> > + .min_dram_ib = 800000,
> > + .min_prefill_lines = 40,
> > + /* FIXME: lut tables */
> > + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
> > + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
> > + .qos_lut_tbl = {
> > + {.nentry = ARRAY_SIZE(sc7180_qos_linear),
> > + .entries = sc7180_qos_linear
> > + },
> > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> > + .entries = sc7180_qos_macrotile
> > + },
> > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> > + .entries = sc7180_qos_nrt
> > + },
> > + /* TODO: macrotile-qseed is different from macrotile */
> > + },
> > + .cdp_cfg = {
> > + {.rd_enable = 1, .wr_enable = 1},
> > + {.rd_enable = 1, .wr_enable = 0}
> > + },
> > + .clk_inefficiency_factor = 105,
> > + .bw_inefficiency_factor = 120,
> > +};
> > +
> > static const struct dpu_perf_cfg qcm2290_perf_data = {
> > .max_bw_low = 2700000,
> > .max_bw_high = 2700000,
> > @@ -1876,6 +2064,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
> > .mdss_irqs = IRQ_SM8250_MASK,
> > };
> >
> > +static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
> > + .caps = &sm8350_dpu_caps,
> > + .mdp_count = ARRAY_SIZE(sm8350_mdp),
> > + .mdp = sm8350_mdp,
> > + .ctl_count = ARRAY_SIZE(sm8350_ctl),
> > + .ctl = sm8350_ctl,
> > + .sspp_count = ARRAY_SIZE(sm8250_sspp),
> > + .sspp = sm8250_sspp,
> > + .mixer_count = ARRAY_SIZE(sm8150_lm),
> > + .mixer = sm8150_lm,
> > + .dspp_count = ARRAY_SIZE(sm8150_dspp),
> > + .dspp = sm8150_dspp,
> > + .pingpong_count = ARRAY_SIZE(sm8350_pp),
> > + .pingpong = sm8350_pp,
> > + .dsc_count = ARRAY_SIZE(sm8350_dsc),
> > + .dsc = sm8350_dsc,
> > + .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
> > + .merge_3d = sm8350_merge_3d,
> > + .intf_count = ARRAY_SIZE(sm8350_intf),
> > + .intf = sm8350_intf,
> > + .vbif_count = ARRAY_SIZE(sdm845_vbif),
> > + .vbif = sdm845_vbif,
> > + .reg_dma_count = 1,
> > + .dma_cfg = &sm8250_regdma,
> > + .perf = &sm8350_perf_data,
> > + .mdss_irqs = IRQ_SM8350_MASK,
> > +};
> > +
> > static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
> > .caps = &sc7280_dpu_caps,
> > .mdp_count = ARRAY_SIZE(sc7280_mdp),
> > @@ -1933,6 +2149,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
> > { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
> > { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
> > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
> > + { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
> > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
> > };
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index 71fe4c505f5b..e59630e06110 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -45,6 +45,7 @@
> > #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
> > #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
> > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
> > +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
> > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
> >
> > #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
>
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 6/9] arm64: dts: qcom: sm8350: Use 2 interconnect cells
2022-10-28 13:44 ` Bjorn Andersson
@ 2022-11-11 13:52 ` Robert Foss
0 siblings, 0 replies; 30+ messages in thread
From: Robert Foss @ 2022-11-11 13:52 UTC (permalink / raw)
To: Bjorn Andersson
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
dmitry.baryshkov, freedreno
On Fri, 28 Oct 2022 at 15:44, Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Fri, Oct 28, 2022 at 02:08:09PM +0200, Robert Foss wrote:
> > Use two interconnect cells in order to optionally
> > support a path tag.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++----------
> > 1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > index 606fab087945..b6e44cd3b394 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > @@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 {
> > config_noc: interconnect@1500000 {
> > compatible = "qcom,sm8350-config-noc";
> > reg = <0 0x01500000 0 0xa580>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
>
> You also need amend all the interconnects references with the additional
> tag cell.
Ack
>
> Regards,
> Bjorn
>
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > mc_virt: interconnect@1580000 {
> > compatible = "qcom,sm8350-mc-virt";
> > reg = <0 0x01580000 0 0x1000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > system_noc: interconnect@1680000 {
> > compatible = "qcom,sm8350-system-noc";
> > reg = <0 0x01680000 0 0x1c200>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > aggre1_noc: interconnect@16e0000 {
> > compatible = "qcom,sm8350-aggre1-noc";
> > reg = <0 0x016e0000 0 0x1f180>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > aggre2_noc: interconnect@1700000 {
> > compatible = "qcom,sm8350-aggre2-noc";
> > reg = <0 0x01700000 0 0x33000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > mmss_noc: interconnect@1740000 {
> > compatible = "qcom,sm8350-mmss-noc";
> > reg = <0 0x01740000 0 0x1f080>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > lpass_ag_noc: interconnect@3c40000 {
> > compatible = "qcom,sm8350-lpass-ag-noc";
> > reg = <0 0x03c40000 0 0xf080>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > compute_noc: interconnect@a0c0000{
> > compatible = "qcom,sm8350-compute-noc";
> > reg = <0 0x0a0c0000 0 0xa180>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > @@ -2420,14 +2420,14 @@ usb_2_ssphy: phy@88ebe00 {
> > dc_noc: interconnect@90c0000 {
> > compatible = "qcom,sm8350-dc-noc";
> > reg = <0 0x090c0000 0 0x4200>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > gem_noc: interconnect@9100000 {
> > compatible = "qcom,sm8350-gem-noc";
> > reg = <0 0x09100000 0 0xb4000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes
2022-10-28 22:01 ` Krzysztof Kozlowski
@ 2022-11-11 15:16 ` Robert Foss
0 siblings, 0 replies; 30+ messages in thread
From: Robert Foss @ 2022-11-11 15:16 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
Dmitry Baryshkov, freedreno
On Sat, 29 Oct 2022 at 00:01, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 28/10/2022 08:08, Robert Foss wrote:
> > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
> > nodes the display subsystem is configured to support
> > one DSI output.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++++++++++++++++++++++++++-
> > 1 file changed, 192 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > index b6e44cd3b394..eaa3cdee1860 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > @@ -3,6 +3,7 @@
> > * Copyright (c) 2020, Linaro Limited
> > */
> >
> > +#include <dt-bindings/interconnect/qcom,sm8350.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> > #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> > @@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a800000 {
> > };
> > };
> >
> > + mdss: mdss@ae00000 {
> > + compatible = "qcom,sm8350-mdss";
> > + reg = <0 0x0ae00000 0 0x1000>;
> > + reg-names = "mdss";
> > +
> > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> > + interconnect-names = "mdp0-mem", "mdp1-mem";
> > +
> > + power-domains = <&dispcc MDSS_GDSC>;
> > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > + clock-names = "iface", "bus", "nrt_bus", "core";
> > +
> > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > +
> > + status = "ok";
>
> No need for this.
Ack, I'll switch to disabled.
>
> > +
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + mdss_mdp: mdp@ae01000 {
>
> Node name: display-controller
Ack.
> > + compatible = "qcom,sm8350-dpu";
> > + reg = <0 0x0ae01000 0 0x8f000>,
> > + <0 0x0aeb0000 0 0x2008>;
> > + reg-names = "mdp", "vbif";
> > + iommus = <&apps_smmu 0x820 0x402>;
> > +
> > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + clock-names = "bus",
> > + "nrt_bus",
> > + "iface",
> > + "lut",
> > + "core",
> > + "vsync";
> > +
> > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + assigned-clock-rates = <19200000>;
> > +
> > + operating-points-v2 = <&mdp_opp_table>;
> > + power-domains = <&rpmhpd SM8350_MMCX>;
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <0>;
> > +
> > + status = "ok";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + dpu_intf1_out: endpoint {
> > + remote-endpoint = <&dsi0_in>;
> > + };
> > + };
> > + };
> > +
> > + mdp_opp_table: mdp-opp-table {
>
> I have doubts that it passes dtbs_checks... opp-table
Ack.
>
> > + compatible = "operating-points-v2";
> > +
> > + opp-200000000 {
> > + opp-hz = /bits/ 64 <200000000>;
> > + required-opps = <&rpmhpd_opp_low_svs>;
> > + };
> > +
> > + opp-300000000 {
> > + opp-hz = /bits/ 64 <300000000>;
> > + required-opps = <&rpmhpd_opp_svs>;
> > + };
> > +
> > + opp-345000000 {
> > + opp-hz = /bits/ 64 <345000000>;
> > + required-opps = <&rpmhpd_opp_svs_l1>;
> > + };
> > +
> > + opp-460000000 {
> > + opp-hz = /bits/ 64 <460000000>;
> > + required-opps = <&rpmhpd_opp_nom>;
> > + };
> > + };
> > + };
> > +
> > + dsi0: dsi@ae94000 {
> > + compatible = "qcom,mdss-dsi-ctrl";
> > + reg = <0 0x0ae94000 0 0x400>;
> > + reg-names = "dsi_ctrl";
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <4>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> > + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>;
> > + clock-names = "byte",
> > + "byte_intf",
> > + "pixel",
> > + "core",
> > + "iface",
> > + "bus";
> > +
> > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> > + assigned-clock-parents = <&dsi0_phy 0>,
> > + <&dsi0_phy 1>;
> > +
> > + operating-points-v2 = <&dsi_opp_table>;
> > + power-domains = <&rpmhpd SM8350_MMCX>;
> > +
> > + phys = <&dsi0_phy>;
> > + phy-names = "dsi";
> > +
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + dsi0_in: endpoint {
> > + remote-endpoint = <&dpu_intf1_out>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + dsi0_out: endpoint {
> > + };
> > + };
> > + };
> > + };
> > +
> > + dsi0_phy: dsi-phy@ae94400 {
>
> Just "phy". I think Dmitry was renaming all of these.
Ack.
>
> > + compatible = "qcom,dsi-phy-5nm-8350";
> > + reg = <0 0x0ae94400 0 0x200>,
> > + <0 0x0ae94600 0 0x280>,
> > + <0 0x0ae94900 0 0x260>;
> > + reg-names = "dsi_phy",
> > + "dsi_phy_lane",
> > + "dsi_pll";
> > +
> > + #clock-cells = <1>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "iface", "ref";
> > +
> > + status = "disabled";
> > +
> > + dsi_opp_table: dsi-opp-table {
>
> opp-table
Ack
>
> Run `make dtbs_check`
I had a look after fixing the above and I'm seeing some other issues.
Due to the dts/dt-binding rework that Dmitry is doing, I'll leave some
warnings, which can be addressed once the rework changes have landed.
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
2022-10-28 22:03 ` Krzysztof Kozlowski
@ 2022-11-11 15:17 ` Robert Foss
0 siblings, 0 replies; 30+ messages in thread
From: Robert Foss @ 2022-11-11 15:17 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
dmitry.baryshkov, freedreno
On Sat, 29 Oct 2022 at 00:03, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 28/10/2022 08:08, Robert Foss wrote:
> > Enable the display subsystem and the dsi0 output for
> > the sm8350-hdk board.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > index e6deb08c6da0..6e07feb4b3b2 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > @@ -213,10 +213,32 @@ &cdsp {
> > firmware-name = "qcom/sm8350/cdsp.mbn";
> > };
> >
> > +&dispcc {
> > + status = "okay";
> > +};
> > +
> > +&dsi0 {
> > + status = "okay";
>
> Status is the last property.
Ack.
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-10-28 13:57 ` Bjorn Andersson
@ 2022-11-11 15:18 ` Robert Foss
0 siblings, 0 replies; 30+ messages in thread
From: Robert Foss @ 2022-11-11 15:18 UTC (permalink / raw)
To: Bjorn Andersson
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
dmitry.baryshkov, freedreno
On Fri, 28 Oct 2022 at 15:57, Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Fri, Oct 28, 2022 at 02:08:12PM +0200, Robert Foss wrote:
> > The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
> >
> > In order to toggle the board to enable the HDMI output,
> > switch #7 & #8 on the rightmost multi-switch package have
> > to be toggled to On.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 106 ++++++++++++++++++++++++
> > 1 file changed, 106 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > index 6e07feb4b3b2..6666b38b58f8 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > @@ -20,6 +20,17 @@ chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > + hdmi-out {
> > + compatible = "hdmi-connector";
> > + type = "a";
> > +
> > + port {
> > + hdmi_con: endpoint {
> > + remote-endpoint = <<9611_out>;
> > + };
> > + };
> > + };
> > +
> > vph_pwr: vph-pwr-regulator {
> > compatible = "regulator-fixed";
> > regulator-name = "vph_pwr";
> > @@ -29,6 +40,32 @@ vph_pwr: vph-pwr-regulator {
> > regulator-always-on;
> > regulator-boot-on;
> > };
> > +
> > + lt9611_1v2: lt9611-1v2 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "LT9611_1V2";
> > +
> > + vin-supply = <&vph_pwr>;
> > + regulator-min-microvolt = <1200000>;
> > + regulator-max-microvolt = <1200000>;
> > + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + regulator-boot-on;
> > + regulator-always-on;
>
> Why is this always-on?
It shouldn't be. Removing this in v2.
>
> > + };
> > +
> > + lt9611_3v3: lt9611-3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "LT9611_3V3";
> > +
> > + vin-supply = <&vreg_bob>;
> > + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + enable-active-high;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > };
> >
> > &adsp {
> > @@ -220,6 +257,15 @@ &dispcc {
> > &dsi0 {
> > status = "okay";
> > vdda-supply = <&vreg_l6b_1p2>;
> > +
> > + ports {
> > + port@1 {
> > + endpoint {
> > + remote-endpoint = <<9611_a>;
> > + data-lanes = <0 1 2 3>;
> > + };
> > + };
> > + };
> > };
> >
> > &dsi0_phy {
> > @@ -231,6 +277,48 @@ &gpi_dma1 {
> > status = "okay";
> > };
> >
> > +&i2c15 {
> > + status = "okay";
>
> Please keep status last. (Yes I see that it goes against the convention
> in this file, so let's update that at some point as well)
Ack.
>
> > + clock-frequency = <400000>;
> > +
> > + lt9611_codec: hdmi-bridge@2b {
> > + compatible = "lontium,lt9611uxc";
> > + reg = <0x2b>;
> > + status = "okay";
>
> This is the default, you can omit it.
Ack.
>
> > +
> > + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
> > + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
> > +
> > + vdd-supply = <<9611_1v2>;
> > + vcc-supply = <<9611_3v3>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > +
> > + lt9611_a: endpoint {
> > + remote-endpoint = <&dsi0_out>;
> > + };
> > + };
> > +
> > + port@2 {
> > + reg = <2>;
> > +
> > + lt9611_out: endpoint {
> > + remote-endpoint = <&hdmi_con>;
> > + };
> > + };
> > +
> > + };
> > + };
> > +};
> > +
> > &mdss {
> > status = "okay";
> > };
> > @@ -248,6 +336,10 @@ &qupv3_id_0 {
> > status = "okay";
> > };
> >
> > +&qupv3_id_2 {
> > + status = "okay";
> > +};
> > +
> > &slpi {
> > status = "okay";
> > firmware-name = "qcom/sm8350/slpi.mbn";
> > @@ -544,4 +636,18 @@ usb_hub_enabled_state: usb-hub-enabled-state {
> > drive-strength = <2>;
> > output-low;
> > };
> > +
> > + lt9611_rst_pin: lt9611-rst-state {
> > + pins = "gpio48";
> > + function = "normal";
> > +
> > + output-high;
> > + input-disable;
> > + };
> > +
> > + lt9611_irq_pin: lt9611-irq {
>
> pinctrl state nodes should be suffixed with "-state".
>
> And you can lump the two pins into a single -state, with rst-pins and
> irq-pins as subnodes, defining the two pins.
>
> Regards,
> Bjorn
>
> > + pins = "gpio50";
> > + function = "gpio";
> > + bias-disable;
> > + };
> > };
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
2022-10-28 22:05 ` Krzysztof Kozlowski
@ 2022-11-11 15:20 ` Robert Foss
0 siblings, 0 replies; 30+ messages in thread
From: Robert Foss @ 2022-11-11 15:20 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: airlied, konrad.dybcio, dri-devel, bjorn.andersson,
krzysztof.kozlowski+dt, angelogioacchino.delregno, vinod.koul,
Jonathan Marek, quic_vpolimer, agross, quic_jesszhan, devicetree,
linux-arm-msm, quic_abhinavk, swboyd, robh+dt, sean,
quic_kalyant, loic.poulain, dianders, linux-kernel, vkoul,
dmitry.baryshkov, freedreno
On Sat, 29 Oct 2022 at 00:06, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 28/10/2022 08:08, Robert Foss wrote:
> > The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
> >
> > In order to toggle the board to enable the HDMI output,
> > switch #7 & #8 on the rightmost multi-switch package have
> > to be toggled to On.
> >
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 106 ++++++++++++++++++++++++
> > 1 file changed, 106 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > index 6e07feb4b3b2..6666b38b58f8 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > @@ -20,6 +20,17 @@ chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > + hdmi-out {
>
> Generic node names, so hdmi-connector or just connector.
Ack.
>
> > + compatible = "hdmi-connector";
> > + type = "a";
> > +
> > + port {
> > + hdmi_con: endpoint {
> > + remote-endpoint = <<9611_out>;
> > + };
> > + };
> > + };
> > +
> > vph_pwr: vph-pwr-regulator {
> > compatible = "regulator-fixed";
> > regulator-name = "vph_pwr";
> > @@ -29,6 +40,32 @@ vph_pwr: vph-pwr-regulator {
> > regulator-always-on;
> > regulator-boot-on;
> > };
> > +
> > + lt9611_1v2: lt9611-1v2 {
>
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Ack.
>
> > + compatible = "regulator-fixed";
> > + regulator-name = "LT9611_1V2";
> > +
> > + vin-supply = <&vph_pwr>;
> > + regulator-min-microvolt = <1200000>;
> > + regulator-max-microvolt = <1200000>;
> > + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + lt9611_3v3: lt9611-3v3 {
>
> Ditto
Ack.
>
>
> > + compatible = "regulator-fixed";
> > + regulator-name = "LT9611_3V3";
> > +
> > + vin-supply = <&vreg_bob>;
> > + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + enable-active-high;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > };
> >
> > &adsp {
> > @@ -220,6 +257,15 @@ &dispcc {
> > &dsi0 {
> > status = "okay";
> > vdda-supply = <&vreg_l6b_1p2>;
> > +
> > + ports {
> > + port@1 {
> > + endpoint {
> > + remote-endpoint = <<9611_a>;
> > + data-lanes = <0 1 2 3>;
> > + };
> > + };
> > + };
> > };
> >
> > &dsi0_phy {
> > @@ -231,6 +277,48 @@ &gpi_dma1 {
> > status = "okay";
> > };
> >
> > +&i2c15 {
> > + status = "okay";
>
> status is the last property
Ack.
>
> > + clock-frequency = <400000>;
> > +
> > + lt9611_codec: hdmi-bridge@2b {
> > + compatible = "lontium,lt9611uxc";
> > + reg = <0x2b>;
> > + status = "okay";
>
> Why status?
It should be removed. Fixing in v2.
>
> > +
> > + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
> > + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
> > +
> > + vdd-supply = <<9611_1v2>;
> > + vcc-supply = <<9611_3v3>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > +
> > + lt9611_a: endpoint {
> > + remote-endpoint = <&dsi0_out>;
> > + };
> > + };
> > +
> > + port@2 {
> > + reg = <2>;
> > +
> > + lt9611_out: endpoint {
> > + remote-endpoint = <&hdmi_con>;
> > + };
> > + };
> > +
>
> No need for blank line
Ack
>
> > + };
> > + };
> > +};
> > +
> > &mdss {
> > status = "okay";
> > };
> > @@ -248,6 +336,10 @@ &qupv3_id_0 {
> > status = "okay";
> > };
> >
> > +&qupv3_id_2 {
> > + status = "okay";
> > +};
> > +
> > &slpi {
> > status = "okay";
> > firmware-name = "qcom/sm8350/slpi.mbn";
> > @@ -544,4 +636,18 @@ usb_hub_enabled_state: usb-hub-enabled-state {
> > drive-strength = <2>;
> > output-low;
> > };
> > +
> > + lt9611_rst_pin: lt9611-rst-state {
> > + pins = "gpio48";
> > + function = "normal";
> > +
> > + output-high;
> > + input-disable;
> > + };
> > +
> > + lt9611_irq_pin: lt9611-irq {
>
> Missing suffix 'state'.
Ack.
>
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
v1 was missing the bindings, v2 will include bindings for there parts.
>
> Rebase your changes on last linux-next.
Ack.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2022-11-11 15:20 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-28 12:08 [PATCH v1 0/9] Enable Display for SM8350 Robert Foss
2022-10-28 12:08 ` [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display Robert Foss
2022-10-28 12:13 ` Dmitry Baryshkov
2022-10-28 12:19 ` Dmitry Baryshkov
2022-10-28 12:29 ` Dmitry Baryshkov
2022-10-28 12:08 ` [PATCH v1 2/9] drm/msm/dpu: Refactor sc7280_pp location Robert Foss
2022-10-28 12:14 ` Dmitry Baryshkov
2022-10-28 12:08 ` [PATCH v1 3/9] drm/msm/dpu: Add SM8350 to hw catalog Robert Foss
2022-10-28 12:26 ` Dmitry Baryshkov
2022-11-11 12:39 ` Robert Foss
2022-10-28 12:08 ` [PATCH v1 4/9] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names Robert Foss
2022-10-28 12:08 ` [PATCH v1 5/9] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name Robert Foss
2022-10-28 12:08 ` [PATCH v1 6/9] arm64: dts: qcom: sm8350: Use 2 interconnect cells Robert Foss
2022-10-28 13:44 ` Bjorn Andersson
2022-11-11 13:52 ` Robert Foss
2022-10-28 12:08 ` [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes Robert Foss
2022-10-28 13:50 ` Bjorn Andersson
2022-10-28 22:01 ` Krzysztof Kozlowski
2022-11-11 15:16 ` Robert Foss
2022-10-28 12:08 ` [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Robert Foss
2022-10-28 13:51 ` Bjorn Andersson
2022-10-28 22:03 ` Krzysztof Kozlowski
2022-11-11 15:17 ` Robert Foss
2022-10-28 12:08 ` [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Robert Foss
2022-10-28 13:56 ` Dmitry Baryshkov
2022-11-03 14:19 ` Dmitry Baryshkov
2022-10-28 13:57 ` Bjorn Andersson
2022-11-11 15:18 ` Robert Foss
2022-10-28 22:05 ` Krzysztof Kozlowski
2022-11-11 15:20 ` Robert Foss
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