From: Jason-JH.Lin <jason-jh.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Jeffrey Kardatzke <jkardatzke@google.com>,
devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>,
Project_Global_Chrome_Upstream_Group@mediatek.com,
"Jason-JH . Lin" <jason-jh.lin@mediatek.com>,
Singo Chang <singo.chang@mediatek.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linaro-mm-sig@lists.linaro.org,
Jason-ch Chen <jason-ch.chen@mediatek.com>,
Nancy Lin <nancy.lin@mediatek.com>,
linux-mediatek@lists.infradead.org,
Shawn Sung <shawn.sung@mediatek.com>,
Johnson Wang <johnson.wang@mediatek.com>,
linux-arm-kernel@lists.infradead.org,
linux-media@vger.kernel.org
Subject: [PATCH v2 07/11] drm/mediatek: Add secure layer config support for ovl
Date: Mon, 23 Oct 2023 12:45:44 +0800 [thread overview]
Message-ID: <20231023044549.21412-8-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20231023044549.21412-1-jason-jh.lin@mediatek.com>
Add secure layer config support for ovl.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 ++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 31 +++++++++++++++++--
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 12 +++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
4 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2254038519e1..dec937b183a8 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -9,6 +9,7 @@
#include <linux/soc/mediatek/mtk-cmdq.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include "mtk_drm_ddp_comp.h"
#include "mtk_drm_plane.h"
#include "mtk_mdp_rdma.h"
@@ -79,6 +80,7 @@ void mtk_ovl_clk_disable(struct device *dev);
void mtk_ovl_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+u64 mtk_ovl_get_sec_port(struct mtk_ddp_comp *comp, unsigned int idx);
int mtk_ovl_layer_check(struct device *dev, unsigned int idx,
struct mtk_plane_state *mtk_state);
void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
@@ -112,6 +114,7 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev);
void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+u64 mtk_ovl_adaptor_get_sec_port(struct mtk_ddp_comp *comp, unsigned int idx);
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
struct mtk_plane_state *state,
struct cmdq_pkt *cmdq_pkt);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 2bffe4245466..76e832e4875a 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -46,6 +46,7 @@
#define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
#define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04)
#define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08)
+#define DISP_REG_OVL_SECURE 0x0fc0
#define GMC_THRESHOLD_BITS 16
#define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
@@ -126,8 +127,19 @@ struct mtk_disp_ovl {
const struct mtk_disp_ovl_data *data;
void (*vblank_cb)(void *data);
void *vblank_cb_data;
+ resource_size_t regs_pa;
};
+u64 mtk_ovl_get_sec_port(struct mtk_ddp_comp *comp, unsigned int idx)
+{
+ if (comp->id == DDP_COMPONENT_OVL0)
+ return 1ULL << CMDQ_SEC_DISP_OVL0;
+ else if (comp->id == DDP_COMPONENT_OVL1)
+ return 1ULL << CMDQ_SEC_DISP_OVL1;
+
+ return 0;
+}
+
static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
{
struct mtk_disp_ovl *priv = dev_id;
@@ -449,8 +461,22 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
DISP_REG_OVL_SRC_SIZE(idx));
mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_OFFSET(idx));
- mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
- DISP_REG_OVL_ADDR(ovl, idx));
+
+ if (state->pending.is_sec) {
+ const struct drm_format_info *fmt_info = drm_format_info(fmt);
+ unsigned int buf_size = (pending->height - 1) * pending->pitch +
+ pending->width * fmt_info->cpp[0];
+
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
+ DISP_REG_OVL_SECURE, BIT(idx));
+ mtk_ddp_sec_write(cmdq_pkt, ovl->regs_pa + DISP_REG_OVL_ADDR(ovl, idx),
+ pending->addr, CMDQ_IWC_H_2_MVA, 0, buf_size, 0);
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
+ DISP_REG_OVL_SECURE, BIT(idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
+ DISP_REG_OVL_ADDR(ovl, idx));
+ }
if (is_afbc) {
mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,
@@ -529,6 +555,7 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs_pa = res->start;
priv->regs = devm_ioremap_resource(dev, res);
if (IS_ERR(priv->regs)) {
dev_err(dev, "failed to ioremap ovl\n");
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index 6bf6367853fb..28a0bccfb0b9 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -83,6 +83,18 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
[OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
};
+static const u64 ovl_adaptor_sec_port[] = {
+ 1ULL << CMDQ_SEC_VDO1_DISP_RDMA_L0,
+ 1ULL << CMDQ_SEC_VDO1_DISP_RDMA_L1,
+ 1ULL << CMDQ_SEC_VDO1_DISP_RDMA_L2,
+ 1ULL << CMDQ_SEC_VDO1_DISP_RDMA_L3,
+};
+
+u64 mtk_ovl_adaptor_get_sec_port(struct mtk_ddp_comp *comp, unsigned int idx)
+{
+ return ovl_adaptor_sec_port[idx];
+}
+
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
struct mtk_plane_state *state,
struct cmdq_pkt *cmdq_pkt)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 3dca936b9143..eec3a1cc2ed4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -373,6 +373,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
.bgclr_in_off = mtk_ovl_bgclr_in_off,
.get_formats = mtk_ovl_get_formats,
.get_num_formats = mtk_ovl_get_num_formats,
+ .get_sec_port = mtk_ovl_get_sec_port,
};
static const struct mtk_ddp_comp_funcs ddp_postmask = {
@@ -424,6 +425,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
.remove = mtk_ovl_adaptor_remove_comp,
.get_formats = mtk_ovl_adaptor_get_formats,
.get_num_formats = mtk_ovl_adaptor_get_num_formats,
+ .get_sec_port = mtk_ovl_adaptor_get_sec_port,
};
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
--
2.18.0
next prev parent reply other threads:[~2023-10-23 4:46 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 4:45 [PATCH v2 00/11] Add mediate-drm secure flow for SVP Jason-JH.Lin
2023-10-23 4:45 ` [PATCH v2 01/11] drm/mediatek: Add interface to allocate MediaTek GEM buffer Jason-JH.Lin
2023-10-24 8:37 ` AngeloGioacchino Del Regno
2023-10-25 7:47 ` Jason-JH Lin (林睿祥)
2023-10-23 4:45 ` [PATCH v2 02/11] drm/mediatek/uapi: Add DRM_MTK_GEM_CREATED_ENCRYPTTED flag Jason-JH.Lin
2023-10-24 8:37 ` AngeloGioacchino Del Regno
2023-10-25 7:51 ` Jason-JH Lin (林睿祥)
2023-10-23 4:45 ` [PATCH v2 03/11] drm/mediatek: Add secure buffer control flow to mtk_drm_gem Jason-JH.Lin
2023-10-24 8:37 ` AngeloGioacchino Del Regno
2023-10-25 7:50 ` Jason-JH Lin (林睿祥)
2023-10-23 4:45 ` [PATCH v2 04/11] drm/mediatek: Add secure identify flag and funcution to mtk_drm_plane Jason-JH.Lin
2023-10-24 3:35 ` CK Hu (胡俊光)
2023-10-25 6:39 ` Jason-JH Lin (林睿祥)
2023-10-23 4:45 ` [PATCH v2 05/11] drm/mediatek: Add mtk_ddp_sec_write to config secure buffer info Jason-JH.Lin
2023-10-24 8:37 ` AngeloGioacchino Del Regno
2023-10-25 7:53 ` Jason-JH Lin (林睿祥)
2023-10-23 4:45 ` [PATCH v2 06/11] drm/mediatek: Add get_sec_port interface to mtk_ddp_comp Jason-JH.Lin
2023-10-23 4:45 ` Jason-JH.Lin [this message]
2023-10-24 8:37 ` [PATCH v2 07/11] drm/mediatek: Add secure layer config support for ovl AngeloGioacchino Del Regno
2023-10-25 7:57 ` Jason-JH Lin (林睿祥)
2023-10-25 3:08 ` CK Hu (胡俊光)
2023-10-25 8:01 ` Jason-JH Lin (林睿祥)
2023-10-26 10:07 ` CK Hu (胡俊光)
2023-11-05 13:18 ` Jason-JH Lin (林睿祥)
2023-11-06 1:33 ` CK Hu (胡俊光)
2023-11-06 2:51 ` Jason-JH Lin (林睿祥)
2023-10-23 4:45 ` [PATCH v2 08/11] drm/mediatek: Add secure layer config support for ovl_adaptor Jason-JH.Lin
2023-10-24 8:37 ` AngeloGioacchino Del Regno
2023-10-25 8:03 ` Jason-JH Lin (林睿祥)
2023-10-23 4:45 ` [PATCH v2 09/11] drm/mediatek: Add secure flow support to mediatek-drm Jason-JH.Lin
2023-10-24 7:42 ` CK Hu (胡俊光)
2023-10-25 8:31 ` Jason-JH Lin (林睿祥)
2023-10-31 6:01 ` CK Hu (胡俊光)
2023-11-05 13:04 ` Jason-JH Lin (林睿祥)
2023-11-06 1:27 ` CK Hu (胡俊光)
2023-11-06 2:59 ` Jason-JH Lin (林睿祥)
2023-11-06 3:11 ` CK Hu (胡俊光)
2023-11-06 5:48 ` Jason-JH Lin (林睿祥)
2023-10-23 4:45 ` [PATCH v2 10/11] drm/mediatek: Add cmdq_insert_backup_cookie before secure pkt finalize Jason-JH.Lin
2023-10-26 2:26 ` CK Hu (胡俊光)
2023-11-05 13:35 ` Jason-JH Lin (林睿祥)
2023-11-06 1:36 ` CK Hu (胡俊光)
2023-11-06 1:59 ` Jason-JH Lin (林睿祥)
2023-10-23 4:45 ` [PATCH v2 11/11] arm64: dts: mt8195: Add secure mbox settings for vdosys Jason-JH.Lin
2023-10-31 2:12 ` [PATCH v2 00/11] Add mediate-drm secure flow for SVP CK Hu (胡俊光)
2023-11-05 13:44 ` Jason-JH Lin (林睿祥)
2023-11-06 1:37 ` CK Hu (胡俊光)
2023-11-06 2:00 ` Jason-JH Lin (林睿祥)
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