* [PATCH 0/6] Enable Adaptive Sync SDP Support for DP
@ 2024-02-22 12:12 Mitul Golani
2024-02-22 12:12 ` [PATCH 1/6] drm/dp: Add an support to indicate if sink supports AS SDP Mitul Golani
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Mitul Golani @ 2024-02-22 12:12 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, ankit.k.nautiyal, Mitul Golani
An Adaptive Sync SDP allows a DP protocol converter to
forward Adaptive Sync video with minimal buffering overhead
within the converter. An Adaptive-Sync-capable DP protocol
converter indicates its support by setting the related bit
in the DPCD register.
Computes AS SDP values based on the display configuration,
ensuring proper handling of Variable Refresh Rate (VRR)
in the context of Adaptive Sync.
--v2:
- Update logging to Patch-1
- use as_sdp instead of async
- Put definitions to correct placeholders from where it is defined.
- Update member types of as_sdp for uniformity.
- Correct use of REG_BIT and REG_GENMASK.
- Remove unrelated comments and changes.
- Correct code indents.
- separate out patch changes for intel_read/write_dp_sdp.
--v3:
- Add VIDEO_DIP_ASYNC_DATA_SIZE definition and comment in as_sdp_pack
function to patch 2 as originally used there. [Patch 2].
- Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes [Patch 3].
--v4:
- Add check for HAS_VRR before writing AS SDP. [Patch 3].
--v5:
- Add missing check for HAS_VRR before reading AS SDP as well [Patch 3].
--v6:
- Rebase all patches.
- Compute TRANS_VRR_VSYNC.
-v7:
- Move vrr_vsync_start/end to compute config.
- Use correct function for drm_debug_printer.
-v8:
- Code refactoring.
- Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
- Update bit fields of VRR_VSYNC_START/END.(Ankit)
- Send patches to dri-devel.(Ankit)
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
- Remove unused bitfield define, AS_SDP_ENABLE.
- Add support in drm for Adaptive Sync sink status, which can be
used later as a check for read/write sdp. (Ankit)
-v9:
- Add enum to operation mode to represent different AVT and
FAVT modes. (Ankit)
- Operation_mode, target_rr etc should be filled from as_sdp struct. (Ankit)
- Fill as_sdp->*All Params* from compute config, read from the sdp. (Ankit)
- Move configs to the appropriate patch where it used first.(Ankit)
- There should be a check if as sdp is enable is set or not. (Ankit)
- Add variables in crtc state->vrr for ad sdp enable and operation mode. (Ankit)
- Use above variables for tracking AS SDP. (Ankit)
- Revert unused changes. (Ankit)
-v10:
- Send Patches to dri-devel (Ankit).
Mitul Golani (6):
drm/dp: Add an support to indicate if sink supports AS SDP
drm: Add Adaptive Sync SDP logging
drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
drm/i915/display: Compute AS SDP parameters.
drm/i915/display: Compute vrr_vsync params
drm/i915/display: Read/Write AS sdp only when sink/source has enabled
drivers/gpu/drm/display/drm_dp_helper.c | 37 ++++++
.../drm/i915/display/intel_crtc_state_dump.c | 12 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_dp.c | 122 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 12 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 23 ++++
drivers/gpu/drm/i915/i915_reg.h | 15 +++
include/drm/display/drm_dp.h | 9 ++
include/drm/display/drm_dp_helper.h | 34 +++++
12 files changed, 271 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/6] drm/dp: Add an support to indicate if sink supports AS SDP
2024-02-22 12:12 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
@ 2024-02-22 12:12 ` Mitul Golani
2024-02-22 12:12 ` [PATCH 2/6] drm: Add Adaptive Sync SDP logging Mitul Golani
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2024-02-22 12:12 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, ankit.k.nautiyal, Mitul Golani
Add an API which indicates the sink support Adaptive Sync SDP,
which can be used by the rest of the DP programming.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 25 +++++++++++++++++++++++++
include/drm/display/drm_dp_helper.h | 2 ++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 8d6ce46471ae..81c5507928f5 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2913,6 +2913,31 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc)
}
EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
+/**
+ * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
+ * @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
+ *
+ * Returns true if adaptive sync sdp is supported, else returns false
+ */
+bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ u8 rx_feature;
+
+ if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
+ return false;
+
+ if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
+ &rx_feature) != 1) {
+ drm_dbg_dp(aux->drm_dev,
+ "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
+ return false;
+ }
+
+ return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED);
+}
+EXPORT_SYMBOL(drm_dp_as_sdp_supported);
+
/**
* drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
* @dpcd: DisplayPort configuration data
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index d02014a87f12..a0356721de0f 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -100,6 +100,8 @@ struct drm_dp_vsc_sdp {
void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);
+bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/6] drm: Add Adaptive Sync SDP logging
2024-02-22 12:12 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
2024-02-22 12:12 ` [PATCH 1/6] drm/dp: Add an support to indicate if sink supports AS SDP Mitul Golani
@ 2024-02-22 12:12 ` Mitul Golani
2024-02-22 12:12 ` [PATCH 3/6] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP Mitul Golani
` (3 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2024-02-22 12:12 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, ankit.k.nautiyal, Mitul Golani
Add structure representing Adaptive Sync Secondary Data
Packet (AS SDP). Also, add Adaptive Sync SDP logging in
drm_dp_helper.c to facilitate debugging.
--v2:
- Update logging. [Jani, Ankit]
- use as_sdp instead of async [Ankit]
- Correct define placeholders to where it is being actually used. [Jani]
- Update members in as_sdp structure and make it uniform. [Jani]
--v3:
- Add changes dri-devel mail list. No code changes.
--v4:
- Instead of directly using operation mode, use enum to accommodate
all operation modes (Ankit).
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 12 +++++++
.../drm/i915/display/intel_crtc_state_dump.c | 12 +++++++
.../drm/i915/display/intel_display_types.h | 1 +
include/drm/display/drm_dp.h | 9 ++++++
include/drm/display/drm_dp_helper.h | 32 +++++++++++++++++++
5 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 81c5507928f5..a5804c9c245d 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2913,6 +2913,18 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc)
}
EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
+void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp)
+{
+ drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
+ as_sdp->revision, as_sdp->length);
+ drm_printf(p, " vtotal: %d\n", as_sdp->vtotal);
+ drm_printf(p, " target_rr: %d\n", as_sdp->target_rr);
+ drm_printf(p, " duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
+ drm_printf(p, " duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
+ drm_printf(p, " operation_mode: %d\n", as_sdp->mode);
+}
+EXPORT_SYMBOL(drm_dp_as_sdp_log);
+
/**
* drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
* @aux: DisplayPort AUX channel
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4bcf446c75f4..26d77c2934e8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -60,6 +60,15 @@ intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
drm_dp_vsc_sdp_log(&p, vsc);
}
+static void
+intel_dump_dp_as_sdp(struct drm_i915_private *i915,
+ const struct drm_dp_as_sdp *as_sdp)
+{
+ struct drm_printer p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, "AS_SDP");
+
+ drm_dp_as_sdp_log(&p, as_sdp);
+}
+
static void
intel_dump_buffer(struct drm_i915_private *i915,
const char *prefix, const u8 *buf, size_t len)
@@ -299,6 +308,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+ intel_dump_dp_as_sdp(i915, &pipe_config->infoframes.as_sdp);
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(DP_SDP_VSC))
intel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0d4012097db1..a6991bc3f07b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1332,6 +1332,7 @@ struct intel_crtc_state {
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
struct drm_dp_vsc_sdp vsc;
+ struct drm_dp_as_sdp as_sdp;
} infoframes;
u8 eld[MAX_ELD_BYTES];
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 281afff6ee4e..537d6b7148af 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1578,10 +1578,12 @@ enum drm_dp_phy {
#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
#define DP_SDP_ISRC 0x06 /* DP 1.2 */
#define DP_SDP_VSC 0x07 /* DP 1.2 */
+#define DP_SDP_ADAPTIVE_SYNC 0x22 /* DP 1.4 */
#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
#define DP_SDP_PPS 0x10 /* DP 1.4 */
#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
+
/* 0x80+ CEA-861 infoframe types */
#define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
@@ -1737,4 +1739,11 @@ enum dp_content_type {
DP_CONTENT_TYPE_GAME = 0x04,
};
+enum operation_mode {
+ DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
+ DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
+ DP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02,
+ DP_AS_SDP_FAVT_TRR_REACHED = 0x03
+};
+
#endif /* _DRM_DP_H_ */
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index a0356721de0f..bd6205776272 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -98,6 +98,36 @@ struct drm_dp_vsc_sdp {
enum dp_content_type content_type;
};
+/**
+ * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP
+ *
+ * This structure represents a DP AS SDP of drm
+ * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and
+ * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]
+ *
+ * @sdp_type: secondary-data packet type
+ * @length: number of valid data bytes
+ * @vmin: minimum vtotal
+ * @vmax: maximum vtotal
+ * @duration_incr_ms: Successive frame duration increase
+ * @duration_decr_ms: Successive frame duration decrease
+ * @operation_mode: Adaptive Sync Operation Mode
+ */
+
+struct drm_dp_as_sdp {
+ unsigned char sdp_type;
+ unsigned char revision;
+ unsigned char length;
+ int vtotal;
+ int target_rr;
+ int duration_incr_ms;
+ int duration_decr_ms;
+ enum operation_mode mode;
+};
+
+void drm_dp_as_sdp_log(struct drm_printer *p,
+ const struct drm_dp_as_sdp *as_sdp);
+
void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);
bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
@@ -809,6 +839,8 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
+#define AS_SDP_OP_MODE GENMASK(1, 0)
+
int drm_dp_bw_overhead(int lane_count, int hactive,
int dsc_slice_count,
int bpp_x16, unsigned long flags);
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/6] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
2024-02-22 12:12 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
2024-02-22 12:12 ` [PATCH 1/6] drm/dp: Add an support to indicate if sink supports AS SDP Mitul Golani
2024-02-22 12:12 ` [PATCH 2/6] drm: Add Adaptive Sync SDP logging Mitul Golani
@ 2024-02-22 12:12 ` Mitul Golani
2024-02-26 9:43 ` Nautiyal, Ankit K
2024-02-22 12:12 ` [PATCH 4/6] drm/i915/display: Compute AS SDP parameters Mitul Golani
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Mitul Golani @ 2024-02-22 12:12 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, ankit.k.nautiyal, Mitul Golani
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 89 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++-
drivers/gpu/drm/i915/display/intel_vrr.c | 5 ++
drivers/gpu/drm/i915/i915_reg.h | 8 ++
5 files changed, 111 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a6991bc3f07b..2accfe41160d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1414,6 +1414,7 @@ struct intel_crtc_state {
bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
+ u8 as_sdp_mode;
} vrr;
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 217196196e50..b370e1da4735 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -95,7 +95,6 @@
#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
-
/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
@@ -4089,6 +4088,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
return false;
}
+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
+ struct dp_sdp *sdp, size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ /* Prepare AS (Adaptive Sync) SDP Header */
+ sdp->sdp_header.HB0 = 0;
+ sdp->sdp_header.HB1 = as_sdp->sdp_type;
+ sdp->sdp_header.HB2 = 0x02;
+ sdp->sdp_header.HB3 = as_sdp->length;
+
+ /* Fill AS (Adaptive Sync) SDP Payload */
+ sdp->db[0] = as_sdp->mode;
+ sdp->db[1] = as_sdp->vtotal & 0xFF;
+ sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
+ sdp->db[3] = as_sdp->target_rr;
+ sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
+
+ return length;
+}
+
static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
struct dp_sdp *sdp, size_t size)
{
@@ -4256,6 +4281,10 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
&crtc_state->infoframes.drm.drm,
&sdp, sizeof(sdp));
break;
+ case DP_SDP_ADAPTIVE_SYNC:
+ len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
+ sizeof(sdp));
+ break;
default:
MISSING_CASE(type);
return;
@@ -4276,7 +4305,8 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
- VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+ VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
+ VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
@@ -4298,6 +4328,36 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static
+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(as_sdp, 0, sizeof(*as_sdp));
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB2 != 0x02)
+ return -EINVAL;
+
+ if ((sdp->sdp_header.HB3 & 0x3F) != 9)
+ return -EINVAL;
+
+ as_sdp->mode = sdp->db[0] & AS_SDP_OP_MODE;
+ as_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1];
+ as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+
+ return 0;
+}
+
static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
const void *buffer, size_t size)
{
@@ -4368,6 +4428,27 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
return 0;
}
+static int
+intel_read_dp_metadata_infoframe_as_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct drm_dp_as_sdp *as_sdp)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ unsigned int type = DP_SDP_ADAPTIVE_SYNC;
+ struct dp_sdp sdp = {};
+ int ret;
+
+ dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
+ sizeof(sdp));
+
+ ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");
+
+ return ret;
+}
+
static int
intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
const void *buffer, size_t size)
@@ -4474,6 +4555,10 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
&crtc_state->infoframes.drm.drm);
break;
+ case DP_SDP_ADAPTIVE_SYNC:
+ intel_read_dp_metadata_infoframe_as_sdp(encoder, crtc_state,
+ &crtc_state->infoframes.as_sdp);
+ break;
default:
MISSING_CASE(type);
break;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7020e5806109..69e0876f43aa 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -137,6 +137,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return VIDEO_DIP_ENABLE_GMP_HSW;
case DP_SDP_VSC:
return VIDEO_DIP_ENABLE_VSC_HSW;
+ case DP_SDP_ADAPTIVE_SYNC:
+ return VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
case DP_SDP_PPS:
return VDIP_ENABLE_PPS;
case HDMI_INFOFRAME_TYPE_AVI:
@@ -164,6 +166,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
case DP_SDP_VSC:
return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
+ case DP_SDP_ADAPTIVE_SYNC:
+ return TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i);
case DP_SDP_PPS:
return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_AVI:
@@ -186,6 +190,8 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
switch (type) {
case DP_SDP_VSC:
return VIDEO_DIP_VSC_DATA_SIZE;
+ case DP_SDP_ADAPTIVE_SYNC:
+ return VIDEO_DIP_ASYNC_DATA_SIZE;
case DP_SDP_PPS:
return VIDEO_DIP_PPS_DATA_SIZE;
case HDMI_PACKET_TYPE_GAMUT_METADATA:
@@ -558,7 +564,8 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
- VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+ VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+ VIDEO_DIP_ENABLE_ADAPTIVE_SYNC);
if (DISPLAY_VER(dev_priv) >= 10)
mask |= VIDEO_DIP_ENABLE_DRM_GLK;
@@ -570,6 +577,7 @@ static const u8 infoframe_type_to_idx[] = {
HDMI_PACKET_TYPE_GENERAL_CONTROL,
HDMI_PACKET_TYPE_GAMUT_METADATA,
DP_SDP_VSC,
+ DP_SDP_ADAPTIVE_SYNC,
HDMI_INFOFRAME_TYPE_AVI,
HDMI_INFOFRAME_TYPE_SPD,
HDMI_INFOFRAME_TYPE_VENDOR,
@@ -1212,7 +1220,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
- VIDEO_DIP_ENABLE_DRM_GLK);
+ VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_ADAPTIVE_SYNC);
if (!enable) {
intel_de_write(dev_priv, reg, val);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..d2ab7e571e62 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -113,6 +113,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
const struct drm_display_info *info = &connector->base.display_info;
int vmin, vmax;
@@ -165,6 +166,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
if (crtc_state->uapi.vrr_enabled) {
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+ if (drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd))
+ crtc_state->vrr.as_sdp_mode =
+ DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e00557e1a57f..c02ea07af4c2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2312,6 +2312,7 @@
* (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
+#define VIDEO_DIP_ASYNC_DATA_SIZE 36
#define VIDEO_DIP_GMP_DATA_SIZE 36
#define VIDEO_DIP_VSC_DATA_SIZE 36
#define VIDEO_DIP_PPS_DATA_SIZE 132
@@ -2350,6 +2351,8 @@
#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
+/* ADL and later: */
+#define VIDEO_DIP_ENABLE_ADAPTIVE_SYNC REG_BIT(23)
/* Panel fitting */
#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
@@ -5040,6 +5043,7 @@
#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
+#define _VIDEO_DIP_AS_SDP_DATA_A 0x60484
#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
@@ -5054,6 +5058,7 @@
#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
+#define _VIDEO_DIP_AS_SDP_DATA_B 0x61484
#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
@@ -5083,6 +5088,9 @@
#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
+/*ADLP and later: */
+#define TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(trans,\
+ _VIDEO_DIP_AS_SDP_DATA_A + (i) * 4)
#define _HSW_STEREO_3D_CTL_A 0x70020
#define S3D_ENABLE (1 << 31)
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/6] drm/i915/display: Compute AS SDP parameters.
2024-02-22 12:12 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
` (2 preceding siblings ...)
2024-02-22 12:12 ` [PATCH 3/6] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP Mitul Golani
@ 2024-02-22 12:12 ` Mitul Golani
2024-02-26 9:55 ` Nautiyal, Ankit K
2024-02-22 12:12 ` [PATCH 5/6] drm/i915/display: Compute vrr_vsync params Mitul Golani
2024-02-22 12:12 ` [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled Mitul Golani
5 siblings, 1 reply; 13+ messages in thread
From: Mitul Golani @ 2024-02-22 12:12 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, ankit.k.nautiyal, Mitul Golani
Add necessary functions definitions to enable
and compute AS SDP data. The new `intel_dp_compute_as_sdp`
function computes AS SDP values based on the display
configuration, ensuring proper handling of Variable Refresh
Rate (VRR).
--v2:
- Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit]
- separate patch for intel_read/write_dp_sdp [Ankit].
- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit]
- To fix indentation [Ankit]
--v3:
- Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.
--v4:
- Add HAS_VRR check before write as sdp.
--v5:
- Add missed HAS_VRR check before read as sdp.
--v6:
Use Adaptive Sync sink status, which can be
used as a check for read/write sdp. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++-
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2accfe41160d..93b4b7dff1d0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1415,6 +1415,7 @@ struct intel_crtc_state {
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
u8 as_sdp_mode;
+ bool as_sdp_enable;
} vrr;
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b370e1da4735..5c1e2301dd52 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2617,6 +2617,33 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
}
+static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
+ struct intel_connector *connector = intel_dp->attached_connector;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ int vrefresh = drm_mode_vrefresh(adjusted_mode);
+
+ if (!intel_vrr_is_in_range(connector, vrefresh) || !crtc_state->vrr.as_sdp_enable)
+ return;
+
+ as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+ as_sdp->length = 0x9;
+ as_sdp->mode = crtc_state->vrr.as_sdp_mode;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+
+ if (as_sdp->mode == DP_AS_SDP_AVT_FIXED_VTOTAL) {
+ as_sdp->target_rr = 0;
+ as_sdp->duration_incr_ms = 0;
+ as_sdp->duration_incr_ms = 0;
+ }
+
+ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
+}
+
static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
@@ -2942,6 +2969,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
g4x_dp_set_clock(encoder, pipe_config);
intel_vrr_compute_config(pipe_config, conn_state);
+ intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d2ab7e571e62..08e3ba69bd30 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -167,9 +167,11 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
- if (drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd))
+ if (drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd)) {
+ crtc_state->vrr.as_sdp_enable = true;
crtc_state->vrr.as_sdp_mode =
DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
+ }
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/6] drm/i915/display: Compute vrr_vsync params
2024-02-22 12:12 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
` (3 preceding siblings ...)
2024-02-22 12:12 ` [PATCH 4/6] drm/i915/display: Compute AS SDP parameters Mitul Golani
@ 2024-02-22 12:12 ` Mitul Golani
2024-02-26 10:03 ` Nautiyal, Ankit K
2024-02-22 12:12 ` [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled Mitul Golani
5 siblings, 1 reply; 13+ messages in thread
From: Mitul Golani @ 2024-02-22 12:12 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, ankit.k.nautiyal, Mitul Golani
Compute vrr_vsync_start/end which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
- Update bit fields of VRR_VSYNC_START/END.(Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 12 ++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 00ac65a14029..5994f7fcbb6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5321,6 +5321,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+ PIPE_CONF_CHECK_BOOL(vrr.as_sdp_enable);
}
#undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 93b4b7dff1d0..7859e4baad4b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1416,6 +1416,7 @@ struct intel_crtc_state {
u16 flipline, vmin, vmax, guardband;
u8 as_sdp_mode;
bool as_sdp_enable;
+ u32 vsync_end, vsync_start;
} vrr;
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 08e3ba69bd30..29ddf504d94b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -150,6 +150,13 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
+ crtc_state->vrr.vsync_start =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+ VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start));
+ crtc_state->vrr.vsync_end =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+ (VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16));
+
/*
* For XE_LPD+, we use guardband and pipeline override
* is deprecated.
@@ -273,8 +280,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
u32 trans_vrr_ctl;
trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
+ bool as_sdp_enabled =
+ intel_de_read(dev_priv,
+ HSW_TVIDEO_DIP_CTL(cpu_transcoder));
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ crtc_state->vrr.as_sdp_enable =
+ as_sdp_enabled & VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
if (DISPLAY_VER(dev_priv) >= 13)
crtc_state->vrr.guardband =
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c02ea07af4c2..3e0853458ef4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2007,7 +2007,9 @@
#define _TRANS_VRR_CTL_B 0x61420
#define _TRANS_VRR_CTL_C 0x62420
#define _TRANS_VRR_CTL_D 0x63420
+#define _TRANS_VRR_VSYNC_A 0x60078
#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
+#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A)
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
@@ -2087,6 +2089,11 @@
#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
+#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
+#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
+#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
+#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
+
#define _TRANS_PUSH_A 0x60A70
#define _TRANS_PUSH_B 0x61A70
#define _TRANS_PUSH_C 0x62A70
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled
2024-02-22 12:12 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
` (4 preceding siblings ...)
2024-02-22 12:12 ` [PATCH 5/6] drm/i915/display: Compute vrr_vsync params Mitul Golani
@ 2024-02-22 12:12 ` Mitul Golani
5 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2024-02-22 12:12 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, ankit.k.nautiyal, Mitul Golani
Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++++
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++++
drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++
4 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..a1f46e4a8fa1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
/* XXX: DSI transcoder paranoia */
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
@@ -3972,6 +3973,10 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
+ if (HAS_AS_SDP(dev_priv) &&
+ drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd))
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+
intel_audio_codec_get_config(encoder, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..6399fbc6c738 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
+#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5c1e2301dd52..706878a361e7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4336,6 +4336,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
if (!enable && HAS_DSC(dev_priv))
@@ -4353,6 +4354,10 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+ if (HAS_AS_SDP(dev_priv) &&
+ drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd))
+ intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
+
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 29ddf504d94b..f4bf0518a816 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -217,6 +217,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
+
+ if (crtc_state->vrr.as_sdp_enable)
+ intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+ crtc_state->vrr.vsync_end << 16 | crtc_state->vrr.vsync_start);
}
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 3/6] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
2024-02-22 12:12 ` [PATCH 3/6] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP Mitul Golani
@ 2024-02-26 9:43 ` Nautiyal, Ankit K
0 siblings, 0 replies; 13+ messages in thread
From: Nautiyal, Ankit K @ 2024-02-26 9:43 UTC (permalink / raw)
To: Mitul Golani, intel-gfx; +Cc: dri-devel
On 2/22/2024 5:42 PM, Mitul Golani wrote:
> Add the necessary structures and functions to handle reading and
> unpacking Adaptive Sync Secondary Data Packets. Also add support
> to write and pack AS SDP.
>
> --v2:
> - Correct use of REG_BIT and REG_GENMASK. [Jani]
> - Use as_sdp instead of async. [Jani]
> - Remove unrelated comments and changes. [Jani]
> - Correct code indent. [Jani]
>
> --v3:
> - Update definition names for AS SDP which are starting from
> HSW, as these defines are applicable for ADLP+.(Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 89 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++-
> drivers/gpu/drm/i915/display/intel_vrr.c | 5 ++
> drivers/gpu/drm/i915/i915_reg.h | 8 ++
> 5 files changed, 111 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index a6991bc3f07b..2accfe41160d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1414,6 +1414,7 @@ struct intel_crtc_state {
> bool enable, in_range;
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> + u8 as_sdp_mode;
I think this is DP specific, lets not add this thing here.
> } vrr;
>
> /* Stream Splitter for eDP MSO */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 217196196e50..b370e1da4735 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -95,7 +95,6 @@
> #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
> #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
>
> -
> /* Constants for DP DSC configurations */
> static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
>
> @@ -4089,6 +4088,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
> return false;
> }
>
> +static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
> + struct dp_sdp *sdp, size_t size)
> +{
> + size_t length = sizeof(struct dp_sdp);
> +
> + if (size < length)
> + return -ENOSPC;
> +
> + memset(sdp, 0, size);
> +
> + /* Prepare AS (Adaptive Sync) SDP Header */
> + sdp->sdp_header.HB0 = 0;
> + sdp->sdp_header.HB1 = as_sdp->sdp_type;
> + sdp->sdp_header.HB2 = 0x02;
> + sdp->sdp_header.HB3 = as_sdp->length;
> +
> + /* Fill AS (Adaptive Sync) SDP Payload */
> + sdp->db[0] = as_sdp->mode;
> + sdp->db[1] = as_sdp->vtotal & 0xFF;
> + sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
> + sdp->db[3] = as_sdp->target_rr;
> + sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
> +
> + return length;
> +}
> +
> static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
> struct dp_sdp *sdp, size_t size)
> {
> @@ -4256,6 +4281,10 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
> &crtc_state->infoframes.drm.drm,
> &sdp, sizeof(sdp));
> break;
> + case DP_SDP_ADAPTIVE_SYNC:
> + len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
> + sizeof(sdp));
> + break;
> default:
> MISSING_CASE(type);
> return;
> @@ -4276,7 +4305,8 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
> i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
> u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
> VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
> - VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
> + VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
> + VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
> u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
>
> /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
> @@ -4298,6 +4328,36 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
> intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
> }
>
> +static
> +int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
> + const void *buffer, size_t size)
> +{
> + const struct dp_sdp *sdp = buffer;
> +
> + if (size < sizeof(struct dp_sdp))
> + return -EINVAL;
> +
> + memset(as_sdp, 0, sizeof(*as_sdp));
> +
> + if (sdp->sdp_header.HB0 != 0)
> + return -EINVAL;
> +
> + if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
> + return -EINVAL;
> +
> + if (sdp->sdp_header.HB2 != 0x02)
> + return -EINVAL;
> +
> + if ((sdp->sdp_header.HB3 & 0x3F) != 9)
> + return -EINVAL;
> +
> + as_sdp->mode = sdp->db[0] & AS_SDP_OP_MODE;
> + as_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1];
> + as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
> +
> + return 0;
> +}
> +
> static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
> const void *buffer, size_t size)
> {
> @@ -4368,6 +4428,27 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
> return 0;
> }
>
> +static int
> +intel_read_dp_metadata_infoframe_as_sdp(struct intel_encoder *encoder,
Drop metadata here.
> + struct intel_crtc_state *crtc_state,
> + struct drm_dp_as_sdp *as_sdp)
> +{
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + unsigned int type = DP_SDP_ADAPTIVE_SYNC;
> + struct dp_sdp sdp = {};
> + int ret;
> +
> + dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
> + sizeof(sdp));
> +
> + ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
> + if (ret)
> + drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");
> +
> + return ret;
> +}
> +
> static int
> intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
> const void *buffer, size_t size)
> @@ -4474,6 +4555,10 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
> intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
> &crtc_state->infoframes.drm.drm);
> break;
> + case DP_SDP_ADAPTIVE_SYNC:
> + intel_read_dp_metadata_infoframe_as_sdp(encoder, crtc_state,
> + &crtc_state->infoframes.as_sdp);
> + break;
> default:
> MISSING_CASE(type);
> break;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 7020e5806109..69e0876f43aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -137,6 +137,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
> return VIDEO_DIP_ENABLE_GMP_HSW;
> case DP_SDP_VSC:
> return VIDEO_DIP_ENABLE_VSC_HSW;
> + case DP_SDP_ADAPTIVE_SYNC:
> + return VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
> case DP_SDP_PPS:
> return VDIP_ENABLE_PPS;
> case HDMI_INFOFRAME_TYPE_AVI:
> @@ -164,6 +166,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
> return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
> case DP_SDP_VSC:
> return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
> + case DP_SDP_ADAPTIVE_SYNC:
> + return TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i);
> case DP_SDP_PPS:
> return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
> case HDMI_INFOFRAME_TYPE_AVI:
> @@ -186,6 +190,8 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
> switch (type) {
> case DP_SDP_VSC:
> return VIDEO_DIP_VSC_DATA_SIZE;
> + case DP_SDP_ADAPTIVE_SYNC:
> + return VIDEO_DIP_ASYNC_DATA_SIZE;
> case DP_SDP_PPS:
> return VIDEO_DIP_PPS_DATA_SIZE;
> case HDMI_PACKET_TYPE_GAMUT_METADATA:
> @@ -558,7 +564,8 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
>
> mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
> VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> - VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
> + VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
> + VIDEO_DIP_ENABLE_ADAPTIVE_SYNC);
>
> if (DISPLAY_VER(dev_priv) >= 10)
> mask |= VIDEO_DIP_ENABLE_DRM_GLK;
> @@ -570,6 +577,7 @@ static const u8 infoframe_type_to_idx[] = {
> HDMI_PACKET_TYPE_GENERAL_CONTROL,
> HDMI_PACKET_TYPE_GAMUT_METADATA,
> DP_SDP_VSC,
> + DP_SDP_ADAPTIVE_SYNC,
> HDMI_INFOFRAME_TYPE_AVI,
> HDMI_INFOFRAME_TYPE_SPD,
> HDMI_INFOFRAME_TYPE_VENDOR,
> @@ -1212,7 +1220,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
> val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
> VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
> VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
> - VIDEO_DIP_ENABLE_DRM_GLK);
> + VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_ADAPTIVE_SYNC);
>
> if (!enable) {
> intel_de_write(dev_priv, reg, val);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5d905f932cb4..d2ab7e571e62 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -113,6 +113,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> + struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> const struct drm_display_info *info = &connector->base.display_info;
> int vmin, vmax;
> @@ -165,6 +166,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> if (crtc_state->uapi.vrr_enabled) {
> crtc_state->vrr.enable = true;
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> +
> + if (drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd))
> + crtc_state->vrr.as_sdp_mode =
> + DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e00557e1a57f..c02ea07af4c2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2312,6 +2312,7 @@
> * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
> * of the infoframe structure specified by CEA-861. */
> #define VIDEO_DIP_DATA_SIZE 32
> +#define VIDEO_DIP_ASYNC_DATA_SIZE 36
> #define VIDEO_DIP_GMP_DATA_SIZE 36
> #define VIDEO_DIP_VSC_DATA_SIZE 36
> #define VIDEO_DIP_PPS_DATA_SIZE 132
> @@ -2350,6 +2351,8 @@
> #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
> #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
> +/* ADL and later: */
> +#define VIDEO_DIP_ENABLE_ADAPTIVE_SYNC REG_BIT(23)
For consistency, perhaps VIDEO_DIP_ENABLE_ADAPTIVE_SYNC_ADL would be better.
Same with others macros below.
Regards,
Ankit
>
> /* Panel fitting */
> #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
> @@ -5040,6 +5043,7 @@
> #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
> #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
> #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
> +#define _VIDEO_DIP_AS_SDP_DATA_A 0x60484
> #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
> #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
> #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
> @@ -5054,6 +5058,7 @@
> #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
> #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
> #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
> +#define _VIDEO_DIP_AS_SDP_DATA_B 0x61484
> #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
> #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
> #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
> @@ -5083,6 +5088,9 @@
> #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
> #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
> #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
> +/*ADLP and later: */
> +#define TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(trans,\
> + _VIDEO_DIP_AS_SDP_DATA_A + (i) * 4)
>
> #define _HSW_STEREO_3D_CTL_A 0x70020
> #define S3D_ENABLE (1 << 31)
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/6] drm/i915/display: Compute AS SDP parameters.
2024-02-22 12:12 ` [PATCH 4/6] drm/i915/display: Compute AS SDP parameters Mitul Golani
@ 2024-02-26 9:55 ` Nautiyal, Ankit K
0 siblings, 0 replies; 13+ messages in thread
From: Nautiyal, Ankit K @ 2024-02-26 9:55 UTC (permalink / raw)
To: Mitul Golani, intel-gfx; +Cc: dri-devel
On 2/22/2024 5:42 PM, Mitul Golani wrote:
> Add necessary functions definitions to enable
> and compute AS SDP data. The new `intel_dp_compute_as_sdp`
> function computes AS SDP values based on the display
> configuration, ensuring proper handling of Variable Refresh
> Rate (VRR).
>
> --v2:
> - Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit]
> - separate patch for intel_read/write_dp_sdp [Ankit].
> - _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit]
> - To fix indentation [Ankit]
>
> --v3:
> - Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.
>
> --v4:
> - Add HAS_VRR check before write as sdp.
>
> --v5:
> - Add missed HAS_VRR check before read as sdp.
>
> --v6:
> Use Adaptive Sync sink status, which can be
> used as a check for read/write sdp. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++-
> 3 files changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2accfe41160d..93b4b7dff1d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1415,6 +1415,7 @@ struct intel_crtc_state {
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> u8 as_sdp_mode;
> + bool as_sdp_enable;
This is again specific to DP, we can do away with this in vrr struct.
> } vrr;
>
> /* Stream Splitter for eDP MSO */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index b370e1da4735..5c1e2301dd52 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2617,6 +2617,33 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
> }
>
> +static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> +{
> + struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
> + struct intel_connector *connector = intel_dp->attached_connector;
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + int vrefresh = drm_mode_vrefresh(adjusted_mode);
> +
> + if (!intel_vrr_is_in_range(connector, vrefresh) || !crtc_state->vrr.as_sdp_enable)
> + return;
> +
> + as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
> + as_sdp->length = 0x9;
> + as_sdp->mode = crtc_state->vrr.as_sdp_mode;
> + as_sdp->vtotal = adjusted_mode->vtotal;
> +
> + if (as_sdp->mode == DP_AS_SDP_AVT_FIXED_VTOTAL) {
Currently we are just supporting DP_AS_SDP_AVT_FIXED_VTOTAL so this
check is not required.
But we can add a comment mentioning the same.
> + as_sdp->target_rr = 0;
> + as_sdp->duration_incr_ms = 0;
> + as_sdp->duration_incr_ms = 0;
> + }
> +
> + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> +}
We will need to add this to state checker, something like
PIPE_CONF_CHECK_DP_AS_SDP and add function to compare the adaptive sync
sdp struct.
Regards,
Ankit
> +
> static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> @@ -2942,6 +2969,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> g4x_dp_set_clock(encoder, pipe_config);
>
> intel_vrr_compute_config(pipe_config, conn_state);
> + intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
> intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
> intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index d2ab7e571e62..08e3ba69bd30 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -167,9 +167,11 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> crtc_state->vrr.enable = true;
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>
> - if (drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd))
> + if (drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd)) {
> + crtc_state->vrr.as_sdp_enable = true;
> crtc_state->vrr.as_sdp_mode =
> DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
> + }
> }
> }
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/6] drm/i915/display: Compute vrr_vsync params
2024-02-22 12:12 ` [PATCH 5/6] drm/i915/display: Compute vrr_vsync params Mitul Golani
@ 2024-02-26 10:03 ` Nautiyal, Ankit K
0 siblings, 0 replies; 13+ messages in thread
From: Nautiyal, Ankit K @ 2024-02-26 10:03 UTC (permalink / raw)
To: Mitul Golani, intel-gfx; +Cc: dri-devel
On 2/22/2024 5:42 PM, Mitul Golani wrote:
> Compute vrr_vsync_start/end which sets the position
> for hardware to send the Vsync at a fixed position
> relative to the end of the Vblank.
>
> --v2:
> - Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
> - Update bit fields of VRR_VSYNC_START/END.(Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 12 ++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> 4 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 00ac65a14029..5994f7fcbb6a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5321,6 +5321,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(vrr.flipline);
> PIPE_CONF_CHECK_I(vrr.pipeline_full);
> PIPE_CONF_CHECK_I(vrr.guardband);
> + PIPE_CONF_CHECK_BOOL(vrr.as_sdp_enable);
Need to add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
> }
>
> #undef PIPE_CONF_CHECK_X
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 93b4b7dff1d0..7859e4baad4b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1416,6 +1416,7 @@ struct intel_crtc_state {
> u16 flipline, vmin, vmax, guardband;
> u8 as_sdp_mode;
> bool as_sdp_enable;
> + u32 vsync_end, vsync_start;
> } vrr;
>
> /* Stream Splitter for eDP MSO */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 08e3ba69bd30..29ddf504d94b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -150,6 +150,13 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>
> crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
>
> + crtc_state->vrr.vsync_start =
> + (crtc_state->hw.adjusted_mode.crtc_vtotal -
> + VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start));
> + crtc_state->vrr.vsync_end =
> + (crtc_state->hw.adjusted_mode.crtc_vtotal -
> + (VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16));
Need to add trans_vrr_start/end also in vrr_get_config.
Make sure to read/write these only when we intend to send adaptive_sync sdp.
Regards,
Ankit
> +
> /*
> * For XE_LPD+, we use guardband and pipeline override
> * is deprecated.
> @@ -273,8 +280,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> u32 trans_vrr_ctl;
>
> trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
> + bool as_sdp_enabled =
> + intel_de_read(dev_priv,
> + HSW_TVIDEO_DIP_CTL(cpu_transcoder));
>
> crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
> + crtc_state->vrr.as_sdp_enable =
> + as_sdp_enabled & VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
>
> if (DISPLAY_VER(dev_priv) >= 13)
> crtc_state->vrr.guardband =
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c02ea07af4c2..3e0853458ef4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2007,7 +2007,9 @@
> #define _TRANS_VRR_CTL_B 0x61420
> #define _TRANS_VRR_CTL_C 0x62420
> #define _TRANS_VRR_CTL_D 0x63420
> +#define _TRANS_VRR_VSYNC_A 0x60078
> #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
> +#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A)
> #define VRR_CTL_VRR_ENABLE REG_BIT(31)
> #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> @@ -2087,6 +2089,11 @@
> #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
> #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
>
> +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
> +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
> +
> #define _TRANS_PUSH_A 0x60A70
> #define _TRANS_PUSH_B 0x61A70
> #define _TRANS_PUSH_C 0x62A70
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled
2024-02-16 14:20 ` [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled Mitul Golani
@ 2024-02-20 6:37 ` Nautiyal, Ankit K
0 siblings, 0 replies; 13+ messages in thread
From: Nautiyal, Ankit K @ 2024-02-20 6:37 UTC (permalink / raw)
To: Mitul Golani, intel-gfx; +Cc: dri-devel
On 2/16/2024 7:50 PM, Mitul Golani wrote:
> Write/Read Adaptive sync SDP only when Sink and Source is enabled
> for the same. Also along with write TRANS_VRR_VSYNC values.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
> .../gpu/drm/i915/display/intel_display_device.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 7 +++++++
> 5 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bea441590204..68cd49193d03 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> /* XXX: DSI transcoder paranoia */
> if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
> @@ -3972,6 +3973,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>
> + if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
> + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
> +
> intel_audio_codec_get_config(encoder, pipe_config);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index fe4268813786..6399fbc6c738 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -68,6 +68,7 @@ struct drm_printer;
> #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
> BIT(trans)) != 0)
> #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
> +#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
> #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
> #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
> #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0759266e7bfb..5bd99fa8f200 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -119,6 +119,17 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> return dig_port->base.type == INTEL_OUTPUT_EDP;
> }
>
> +bool
> +intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp)
> +{
> + u8 dpcd[DP_RECEIVER_CAP_SIZE];
> +
> + if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
> + return -EIO;
> +
This is already read in intel_dp->dpcd, we can use that.
> + return drm_dp_as_sdp_supported(&intel_dp->aux, dpcd);
> +}
> +
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>
> /* Is link rate UHBR and thus 128b/132b? */
> @@ -4330,6 +4341,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
> VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
> VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
> u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
> if (!enable && HAS_DSC(dev_priv))
> @@ -4347,6 +4359,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
>
> intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
>
> + if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
> + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
> +
> intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 530cc97bc42f..09ab313af896 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -180,5 +180,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> struct link_config_limits *limits);
>
> void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
> +bool intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 2fa0004d00c7..86729e145991 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -192,6 +192,9 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + bool is_as_sdp_enabled = intel_de_read(dev_priv,
> + HSW_TVIDEO_DIP_CTL(cpu_transcoder)) &
> + VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
>
> /*
> * TRANS_SET_CONTEXT_LATENCY with VRR enabled
> @@ -210,6 +213,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
> intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
> intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
> +
> + if (is_as_sdp_enabled)
As mentioned in Patch#4, lets use the crtc_state->vrr.as_sdp_enable,
instead of this.
Regards,
Ankit
> + intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
> + crtc_state->vrr.vsync_end << 16 | crtc_state->vrr.vsync_start);
> }
>
> void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled
2024-02-16 14:20 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
@ 2024-02-16 14:20 ` Mitul Golani
2024-02-20 6:37 ` Nautiyal, Ankit K
0 siblings, 1 reply; 13+ messages in thread
From: Mitul Golani @ 2024-02-16 14:20 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal, dri-devel, Mitul Golani
Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
.../gpu/drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 15 +++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 7 +++++++
5 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..68cd49193d03 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
/* XXX: DSI transcoder paranoia */
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
@@ -3972,6 +3973,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
+ if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+
intel_audio_codec_get_config(encoder, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..6399fbc6c738 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
+#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0759266e7bfb..5bd99fa8f200 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -119,6 +119,17 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
return dig_port->base.type == INTEL_OUTPUT_EDP;
}
+bool
+intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp)
+{
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
+ return -EIO;
+
+ return drm_dp_as_sdp_supported(&intel_dp->aux, dpcd);
+}
+
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
@@ -4330,6 +4341,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
if (!enable && HAS_DSC(dev_priv))
@@ -4347,6 +4359,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+ if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
+ intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
+
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 530cc97bc42f..09ab313af896 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -180,5 +180,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
struct link_config_limits *limits);
void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
+bool intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2fa0004d00c7..86729e145991 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -192,6 +192,9 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ bool is_as_sdp_enabled = intel_de_read(dev_priv,
+ HSW_TVIDEO_DIP_CTL(cpu_transcoder)) &
+ VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
/*
* TRANS_SET_CONTEXT_LATENCY with VRR enabled
@@ -210,6 +213,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
+
+ if (is_as_sdp_enabled)
+ intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+ crtc_state->vrr.vsync_end << 16 | crtc_state->vrr.vsync_start);
}
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled
2024-02-16 14:18 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
@ 2024-02-16 14:18 ` Mitul Golani
0 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2024-02-16 14:18 UTC (permalink / raw)
To: intel-gfx-trybot; +Cc: ankit.k.nautiyal, dri-devel, Mitul Golani
Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
.../gpu/drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 15 +++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 7 +++++++
5 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..68cd49193d03 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
/* XXX: DSI transcoder paranoia */
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
@@ -3972,6 +3973,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
+ if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+
intel_audio_codec_get_config(encoder, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..6399fbc6c738 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
+#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0759266e7bfb..5bd99fa8f200 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -119,6 +119,17 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
return dig_port->base.type == INTEL_OUTPUT_EDP;
}
+bool
+intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp)
+{
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
+ return -EIO;
+
+ return drm_dp_as_sdp_supported(&intel_dp->aux, dpcd);
+}
+
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
@@ -4330,6 +4341,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
if (!enable && HAS_DSC(dev_priv))
@@ -4347,6 +4359,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+ if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
+ intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
+
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 530cc97bc42f..09ab313af896 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -180,5 +180,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
struct link_config_limits *limits);
void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
+bool intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2fa0004d00c7..86729e145991 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -192,6 +192,9 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ bool is_as_sdp_enabled = intel_de_read(dev_priv,
+ HSW_TVIDEO_DIP_CTL(cpu_transcoder)) &
+ VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
/*
* TRANS_SET_CONTEXT_LATENCY with VRR enabled
@@ -210,6 +213,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
+
+ if (is_as_sdp_enabled)
+ intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+ crtc_state->vrr.vsync_end << 16 | crtc_state->vrr.vsync_start);
}
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-02-26 10:04 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-22 12:12 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
2024-02-22 12:12 ` [PATCH 1/6] drm/dp: Add an support to indicate if sink supports AS SDP Mitul Golani
2024-02-22 12:12 ` [PATCH 2/6] drm: Add Adaptive Sync SDP logging Mitul Golani
2024-02-22 12:12 ` [PATCH 3/6] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP Mitul Golani
2024-02-26 9:43 ` Nautiyal, Ankit K
2024-02-22 12:12 ` [PATCH 4/6] drm/i915/display: Compute AS SDP parameters Mitul Golani
2024-02-26 9:55 ` Nautiyal, Ankit K
2024-02-22 12:12 ` [PATCH 5/6] drm/i915/display: Compute vrr_vsync params Mitul Golani
2024-02-26 10:03 ` Nautiyal, Ankit K
2024-02-22 12:12 ` [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled Mitul Golani
-- strict thread matches above, loose matches on Subject: below --
2024-02-16 14:20 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
2024-02-16 14:20 ` [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled Mitul Golani
2024-02-20 6:37 ` Nautiyal, Ankit K
2024-02-16 14:18 [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Mitul Golani
2024-02-16 14:18 ` [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled Mitul Golani
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