* [PATCH 0/5] drm/i915: cleanup dead code
@ 2024-03-06 19:36 Lucas De Marchi
2024-03-06 19:36 ` [PATCH 1/5] drm/i915: Drop WA 16015675438 Lucas De Marchi
` (5 more replies)
0 siblings, 6 replies; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-06 19:36 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Lucas De Marchi
Remove platforms that never had their PCI IDs added to the driver and
are of course marked with requiring force_probe. Note that most of the
code for those platforms is actually used by subsequent ones, so it's
not a huge amount of code being removed.
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h is also changed on the
xe side, but that should be ok: the defines are there only for compat
reasons while building the display side (and none of these platforms
have display, so it's build-issue only).
First patch is what motivated the others and was submitted alone
@ 20240306144723.1826977-1-lucas.demarchi@intel.com .
While loooking at this WA I was wondering why we still had some of that
code around.
Build-tested only for now.
Lucas De Marchi (5):
drm/i915: Drop WA 16015675438
drm/i915: Drop dead code for xehpsdv
drm/i915: Update IP_VER(12, 50)
drm/i915: Drop dead code for pvc
drm/i915: Remove special handling for !RCS_MASK()
Documentation/gpu/rfc/i915_vm_bind.h | 11 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 4 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 8 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 5 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40 ++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 43 +---
.../drm/i915/gt/intel_execlists_submission.c | 10 +-
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 --
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 52 +----
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 59 ------
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 51 +----
drivers/gpu/drm/i915/gt/intel_migrate.c | 22 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 52 +----
drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 13 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 193 +-----------------
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 6 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 -
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 12 --
drivers/gpu/drm/i915/i915_drv.h | 13 --
drivers/gpu/drm/i915/i915_getparam.c | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
drivers/gpu/drm/i915/i915_hwmon.c | 6 -
drivers/gpu/drm/i915/i915_pci.c | 61 +-----
drivers/gpu/drm/i915/i915_perf.c | 19 +-
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 4 +-
drivers/gpu/drm/i915/intel_clock_gating.c | 26 +--
drivers/gpu/drm/i915/intel_device_info.c | 2 -
drivers/gpu/drm/i915/intel_device_info.h | 2 -
drivers/gpu/drm/i915/intel_step.c | 80 +-------
drivers/gpu/drm/i915/intel_uncore.c | 159 +--------------
drivers/gpu/drm/i915/selftests/intel_uncore.c | 3 -
.../gpu/drm/xe/compat-i915-headers/i915_drv.h | 6 -
43 files changed, 110 insertions(+), 928 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/5] drm/i915: Drop WA 16015675438
2024-03-06 19:36 [PATCH 0/5] drm/i915: cleanup dead code Lucas De Marchi
@ 2024-03-06 19:36 ` Lucas De Marchi
2024-03-12 22:54 ` Matt Roper
2024-03-06 19:36 ` [PATCH 2/5] drm/i915: Drop dead code for xehpsdv Lucas De Marchi
` (4 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-06 19:36 UTC (permalink / raw)
To: intel-gfx
Cc: dri-devel, Lucas De Marchi, Mateusz Jablonski, Michal Mrozek,
Rodrigo Vivi
With dynamic load-balancing disabled on the compute side, there's no
reason left to enable WA 16015675438. Drop it from both PVC and DG2.
Note that this can be done because now the driver always set a fixed
partition of EUs during initialization via the ccs_mode configuration.
The flag to GuC is still needed because of 18020744125, so update
the comment accordingly.
Cc: Mateusz Jablonski <mateusz.jablonski@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +-----
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d67d44611c28..7f812409c30a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2928,14 +2928,10 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
}
- if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) {
+ if (IS_PONTEVECCHIO(i915) || IS_DG2(i915))
/* Wa_14015227452:dg2,pvc */
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
- /* Wa_16015675438:dg2,pvc */
- wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
- }
-
if (IS_DG2(i915)) {
/*
* Wa_16011620976:dg2_g11
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index d2b7425bbdcc..c6603793af89 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -315,7 +315,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (IS_DG2_G11(gt->i915))
flags |= GUC_WA_CONTEXT_ISOLATION;
- /* Wa_16015675438 */
+ /* Wa_18020744125 */
if (!RCS_MASK(gt))
flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/5] drm/i915: Drop dead code for xehpsdv
2024-03-06 19:36 [PATCH 0/5] drm/i915: cleanup dead code Lucas De Marchi
2024-03-06 19:36 ` [PATCH 1/5] drm/i915: Drop WA 16015675438 Lucas De Marchi
@ 2024-03-06 19:36 ` Lucas De Marchi
2024-03-11 15:16 ` Rodrigo Vivi
2024-03-12 22:58 ` Matt Roper
2024-03-06 19:36 ` [PATCH 3/5] drm/i915: Update IP_VER(12, 50) Lucas De Marchi
` (3 subsequent siblings)
5 siblings, 2 replies; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-06 19:36 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Lucas De Marchi
PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.
The registers not used anymore are also removed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Potential problem here that needs a deeper look, the changes in
__gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
I removed them, but it needs to be double checked with spec and CI
results.
Documentation/gpu/rfc/i915_vm_bind.h | 11 +--
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40 ++++----
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 ---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 20 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 50 ----------
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 ++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 43 ---------
drivers/gpu/drm/i915/gt/intel_migrate.c | 18 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 31 ------
drivers/gpu/drm/i915/gt/intel_rps.c | 2 -
drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 -------------------
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 4 -
drivers/gpu/drm/i915/i915_hwmon.c | 6 --
drivers/gpu/drm/i915/i915_pci.c | 17 ----
drivers/gpu/drm/i915/i915_perf.c | 11 +--
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_step.c | 10 --
drivers/gpu/drm/i915/intel_uncore.c | 15 +--
drivers/gpu/drm/i915/selftests/intel_uncore.c | 1 -
| 2 -
24 files changed, 51 insertions(+), 380 deletions(-)
diff --git a/Documentation/gpu/rfc/i915_vm_bind.h b/Documentation/gpu/rfc/i915_vm_bind.h
index 8a8fcd4fceac..bc26dc126104 100644
--- a/Documentation/gpu/rfc/i915_vm_bind.h
+++ b/Documentation/gpu/rfc/i915_vm_bind.h
@@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
* Multiple VA mappings can be created to the same section of the object
* (aliasing).
*
- * The @start, @offset and @length must be 4K page aligned. However the DG2
- * and XEHPSDV has 64K page size for device local memory and has compact page
- * table. On those platforms, for binding device local-memory objects, the
- * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
- * the local memory 64K page and the system memory 4K page bindings in the same
- * 2M range.
+ * The @start, @offset and @length must be 4K page aligned. However the DG2 has
+ * 64K page size for device local memory and has compact page table. On that
+ * platform, for binding device local-memory objects, the @start, @offset and
+ * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K
+ * page and the system memory 4K page bindings in the same 2M range.
*
* Error code -EINVAL will be returned if @start, @offset and @length are not
* properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index fa46d2308b0e..1bd0e041e15c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
}
static void
-xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
- struct i915_vma_resource *vma_res,
- struct sgt_dma *iter,
- unsigned int pat_index,
- u32 flags)
+xehp_ppgtt_insert_huge(struct i915_address_space *vm,
+ struct i915_vma_resource *vma_res,
+ struct sgt_dma *iter,
+ unsigned int pat_index,
+ u32 flags)
{
const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
unsigned int rem = sg_dma_len(iter->sg);
@@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
struct sgt_dma iter = sgt_dma(vma_res);
if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
- if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
- xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
+ if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
+ xehp_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
else
gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
} else {
@@ -781,11 +781,11 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
-static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
- dma_addr_t addr,
- u64 offset,
- unsigned int pat_index,
- u32 flags)
+static void xehp_ppgtt_insert_entry_lm(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ unsigned int pat_index,
+ u32 flags)
{
u64 idx = offset >> GEN8_PTE_SHIFT;
struct i915_page_directory * const pdp =
@@ -810,15 +810,15 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, pat_index, flags);
}
-static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
- dma_addr_t addr,
- u64 offset,
- unsigned int pat_index,
- u32 flags)
+static void xehp_ppgtt_insert_entry(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ unsigned int pat_index,
+ u32 flags)
{
if (flags & PTE_LM)
- return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
- pat_index, flags);
+ return xehp_ppgtt_insert_entry_lm(vm, addr, offset,
+ pat_index, flags);
return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index, flags);
}
@@ -1042,7 +1042,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
if (HAS_64K_PAGES(gt->i915))
- ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
+ ppgtt->vm.insert_page = xehp_ppgtt_insert_entry;
else
ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 6d440de8ba01..1e925c75fb08 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -103,19 +103,6 @@ static const struct gsc_def gsc_def_dg1[] = {
}
};
-static const struct gsc_def gsc_def_xehpsdv[] = {
- {
- /* HECI1 not enabled on the device. */
- },
- {
- .name = "mei-gscfi",
- .bar = DG1_GSC_HECI2_BASE,
- .bar_size = GSC_BAR_LENGTH,
- .use_polling = true,
- .slow_firmware = true,
- }
-};
-
static const struct gsc_def gsc_def_dg2[] = {
{
.name = "mei-gsc",
@@ -188,8 +175,6 @@ static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
if (IS_DG1(i915)) {
def = &gsc_def_dg1[intf_id];
- } else if (IS_XEHPSDV(i915)) {
- def = &gsc_def_xehpsdv[intf_id];
} else if (IS_DG2(i915)) {
def = &gsc_def_dg2[intf_id];
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index e253750a51c5..5a2bd8de155a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -57,24 +57,12 @@ static const struct intel_mmio_range icl_l3bank_steering_table[] = {
* are of a "GAM" subclass that has special rules. Thus we use a separate
* GAM table farther down for those.
*/
-static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
+static const struct intel_mmio_range dg2_mslice_steering_table[] = {
{ 0x00DD00, 0x00DDFF },
{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
{},
};
-static const struct intel_mmio_range xehpsdv_gam_steering_table[] = {
- { 0x004000, 0x004AFF },
- { 0x00C800, 0x00CFFF },
- {},
-};
-
-static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
- { 0x00B000, 0x00B0FF },
- { 0x00D800, 0x00D8FF },
- {},
-};
-
static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{ 0x00B000, 0x00B0FF },
{ 0x00D880, 0x00D8FF },
@@ -188,17 +176,13 @@ void intel_gt_mcr_init(struct intel_gt *gt)
} else if (IS_PONTEVECCHIO(i915)) {
gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
} else if (IS_DG2(i915)) {
- gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
+ gt->steering_table[MSLICE] = dg2_mslice_steering_table;
gt->steering_table[LNCF] = dg2_lncf_steering_table;
/*
* No need to hook up the GAM table since it has a dedicated
* steering control register on DG2 and can use implicit
* steering.
*/
- } else if (IS_XEHPSDV(i915)) {
- gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
- gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
- gt->steering_table[GAM] = xehpsdv_gam_steering_table;
} else if (GRAPHICS_VER(i915) >= 11 &&
GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
gt->steering_table[L3BANK] = icl_l3bank_steering_table;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 50962cfd1353..919c07903767 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -718,44 +718,11 @@
#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
#define VFUNIT_CLKGATE_DIS REG_BIT(20)
-#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
#define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
#define GAMEDIA_CLKGATE_DIS REG_BIT(11)
#define HSUNIT_CLKGATE_DIS REG_BIT(8)
#define VSUNIT_CLKGATE_DIS REG_BIT(3)
-#define UNSLCGCTL9440 _MMIO(0x9440)
-#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
-#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
-#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
-#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
-#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
-#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
-#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
-#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
-#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
-#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
-#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
-#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
-
-#define UNSLCGCTL9444 _MMIO(0x9444)
-#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
-#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
-#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
-#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
-#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
-#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
-#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
-#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
-#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
-#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
-#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
-#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
-#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
-#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
-#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
-#define LTCDD_CLKGATE_DIS REG_BIT(10)
-
#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
@@ -765,9 +732,6 @@
#define L3_CLKGATE_DIS REG_BIT(16)
#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
-#define SCCGCTL94DC MCR_REG(0x94dc)
-#define CG3DDISURB REG_BIT(14)
-
#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
@@ -1046,9 +1010,6 @@
#define XEHP_L3SQCREG5 MCR_REG(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
-#define MLTICTXCTL MCR_REG(0xb170)
-#define TDONRENDER REG_BIT(2)
-
#define XEHP_L3SCQREG7 MCR_REG(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
@@ -1057,9 +1018,6 @@
#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
#define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
-#define L3SQCREG1_CCS0 MCR_REG(0xb200)
-#define FLUSHALLNONCOH REG_BIT(5)
-
#define GEN11_GLBLINVL _MMIO(0xb404)
#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
@@ -1109,7 +1067,6 @@
#define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
#define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */
-#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
#define RENDER_MOD_CTRL MCR_REG(0xcf2c)
#define COMP_MOD_CTRL MCR_REG(0xcf30)
#define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */
@@ -1185,7 +1142,6 @@
#define EU_PERF_CNTL4 PERF_REG(0xe45c)
#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
-#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
@@ -1202,7 +1158,6 @@
#define FLOW_CONTROL_ENABLE REG_BIT(15)
#define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12)
-#define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
#define STALL_DOP_GATING_DISABLE REG_BIT(5)
#define THROTTLE_12_5 REG_GENMASK(4, 2)
@@ -1679,11 +1634,6 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
-#define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004)
-#define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008)
-#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
-#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
-
/*
* Standalone Media's non-engine GT registers are located at their regular GT
* offsets plus 0x380000. This extra offset is stored inside the intel_uncore
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index eca4a6a65556..d7784650e4d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -573,7 +573,6 @@ static ssize_t media_freq_factor_show(struct kobject *kobj,
char *buff)
{
struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
- struct intel_guc_slpc *slpc = >_to_guc(gt)->slpc;
intel_wakeref_t wakeref;
u32 mode;
@@ -581,20 +580,12 @@ static ssize_t media_freq_factor_show(struct kobject *kobj,
* Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
* GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
*/
- if (IS_XEHPSDV(gt->i915) &&
- slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
- /*
- * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
- * the media_ratio_mode, just return the cached media ratio
- */
- mode = slpc->media_ratio_mode;
- } else {
- with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
- mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
- SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
- SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
- }
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
+
+ mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
+ SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
+ SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7c367ba8d9dc..7f1b00cb9924 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -546,47 +546,6 @@ static const u8 gen12_rcs_offsets[] = {
END
};
-static const u8 xehp_rcs_offsets[] = {
- NOP(1),
- LRI(13, POSTED),
- REG16(0x244),
- REG(0x034),
- REG(0x030),
- REG(0x038),
- REG(0x03c),
- REG(0x168),
- REG(0x140),
- REG(0x110),
- REG(0x1c0),
- REG(0x1c4),
- REG(0x1c8),
- REG(0x180),
- REG16(0x2b4),
-
- NOP(5),
- LRI(9, POSTED),
- REG16(0x3a8),
- REG16(0x28c),
- REG16(0x288),
- REG16(0x284),
- REG16(0x280),
- REG16(0x27c),
- REG16(0x278),
- REG16(0x274),
- REG16(0x270),
-
- LRI(3, POSTED),
- REG(0x1b0),
- REG16(0x5a8),
- REG16(0x5ac),
-
- NOP(6),
- LRI(1, 0),
- REG(0x0c8),
-
- END
-};
-
static const u8 dg2_rcs_offsets[] = {
NOP(1),
LRI(15, POSTED),
@@ -695,8 +654,6 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
return mtl_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
- else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
- return xehp_rcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_rcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 11)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 576e5ef0289b..86ba2f2e485c 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -35,9 +35,9 @@ static bool engine_supports_migration(struct intel_engine_cs *engine)
return true;
}
-static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
- struct i915_page_table *pt,
- void *data)
+static void xehp_toggle_pdes(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
{
struct insert_pte_data *d = data;
@@ -52,9 +52,9 @@ static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
d->offset += SZ_2M;
}
-static void xehpsdv_insert_pte(struct i915_address_space *vm,
- struct i915_page_table *pt,
- void *data)
+static void xehp_insert_pte(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
{
struct insert_pte_data *d = data;
@@ -120,7 +120,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
* 512 entry layout using 4K GTT pages. The other two windows just map
* lmem pages and must use the new compact 32 entry layout using 64K GTT
* pages, which ensures we can address any lmem object that the user
- * throws at us. We then also use the xehpsdv_toggle_pdes as a way of
+ * throws at us. We then also use the xehp_toggle_pdes as a way of
* just toggling the PDE bit(GEN12_PDE_64K) for us, to enable the
* compact layout for each of these page-tables, that fall within the
* [CHUNK_SIZE, 3 * CHUNK_SIZE) range.
@@ -209,12 +209,12 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
/* Now allow the GPU to rewrite the PTE via its own ppGTT */
if (HAS_64K_PAGES(gt->i915)) {
vm->vm.foreach(&vm->vm, base, d.offset - base,
- xehpsdv_insert_pte, &d);
+ xehp_insert_pte, &d);
d.offset = base + CHUNK_SZ;
vm->vm.foreach(&vm->vm,
d.offset,
2 * CHUNK_SZ,
- xehpsdv_toggle_pdes, &d);
+ xehp_toggle_pdes, &d);
} else {
vm->vm.foreach(&vm->vm, base, d.offset - base,
insert_pte, &d);
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 25c1023eb5f9..c931c56945bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -367,31 +367,6 @@ static const struct drm_i915_mocs_entry gen12_mocs_table[] = {
L3_3_WB),
};
-static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
- /* wa_1608975824 */
- MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
-
- /* UC - Coherent; GO:L3 */
- MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
- /* UC - Coherent; GO:Memory */
- MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
- /* UC - Non-Coherent; GO:Memory */
- MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
- /* UC - Non-Coherent; GO:L3 */
- MOCS_ENTRY(4, 0, L3_1_UC),
-
- /* WB */
- MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
-
- /* HW Reserved - SW program but never use. */
- MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
- MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
- MOCS_ENTRY(60, 0, L3_1_UC),
- MOCS_ENTRY(61, 0, L3_1_UC),
- MOCS_ENTRY(62, 0, L3_1_UC),
- MOCS_ENTRY(63, 0, L3_1_UC),
-};
-
static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
/* UC - Coherent; GO:L3 */
MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
@@ -514,12 +489,6 @@ static unsigned int get_mocs_settings(struct drm_i915_private *i915,
table->uc_index = 1;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
table->unused_entries_index = 3;
- } else if (IS_XEHPSDV(i915)) {
- table->size = ARRAY_SIZE(xehpsdv_mocs_table);
- table->table = xehpsdv_mocs_table;
- table->uc_index = 2;
- table->n_entries = GEN9_NUM_MOCS_ENTRIES;
- table->unused_entries_index = 5;
} else if (IS_DG1(i915)) {
table->size = ARRAY_SIZE(dg1_mocs_table);
table->table = dg1_mocs_table;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 9c6812257ac2..2a6a8134782d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1088,8 +1088,6 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
if (IS_PONTEVECCHIO(i915))
return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
- else if (IS_XEHPSDV(i915))
- return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);
else if (IS_GEN9_LP(i915))
return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
else
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 7f812409c30a..33d543d9bf44 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -922,8 +922,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
; /* noop; none at this time */
else if (IS_DG2(i915))
dg2_ctx_workarounds_init(engine, wal);
- else if (IS_XEHPSDV(i915))
- ; /* noop; none at this time */
else if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
else if (GRAPHICS_VER(i915) == 12)
@@ -1350,9 +1348,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
gt->steering_table[MSLICE] = NULL;
}
- if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0))
- gt->steering_table[GAM] = NULL;
-
slice = __ffs(slice_mask);
subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
GEN_DSS_PER_GSLICE;
@@ -1519,76 +1514,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
}
-static void
-xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
-{
- struct drm_i915_private *i915 = gt->i915;
-
- xehp_init_mcr(gt, wal);
-
- /* Wa_1409757795:xehpsdv */
- wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB);
-
- /* Wa_18011725039:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
- wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
- wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
- }
-
- /* Wa_16011155590:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
- TSGUNIT_CLKGATE_DIS);
-
- /* Wa_14011780169:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) {
- wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
- GAMTLBVDBOX7_CLKGATE_DIS |
- GAMTLBVDBOX6_CLKGATE_DIS |
- GAMTLBVDBOX5_CLKGATE_DIS |
- GAMTLBVDBOX4_CLKGATE_DIS |
- GAMTLBVDBOX3_CLKGATE_DIS |
- GAMTLBVDBOX2_CLKGATE_DIS |
- GAMTLBVDBOX1_CLKGATE_DIS |
- GAMTLBVDBOX0_CLKGATE_DIS |
- GAMTLBKCR_CLKGATE_DIS |
- GAMTLBGUC_CLKGATE_DIS |
- GAMTLBBLT_CLKGATE_DIS);
- wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS |
- GAMTLBGFXA1_CLKGATE_DIS |
- GAMTLBCOMPA0_CLKGATE_DIS |
- GAMTLBCOMPA1_CLKGATE_DIS |
- GAMTLBCOMPB0_CLKGATE_DIS |
- GAMTLBCOMPB1_CLKGATE_DIS |
- GAMTLBCOMPC0_CLKGATE_DIS |
- GAMTLBCOMPC1_CLKGATE_DIS |
- GAMTLBCOMPD0_CLKGATE_DIS |
- GAMTLBCOMPD1_CLKGATE_DIS |
- GAMTLBMERT_CLKGATE_DIS |
- GAMTLBVEBOX3_CLKGATE_DIS |
- GAMTLBVEBOX2_CLKGATE_DIS |
- GAMTLBVEBOX1_CLKGATE_DIS |
- GAMTLBVEBOX0_CLKGATE_DIS);
- }
-
- /* Wa_16012725990:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER))
- wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS);
-
- /* Wa_14011060649:xehpsdv */
- wa_14011060649(gt, wal);
-
- /* Wa_14012362059:xehpsdv */
- wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
-
- /* Wa_14014368820:xehpsdv */
- wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
- INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
-
- /* Wa_14010670810:xehpsdv */
- wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
-}
-
static void
dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
@@ -1758,8 +1683,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
pvc_gt_workarounds_init(gt, wal);
else if (IS_DG2(i915))
dg2_gt_workarounds_init(gt, wal);
- else if (IS_XEHPSDV(i915))
- xehpsdv_gt_workarounds_init(gt, wal);
else if (IS_DG1(i915))
dg1_gt_workarounds_init(gt, wal);
else if (GRAPHICS_VER(i915) == 12)
@@ -2231,8 +2154,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
pvc_whitelist_build(engine);
else if (IS_DG2(i915))
dg2_whitelist_build(engine);
- else if (IS_XEHPSDV(i915))
- ; /* none needed */
else if (GRAPHICS_VER(i915) == 12)
tgl_whitelist_build(engine);
else if (GRAPHICS_VER(i915) == 11)
@@ -2968,22 +2889,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
0 /* write-only, so skip validation */,
true);
}
-
- if (IS_XEHPSDV(i915)) {
- /* Wa_1409954639 */
- wa_mcr_masked_en(wal,
- GEN8_ROW_CHICKEN,
- SYSTOLIC_DOP_CLOCK_GATING_DIS);
-
- /* Wa_1607196519 */
- wa_mcr_masked_en(wal,
- GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_GRF_CLEAR);
-
- /* Wa_14010449647:xehpsdv */
- wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
- GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
- }
}
static void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 6dfe5d9456c6..28277321d9ca 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -51,8 +51,8 @@ static void uc_expand_default_options(struct intel_uc *uc)
/* Default: enable HuC authentication and GuC submission */
i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
- /* XEHPSDV and PVC do not use HuC */
- if (IS_XEHPSDV(i915) || IS_PONTEVECCHIO(i915))
+ /* PVC does not use HuC */
+ if (IS_PONTEVECCHIO(i915))
i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e81b3b2858ac..dff056587459 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -544,7 +544,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
-#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
@@ -621,9 +620,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TIGERLAKE_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
-#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
- (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
-
#define IS_PVC_BD_STEP(__i915, since, until) \
(IS_PONTEVECCHIO(__i915) && \
IS_BASEDIE_STEP(__i915, since, until))
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index 8c3f443c8347..11bd42e03b73 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -738,12 +738,6 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
- } else if (IS_XEHPSDV(i915)) {
- hwmon->rg.pkg_power_sku_unit = GT0_PACKAGE_POWER_SKU_UNIT;
- hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
- hwmon->rg.pkg_rapl_limit = GT0_PACKAGE_RAPL_LIMIT;
- hwmon->rg.energy_status_all = GT0_PLATFORM_ENERGY_STATUS;
- hwmon->rg.energy_status_tile = GT0_PACKAGE_ENERGY_STATUS;
} else {
hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8b4fdeabb12a..b318b7c6bf73 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -734,23 +734,6 @@ static const struct intel_device_info adl_p_info = {
.__runtime.media.ip.ver = 12, \
.__runtime.media.ip.rel = 50
-__maybe_unused
-static const struct intel_device_info xehpsdv_info = {
- XE_HP_FEATURES,
- XE_HPM_FEATURES,
- DGFX_FEATURES,
- PLATFORM(INTEL_XEHPSDV),
- .has_64k_pages = 1,
- .has_media_ratio_mode = 1,
- .platform_engine_mask =
- BIT(RCS0) | BIT(BCS0) |
- BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
- BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
- BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
- BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
- .require_force_probe = 1,
-};
-
#define DG2_FEATURES \
XE_HP_FEATURES, \
XE_HPM_FEATURES, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index bd9d812b1afa..1637c1d235e9 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2881,11 +2881,11 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
int ret;
/*
- * Wa_1508761755:xehpsdv, dg2
+ * Wa_1508761755
* EU NOA signals behave incorrectly if EU clock gating is enabled.
* Disable thread stall DOP gating and EU DOP gating.
*/
- if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+ if (IS_DG2(i915)) {
intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
@@ -2911,7 +2911,7 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
/*
* Initialize Super Queue Internal Cnt Register
* Set PMON Enable in order to collect valid metrics.
- * Enable byets per clock reporting in OA for XEHPSDV onward.
+ * Enable byets per clock reporting in OA.
*/
sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
@@ -2971,10 +2971,9 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
u32 sqcnt1;
/*
- * Wa_1508761755:xehpsdv, dg2
- * Enable thread stall DOP gating and EU DOP gating.
+ * Wa_1508761755: Enable thread stall DOP gating and EU DOP gating.
*/
- if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+ if (IS_DG2(i915)) {
intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e00557e1a57f..a120c17aafcc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1750,7 +1750,6 @@
#define BXT_RP_STATE_CAP _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
-#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
#define PVC_RP_STATE_CAP _MMIO(0x281014)
#define MTL_RP_STATE_CAP _MMIO(0x138000)
@@ -5401,7 +5400,7 @@
#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
-#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
+#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 9c21ce69bd98..93ab44190a47 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -349,13 +349,6 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);
}
-static void xehpsdv_init_clock_gating(struct drm_i915_private *i915)
-{
- /* Wa_22010146351:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
-}
-
static void dg2_init_clock_gating(struct drm_i915_private *i915)
{
/* Wa_22010954014:dg2 */
@@ -764,7 +757,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs =
CG_FUNCS(pvc);
CG_FUNCS(dg2);
-CG_FUNCS(xehpsdv);
CG_FUNCS(cfl);
CG_FUNCS(skl);
CG_FUNCS(kbl);
@@ -801,8 +793,6 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
i915->clock_gating_funcs = &pvc_clock_gating_funcs;
else if (IS_DG2(i915))
i915->clock_gating_funcs = &dg2_clock_gating_funcs;
- else if (IS_XEHPSDV(i915))
- i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
i915->clock_gating_funcs = &cfl_clock_gating_funcs;
else if (IS_SKYLAKE(i915))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 59bea1398c91..de28cbe758f7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -70,7 +70,6 @@ static const char * const platform_names[] = {
PLATFORM_NAME(DG1),
PLATFORM_NAME(ALDERLAKE_S),
PLATFORM_NAME(ALDERLAKE_P),
- PLATFORM_NAME(XEHPSDV),
PLATFORM_NAME(DG2),
PLATFORM_NAME(PONTEVECCHIO),
PLATFORM_NAME(METEORLAKE),
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index eba2f0b919c8..2299327e59f0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -87,7 +87,6 @@ enum intel_platform {
INTEL_DG1,
INTEL_ALDERLAKE_S,
INTEL_ALDERLAKE_P,
- INTEL_XEHPSDV,
INTEL_DG2,
INTEL_PONTEVECCHIO,
INTEL_METEORLAKE,
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index b4162f1be765..d524bfe17c27 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -102,13 +102,6 @@ static const struct intel_step_info adlp_revids[] = {
[0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
};
-static const struct intel_step_info xehpsdv_revids[] = {
- [0x0] = { COMMON_GT_MEDIA_STEP(A0) },
- [0x1] = { COMMON_GT_MEDIA_STEP(A1) },
- [0x4] = { COMMON_GT_MEDIA_STEP(B0) },
- [0x8] = { COMMON_GT_MEDIA_STEP(C0) },
-};
-
static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 },
@@ -190,9 +183,6 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_DG2_G12(i915)) {
revids = dg2_g12_revid_step_tbl;
size = ARRAY_SIZE(dg2_g12_revid_step_tbl);
- } else if (IS_XEHPSDV(i915)) {
- revids = xehpsdv_revids;
- size = ARRAY_SIZE(xehpsdv_revids);
} else if (IS_ALDERLAKE_P_N(i915)) {
revids = adlp_n_revids;
size = ARRAY_SIZE(adlp_n_revids);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 76400e9c40f0..4f1e56187442 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1536,17 +1536,12 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
0x13200 - 0x133ff: VD2 (DG2 only) \
0x13400 - 0x13fff: reserved */ \
- GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
0x15000 - 0x15fff: gt (DG2 only) \
0x16000 - 0x16dff: reserved */ \
GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
- 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
+ GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
0x21000 - 0x21fff: reserved */ \
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
@@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
0x1f6e00 - 0x1f7fff: reserved */ \
GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
-static const struct intel_forcewake_range __xehp_fw_ranges[] = {
- XEHP_FWRANGES(FORCEWAKE_GT)
-};
-
static const struct intel_forcewake_range __dg2_fw_ranges[] = {
XEHP_FWRANGES(FORCEWAKE_RENDER)
};
@@ -2584,10 +2575,6 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
- } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
- ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
- ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
} else if (GRAPHICS_VER(i915) >= 12) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 4f98aa8a861e..502bcadc5f39 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -119,7 +119,6 @@ int intel_uncore_mock_selftests(void)
{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
- { __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
{ __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
{ __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
{ __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
--git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index fef969112b1d..a7e7ec3b5db9 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -85,7 +85,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)
-#define IS_XEHPSDV(dev_priv) (dev_priv && 0)
#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
@@ -130,7 +129,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
#define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \
((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
IS_GRAPHICS_STEP(xe, first, last))
-#define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last) (IS_XEHPSDV(xe) && IS_GRAPHICS_STEP(xe, first, last))
/* XXX: No basedie stepping support yet */
#define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) && IS_PONTEVECCHIO(xe))
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/5] drm/i915: Update IP_VER(12, 50)
2024-03-06 19:36 [PATCH 0/5] drm/i915: cleanup dead code Lucas De Marchi
2024-03-06 19:36 ` [PATCH 1/5] drm/i915: Drop WA 16015675438 Lucas De Marchi
2024-03-06 19:36 ` [PATCH 2/5] drm/i915: Drop dead code for xehpsdv Lucas De Marchi
@ 2024-03-06 19:36 ` Lucas De Marchi
2024-03-11 15:18 ` Rodrigo Vivi
2024-03-06 19:36 ` [PATCH 4/5] drm/i915: Drop dead code for pvc Lucas De Marchi
` (2 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-06 19:36 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Lucas De Marchi
With no platform declaring graphics/media IP_VER(12, 50), replace the
checks throughout the code with IP_VER(12, 55) so the code makes sense
by itself with no additional explanation of previous baggage.
The info override for the various _info is then changed so the version
definition is clearer without pointless overrides.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 4 ++--
.../gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 8 ++++----
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 ++---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 10 +++++-----
drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 8 ++++----
drivers/gpu/drm/i915/gt/intel_migrate.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_getparam.c | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 5 ++---
drivers/gpu/drm/i915/i915_pci.c | 12 ++++--------
drivers/gpu/drm/i915/i915_perf.c | 8 ++++----
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
24 files changed, 50 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 3ff3d8889c6c..edb54903be0a 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -713,7 +713,7 @@ static int igt_ppgtt_huge_fill(void *arg)
{
struct drm_i915_private *i915 = arg;
unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
- bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+ bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
struct i915_address_space *vm;
struct i915_gem_context *ctx;
unsigned long max_pages;
@@ -857,7 +857,7 @@ static int igt_ppgtt_huge_fill(void *arg)
static int igt_ppgtt_64K(void *arg)
{
struct drm_i915_private *i915 = arg;
- bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
+ bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 10a7847f1b04..bac15196b4d2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -117,7 +117,7 @@ static bool fastblit_supports_x_tiling(const struct drm_i915_private *i915)
if (gen < 12)
return true;
- if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
return false;
return HAS_DISPLAY(i915);
@@ -166,7 +166,7 @@ static int prepare_blit(const struct tiled_blits *t,
src_pitch = t->width; /* in dwords */
if (src->tiling == CLIENT_TILING_Y) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
- if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))
src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
} else if (src->tiling == CLIENT_TILING_X) {
src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
@@ -177,7 +177,7 @@ static int prepare_blit(const struct tiled_blits *t,
dst_pitch = t->width; /* in dwords */
if (dst->tiling == CLIENT_TILING_Y) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
- if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))
dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
} else if (dst->tiling == CLIENT_TILING_X) {
dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
@@ -365,7 +365,7 @@ static u64 tiled_offset(const struct intel_gt *gt,
v += x;
swizzle = gt->ggtt->bit_6_swizzle_x;
- } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
/* Y-major tiling layout is Tile4 for Xe_HP and beyond */
v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1bf13e3d307..24d1c28201fa 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -827,7 +827,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
cs = gen12_emit_pipe_control(cs, 0,
PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
- if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f553cf4e6449..75bde8c1aa5d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -765,14 +765,14 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt)
* and bits have disable semantices.
*/
media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
- if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
+ if (MEDIA_VER_FULL(i915) < IP_VER(12, 55))
media_fuse = ~media_fuse;
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
GEN11_GT_VEBOX_DISABLE_SHIFT;
- if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) {
fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
} else {
@@ -1193,7 +1193,6 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine)
if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
- GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
regs = xehp_regs;
num = ARRAY_SIZE(xehp_regs);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 42aade0faf2d..4bc6c437e7f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -493,7 +493,7 @@ __execlists_schedule_in(struct i915_request *rq)
/* Use a fixed tag for OA and friends */
GEM_BUG_ON(ce->tag <= BITS_PER_LONG);
ce->lrc.ccid = ce->tag;
- } else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
/* We don't need a strict matching tag, just different values */
unsigned int tag = ffs(READ_ONCE(engine->context_tag));
@@ -613,7 +613,7 @@ static void __execlists_schedule_out(struct i915_request * const rq,
intel_engine_add_retire(engine, ce->timeline);
ccid = ce->lrc.ccid;
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
ccid >>= XEHP_SW_CTX_ID_SHIFT - 32;
ccid &= XEHP_MAX_CONTEXT_HW_ID;
} else {
@@ -1907,7 +1907,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
head, upper_32_bits(csb), lower_32_bits(csb));
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
promote = xehp_csb_parse(csb);
else if (GRAPHICS_VER(engine->i915) >= 12)
promote = gen12_csb_parse(csb);
@@ -3479,7 +3479,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
}
}
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
if (intel_engine_has_preemption(engine))
engine->emit_bb_start = xehp_emit_bb_start;
else
@@ -3582,7 +3582,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
if (GRAPHICS_VER(engine->i915) >= 11 &&
- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 50)) {
+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 55)) {
execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index a425db5ed3a2..2c6d31b8fc1a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -278,7 +278,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
intel_uncore_posting_read(uncore,
XELPMP_RING_FAULT_REG);
- } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
intel_gt_mcr_multicast_rmw(gt, XEHP_RING_FAULT_REG,
RING_FAULT_VALID, 0);
intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
@@ -403,7 +403,7 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
xehp_check_faults(gt);
else if (GRAPHICS_VER(i915) >= 8)
gen8_check_faults(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 5a2bd8de155a..29443bf7c06c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -184,7 +184,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
* steering.
*/
} else if (GRAPHICS_VER(i915) >= 11 &&
- GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
+ GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) {
gt->steering_table[L3BANK] = icl_l3bank_steering_table;
gt->info.l3bank_mask =
~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
@@ -829,7 +829,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
if (IS_PONTEVECCHIO(gt->i915)) {
*group = dss / GEN_DSS_PER_CSLICE;
*instance = dss % GEN_DSS_PER_CSLICE;
- } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
*group = dss / GEN_DSS_PER_GSLICE;
*instance = dss % GEN_DSS_PER_GSLICE;
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
index 01ac565a56a4..a67a4c35a4fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
@@ -54,7 +54,7 @@ int intel_gt_mcr_wait_for_reg(struct intel_gt *gt,
* the topology, so we lookup the DSS ID directly in "slice 0."
*/
#define _HAS_SS(ss_, gt_, group_, instance_) ( \
- GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \
+ GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 55) ? \
intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 7811a8c9da06..30b128b1fde7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -680,7 +680,7 @@ void setup_private_pat(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
xelpg_setup_private_ppat(gt);
- else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
xehp_setup_private_ppat(gt);
else if (GRAPHICS_VER(i915) >= 12)
tgl_setup_private_ppat(uncore);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7f1b00cb9924..b387146ede98 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -676,7 +676,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return 0x70;
else if (GRAPHICS_VER(engine->i915) >= 12)
return 0x60;
@@ -690,7 +690,7 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return 0x80;
else if (GRAPHICS_VER(engine->i915) >= 12)
return 0x70;
@@ -705,7 +705,7 @@ static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return 0x84;
else if (GRAPHICS_VER(engine->i915) >= 12)
return 0x74;
@@ -752,7 +752,7 @@ static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)
static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
{
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
/*
* Note that the CSFE context has a dummy slot for CMD_BUF_CCTL
* simply to match the RCS context image layout.
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 86ba2f2e485c..6f7af4077135 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -925,7 +925,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
ring_sz = XY_FAST_COLOR_BLT_DW;
else if (ver >= 8)
ring_sz = 8;
@@ -936,7 +936,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
if (IS_ERR(cs))
return PTR_ERR(cs);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
*cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
(XY_FAST_COLOR_BLT_DW - 2);
*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c931c56945bd..9fac5e2318e2 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -639,7 +639,7 @@ static void init_l3cc_table(struct intel_gt *gt,
intel_gt_mcr_lock(gt, &flags);
for_each_l3cc(l3cc, table, i)
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55))
intel_gt_mcr_multicast_write_fw(gt, XEHP_LNCFCMOCS(i), l3cc);
else
intel_uncore_write_fw(gt->uncore, GEN9_LNCFCMOCS(i), l3cc);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6a3246240e81..5eec9cd6199f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -642,7 +642,7 @@ void intel_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
xehp_sseu_info_init(gt);
else if (GRAPHICS_VER(i915) >= 12)
gen12_sseu_info_init(gt);
@@ -851,7 +851,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
{
if (sseu->max_slices == 0)
drm_printf(p, "Unavailable\n");
- else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
sseu_print_xehp_topology(sseu, p);
else
sseu_print_hsw_topology(sseu, p);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 33d543d9bf44..750bf08ee7c1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2770,7 +2770,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
THREAD_EX_ARB_MODE_RR_AFTER_DEP);
- if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
}
@@ -2969,7 +2969,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
const struct i915_range *mcr_ranges;
int i;
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
mcr_ranges = mcr_ranges_xehp;
else if (GRAPHICS_VER(i915) >= 12)
mcr_ranges = mcr_ranges_gen12;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index c6603793af89..da6cc268e7b2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -286,7 +286,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
/* Wa_22012773006:gen11,gen12 < XeHP */
if (GRAPHICS_VER(gt->i915) >= 11 &&
- GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
+ GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 55))
flags |= GUC_WA_POLLCS;
/* Wa_14014475959 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index af63973c4e4b..65f8724c3cf9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -393,7 +393,7 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
/* add in local MOCS registers */
for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
else
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
@@ -503,7 +503,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
#define XEHP_LR_HW_CONTEXT_SIZE (96 * sizeof(u32))
-#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50) ? \
+#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55) ? \
XEHP_LR_HW_CONTEXT_SIZE : \
LR_HW_CONTEXT_SIZE)
#define LRC_SKIP_SIZE(i915) (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SZ(i915))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 52332bb14339..a35e32695e1b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -26,7 +26,7 @@ static void guc_prepare_xfer(struct intel_gt *gt)
GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
GUC_ENABLE_MIA_CLOCK_GATING;
- if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 55))
shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
GUC_ENABLE_MIA_CACHING;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index cc076e9302ad..4a5331ee43b8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4507,7 +4507,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
*/
engine->emit_bb_start = gen8_emit_bb_start;
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
engine->emit_bb_start = xehp_emit_bb_start;
}
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 5c3fec63cb4c..fc4c3d4e2b40 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -160,7 +160,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
break;
case I915_PARAM_SLICE_MASK:
/* Not supported from Xe_HP onward; use topology queries */
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
return -EINVAL;
value = sseu->slice_mask;
@@ -169,7 +169,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
break;
case I915_PARAM_SUBSLICE_MASK:
/* Not supported from Xe_HP onward; use topology queries */
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
return -EINVAL;
/* Only copy bits from the first slice */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index a0b784ebaddd..2594eb10c559 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1245,8 +1245,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA)
ee->fault_reg = intel_uncore_read(engine->uncore,
XELPMP_RING_FAULT_REG);
-
- else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
ee->fault_reg = intel_gt_mcr_read_any(engine->gt,
XEHP_RING_FAULT_REG);
else if (GRAPHICS_VER(i915) >= 12)
@@ -1852,7 +1851,7 @@ static void gt_record_global_regs(struct intel_gt_coredump *gt)
if (GRAPHICS_VER(i915) == 7)
gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
XEHP_FAULT_TLB_DATA0);
gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b318b7c6bf73..8b673fdcf178 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -705,8 +705,6 @@ static const struct intel_device_info adl_p_info = {
I915_GTT_PAGE_SIZE_2M
#define XE_HP_FEATURES \
- .__runtime.graphics.ip.ver = 12, \
- .__runtime.graphics.ip.rel = 50, \
XE_HP_PAGE_SIZES, \
TGL_CACHELEVEL, \
.dma_mask_size = 46, \
@@ -730,15 +728,12 @@ static const struct intel_device_info adl_p_info = {
.__runtime.ppgtt_size = 48, \
.__runtime.ppgtt_type = INTEL_PPGTT_FULL
-#define XE_HPM_FEATURES \
- .__runtime.media.ip.ver = 12, \
- .__runtime.media.ip.rel = 50
-
#define DG2_FEATURES \
XE_HP_FEATURES, \
- XE_HPM_FEATURES, \
DGFX_FEATURES, \
+ .__runtime.graphics.ip.ver = 12, \
.__runtime.graphics.ip.rel = 55, \
+ .__runtime.media.ip.ver = 12, \
.__runtime.media.ip.rel = 55, \
PLATFORM(INTEL_DG2), \
.has_64k_pages = 1, \
@@ -773,9 +768,10 @@ static const struct intel_device_info ats_m_info = {
__maybe_unused
static const struct intel_device_info pvc_info = {
XE_HPC_FEATURES,
- XE_HPM_FEATURES,
DGFX_FEATURES,
+ .__runtime.graphics.ip.ver = 12,
.__runtime.graphics.ip.rel = 60,
+ .__runtime.media.ip.ver = 12,
.__runtime.media.ip.rel = 60,
PLATFORM(INTEL_PONTEVECCHIO),
.has_flat_ccs = 0,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1637c1d235e9..a7d86529033a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -292,7 +292,7 @@ static u32 i915_perf_stream_paranoid = true;
#define OAREPORT_REASON_CTX_SWITCH (1<<3)
#define OAREPORT_REASON_CLK_RATIO (1<<5)
-#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
/* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
*
@@ -817,7 +817,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
*/
if (oa_report_ctx_invalid(stream, report) &&
- GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 50)) {
+ GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 55)) {
ctx_id = INVALID_CTX_ID;
oa_context_id_squash(stream, report32);
}
@@ -1419,7 +1419,7 @@ static int gen12_get_render_context_id(struct i915_perf_stream *stream)
mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
(GEN12_GUC_SW_CTX_ID_SHIFT - 32);
- } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
+ } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 55)) {
ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
(XEHP_SW_CTX_ID_SHIFT - 32);
@@ -4122,7 +4122,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
props->hold_preemption = !!value;
break;
case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
- if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 55)) {
drm_dbg(&perf->i915->drm,
"SSEU config not supported on gfx %x\n",
GRAPHICS_VER_FULL(perf->i915));
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 3baa2f54a86e..14d9ec0ed777 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -105,7 +105,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,
struct intel_engine_cs *engine;
struct i915_engine_class_instance classinstance;
- if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
return -ENODEV;
classinstance = *((struct i915_engine_class_instance *)&query_item->flags);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 4f1e56187442..0ceb4b50e349 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2721,7 +2721,7 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
* the forcewake domain if any of the other engines
* in the same media slice are present.
*/
- if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) {
+ if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 55) && i % 2 == 0) {
if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1)))
continue;
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/5] drm/i915: Drop dead code for pvc
2024-03-06 19:36 [PATCH 0/5] drm/i915: cleanup dead code Lucas De Marchi
` (2 preceding siblings ...)
2024-03-06 19:36 ` [PATCH 3/5] drm/i915: Update IP_VER(12, 50) Lucas De Marchi
@ 2024-03-06 19:36 ` Lucas De Marchi
2024-03-11 15:29 ` Rodrigo Vivi
2024-03-06 19:36 ` [PATCH 5/5] drm/i915: Remove special handling for !RCS_MASK() Lucas De Marchi
2024-03-11 17:43 ` [PATCH 0/5] drm/i915: cleanup dead code Tvrtko Ursulin
5 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-06 19:36 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Lucas De Marchi
PCI IDs for PVC were never added and platform always marked with
force_probe. Drop what's not used and rename some places as needed.
The registers not used anymore are also removed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ----
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 30 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 9 --
drivers/gpu/drm/i915/gt/intel_mocs.c | 19 ---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 9 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 90 +----------
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 12 --
drivers/gpu/drm/i915/i915_drv.h | 9 --
drivers/gpu/drm/i915/i915_pci.c | 36 -----
drivers/gpu/drm/i915/i915_reg.h | 1 -
drivers/gpu/drm/i915/intel_clock_gating.c | 16 +-
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_step.c | 70 +--------
drivers/gpu/drm/i915/intel_uncore.c | 142 ------------------
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 -
| 4 -
21 files changed, 12 insertions(+), 485 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0c5cdab278b6..d3300ae3053f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -386,7 +386,7 @@ struct drm_i915_gem_object {
* and kernel mode driver for caching policy control after GEN12.
* In the meantime platform specific tables are created to translate
* i915_cache_level into pat index, for more details check the macros
- * defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.
+ * defined i915/i915_pci.c, e.g. MTL_CACHELEVEL.
* For backward compatibility, this field contains values exactly match
* the entries of enum i915_cache_level for pre-GEN12 platforms (See
* LEGACY_CACHELEVEL), so that the PTE encode functions for these
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 24d1c28201fa..2e27bcb52e0d 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -189,9 +189,6 @@ static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine)
{
i915_reg_t reg = gen12_get_aux_inv_reg(engine);
- if (IS_PONTEVECCHIO(engine->i915))
- return false;
-
/*
* So far platforms supported by i915 having flat ccs do not require
* AUX invalidation. Check also whether the engine requires it.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 75bde8c1aa5d..396f5fe993c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -839,38 +839,6 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
}
}
-static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
-{
- struct drm_i915_private *i915 = gt->i915;
- struct intel_gt_info *info = >->info;
- unsigned long meml3_mask;
- unsigned long quad;
-
- if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
- GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
- return;
-
- meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
- meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
-
- /*
- * Link Copy engines may be fused off according to meml3_mask. Each
- * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
- */
- for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
- unsigned int instance = quad * 2 + 1;
- intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
- _BCS(instance));
-
- if (mask & info->engine_mask) {
- gt_dbg(gt, "bcs%u fused off\n", instance);
- gt_dbg(gt, "bcs%u fused off\n", instance + 1);
-
- info->engine_mask &= ~mask;
- }
- }
-}
-
/*
* Determine which engines are fused off in our particular hardware.
* Note that we have a catch-22 situation where we need to be able to access
@@ -889,7 +857,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
engine_mask_apply_media_fuses(gt);
engine_mask_apply_compute_fuses(gt);
- engine_mask_apply_copy_fuses(gt);
/*
* The only use of the GSC CS is to load and communicate with the GSC
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 29443bf7c06c..b8912bd6c08e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -69,27 +69,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-/*
- * We have several types of MCR registers on PVC where steering to (0,0)
- * will always provide us with a non-terminated value. We'll stick them
- * all in the same table for simplicity.
- */
-static const struct intel_mmio_range pvc_instance0_steering_table[] = {
- { 0x004000, 0x004AFF }, /* HALF-BSLICE */
- { 0x008800, 0x00887F }, /* CC */
- { 0x008A80, 0x008AFF }, /* TILEPSMI */
- { 0x00B000, 0x00B0FF }, /* HALF-BSLICE */
- { 0x00B100, 0x00B3FF }, /* L3BANK */
- { 0x00C800, 0x00CFFF }, /* HALF-BSLICE */
- { 0x00D800, 0x00D8FF }, /* HALF-BSLICE */
- { 0x00DD00, 0x00DDFF }, /* BSLICE */
- { 0x00E900, 0x00E9FF }, /* HALF-BSLICE */
- { 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */
- { 0x00F000, 0x00FFFF }, /* HALF-BSLICE */
- { 0x024180, 0x0241FF }, /* HALF-BSLICE */
- {},
-};
-
static const struct intel_mmio_range xelpg_instance0_steering_table[] = {
{ 0x000B00, 0x000BFF }, /* SQIDI */
{ 0x001000, 0x001FFF }, /* SQIDI */
@@ -173,8 +152,6 @@ void intel_gt_mcr_init(struct intel_gt *gt)
gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table;
gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;
gt->steering_table[DSS] = xelpg_dss_steering_table;
- } else if (IS_PONTEVECCHIO(i915)) {
- gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
} else if (IS_DG2(i915)) {
gt->steering_table[MSLICE] = dg2_mslice_steering_table;
gt->steering_table[LNCF] = dg2_lncf_steering_table;
@@ -805,8 +782,6 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
for (int i = 0; i < NUM_STEERING_TYPES; i++)
if (gt->steering_table[i])
report_steering_type(p, gt, i, dump_table);
- } else if (IS_PONTEVECCHIO(gt->i915)) {
- report_steering_type(p, gt, INSTANCE0, dump_table);
} else if (HAS_MSLICE_STEERING(gt->i915)) {
report_steering_type(p, gt, MSLICE, dump_table);
report_steering_type(p, gt, LNCF, dump_table);
@@ -826,10 +801,7 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
unsigned int *group, unsigned int *instance)
{
- if (IS_PONTEVECCHIO(gt->i915)) {
- *group = dss / GEN_DSS_PER_CSLICE;
- *instance = dss % GEN_DSS_PER_CSLICE;
- } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
*group = dss / GEN_DSS_PER_GSLICE;
*instance = dss % GEN_DSS_PER_GSLICE;
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 919c07903767..8d8d781b44b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -953,10 +953,6 @@
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
#define GEN7_L3AGDIS (1 << 19)
-#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c)
-#define XEHPC_HOSTCACHEEN REG_BIT(1)
-#define XEHPC_OVRLSCCC REG_BIT(0)
-
#define GEN7_L3CNTLREG2 _MMIO(0xb020)
/* MOCS (Memory Object Control State) registers */
@@ -1013,11 +1009,6 @@
#define XEHP_L3SCQREG7 MCR_REG(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
-#define XEHPC_L3SCRUB MCR_REG(0xb18c)
-#define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12)
-#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
-#define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
-
#define GEN11_GLBLINVL _MMIO(0xb404)
#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 9fac5e2318e2..d791d63d49b4 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -53,7 +53,6 @@ struct drm_i915_mocs_table {
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
-#define PVC_NUM_MOCS_ENTRIES 3
#define MTL_NUM_MOCS_ENTRIES 16
/* (e)LLC caching options */
@@ -379,17 +378,6 @@ static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
};
-static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
- /* Error */
- MOCS_ENTRY(0, 0, L3_3_WB),
-
- /* UC */
- MOCS_ENTRY(1, 0, L3_1_UC),
-
- /* WB */
- MOCS_ENTRY(2, 0, L3_3_WB),
-};
-
static const struct drm_i915_mocs_entry mtl_mocs_table[] = {
/* Error - Reserved for Non-Use */
MOCS_ENTRY(0,
@@ -476,13 +464,6 @@ static unsigned int get_mocs_settings(struct drm_i915_private *i915,
table->n_entries = MTL_NUM_MOCS_ENTRIES;
table->uc_index = 9;
table->unused_entries_index = 1;
- } else if (IS_PONTEVECCHIO(i915)) {
- table->size = ARRAY_SIZE(pvc_mocs_table);
- table->table = pvc_mocs_table;
- table->n_entries = PVC_NUM_MOCS_ENTRIES;
- table->uc_index = 1;
- table->wb_index = 2;
- table->unused_entries_index = 2;
} else if (IS_DG2(i915)) {
table->size = ARRAY_SIZE(dg2_mocs_table);
table->table = dg2_mocs_table;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 2a6a8134782d..b4d2f80ed609 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1086,9 +1086,7 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
struct drm_i915_private *i915 = rps_to_i915(rps);
struct intel_uncore *uncore = rps_to_uncore(rps);
- if (IS_PONTEVECCHIO(i915))
- return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
- else if (IS_GEN9_LP(i915))
+ if (IS_GEN9_LP(i915))
return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
else
return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 5eec9cd6199f..c8fadf58d836 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -214,13 +214,8 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
int num_compute_regs, num_geometry_regs;
int eu;
- if (IS_PONTEVECCHIO(gt->i915)) {
- num_geometry_regs = 0;
- num_compute_regs = 2;
- } else {
- num_geometry_regs = 1;
- num_compute_regs = 1;
- }
+ num_geometry_regs = 1;
+ num_compute_regs = 1;
/*
* The concept of slice has been removed in Xe_HP. To be compatible
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 750bf08ee7c1..13a316acef61 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -257,12 +257,6 @@ wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
wa_write_clr_set(wal, reg, ~0, set);
}
-static void
-wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
-{
- wa_mcr_write_clr_set(wal, reg, ~0, set);
-}
-
static void
wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
{
@@ -918,8 +912,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_ctx_workarounds_init(engine, wal);
- else if (IS_PONTEVECCHIO(i915))
- ; /* noop; none at this time */
else if (IS_DG2(i915))
dg2_ctx_workarounds_init(engine, wal);
else if (IS_DG1(i915))
@@ -1374,20 +1366,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
__set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0);
}
-static void
-pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
-{
- unsigned int dss;
-
- /*
- * Setup implicit steering for COMPUTE and DSS ranges to the first
- * non-fused-off DSS. All other types of MCR registers will be
- * explicitly steered.
- */
- dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0);
- __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE);
-}
-
static void
icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
@@ -1556,24 +1534,6 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
}
-static void
-pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
-{
- pvc_init_mcr(gt, wal);
-
- /* Wa_14015795083 */
- wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
-
- /* Wa_18018781329 */
- wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
-
- /* Wa_16016694945 */
- wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
-}
-
static void
xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
@@ -1649,12 +1609,6 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
}
- if (IS_PONTEVECCHIO(gt->i915)) {
- wa_mcr_write(wal, XEHPC_L3SCRUB,
- SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
- wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
- }
-
if (IS_DG2(gt->i915)) {
wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
@@ -1679,8 +1633,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_gt_workarounds_init(gt, wal);
- else if (IS_PONTEVECCHIO(i915))
- pvc_gt_workarounds_init(gt, wal);
else if (IS_DG2(i915))
dg2_gt_workarounds_init(gt, wal);
else if (IS_DG1(i915))
@@ -2100,30 +2052,6 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine)
}
}
-static void blacklist_trtt(struct intel_engine_cs *engine)
-{
- struct i915_wa_list *w = &engine->whitelist;
-
- /*
- * Prevent read/write access to [0x4400, 0x4600) which covers
- * the TRTT range across all engines. Note that normally userspace
- * cannot access the other engines' trtt control, but for simplicity
- * we cover the entire range on each engine.
- */
- whitelist_reg_ext(w, _MMIO(0x4400),
- RING_FORCE_TO_NONPRIV_DENY |
- RING_FORCE_TO_NONPRIV_RANGE_64);
- whitelist_reg_ext(w, _MMIO(0x4500),
- RING_FORCE_TO_NONPRIV_DENY |
- RING_FORCE_TO_NONPRIV_RANGE_64);
-}
-
-static void pvc_whitelist_build(struct intel_engine_cs *engine)
-{
- /* Wa_16014440446:pvc */
- blacklist_trtt(engine);
-}
-
static void xelpg_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;
@@ -2150,8 +2078,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
; /* none yet */
else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
xelpg_whitelist_build(engine);
- else if (IS_PONTEVECCHIO(i915))
- pvc_whitelist_build(engine);
else if (IS_DG2(i915))
dg2_whitelist_build(engine);
else if (GRAPHICS_VER(i915) == 12)
@@ -2731,13 +2657,10 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
XEHP_BLITTER_ROUND_ROBIN_MODE);
}
-static void
+__maybe_unused static void
ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
- if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) {
- /* Wa_14014999345:pvc */
- wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
- }
+ /* boilerplate for any CCS engine workaround */
}
/*
@@ -2843,14 +2766,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
- IS_PONTEVECCHIO(i915) ||
IS_DG2(i915)) {
/* Wa_22014226127 */
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
}
- if (IS_PONTEVECCHIO(i915) || IS_DG2(i915))
- /* Wa_14015227452:dg2,pvc */
+ if (IS_DG2(i915))
+ /* Wa_14015227452 */
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
if (IS_DG2(i915)) {
@@ -2907,9 +2829,7 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
general_render_compute_wa_init(engine, wal);
- if (engine->class == COMPUTE_CLASS)
- ccs_engine_wa_init(engine, wal);
- else if (engine->class == RENDER_CLASS)
+ if (engine->class == RENDER_CLASS)
rcs_engine_wa_init(engine, wal);
else
xcs_engine_wa_init(engine, wal);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 28277321d9ca..b47051ddf17f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -50,10 +50,6 @@ static void uc_expand_default_options(struct intel_uc *uc)
/* Default: enable HuC authentication and GuC submission */
i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
-
- /* PVC does not use HuC */
- if (IS_PONTEVECCHIO(i915))
- i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
}
/* Reset GuC providing us with fresh state for both GuC and HuC.
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 990eaa029d9c..24c78873b3cf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -156,18 +156,6 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
case 4: return " WB (2-Way Coh)";
default: return " not defined";
}
- } else if (IS_PONTEVECCHIO(i915)) {
- switch (obj->pat_index) {
- case 0: return " UC";
- case 1: return " WC";
- case 2: return " WT";
- case 3: return " WB";
- case 4: return " WT (CLOS1)";
- case 5: return " WB (CLOS1)";
- case 6: return " WT (CLOS2)";
- case 7: return " WT (CLOS2)";
- default: return " not defined";
- }
} else if (GRAPHICS_VER(i915) >= 12) {
switch (obj->pat_index) {
case 0: return " WB";
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dff056587459..cf52d4adaa20 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -545,7 +545,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
-#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
#define IS_LUNARLAKE(i915) 0
@@ -620,14 +619,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TIGERLAKE_UY(i915) \
IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
-#define IS_PVC_BD_STEP(__i915, since, until) \
- (IS_PONTEVECCHIO(__i915) && \
- IS_BASEDIE_STEP(__i915, since, until))
-
-#define IS_PVC_CT_STEP(__i915, since, until) \
- (IS_PONTEVECCHIO(__i915) && \
- IS_GRAPHICS_STEP(__i915, since, until))
-
#define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8b673fdcf178..1e69783ae4fd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -59,14 +59,6 @@
[I915_CACHE_WT] = 2, \
}
-#define PVC_CACHELEVEL \
- .cachelevel_to_pat = { \
- [I915_CACHE_NONE] = 0, \
- [I915_CACHE_LLC] = 3, \
- [I915_CACHE_L3_LLC] = 3, \
- [I915_CACHE_WT] = 2, \
- }
-
#define MTL_CACHELEVEL \
.cachelevel_to_pat = { \
[I915_CACHE_NONE] = 2, \
@@ -756,34 +748,6 @@ static const struct intel_device_info ats_m_info = {
.tuning_thread_rr_after_dep = 1,
};
-#define XE_HPC_FEATURES \
- XE_HP_FEATURES, \
- .dma_mask_size = 52, \
- .has_3d_pipeline = 0, \
- .has_guc_deprivilege = 1, \
- .has_l3_ccs_read = 1, \
- .has_mslice_steering = 0, \
- .has_one_eu_per_fuse_bit = 1
-
-__maybe_unused
-static const struct intel_device_info pvc_info = {
- XE_HPC_FEATURES,
- DGFX_FEATURES,
- .__runtime.graphics.ip.ver = 12,
- .__runtime.graphics.ip.rel = 60,
- .__runtime.media.ip.ver = 12,
- .__runtime.media.ip.rel = 60,
- PLATFORM(INTEL_PONTEVECCHIO),
- .has_flat_ccs = 0,
- .max_pat_index = 7,
- .platform_engine_mask =
- BIT(BCS0) |
- BIT(VCS0) |
- BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
- .require_force_probe = 1,
- PVC_CACHELEVEL,
-};
-
static const struct intel_gt_definition xelpmp_extra_gt[] = {
{
.type = GT_MEDIA,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a120c17aafcc..f8d93bc638fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1750,7 +1750,6 @@
#define BXT_RP_STATE_CAP _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
-#define PVC_RP_STATE_CAP _MMIO(0x281014)
#define MTL_RP_STATE_CAP _MMIO(0x138000)
#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 93ab44190a47..be355c1fefc6 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -356,17 +356,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
SGSI_SIDECLK_DIS);
}
-static void pvc_init_clock_gating(struct drm_i915_private *i915)
-{
- /* Wa_14012385139:pvc */
- if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
- intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
-
- /* Wa_22010954014:pvc */
- if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
- intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
-}
-
static void cnp_init_clock_gating(struct drm_i915_private *i915)
{
if (!HAS_PCH_CNP(i915))
@@ -755,7 +744,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs =
.init_clock_gating = platform##_init_clock_gating, \
}
-CG_FUNCS(pvc);
CG_FUNCS(dg2);
CG_FUNCS(cfl);
CG_FUNCS(skl);
@@ -789,9 +777,7 @@ CG_FUNCS(nop);
*/
void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
{
- if (IS_PONTEVECCHIO(i915))
- i915->clock_gating_funcs = &pvc_clock_gating_funcs;
- else if (IS_DG2(i915))
+ if (IS_DG2(i915))
i915->clock_gating_funcs = &dg2_clock_gating_funcs;
else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
i915->clock_gating_funcs = &cfl_clock_gating_funcs;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index de28cbe758f7..a0a43ea07f11 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -71,7 +71,6 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ALDERLAKE_S),
PLATFORM_NAME(ALDERLAKE_P),
PLATFORM_NAME(DG2),
- PLATFORM_NAME(PONTEVECCHIO),
PLATFORM_NAME(METEORLAKE),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 2299327e59f0..d1a2abc7e513 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -88,7 +88,6 @@ enum intel_platform {
INTEL_ALDERLAKE_S,
INTEL_ALDERLAKE_P,
INTEL_DG2,
- INTEL_PONTEVECCHIO,
INTEL_METEORLAKE,
INTEL_MAX_PLATFORMS
};
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index d524bfe17c27..a5adfb5d8fd2 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -146,8 +146,6 @@ static u8 gmd_to_intel_step(struct drm_i915_private *i915,
return step;
}
-static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
-
void intel_step_init(struct drm_i915_private *i915)
{
const struct intel_step_info *revids = NULL;
@@ -171,10 +169,7 @@ void intel_step_init(struct drm_i915_private *i915)
return;
}
- if (IS_PONTEVECCHIO(i915)) {
- pvc_step_init(i915, revid);
- return;
- } else if (IS_DG2_G10(i915)) {
+ if (IS_DG2_G10(i915)) {
revids = dg2_g10_revid_step_tbl;
size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
} else if (IS_DG2_G11(i915)) {
@@ -267,69 +262,6 @@ void intel_step_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->step = step;
}
-#define PVC_BD_REVID GENMASK(5, 3)
-#define PVC_CT_REVID GENMASK(2, 0)
-
-static const int pvc_bd_subids[] = {
- [0x0] = STEP_A0,
- [0x3] = STEP_B0,
- [0x4] = STEP_B1,
- [0x5] = STEP_B3,
-};
-
-static const int pvc_ct_subids[] = {
- [0x3] = STEP_A0,
- [0x5] = STEP_B0,
- [0x6] = STEP_B1,
- [0x7] = STEP_C0,
-};
-
-static int
-pvc_step_lookup(struct drm_i915_private *i915, const char *type,
- const int *table, int size, int subid)
-{
- if (subid < size && table[subid] != STEP_NONE)
- return table[subid];
-
- drm_warn(&i915->drm, "Unknown %s id 0x%02x\n", type, subid);
-
- /*
- * As on other platforms, try to use the next higher ID if we land on a
- * gap in the table.
- */
- while (subid < size && table[subid] == STEP_NONE)
- subid++;
-
- if (subid < size) {
- drm_dbg(&i915->drm, "Using steppings for %s id 0x%02x\n",
- type, subid);
- return table[subid];
- }
-
- drm_dbg(&i915->drm, "Using future steppings\n");
- return STEP_FUTURE;
-}
-
-/*
- * PVC needs special handling since we don't lookup the
- * revid in a table, but rather specific bitfields within
- * the revid for various components.
- */
-static void pvc_step_init(struct drm_i915_private *i915, int pci_revid)
-{
- int ct_subid, bd_subid;
-
- bd_subid = FIELD_GET(PVC_BD_REVID, pci_revid);
- ct_subid = FIELD_GET(PVC_CT_REVID, pci_revid);
-
- RUNTIME_INFO(i915)->step.basedie_step =
- pvc_step_lookup(i915, "Base Die", pvc_bd_subids,
- ARRAY_SIZE(pvc_bd_subids), bd_subid);
- RUNTIME_INFO(i915)->step.graphics_step =
- pvc_step_lookup(i915, "Compute Tile", pvc_ct_subids,
- ARRAY_SIZE(pvc_ct_subids), ct_subid);
-}
-
#define STEP_NAME_CASE(name) \
case STEP_##name: \
return #name;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0ceb4b50e349..756c44fa4462 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1106,45 +1106,6 @@ static const struct i915_range dg2_shadowed_regs[] = {
{ .start = 0x1F8510, .end = 0x1F8550 },
};
-static const struct i915_range pvc_shadowed_regs[] = {
- { .start = 0x2030, .end = 0x2030 },
- { .start = 0x2510, .end = 0x2550 },
- { .start = 0xA008, .end = 0xA00C },
- { .start = 0xA188, .end = 0xA188 },
- { .start = 0xA278, .end = 0xA278 },
- { .start = 0xA540, .end = 0xA56C },
- { .start = 0xC4C8, .end = 0xC4C8 },
- { .start = 0xC4E0, .end = 0xC4E0 },
- { .start = 0xC600, .end = 0xC600 },
- { .start = 0xC658, .end = 0xC658 },
- { .start = 0x22030, .end = 0x22030 },
- { .start = 0x22510, .end = 0x22550 },
- { .start = 0x1C0030, .end = 0x1C0030 },
- { .start = 0x1C0510, .end = 0x1C0550 },
- { .start = 0x1C4030, .end = 0x1C4030 },
- { .start = 0x1C4510, .end = 0x1C4550 },
- { .start = 0x1C8030, .end = 0x1C8030 },
- { .start = 0x1C8510, .end = 0x1C8550 },
- { .start = 0x1D0030, .end = 0x1D0030 },
- { .start = 0x1D0510, .end = 0x1D0550 },
- { .start = 0x1D4030, .end = 0x1D4030 },
- { .start = 0x1D4510, .end = 0x1D4550 },
- { .start = 0x1D8030, .end = 0x1D8030 },
- { .start = 0x1D8510, .end = 0x1D8550 },
- { .start = 0x1E0030, .end = 0x1E0030 },
- { .start = 0x1E0510, .end = 0x1E0550 },
- { .start = 0x1E4030, .end = 0x1E4030 },
- { .start = 0x1E4510, .end = 0x1E4550 },
- { .start = 0x1E8030, .end = 0x1E8030 },
- { .start = 0x1E8510, .end = 0x1E8550 },
- { .start = 0x1F0030, .end = 0x1F0030 },
- { .start = 0x1F0510, .end = 0x1F0550 },
- { .start = 0x1F4030, .end = 0x1F4030 },
- { .start = 0x1F4510, .end = 0x1F4550 },
- { .start = 0x1F8030, .end = 0x1F8030 },
- { .start = 0x1F8510, .end = 0x1F8550 },
-};
-
static const struct i915_range mtl_shadowed_regs[] = {
{ .start = 0x2030, .end = 0x2030 },
{ .start = 0x2510, .end = 0x2550 },
@@ -1626,105 +1587,6 @@ static const struct intel_forcewake_range __dg2_fw_ranges[] = {
XEHP_FWRANGES(FORCEWAKE_RENDER)
};
-static const struct intel_forcewake_range __pvc_fw_ranges[] = {
- GEN_FW_RANGE(0x0, 0xaff, 0),
- GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
- GEN_FW_RANGE(0xc00, 0xfff, 0),
- GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
- 0x4000 - 0x4aff: gt
- 0x4b00 - 0x4fff: reserved
- 0x5000 - 0x51ff: gt
- 0x5200 - 0x52ff: reserved
- 0x5300 - 0x53ff: gt
- 0x5400 - 0x7fff: reserved
- 0x8000 - 0x813f: gt */
- GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8180, 0x81ff, 0),
- GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
- 0x8200 - 0x82ff: gt
- 0x8300 - 0x84ff: reserved
- 0x8500 - 0x887f: gt
- 0x8880 - 0x8a7f: reserved
- 0x8a80 - 0x8aff: gt
- 0x8b00 - 0x8fff: reserved
- 0x9000 - 0x947f: gt
- 0x9480 - 0x94cf: reserved */
- GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x9560, 0x967f, 0), /*
- 0x9560 - 0x95ff: always on
- 0x9600 - 0x967f: reserved */
- GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
- 0x9680 - 0x96ff: render
- 0x9700 - 0x97ff: reserved */
- GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
- 0x9800 - 0xb4ff: gt
- 0xb500 - 0xbfff: reserved
- 0xc000 - 0xcfff: gt */
- GEN_FW_RANGE(0xd000, 0xd3ff, 0),
- GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT),
- GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
- 0xdd00 - 0xddff: gt
- 0xde00 - 0xde7f: reserved */
- GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
- 0xde80 - 0xdeff: render
- 0xdf00 - 0xe1ff: reserved
- 0xe200 - 0xe7ff: render
- 0xe800 - 0xe8ff: reserved */
- GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
- 0xe900 - 0xe9ff: gt
- 0xea00 - 0xebff: reserved
- 0xec00 - 0xffff: gt
- 0x10000 - 0x11fff: reserved */
- GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
- 0x12000 - 0x127ff: always on
- 0x12800 - 0x12fff: reserved */
- GEN_FW_RANGE(0x13000, 0x19fff, FORCEWAKE_GT), /*
- 0x13000 - 0x135ff: gt
- 0x13600 - 0x147ff: reserved
- 0x14800 - 0x153ff: gt
- 0x15400 - 0x19fff: reserved */
- GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /*
- 0x1a000 - 0x1ffff: render
- 0x20000 - 0x21fff: reserved */
- GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
- 24000 - 0x2407f: always on
- 24080 - 0x2417f: reserved */
- GEN_FW_RANGE(0x24180, 0x25fff, FORCEWAKE_GT), /*
- 0x24180 - 0x241ff: gt
- 0x24200 - 0x251ff: reserved
- 0x25200 - 0x252ff: gt
- 0x25300 - 0x25fff: reserved */
- GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
- 0x26000 - 0x27fff: render
- 0x28000 - 0x2ffff: reserved */
- GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x40000, 0x1bffff, 0),
- GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
- 0x1c0000 - 0x1c2bff: VD0
- 0x1c2c00 - 0x1c2cff: reserved
- 0x1c2d00 - 0x1c2dff: VD0
- 0x1c2e00 - 0x1c3eff: reserved
- 0x1c3f00 - 0x1c3fff: VD0 */
- GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
- 0x1c4000 - 0x1c6aff: VD1
- 0x1c6b00 - 0x1c7eff: reserved
- 0x1c7f00 - 0x1c7fff: VD1
- 0x1c8000 - 0x1cffff: reserved */
- GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
- 0x1d0000 - 0x1d2aff: VD2
- 0x1d2b00 - 0x1d3eff: reserved
- 0x1d3f00 - 0x1d3fff: VD2
- 0x1d4000 - 0x23ffff: reserved */
- GEN_FW_RANGE(0x240000, 0x3dffff, 0),
- GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT),
-};
-
static const struct intel_forcewake_range __mtl_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, 0),
GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
@@ -2567,10 +2429,6 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
ASSIGN_FW_DOMAINS_TABLE(uncore, __mtl_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, mtl_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
- } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) {
- ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges);
- ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 502bcadc5f39..41eaa9b7f67d 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -71,7 +71,6 @@ static int intel_shadow_table_check(void)
{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
{ dg2_shadowed_regs, ARRAY_SIZE(dg2_shadowed_regs) },
- { pvc_shadowed_regs, ARRAY_SIZE(pvc_shadowed_regs) },
{ mtl_shadowed_regs, ARRAY_SIZE(mtl_shadowed_regs) },
{ xelpmp_shadowed_regs, ARRAY_SIZE(xelpmp_shadowed_regs) },
};
@@ -119,7 +118,6 @@ int intel_uncore_mock_selftests(void)
{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
- { __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
{ __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
{ __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
};
--git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index a7e7ec3b5db9..a01d1b869c2d 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -86,7 +86,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)
#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
-#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
@@ -130,9 +129,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
IS_GRAPHICS_STEP(xe, first, last))
-/* XXX: No basedie stepping support yet */
-#define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) && IS_PONTEVECCHIO(xe))
-
#define IS_TIGERLAKE_DISPLAY_STEP(xe, first, last) (IS_TIGERLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
#define IS_ROCKETLAKE_DISPLAY_STEP(xe, first, last) (IS_ROCKETLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
#define IS_DG1_DISPLAY_STEP(xe, first, last) (IS_DG1(xe) && IS_DISPLAY_STEP(xe, first, last))
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 5/5] drm/i915: Remove special handling for !RCS_MASK()
2024-03-06 19:36 [PATCH 0/5] drm/i915: cleanup dead code Lucas De Marchi
` (3 preceding siblings ...)
2024-03-06 19:36 ` [PATCH 4/5] drm/i915: Drop dead code for pvc Lucas De Marchi
@ 2024-03-06 19:36 ` Lucas De Marchi
2024-03-11 17:43 ` [PATCH 0/5] drm/i915: cleanup dead code Tvrtko Ursulin
5 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-06 19:36 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Lucas De Marchi
With both XEHPSDV and PVC removed (as platforms, most of their code
remain used by others), there's no need to handle !RCS_MASK() as
other platforms don't ever have fused-off render. Remove those code
paths and the special WA flag when initializing GuC.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 ++---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 ----
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 -
3 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 396f5fe993c3..476651bd0a21 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -497,9 +497,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
engine->logical_mask = BIT(logical_instance);
__sprint_engine_name(engine);
- if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
- __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
- engine->class == RENDER_CLASS)
+ if ((engine->class == COMPUTE_CLASS || engine->class == RENDER_CLASS) &&
+ __ffs(CCS_MASK(engine->gt) | RCS_MASK(engine->gt)) == engine->instance)
engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
/* features common between engines sharing EUs */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index da6cc268e7b2..bcc7d5c74192 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -315,10 +315,6 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (IS_DG2_G11(gt->i915))
flags |= GUC_WA_CONTEXT_ISOLATION;
- /* Wa_18020744125 */
- if (!RCS_MASK(gt))
- flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
-
/*
* Wa_14018913170: Applicable to all platforms supported by i915 so
* don't bother testing for all X/Y/Z platforms explicitly.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 8ae1846431da..0e4060adcf14 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -100,7 +100,6 @@
#define GUC_WA_PRE_PARSER BIT(14)
#define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
#define GUC_WA_POLLCS BIT(18)
-#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
#define GUC_WA_ENABLE_TSC_CHECK_ON_RC6 BIT(22)
#define GUC_CTL_FEATURE 2
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv
2024-03-06 19:36 ` [PATCH 2/5] drm/i915: Drop dead code for xehpsdv Lucas De Marchi
@ 2024-03-11 15:16 ` Rodrigo Vivi
2024-03-12 16:29 ` Lucas De Marchi
2024-03-12 22:58 ` Matt Roper
1 sibling, 1 reply; 22+ messages in thread
From: Rodrigo Vivi @ 2024-03-11 15:16 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:
> PCI IDs for XEHPSDV were never added and platform always marked with
> force_probe. Drop what's not used and rename some places to either be
> xehp or dg2, depending on the platform/IP checks.
>
> The registers not used anymore are also removed.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>
> Potential problem here that needs a deeper look, the changes in
> __gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
> I removed them, but it needs to be double checked with spec and CI
> results.
I have checked the specs and your patch looks right because those
bits should be reserved for DG2.
But the main issue I see is that we were using that (wrongly?) for
DG2 so far. So it probably deserves a separate patch anyway.
With this patch only removing the comments and a separate patch
to remove that for DG2 (and standalone CI run on that patch by itself):
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Documentation/gpu/rfc/i915_vm_bind.h | 11 +--
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40 ++++----
> drivers/gpu/drm/i915/gt/intel_gsc.c | 15 ---
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 20 +---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 50 ----------
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 ++--
> drivers/gpu/drm/i915/gt/intel_lrc.c | 43 ---------
> drivers/gpu/drm/i915/gt/intel_migrate.c | 18 ++--
> drivers/gpu/drm/i915/gt/intel_mocs.c | 31 ------
> drivers/gpu/drm/i915/gt/intel_rps.c | 2 -
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 -------------------
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 -
> drivers/gpu/drm/i915/i915_hwmon.c | 6 --
> drivers/gpu/drm/i915/i915_pci.c | 17 ----
> drivers/gpu/drm/i915/i915_perf.c | 11 +--
> drivers/gpu/drm/i915/i915_reg.h | 3 +-
> drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
> drivers/gpu/drm/i915/intel_device_info.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> drivers/gpu/drm/i915/intel_step.c | 10 --
> drivers/gpu/drm/i915/intel_uncore.c | 15 +--
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 1 -
> .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 -
> 24 files changed, 51 insertions(+), 380 deletions(-)
>
> diff --git a/Documentation/gpu/rfc/i915_vm_bind.h b/Documentation/gpu/rfc/i915_vm_bind.h
> index 8a8fcd4fceac..bc26dc126104 100644
> --- a/Documentation/gpu/rfc/i915_vm_bind.h
> +++ b/Documentation/gpu/rfc/i915_vm_bind.h
> @@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
> * Multiple VA mappings can be created to the same section of the object
> * (aliasing).
> *
> - * The @start, @offset and @length must be 4K page aligned. However the DG2
> - * and XEHPSDV has 64K page size for device local memory and has compact page
> - * table. On those platforms, for binding device local-memory objects, the
> - * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
> - * the local memory 64K page and the system memory 4K page bindings in the same
> - * 2M range.
> + * The @start, @offset and @length must be 4K page aligned. However the DG2 has
> + * 64K page size for device local memory and has compact page table. On that
> + * platform, for binding device local-memory objects, the @start, @offset and
> + * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K
> + * page and the system memory 4K page bindings in the same 2M range.
> *
> * Error code -EINVAL will be returned if @start, @offset and @length are not
> * properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index fa46d2308b0e..1bd0e041e15c 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
> }
>
> static void
> -xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
> - struct i915_vma_resource *vma_res,
> - struct sgt_dma *iter,
> - unsigned int pat_index,
> - u32 flags)
> +xehp_ppgtt_insert_huge(struct i915_address_space *vm,
> + struct i915_vma_resource *vma_res,
> + struct sgt_dma *iter,
> + unsigned int pat_index,
> + u32 flags)
> {
> const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
> unsigned int rem = sg_dma_len(iter->sg);
> @@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
> struct sgt_dma iter = sgt_dma(vma_res);
>
> if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
> - if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
> - xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
> + if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
> + xehp_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
> else
> gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
> } else {
> @@ -781,11 +781,11 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
> drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
> }
>
> -static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
> - dma_addr_t addr,
> - u64 offset,
> - unsigned int pat_index,
> - u32 flags)
> +static void xehp_ppgtt_insert_entry_lm(struct i915_address_space *vm,
> + dma_addr_t addr,
> + u64 offset,
> + unsigned int pat_index,
> + u32 flags)
> {
> u64 idx = offset >> GEN8_PTE_SHIFT;
> struct i915_page_directory * const pdp =
> @@ -810,15 +810,15 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
> vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, pat_index, flags);
> }
>
> -static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
> - dma_addr_t addr,
> - u64 offset,
> - unsigned int pat_index,
> - u32 flags)
> +static void xehp_ppgtt_insert_entry(struct i915_address_space *vm,
> + dma_addr_t addr,
> + u64 offset,
> + unsigned int pat_index,
> + u32 flags)
> {
> if (flags & PTE_LM)
> - return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
> - pat_index, flags);
> + return xehp_ppgtt_insert_entry_lm(vm, addr, offset,
> + pat_index, flags);
>
> return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index, flags);
> }
> @@ -1042,7 +1042,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
> ppgtt->vm.insert_entries = gen8_ppgtt_insert;
> if (HAS_64K_PAGES(gt->i915))
> - ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
> + ppgtt->vm.insert_page = xehp_ppgtt_insert_entry;
> else
> ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
> ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index 6d440de8ba01..1e925c75fb08 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -103,19 +103,6 @@ static const struct gsc_def gsc_def_dg1[] = {
> }
> };
>
> -static const struct gsc_def gsc_def_xehpsdv[] = {
> - {
> - /* HECI1 not enabled on the device. */
> - },
> - {
> - .name = "mei-gscfi",
> - .bar = DG1_GSC_HECI2_BASE,
> - .bar_size = GSC_BAR_LENGTH,
> - .use_polling = true,
> - .slow_firmware = true,
> - }
> -};
> -
> static const struct gsc_def gsc_def_dg2[] = {
> {
> .name = "mei-gsc",
> @@ -188,8 +175,6 @@ static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
>
> if (IS_DG1(i915)) {
> def = &gsc_def_dg1[intf_id];
> - } else if (IS_XEHPSDV(i915)) {
> - def = &gsc_def_xehpsdv[intf_id];
> } else if (IS_DG2(i915)) {
> def = &gsc_def_dg2[intf_id];
> } else {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index e253750a51c5..5a2bd8de155a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -57,24 +57,12 @@ static const struct intel_mmio_range icl_l3bank_steering_table[] = {
> * are of a "GAM" subclass that has special rules. Thus we use a separate
> * GAM table farther down for those.
> */
> -static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
> +static const struct intel_mmio_range dg2_mslice_steering_table[] = {
> { 0x00DD00, 0x00DDFF },
> { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
> {},
> };
>
> -static const struct intel_mmio_range xehpsdv_gam_steering_table[] = {
> - { 0x004000, 0x004AFF },
> - { 0x00C800, 0x00CFFF },
> - {},
> -};
> -
> -static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
> - { 0x00B000, 0x00B0FF },
> - { 0x00D800, 0x00D8FF },
> - {},
> -};
> -
> static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> { 0x00B000, 0x00B0FF },
> { 0x00D880, 0x00D8FF },
> @@ -188,17 +176,13 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> } else if (IS_PONTEVECCHIO(i915)) {
> gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
> } else if (IS_DG2(i915)) {
> - gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> + gt->steering_table[MSLICE] = dg2_mslice_steering_table;
> gt->steering_table[LNCF] = dg2_lncf_steering_table;
> /*
> * No need to hook up the GAM table since it has a dedicated
> * steering control register on DG2 and can use implicit
> * steering.
> */
> - } else if (IS_XEHPSDV(i915)) {
> - gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> - gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
> - gt->steering_table[GAM] = xehpsdv_gam_steering_table;
> } else if (GRAPHICS_VER(i915) >= 11 &&
> GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
> gt->steering_table[L3BANK] = icl_l3bank_steering_table;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 50962cfd1353..919c07903767 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -718,44 +718,11 @@
>
> #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
> #define VFUNIT_CLKGATE_DIS REG_BIT(20)
> -#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
> #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
> #define GAMEDIA_CLKGATE_DIS REG_BIT(11)
> #define HSUNIT_CLKGATE_DIS REG_BIT(8)
> #define VSUNIT_CLKGATE_DIS REG_BIT(3)
>
> -#define UNSLCGCTL9440 _MMIO(0x9440)
> -#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
> -#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
> -#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
> -#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
> -#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
> -#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
> -#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
> -#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
> -#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
> -#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
> -#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
> -#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
> -
> -#define UNSLCGCTL9444 _MMIO(0x9444)
> -#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
> -#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
> -#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
> -#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
> -#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
> -#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
> -#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
> -#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
> -#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
> -#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
> -#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
> -#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
> -#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
> -#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
> -#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
> -#define LTCDD_CLKGATE_DIS REG_BIT(10)
> -
> #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> #define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
> #define SARBUNIT_CLKGATE_DIS (1 << 5)
> @@ -765,9 +732,6 @@
> #define L3_CLKGATE_DIS REG_BIT(16)
> #define L3_CR2X_CLKGATE_DIS REG_BIT(17)
>
> -#define SCCGCTL94DC MCR_REG(0x94dc)
> -#define CG3DDISURB REG_BIT(14)
> -
> #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
> #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
> #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
> @@ -1046,9 +1010,6 @@
> #define XEHP_L3SQCREG5 MCR_REG(0xb158)
> #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
>
> -#define MLTICTXCTL MCR_REG(0xb170)
> -#define TDONRENDER REG_BIT(2)
> -
> #define XEHP_L3SCQREG7 MCR_REG(0xb188)
> #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
>
> @@ -1057,9 +1018,6 @@
> #define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
> #define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
>
> -#define L3SQCREG1_CCS0 MCR_REG(0xb200)
> -#define FLUSHALLNONCOH REG_BIT(5)
> -
> #define GEN11_GLBLINVL _MMIO(0xb404)
> #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
> #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
> @@ -1109,7 +1067,6 @@
> #define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
> #define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */
>
> -#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
> #define RENDER_MOD_CTRL MCR_REG(0xcf2c)
> #define COMP_MOD_CTRL MCR_REG(0xcf30)
> #define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */
> @@ -1185,7 +1142,6 @@
> #define EU_PERF_CNTL4 PERF_REG(0xe45c)
>
> #define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
> -#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
> #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
> #define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
> #define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
> @@ -1202,7 +1158,6 @@
> #define FLOW_CONTROL_ENABLE REG_BIT(15)
> #define UGM_BACKUP_MODE REG_BIT(13)
> #define MDQ_ARBITRATION_MODE REG_BIT(12)
> -#define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10)
> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
> #define STALL_DOP_GATING_DISABLE REG_BIT(5)
> #define THROTTLE_12_5 REG_GENMASK(4, 2)
> @@ -1679,11 +1634,6 @@
>
> #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
>
> -#define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004)
> -#define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008)
> -#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
> -#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
> -
> /*
> * Standalone Media's non-engine GT registers are located at their regular GT
> * offsets plus 0x380000. This extra offset is stored inside the intel_uncore
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index eca4a6a65556..d7784650e4d9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -573,7 +573,6 @@ static ssize_t media_freq_factor_show(struct kobject *kobj,
> char *buff)
> {
> struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
> - struct intel_guc_slpc *slpc = >_to_guc(gt)->slpc;
> intel_wakeref_t wakeref;
> u32 mode;
>
> @@ -581,20 +580,12 @@ static ssize_t media_freq_factor_show(struct kobject *kobj,
> * Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
> * GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
> */
> - if (IS_XEHPSDV(gt->i915) &&
> - slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
> - /*
> - * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
> - * the media_ratio_mode, just return the cached media ratio
> - */
> - mode = slpc->media_ratio_mode;
> - } else {
> - with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> - mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
> - mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
> - SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
> - SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
> - }
> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> + mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
> +
> + mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
> + SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
> + SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
>
> return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7c367ba8d9dc..7f1b00cb9924 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -546,47 +546,6 @@ static const u8 gen12_rcs_offsets[] = {
> END
> };
>
> -static const u8 xehp_rcs_offsets[] = {
> - NOP(1),
> - LRI(13, POSTED),
> - REG16(0x244),
> - REG(0x034),
> - REG(0x030),
> - REG(0x038),
> - REG(0x03c),
> - REG(0x168),
> - REG(0x140),
> - REG(0x110),
> - REG(0x1c0),
> - REG(0x1c4),
> - REG(0x1c8),
> - REG(0x180),
> - REG16(0x2b4),
> -
> - NOP(5),
> - LRI(9, POSTED),
> - REG16(0x3a8),
> - REG16(0x28c),
> - REG16(0x288),
> - REG16(0x284),
> - REG16(0x280),
> - REG16(0x27c),
> - REG16(0x278),
> - REG16(0x274),
> - REG16(0x270),
> -
> - LRI(3, POSTED),
> - REG(0x1b0),
> - REG16(0x5a8),
> - REG16(0x5ac),
> -
> - NOP(6),
> - LRI(1, 0),
> - REG(0x0c8),
> -
> - END
> -};
> -
> static const u8 dg2_rcs_offsets[] = {
> NOP(1),
> LRI(15, POSTED),
> @@ -695,8 +654,6 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> return mtl_rcs_offsets;
> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_rcs_offsets;
> - else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> - return xehp_rcs_offsets;
> else if (GRAPHICS_VER(engine->i915) >= 12)
> return gen12_rcs_offsets;
> else if (GRAPHICS_VER(engine->i915) >= 11)
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 576e5ef0289b..86ba2f2e485c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -35,9 +35,9 @@ static bool engine_supports_migration(struct intel_engine_cs *engine)
> return true;
> }
>
> -static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
> - struct i915_page_table *pt,
> - void *data)
> +static void xehp_toggle_pdes(struct i915_address_space *vm,
> + struct i915_page_table *pt,
> + void *data)
> {
> struct insert_pte_data *d = data;
>
> @@ -52,9 +52,9 @@ static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
> d->offset += SZ_2M;
> }
>
> -static void xehpsdv_insert_pte(struct i915_address_space *vm,
> - struct i915_page_table *pt,
> - void *data)
> +static void xehp_insert_pte(struct i915_address_space *vm,
> + struct i915_page_table *pt,
> + void *data)
> {
> struct insert_pte_data *d = data;
>
> @@ -120,7 +120,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
> * 512 entry layout using 4K GTT pages. The other two windows just map
> * lmem pages and must use the new compact 32 entry layout using 64K GTT
> * pages, which ensures we can address any lmem object that the user
> - * throws at us. We then also use the xehpsdv_toggle_pdes as a way of
> + * throws at us. We then also use the xehp_toggle_pdes as a way of
> * just toggling the PDE bit(GEN12_PDE_64K) for us, to enable the
> * compact layout for each of these page-tables, that fall within the
> * [CHUNK_SIZE, 3 * CHUNK_SIZE) range.
> @@ -209,12 +209,12 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
> /* Now allow the GPU to rewrite the PTE via its own ppGTT */
> if (HAS_64K_PAGES(gt->i915)) {
> vm->vm.foreach(&vm->vm, base, d.offset - base,
> - xehpsdv_insert_pte, &d);
> + xehp_insert_pte, &d);
> d.offset = base + CHUNK_SZ;
> vm->vm.foreach(&vm->vm,
> d.offset,
> 2 * CHUNK_SZ,
> - xehpsdv_toggle_pdes, &d);
> + xehp_toggle_pdes, &d);
> } else {
> vm->vm.foreach(&vm->vm, base, d.offset - base,
> insert_pte, &d);
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 25c1023eb5f9..c931c56945bd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -367,31 +367,6 @@ static const struct drm_i915_mocs_entry gen12_mocs_table[] = {
> L3_3_WB),
> };
>
> -static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
> - /* wa_1608975824 */
> - MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
> -
> - /* UC - Coherent; GO:L3 */
> - MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
> - /* UC - Coherent; GO:Memory */
> - MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
> - /* UC - Non-Coherent; GO:Memory */
> - MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
> - /* UC - Non-Coherent; GO:L3 */
> - MOCS_ENTRY(4, 0, L3_1_UC),
> -
> - /* WB */
> - MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
> -
> - /* HW Reserved - SW program but never use. */
> - MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
> - MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
> - MOCS_ENTRY(60, 0, L3_1_UC),
> - MOCS_ENTRY(61, 0, L3_1_UC),
> - MOCS_ENTRY(62, 0, L3_1_UC),
> - MOCS_ENTRY(63, 0, L3_1_UC),
> -};
> -
> static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
> /* UC - Coherent; GO:L3 */
> MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
> @@ -514,12 +489,6 @@ static unsigned int get_mocs_settings(struct drm_i915_private *i915,
> table->uc_index = 1;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> table->unused_entries_index = 3;
> - } else if (IS_XEHPSDV(i915)) {
> - table->size = ARRAY_SIZE(xehpsdv_mocs_table);
> - table->table = xehpsdv_mocs_table;
> - table->uc_index = 2;
> - table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> - table->unused_entries_index = 5;
> } else if (IS_DG1(i915)) {
> table->size = ARRAY_SIZE(dg1_mocs_table);
> table->table = dg1_mocs_table;
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 9c6812257ac2..2a6a8134782d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1088,8 +1088,6 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
>
> if (IS_PONTEVECCHIO(i915))
> return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
> - else if (IS_XEHPSDV(i915))
> - return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);
> else if (IS_GEN9_LP(i915))
> return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
> else
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 7f812409c30a..33d543d9bf44 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -922,8 +922,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> ; /* noop; none at this time */
> else if (IS_DG2(i915))
> dg2_ctx_workarounds_init(engine, wal);
> - else if (IS_XEHPSDV(i915))
> - ; /* noop; none at this time */
> else if (IS_DG1(i915))
> dg1_ctx_workarounds_init(engine, wal);
> else if (GRAPHICS_VER(i915) == 12)
> @@ -1350,9 +1348,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> gt->steering_table[MSLICE] = NULL;
> }
>
> - if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0))
> - gt->steering_table[GAM] = NULL;
> -
> slice = __ffs(slice_mask);
> subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
> GEN_DSS_PER_GSLICE;
> @@ -1519,76 +1514,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
> }
>
> -static void
> -xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> -{
> - struct drm_i915_private *i915 = gt->i915;
> -
> - xehp_init_mcr(gt, wal);
> -
> - /* Wa_1409757795:xehpsdv */
> - wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB);
> -
> - /* Wa_18011725039:xehpsdv */
> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
> - wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
> - wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
> - }
> -
> - /* Wa_16011155590:xehpsdv */
> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> - TSGUNIT_CLKGATE_DIS);
> -
> - /* Wa_14011780169:xehpsdv */
> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) {
> - wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
> - GAMTLBVDBOX7_CLKGATE_DIS |
> - GAMTLBVDBOX6_CLKGATE_DIS |
> - GAMTLBVDBOX5_CLKGATE_DIS |
> - GAMTLBVDBOX4_CLKGATE_DIS |
> - GAMTLBVDBOX3_CLKGATE_DIS |
> - GAMTLBVDBOX2_CLKGATE_DIS |
> - GAMTLBVDBOX1_CLKGATE_DIS |
> - GAMTLBVDBOX0_CLKGATE_DIS |
> - GAMTLBKCR_CLKGATE_DIS |
> - GAMTLBGUC_CLKGATE_DIS |
> - GAMTLBBLT_CLKGATE_DIS);
> - wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS |
> - GAMTLBGFXA1_CLKGATE_DIS |
> - GAMTLBCOMPA0_CLKGATE_DIS |
> - GAMTLBCOMPA1_CLKGATE_DIS |
> - GAMTLBCOMPB0_CLKGATE_DIS |
> - GAMTLBCOMPB1_CLKGATE_DIS |
> - GAMTLBCOMPC0_CLKGATE_DIS |
> - GAMTLBCOMPC1_CLKGATE_DIS |
> - GAMTLBCOMPD0_CLKGATE_DIS |
> - GAMTLBCOMPD1_CLKGATE_DIS |
> - GAMTLBMERT_CLKGATE_DIS |
> - GAMTLBVEBOX3_CLKGATE_DIS |
> - GAMTLBVEBOX2_CLKGATE_DIS |
> - GAMTLBVEBOX1_CLKGATE_DIS |
> - GAMTLBVEBOX0_CLKGATE_DIS);
> - }
> -
> - /* Wa_16012725990:xehpsdv */
> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER))
> - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS);
> -
> - /* Wa_14011060649:xehpsdv */
> - wa_14011060649(gt, wal);
> -
> - /* Wa_14012362059:xehpsdv */
> - wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
> -
> - /* Wa_14014368820:xehpsdv */
> - wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
> - INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
> -
> - /* Wa_14010670810:xehpsdv */
> - wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
> -}
> -
> static void
> dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> @@ -1758,8 +1683,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> pvc_gt_workarounds_init(gt, wal);
> else if (IS_DG2(i915))
> dg2_gt_workarounds_init(gt, wal);
> - else if (IS_XEHPSDV(i915))
> - xehpsdv_gt_workarounds_init(gt, wal);
> else if (IS_DG1(i915))
> dg1_gt_workarounds_init(gt, wal);
> else if (GRAPHICS_VER(i915) == 12)
> @@ -2231,8 +2154,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> pvc_whitelist_build(engine);
> else if (IS_DG2(i915))
> dg2_whitelist_build(engine);
> - else if (IS_XEHPSDV(i915))
> - ; /* none needed */
> else if (GRAPHICS_VER(i915) == 12)
> tgl_whitelist_build(engine);
> else if (GRAPHICS_VER(i915) == 11)
> @@ -2968,22 +2889,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> 0 /* write-only, so skip validation */,
> true);
> }
> -
> - if (IS_XEHPSDV(i915)) {
> - /* Wa_1409954639 */
> - wa_mcr_masked_en(wal,
> - GEN8_ROW_CHICKEN,
> - SYSTOLIC_DOP_CLOCK_GATING_DIS);
> -
> - /* Wa_1607196519 */
> - wa_mcr_masked_en(wal,
> - GEN9_ROW_CHICKEN4,
> - GEN12_DISABLE_GRF_CLEAR);
> -
> - /* Wa_14010449647:xehpsdv */
> - wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> - GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> - }
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 6dfe5d9456c6..28277321d9ca 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -51,8 +51,8 @@ static void uc_expand_default_options(struct intel_uc *uc)
> /* Default: enable HuC authentication and GuC submission */
> i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
>
> - /* XEHPSDV and PVC do not use HuC */
> - if (IS_XEHPSDV(i915) || IS_PONTEVECCHIO(i915))
> + /* PVC does not use HuC */
> + if (IS_PONTEVECCHIO(i915))
> i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e81b3b2858ac..dff056587459 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -544,7 +544,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
> #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
> #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
> -#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
> #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
> #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
> #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
> @@ -621,9 +620,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TIGERLAKE_UY(i915) \
> IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
>
> -#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> - (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> -
> #define IS_PVC_BD_STEP(__i915, since, until) \
> (IS_PONTEVECCHIO(__i915) && \
> IS_BASEDIE_STEP(__i915, since, until))
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
> index 8c3f443c8347..11bd42e03b73 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -738,12 +738,6 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
> hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
> hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
> hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
> - } else if (IS_XEHPSDV(i915)) {
> - hwmon->rg.pkg_power_sku_unit = GT0_PACKAGE_POWER_SKU_UNIT;
> - hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
> - hwmon->rg.pkg_rapl_limit = GT0_PACKAGE_RAPL_LIMIT;
> - hwmon->rg.energy_status_all = GT0_PLATFORM_ENERGY_STATUS;
> - hwmon->rg.energy_status_tile = GT0_PACKAGE_ENERGY_STATUS;
> } else {
> hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
> hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 8b4fdeabb12a..b318b7c6bf73 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -734,23 +734,6 @@ static const struct intel_device_info adl_p_info = {
> .__runtime.media.ip.ver = 12, \
> .__runtime.media.ip.rel = 50
>
> -__maybe_unused
> -static const struct intel_device_info xehpsdv_info = {
> - XE_HP_FEATURES,
> - XE_HPM_FEATURES,
> - DGFX_FEATURES,
> - PLATFORM(INTEL_XEHPSDV),
> - .has_64k_pages = 1,
> - .has_media_ratio_mode = 1,
> - .platform_engine_mask =
> - BIT(RCS0) | BIT(BCS0) |
> - BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
> - BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
> - BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
> - BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
> - .require_force_probe = 1,
> -};
> -
> #define DG2_FEATURES \
> XE_HP_FEATURES, \
> XE_HPM_FEATURES, \
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index bd9d812b1afa..1637c1d235e9 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2881,11 +2881,11 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
> int ret;
>
> /*
> - * Wa_1508761755:xehpsdv, dg2
> + * Wa_1508761755
> * EU NOA signals behave incorrectly if EU clock gating is enabled.
> * Disable thread stall DOP gating and EU DOP gating.
> */
> - if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
> + if (IS_DG2(i915)) {
> intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
> _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
> intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
> @@ -2911,7 +2911,7 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
> /*
> * Initialize Super Queue Internal Cnt Register
> * Set PMON Enable in order to collect valid metrics.
> - * Enable byets per clock reporting in OA for XEHPSDV onward.
> + * Enable byets per clock reporting in OA.
> */
> sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
> (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
> @@ -2971,10 +2971,9 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
> u32 sqcnt1;
>
> /*
> - * Wa_1508761755:xehpsdv, dg2
> - * Enable thread stall DOP gating and EU DOP gating.
> + * Wa_1508761755: Enable thread stall DOP gating and EU DOP gating.
> */
> - if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
> + if (IS_DG2(i915)) {
> intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
> _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
> intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e00557e1a57f..a120c17aafcc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1750,7 +1750,6 @@
>
> #define BXT_RP_STATE_CAP _MMIO(0x138170)
> #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
> -#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
> #define PVC_RP_STATE_CAP _MMIO(0x281014)
>
> #define MTL_RP_STATE_CAP _MMIO(0x138000)
> @@ -5401,7 +5400,7 @@
> #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
> #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
> #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> -#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
> +#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
> /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
> #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 9c21ce69bd98..93ab44190a47 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -349,13 +349,6 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
> intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);
> }
>
> -static void xehpsdv_init_clock_gating(struct drm_i915_private *i915)
> -{
> - /* Wa_22010146351:xehpsdv */
> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> - intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
> -}
> -
> static void dg2_init_clock_gating(struct drm_i915_private *i915)
> {
> /* Wa_22010954014:dg2 */
> @@ -764,7 +757,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs =
>
> CG_FUNCS(pvc);
> CG_FUNCS(dg2);
> -CG_FUNCS(xehpsdv);
> CG_FUNCS(cfl);
> CG_FUNCS(skl);
> CG_FUNCS(kbl);
> @@ -801,8 +793,6 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
> i915->clock_gating_funcs = &pvc_clock_gating_funcs;
> else if (IS_DG2(i915))
> i915->clock_gating_funcs = &dg2_clock_gating_funcs;
> - else if (IS_XEHPSDV(i915))
> - i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
> else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
> i915->clock_gating_funcs = &cfl_clock_gating_funcs;
> else if (IS_SKYLAKE(i915))
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 59bea1398c91..de28cbe758f7 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -70,7 +70,6 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(DG1),
> PLATFORM_NAME(ALDERLAKE_S),
> PLATFORM_NAME(ALDERLAKE_P),
> - PLATFORM_NAME(XEHPSDV),
> PLATFORM_NAME(DG2),
> PLATFORM_NAME(PONTEVECCHIO),
> PLATFORM_NAME(METEORLAKE),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index eba2f0b919c8..2299327e59f0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -87,7 +87,6 @@ enum intel_platform {
> INTEL_DG1,
> INTEL_ALDERLAKE_S,
> INTEL_ALDERLAKE_P,
> - INTEL_XEHPSDV,
> INTEL_DG2,
> INTEL_PONTEVECCHIO,
> INTEL_METEORLAKE,
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index b4162f1be765..d524bfe17c27 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -102,13 +102,6 @@ static const struct intel_step_info adlp_revids[] = {
> [0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
> };
>
> -static const struct intel_step_info xehpsdv_revids[] = {
> - [0x0] = { COMMON_GT_MEDIA_STEP(A0) },
> - [0x1] = { COMMON_GT_MEDIA_STEP(A1) },
> - [0x4] = { COMMON_GT_MEDIA_STEP(B0) },
> - [0x8] = { COMMON_GT_MEDIA_STEP(C0) },
> -};
> -
> static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
> [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
> [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 },
> @@ -190,9 +183,6 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_DG2_G12(i915)) {
> revids = dg2_g12_revid_step_tbl;
> size = ARRAY_SIZE(dg2_g12_revid_step_tbl);
> - } else if (IS_XEHPSDV(i915)) {
> - revids = xehpsdv_revids;
> - size = ARRAY_SIZE(xehpsdv_revids);
> } else if (IS_ALDERLAKE_P_N(i915)) {
> revids = adlp_n_revids;
> size = ARRAY_SIZE(adlp_n_revids);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 76400e9c40f0..4f1e56187442 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1536,17 +1536,12 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
> GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
> 0x13200 - 0x133ff: VD2 (DG2 only) \
> 0x13400 - 0x13fff: reserved */ \
> - GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
> - GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
> - GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
> - GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
> GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
> GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
> 0x15000 - 0x15fff: gt (DG2 only) \
> 0x16000 - 0x16dff: reserved */ \
> GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
> - GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
> - 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
> + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
> 0x21000 - 0x21fff: reserved */ \
> GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
> GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
> @@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
> 0x1f6e00 - 0x1f7fff: reserved */ \
> GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
>
> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
> - XEHP_FWRANGES(FORCEWAKE_GT)
> -};
> -
> static const struct intel_forcewake_range __dg2_fw_ranges[] = {
> XEHP_FWRANGES(FORCEWAKE_RENDER)
> };
> @@ -2584,10 +2575,6 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
> ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
> ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
> ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> - } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> - ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
> - ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> } else if (GRAPHICS_VER(i915) >= 12) {
> ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
> ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index 4f98aa8a861e..502bcadc5f39 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -119,7 +119,6 @@ int intel_uncore_mock_selftests(void)
> { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
> { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
> { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
> - { __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
> { __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
> { __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
> { __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> index fef969112b1d..a7e7ec3b5db9 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> @@ -85,7 +85,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1)
> #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
> #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)
> -#define IS_XEHPSDV(dev_priv) (dev_priv && 0)
> #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
> #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
> #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
> @@ -130,7 +129,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
> #define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \
> ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
> IS_GRAPHICS_STEP(xe, first, last))
> -#define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last) (IS_XEHPSDV(xe) && IS_GRAPHICS_STEP(xe, first, last))
>
> /* XXX: No basedie stepping support yet */
> #define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) && IS_PONTEVECCHIO(xe))
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/5] drm/i915: Update IP_VER(12, 50)
2024-03-06 19:36 ` [PATCH 3/5] drm/i915: Update IP_VER(12, 50) Lucas De Marchi
@ 2024-03-11 15:18 ` Rodrigo Vivi
2024-03-11 15:29 ` Lucas De Marchi
0 siblings, 1 reply; 22+ messages in thread
From: Rodrigo Vivi @ 2024-03-11 15:18 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Mar 06, 2024 at 11:36:41AM -0800, Lucas De Marchi wrote:
> With no platform declaring graphics/media IP_VER(12, 50),
this is not true.
We still have
#define XE_HPM_FEATURES \
.__runtime.media.ip.ver = 12, \
.__runtime.media.ip.rel = 50
replace the
> checks throughout the code with IP_VER(12, 55) so the code makes sense
> by itself with no additional explanation of previous baggage.
>
> The info override for the various _info is then changed so the version
> definition is clearer without pointless overrides.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 4 ++--
> .../gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 8 ++++----
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 ++---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 10 +++++-----
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 8 ++++----
> drivers/gpu/drm/i915/gt/intel_migrate.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> drivers/gpu/drm/i915/i915_getparam.c | 4 ++--
> drivers/gpu/drm/i915/i915_gpu_error.c | 5 ++---
> drivers/gpu/drm/i915/i915_pci.c | 12 ++++--------
> drivers/gpu/drm/i915/i915_perf.c | 8 ++++----
> drivers/gpu/drm/i915/i915_query.c | 2 +-
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 24 files changed, 50 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index 3ff3d8889c6c..edb54903be0a 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -713,7 +713,7 @@ static int igt_ppgtt_huge_fill(void *arg)
> {
> struct drm_i915_private *i915 = arg;
> unsigned int supported = RUNTIME_INFO(i915)->page_sizes;
> - bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
> + bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
> struct i915_address_space *vm;
> struct i915_gem_context *ctx;
> unsigned long max_pages;
> @@ -857,7 +857,7 @@ static int igt_ppgtt_huge_fill(void *arg)
> static int igt_ppgtt_64K(void *arg)
> {
> struct drm_i915_private *i915 = arg;
> - bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);
> + bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);
> struct drm_i915_gem_object *obj;
> struct i915_address_space *vm;
> struct i915_gem_context *ctx;
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index 10a7847f1b04..bac15196b4d2 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -117,7 +117,7 @@ static bool fastblit_supports_x_tiling(const struct drm_i915_private *i915)
> if (gen < 12)
> return true;
>
> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
> return false;
>
> return HAS_DISPLAY(i915);
> @@ -166,7 +166,7 @@ static int prepare_blit(const struct tiled_blits *t,
> src_pitch = t->width; /* in dwords */
> if (src->tiling == CLIENT_TILING_Y) {
> src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
> - if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))
> src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
> } else if (src->tiling == CLIENT_TILING_X) {
> src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
> @@ -177,7 +177,7 @@ static int prepare_blit(const struct tiled_blits *t,
> dst_pitch = t->width; /* in dwords */
> if (dst->tiling == CLIENT_TILING_Y) {
> dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
> - if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))
> dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
> } else if (dst->tiling == CLIENT_TILING_X) {
> dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
> @@ -365,7 +365,7 @@ static u64 tiled_offset(const struct intel_gt *gt,
> v += x;
>
> swizzle = gt->ggtt->bit_6_swizzle_x;
> - } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
> + } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
> /* Y-major tiling layout is Tile4 for Xe_HP and beyond */
> v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index e1bf13e3d307..24d1c28201fa 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -827,7 +827,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> cs = gen12_emit_pipe_control(cs, 0,
> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
>
> - if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> + if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index f553cf4e6449..75bde8c1aa5d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -765,14 +765,14 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt)
> * and bits have disable semantices.
> */
> media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 55))
> media_fuse = ~media_fuse;
>
> vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> GEN11_GT_VEBOX_DISABLE_SHIFT;
>
> - if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) {
> fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
> gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> } else {
> @@ -1193,7 +1193,6 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine)
> if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||
> GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
> GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
> - GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
> GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
> regs = xehp_regs;
> num = ARRAY_SIZE(xehp_regs);
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 42aade0faf2d..4bc6c437e7f7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -493,7 +493,7 @@ __execlists_schedule_in(struct i915_request *rq)
> /* Use a fixed tag for OA and friends */
> GEM_BUG_ON(ce->tag <= BITS_PER_LONG);
> ce->lrc.ccid = ce->tag;
> - } else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
> + } else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
> /* We don't need a strict matching tag, just different values */
> unsigned int tag = ffs(READ_ONCE(engine->context_tag));
>
> @@ -613,7 +613,7 @@ static void __execlists_schedule_out(struct i915_request * const rq,
> intel_engine_add_retire(engine, ce->timeline);
>
> ccid = ce->lrc.ccid;
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
> ccid >>= XEHP_SW_CTX_ID_SHIFT - 32;
> ccid &= XEHP_MAX_CONTEXT_HW_ID;
> } else {
> @@ -1907,7 +1907,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
> ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
> head, upper_32_bits(csb), lower_32_bits(csb));
>
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> promote = xehp_csb_parse(csb);
> else if (GRAPHICS_VER(engine->i915) >= 12)
> promote = gen12_csb_parse(csb);
> @@ -3479,7 +3479,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> }
> }
>
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {
> if (intel_engine_has_preemption(engine))
> engine->emit_bb_start = xehp_emit_bb_start;
> else
> @@ -3582,7 +3582,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
>
> engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
> if (GRAPHICS_VER(engine->i915) >= 11 &&
> - GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 50)) {
> + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 55)) {
> execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
> execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index a425db5ed3a2..2c6d31b8fc1a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -278,7 +278,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> intel_uncore_posting_read(uncore,
> XELPMP_RING_FAULT_REG);
>
> - } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> + } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
> intel_gt_mcr_multicast_rmw(gt, XEHP_RING_FAULT_REG,
> RING_FAULT_VALID, 0);
> intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
> @@ -403,7 +403,7 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
> struct drm_i915_private *i915 = gt->i915;
>
> /* From GEN8 onwards we only have one 'All Engine Fault Register' */
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> xehp_check_faults(gt);
> else if (GRAPHICS_VER(i915) >= 8)
> gen8_check_faults(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 5a2bd8de155a..29443bf7c06c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -184,7 +184,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> * steering.
> */
> } else if (GRAPHICS_VER(i915) >= 11 &&
> - GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
> + GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) {
> gt->steering_table[L3BANK] = icl_l3bank_steering_table;
> gt->info.l3bank_mask =
> ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> @@ -829,7 +829,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
> if (IS_PONTEVECCHIO(gt->i915)) {
> *group = dss / GEN_DSS_PER_CSLICE;
> *instance = dss % GEN_DSS_PER_CSLICE;
> - } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
> + } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
> *group = dss / GEN_DSS_PER_GSLICE;
> *instance = dss % GEN_DSS_PER_GSLICE;
> } else {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
> index 01ac565a56a4..a67a4c35a4fa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
> @@ -54,7 +54,7 @@ int intel_gt_mcr_wait_for_reg(struct intel_gt *gt,
> * the topology, so we lookup the DSS ID directly in "slice 0."
> */
> #define _HAS_SS(ss_, gt_, group_, instance_) ( \
> - GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \
> + GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 55) ? \
> intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
> intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 7811a8c9da06..30b128b1fde7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -680,7 +680,7 @@ void setup_private_pat(struct intel_gt *gt)
>
> if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> xelpg_setup_private_ppat(gt);
> - else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> xehp_setup_private_ppat(gt);
> else if (GRAPHICS_VER(i915) >= 12)
> tgl_setup_private_ppat(uncore);
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7f1b00cb9924..b387146ede98 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -676,7 +676,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>
> static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return 0x70;
> else if (GRAPHICS_VER(engine->i915) >= 12)
> return 0x60;
> @@ -690,7 +690,7 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
>
> static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
> {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return 0x80;
> else if (GRAPHICS_VER(engine->i915) >= 12)
> return 0x70;
> @@ -705,7 +705,7 @@ static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)
>
> static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
> {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return 0x84;
> else if (GRAPHICS_VER(engine->i915) >= 12)
> return 0x74;
> @@ -752,7 +752,7 @@ static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)
> static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
> {
>
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> /*
> * Note that the CSFE context has a dummy slot for CMD_BUF_CCTL
> * simply to match the RCS context image layout.
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 86ba2f2e485c..6f7af4077135 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -925,7 +925,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
>
> GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> ring_sz = XY_FAST_COLOR_BLT_DW;
> else if (ver >= 8)
> ring_sz = 8;
> @@ -936,7 +936,7 @@ static int emit_clear(struct i915_request *rq, u32 offset, int size,
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
> *cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
> (XY_FAST_COLOR_BLT_DW - 2);
> *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index c931c56945bd..9fac5e2318e2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -639,7 +639,7 @@ static void init_l3cc_table(struct intel_gt *gt,
>
> intel_gt_mcr_lock(gt, &flags);
> for_each_l3cc(l3cc, table, i)
> - if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55))
> intel_gt_mcr_multicast_write_fw(gt, XEHP_LNCFCMOCS(i), l3cc);
> else
> intel_uncore_write_fw(gt->uncore, GEN9_LNCFCMOCS(i), l3cc);
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 6a3246240e81..5eec9cd6199f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -642,7 +642,7 @@ void intel_sseu_info_init(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> xehp_sseu_info_init(gt);
> else if (GRAPHICS_VER(i915) >= 12)
> gen12_sseu_info_init(gt);
> @@ -851,7 +851,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> {
> if (sseu->max_slices == 0)
> drm_printf(p, "Unavailable\n");
> - else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> sseu_print_xehp_topology(sseu, p);
> else
> sseu_print_hsw_topology(sseu, p);
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 33d543d9bf44..750bf08ee7c1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2770,7 +2770,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
> wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
> THREAD_EX_ARB_MODE_RR_AFTER_DEP);
>
> - if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> + if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
> wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
> }
>
> @@ -2969,7 +2969,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> const struct i915_range *mcr_ranges;
> int i;
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> mcr_ranges = mcr_ranges_xehp;
> else if (GRAPHICS_VER(i915) >= 12)
> mcr_ranges = mcr_ranges_gen12;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index c6603793af89..da6cc268e7b2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -286,7 +286,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>
> /* Wa_22012773006:gen11,gen12 < XeHP */
> if (GRAPHICS_VER(gt->i915) >= 11 &&
> - GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
> + GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 55))
> flags |= GUC_WA_POLLCS;
>
> /* Wa_14014475959 */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index af63973c4e4b..65f8724c3cf9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -393,7 +393,7 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
>
> /* add in local MOCS registers */
> for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
> else
> ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
> @@ -503,7 +503,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
>
> #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
> #define XEHP_LR_HW_CONTEXT_SIZE (96 * sizeof(u32))
> -#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50) ? \
> +#define LR_HW_CONTEXT_SZ(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55) ? \
> XEHP_LR_HW_CONTEXT_SIZE : \
> LR_HW_CONTEXT_SIZE)
> #define LRC_SKIP_SIZE(i915) (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SZ(i915))
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index 52332bb14339..a35e32695e1b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -26,7 +26,7 @@ static void guc_prepare_xfer(struct intel_gt *gt)
> GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
> GUC_ENABLE_MIA_CLOCK_GATING;
>
> - if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 55))
> shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
> GUC_ENABLE_MIA_CACHING;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index cc076e9302ad..4a5331ee43b8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -4507,7 +4507,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> */
>
> engine->emit_bb_start = gen8_emit_bb_start;
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> engine->emit_bb_start = xehp_emit_bb_start;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index 5c3fec63cb4c..fc4c3d4e2b40 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -160,7 +160,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> break;
> case I915_PARAM_SLICE_MASK:
> /* Not supported from Xe_HP onward; use topology queries */
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> return -EINVAL;
>
> value = sseu->slice_mask;
> @@ -169,7 +169,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> break;
> case I915_PARAM_SUBSLICE_MASK:
> /* Not supported from Xe_HP onward; use topology queries */
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> return -EINVAL;
>
> /* Only copy bits from the first slice */
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index a0b784ebaddd..2594eb10c559 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1245,8 +1245,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
> if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA)
> ee->fault_reg = intel_uncore_read(engine->uncore,
> XELPMP_RING_FAULT_REG);
> -
> - else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> ee->fault_reg = intel_gt_mcr_read_any(engine->gt,
> XEHP_RING_FAULT_REG);
> else if (GRAPHICS_VER(i915) >= 12)
> @@ -1852,7 +1851,7 @@ static void gt_record_global_regs(struct intel_gt_coredump *gt)
> if (GRAPHICS_VER(i915) == 7)
> gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
>
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
> gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
> XEHP_FAULT_TLB_DATA0);
> gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b318b7c6bf73..8b673fdcf178 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -705,8 +705,6 @@ static const struct intel_device_info adl_p_info = {
> I915_GTT_PAGE_SIZE_2M
>
> #define XE_HP_FEATURES \
> - .__runtime.graphics.ip.ver = 12, \
> - .__runtime.graphics.ip.rel = 50, \
> XE_HP_PAGE_SIZES, \
> TGL_CACHELEVEL, \
> .dma_mask_size = 46, \
> @@ -730,15 +728,12 @@ static const struct intel_device_info adl_p_info = {
> .__runtime.ppgtt_size = 48, \
> .__runtime.ppgtt_type = INTEL_PPGTT_FULL
>
> -#define XE_HPM_FEATURES \
> - .__runtime.media.ip.ver = 12, \
> - .__runtime.media.ip.rel = 50
> -
> #define DG2_FEATURES \
> XE_HP_FEATURES, \
> - XE_HPM_FEATURES, \
> DGFX_FEATURES, \
> + .__runtime.graphics.ip.ver = 12, \
> .__runtime.graphics.ip.rel = 55, \
> + .__runtime.media.ip.ver = 12, \
> .__runtime.media.ip.rel = 55, \
> PLATFORM(INTEL_DG2), \
> .has_64k_pages = 1, \
> @@ -773,9 +768,10 @@ static const struct intel_device_info ats_m_info = {
> __maybe_unused
> static const struct intel_device_info pvc_info = {
> XE_HPC_FEATURES,
> - XE_HPM_FEATURES,
> DGFX_FEATURES,
> + .__runtime.graphics.ip.ver = 12,
> .__runtime.graphics.ip.rel = 60,
> + .__runtime.media.ip.ver = 12,
> .__runtime.media.ip.rel = 60,
> PLATFORM(INTEL_PONTEVECCHIO),
> .has_flat_ccs = 0,
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 1637c1d235e9..a7d86529033a 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -292,7 +292,7 @@ static u32 i915_perf_stream_paranoid = true;
> #define OAREPORT_REASON_CTX_SWITCH (1<<3)
> #define OAREPORT_REASON_CLK_RATIO (1<<5)
>
> -#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> +#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
>
> /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
> *
> @@ -817,7 +817,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
> */
>
> if (oa_report_ctx_invalid(stream, report) &&
> - GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 50)) {
> + GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 55)) {
> ctx_id = INVALID_CTX_ID;
> oa_context_id_squash(stream, report32);
> }
> @@ -1419,7 +1419,7 @@ static int gen12_get_render_context_id(struct i915_perf_stream *stream)
>
> mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
> (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
> - } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
> + } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 55)) {
> ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
> (XEHP_SW_CTX_ID_SHIFT - 32);
>
> @@ -4122,7 +4122,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
> props->hold_preemption = !!value;
> break;
> case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
> - if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
> + if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 55)) {
> drm_dbg(&perf->i915->drm,
> "SSEU config not supported on gfx %x\n",
> GRAPHICS_VER_FULL(perf->i915));
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 3baa2f54a86e..14d9ec0ed777 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -105,7 +105,7 @@ static int query_geometry_subslices(struct drm_i915_private *i915,
> struct intel_engine_cs *engine;
> struct i915_engine_class_instance classinstance;
>
> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
> return -ENODEV;
>
> classinstance = *((struct i915_engine_class_instance *)&query_item->flags);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 4f1e56187442..0ceb4b50e349 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2721,7 +2721,7 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
> * the forcewake domain if any of the other engines
> * in the same media slice are present.
> */
> - if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) {
> + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 55) && i % 2 == 0) {
> if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1)))
> continue;
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 4/5] drm/i915: Drop dead code for pvc
2024-03-06 19:36 ` [PATCH 4/5] drm/i915: Drop dead code for pvc Lucas De Marchi
@ 2024-03-11 15:29 ` Rodrigo Vivi
2024-03-11 15:35 ` Lucas De Marchi
0 siblings, 1 reply; 22+ messages in thread
From: Rodrigo Vivi @ 2024-03-11 15:29 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Mar 06, 2024 at 11:36:42AM -0800, Lucas De Marchi wrote:
> PCI IDs for PVC were never added and platform always marked with
> force_probe. Drop what's not used and rename some places as needed.
>
> The registers not used anymore are also removed.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 -
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ----
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 30 +---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 9 --
> drivers/gpu/drm/i915/gt/intel_mocs.c | 19 ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 90 +----------
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
> drivers/gpu/drm/i915/i915_debugfs.c | 12 --
> drivers/gpu/drm/i915/i915_drv.h | 9 --
> drivers/gpu/drm/i915/i915_pci.c | 36 -----
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> drivers/gpu/drm/i915/intel_clock_gating.c | 16 +-
> drivers/gpu/drm/i915/intel_device_info.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> drivers/gpu/drm/i915/intel_step.c | 70 +--------
> drivers/gpu/drm/i915/intel_uncore.c | 142 ------------------
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 -
> .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 4 -
> 21 files changed, 12 insertions(+), 485 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 0c5cdab278b6..d3300ae3053f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -386,7 +386,7 @@ struct drm_i915_gem_object {
> * and kernel mode driver for caching policy control after GEN12.
> * In the meantime platform specific tables are created to translate
> * i915_cache_level into pat index, for more details check the macros
> - * defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.
> + * defined i915/i915_pci.c, e.g. MTL_CACHELEVEL.
> * For backward compatibility, this field contains values exactly match
> * the entries of enum i915_cache_level for pre-GEN12 platforms (See
> * LEGACY_CACHELEVEL), so that the PTE encode functions for these
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 24d1c28201fa..2e27bcb52e0d 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -189,9 +189,6 @@ static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine)
> {
> i915_reg_t reg = gen12_get_aux_inv_reg(engine);
>
> - if (IS_PONTEVECCHIO(engine->i915))
> - return false;
> -
> /*
> * So far platforms supported by i915 having flat ccs do not require
> * AUX invalidation. Check also whether the engine requires it.
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 75bde8c1aa5d..396f5fe993c3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -839,38 +839,6 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> }
> }
>
> -static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
> -{
> - struct drm_i915_private *i915 = gt->i915;
> - struct intel_gt_info *info = >->info;
> - unsigned long meml3_mask;
> - unsigned long quad;
> -
> - if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
> - GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
> - return;
> -
> - meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> - meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
> -
> - /*
> - * Link Copy engines may be fused off according to meml3_mask. Each
> - * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
> - */
> - for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
> - unsigned int instance = quad * 2 + 1;
> - intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
> - _BCS(instance));
> -
> - if (mask & info->engine_mask) {
> - gt_dbg(gt, "bcs%u fused off\n", instance);
> - gt_dbg(gt, "bcs%u fused off\n", instance + 1);
> -
> - info->engine_mask &= ~mask;
> - }
> - }
> -}
> -
> /*
> * Determine which engines are fused off in our particular hardware.
> * Note that we have a catch-22 situation where we need to be able to access
> @@ -889,7 +857,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>
> engine_mask_apply_media_fuses(gt);
> engine_mask_apply_compute_fuses(gt);
> - engine_mask_apply_copy_fuses(gt);
>
> /*
> * The only use of the GSC CS is to load and communicate with the GSC
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 29443bf7c06c..b8912bd6c08e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -69,27 +69,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> {},
> };
>
> -/*
> - * We have several types of MCR registers on PVC where steering to (0,0)
> - * will always provide us with a non-terminated value. We'll stick them
> - * all in the same table for simplicity.
> - */
> -static const struct intel_mmio_range pvc_instance0_steering_table[] = {
> - { 0x004000, 0x004AFF }, /* HALF-BSLICE */
> - { 0x008800, 0x00887F }, /* CC */
> - { 0x008A80, 0x008AFF }, /* TILEPSMI */
> - { 0x00B000, 0x00B0FF }, /* HALF-BSLICE */
> - { 0x00B100, 0x00B3FF }, /* L3BANK */
> - { 0x00C800, 0x00CFFF }, /* HALF-BSLICE */
> - { 0x00D800, 0x00D8FF }, /* HALF-BSLICE */
> - { 0x00DD00, 0x00DDFF }, /* BSLICE */
> - { 0x00E900, 0x00E9FF }, /* HALF-BSLICE */
> - { 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */
> - { 0x00F000, 0x00FFFF }, /* HALF-BSLICE */
> - { 0x024180, 0x0241FF }, /* HALF-BSLICE */
> - {},
> -};
> -
> static const struct intel_mmio_range xelpg_instance0_steering_table[] = {
> { 0x000B00, 0x000BFF }, /* SQIDI */
> { 0x001000, 0x001FFF }, /* SQIDI */
> @@ -173,8 +152,6 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table;
> gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;
> gt->steering_table[DSS] = xelpg_dss_steering_table;
> - } else if (IS_PONTEVECCHIO(i915)) {
> - gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
> } else if (IS_DG2(i915)) {
> gt->steering_table[MSLICE] = dg2_mslice_steering_table;
> gt->steering_table[LNCF] = dg2_lncf_steering_table;
> @@ -805,8 +782,6 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
> for (int i = 0; i < NUM_STEERING_TYPES; i++)
> if (gt->steering_table[i])
> report_steering_type(p, gt, i, dump_table);
> - } else if (IS_PONTEVECCHIO(gt->i915)) {
> - report_steering_type(p, gt, INSTANCE0, dump_table);
> } else if (HAS_MSLICE_STEERING(gt->i915)) {
> report_steering_type(p, gt, MSLICE, dump_table);
> report_steering_type(p, gt, LNCF, dump_table);
> @@ -826,10 +801,7 @@ void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
> void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
> unsigned int *group, unsigned int *instance)
> {
> - if (IS_PONTEVECCHIO(gt->i915)) {
> - *group = dss / GEN_DSS_PER_CSLICE;
> - *instance = dss % GEN_DSS_PER_CSLICE;
> - } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
> + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {
> *group = dss / GEN_DSS_PER_GSLICE;
> *instance = dss % GEN_DSS_PER_GSLICE;
> } else {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 919c07903767..8d8d781b44b6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -953,10 +953,6 @@
> #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
> #define GEN7_L3AGDIS (1 << 19)
>
> -#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c)
> -#define XEHPC_HOSTCACHEEN REG_BIT(1)
> -#define XEHPC_OVRLSCCC REG_BIT(0)
> -
> #define GEN7_L3CNTLREG2 _MMIO(0xb020)
>
> /* MOCS (Memory Object Control State) registers */
> @@ -1013,11 +1009,6 @@
> #define XEHP_L3SCQREG7 MCR_REG(0xb188)
> #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
>
> -#define XEHPC_L3SCRUB MCR_REG(0xb18c)
> -#define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12)
> -#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
> -#define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
> -
> #define GEN11_GLBLINVL _MMIO(0xb404)
> #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
> #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 9fac5e2318e2..d791d63d49b4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -53,7 +53,6 @@ struct drm_i915_mocs_table {
>
> /* Helper defines */
> #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
> -#define PVC_NUM_MOCS_ENTRIES 3
> #define MTL_NUM_MOCS_ENTRIES 16
>
> /* (e)LLC caching options */
> @@ -379,17 +378,6 @@ static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
> MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
> };
>
> -static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
> - /* Error */
> - MOCS_ENTRY(0, 0, L3_3_WB),
> -
> - /* UC */
> - MOCS_ENTRY(1, 0, L3_1_UC),
> -
> - /* WB */
> - MOCS_ENTRY(2, 0, L3_3_WB),
> -};
> -
> static const struct drm_i915_mocs_entry mtl_mocs_table[] = {
> /* Error - Reserved for Non-Use */
> MOCS_ENTRY(0,
> @@ -476,13 +464,6 @@ static unsigned int get_mocs_settings(struct drm_i915_private *i915,
> table->n_entries = MTL_NUM_MOCS_ENTRIES;
> table->uc_index = 9;
> table->unused_entries_index = 1;
> - } else if (IS_PONTEVECCHIO(i915)) {
> - table->size = ARRAY_SIZE(pvc_mocs_table);
> - table->table = pvc_mocs_table;
> - table->n_entries = PVC_NUM_MOCS_ENTRIES;
> - table->uc_index = 1;
> - table->wb_index = 2;
> - table->unused_entries_index = 2;
> } else if (IS_DG2(i915)) {
> table->size = ARRAY_SIZE(dg2_mocs_table);
> table->table = dg2_mocs_table;
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 2a6a8134782d..b4d2f80ed609 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1086,9 +1086,7 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
> struct drm_i915_private *i915 = rps_to_i915(rps);
> struct intel_uncore *uncore = rps_to_uncore(rps);
>
> - if (IS_PONTEVECCHIO(i915))
> - return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
> - else if (IS_GEN9_LP(i915))
> + if (IS_GEN9_LP(i915))
> return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
> else
> return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 5eec9cd6199f..c8fadf58d836 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -214,13 +214,8 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> int num_compute_regs, num_geometry_regs;
> int eu;
>
> - if (IS_PONTEVECCHIO(gt->i915)) {
> - num_geometry_regs = 0;
> - num_compute_regs = 2;
> - } else {
> - num_geometry_regs = 1;
> - num_compute_regs = 1;
> - }
> + num_geometry_regs = 1;
> + num_compute_regs = 1;
>
> /*
> * The concept of slice has been removed in Xe_HP. To be compatible
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 750bf08ee7c1..13a316acef61 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -257,12 +257,6 @@ wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
> wa_write_clr_set(wal, reg, ~0, set);
> }
>
> -static void
> -wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
> -{
> - wa_mcr_write_clr_set(wal, reg, ~0, set);
> -}
> -
> static void
> wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
> {
> @@ -918,8 +912,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>
> if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
> xelpg_ctx_workarounds_init(engine, wal);
> - else if (IS_PONTEVECCHIO(i915))
> - ; /* noop; none at this time */
> else if (IS_DG2(i915))
> dg2_ctx_workarounds_init(engine, wal);
> else if (IS_DG1(i915))
> @@ -1374,20 +1366,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0);
> }
>
> -static void
> -pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> -{
> - unsigned int dss;
> -
> - /*
> - * Setup implicit steering for COMPUTE and DSS ranges to the first
> - * non-fused-off DSS. All other types of MCR registers will be
> - * explicitly steered.
> - */
> - dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0);
> - __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE);
> -}
> -
> static void
> icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> @@ -1556,24 +1534,6 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
> }
>
> -static void
> -pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> -{
> - pvc_init_mcr(gt, wal);
> -
> - /* Wa_14015795083 */
> - wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> -
> - /* Wa_18018781329 */
> - wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> - wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> - wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> - wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> -
> - /* Wa_16016694945 */
> - wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
> -}
> -
> static void
> xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> @@ -1649,12 +1609,6 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
> }
>
> - if (IS_PONTEVECCHIO(gt->i915)) {
> - wa_mcr_write(wal, XEHPC_L3SCRUB,
> - SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
> - wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
> - }
> -
> if (IS_DG2(gt->i915)) {
> wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
> @@ -1679,8 +1633,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
>
> if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
> xelpg_gt_workarounds_init(gt, wal);
> - else if (IS_PONTEVECCHIO(i915))
> - pvc_gt_workarounds_init(gt, wal);
> else if (IS_DG2(i915))
> dg2_gt_workarounds_init(gt, wal);
> else if (IS_DG1(i915))
> @@ -2100,30 +2052,6 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine)
> }
> }
>
> -static void blacklist_trtt(struct intel_engine_cs *engine)
> -{
> - struct i915_wa_list *w = &engine->whitelist;
> -
> - /*
> - * Prevent read/write access to [0x4400, 0x4600) which covers
> - * the TRTT range across all engines. Note that normally userspace
> - * cannot access the other engines' trtt control, but for simplicity
> - * we cover the entire range on each engine.
> - */
> - whitelist_reg_ext(w, _MMIO(0x4400),
> - RING_FORCE_TO_NONPRIV_DENY |
> - RING_FORCE_TO_NONPRIV_RANGE_64);
> - whitelist_reg_ext(w, _MMIO(0x4500),
> - RING_FORCE_TO_NONPRIV_DENY |
> - RING_FORCE_TO_NONPRIV_RANGE_64);
> -}
> -
> -static void pvc_whitelist_build(struct intel_engine_cs *engine)
> -{
> - /* Wa_16014440446:pvc */
> - blacklist_trtt(engine);
> -}
> -
> static void xelpg_whitelist_build(struct intel_engine_cs *engine)
> {
> struct i915_wa_list *w = &engine->whitelist;
> @@ -2150,8 +2078,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> ; /* none yet */
> else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
> xelpg_whitelist_build(engine);
> - else if (IS_PONTEVECCHIO(i915))
> - pvc_whitelist_build(engine);
> else if (IS_DG2(i915))
> dg2_whitelist_build(engine);
> else if (GRAPHICS_VER(i915) == 12)
> @@ -2731,13 +2657,10 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> XEHP_BLITTER_ROUND_ROBIN_MODE);
> }
>
> -static void
> +__maybe_unused static void
> ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> - if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) {
> - /* Wa_14014999345:pvc */
> - wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
> - }
> + /* boilerplate for any CCS engine workaround */
> }
>
> /*
> @@ -2843,14 +2766,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>
> if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> - IS_PONTEVECCHIO(i915) ||
> IS_DG2(i915)) {
> /* Wa_22014226127 */
> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> }
>
> - if (IS_PONTEVECCHIO(i915) || IS_DG2(i915))
> - /* Wa_14015227452:dg2,pvc */
> + if (IS_DG2(i915))
> + /* Wa_14015227452 */
> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
>
> if (IS_DG2(i915)) {
> @@ -2907,9 +2829,7 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
> if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
> general_render_compute_wa_init(engine, wal);
>
> - if (engine->class == COMPUTE_CLASS)
> - ccs_engine_wa_init(engine, wal);
> - else if (engine->class == RENDER_CLASS)
I don't believe we need to remove this chunk since we are not deleting the ccs_engine_wa_init.
If we want to keep that as a placeholder we should also keep the caller as well.
> + if (engine->class == RENDER_CLASS)
> rcs_engine_wa_init(engine, wal);
> else
> xcs_engine_wa_init(engine, wal);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 28277321d9ca..b47051ddf17f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -50,10 +50,6 @@ static void uc_expand_default_options(struct intel_uc *uc)
>
> /* Default: enable HuC authentication and GuC submission */
> i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
> -
> - /* PVC does not use HuC */
> - if (IS_PONTEVECCHIO(i915))
> - i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
> }
>
> /* Reset GuC providing us with fresh state for both GuC and HuC.
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 990eaa029d9c..24c78873b3cf 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -156,18 +156,6 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
> case 4: return " WB (2-Way Coh)";
> default: return " not defined";
> }
> - } else if (IS_PONTEVECCHIO(i915)) {
> - switch (obj->pat_index) {
> - case 0: return " UC";
> - case 1: return " WC";
> - case 2: return " WT";
> - case 3: return " WB";
> - case 4: return " WT (CLOS1)";
> - case 5: return " WB (CLOS1)";
> - case 6: return " WT (CLOS2)";
> - case 7: return " WT (CLOS2)";
> - default: return " not defined";
> - }
> } else if (GRAPHICS_VER(i915) >= 12) {
> switch (obj->pat_index) {
> case 0: return " WB";
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dff056587459..cf52d4adaa20 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -545,7 +545,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
> #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
> #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
> -#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
> #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
> #define IS_LUNARLAKE(i915) 0
>
> @@ -620,14 +619,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TIGERLAKE_UY(i915) \
> IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
>
> -#define IS_PVC_BD_STEP(__i915, since, until) \
> - (IS_PONTEVECCHIO(__i915) && \
> - IS_BASEDIE_STEP(__i915, since, until))
> -
> -#define IS_PVC_CT_STEP(__i915, since, until) \
> - (IS_PONTEVECCHIO(__i915) && \
> - IS_GRAPHICS_STEP(__i915, since, until))
> -
> #define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
> #define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
> #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 8b673fdcf178..1e69783ae4fd 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -59,14 +59,6 @@
> [I915_CACHE_WT] = 2, \
> }
>
> -#define PVC_CACHELEVEL \
> - .cachelevel_to_pat = { \
> - [I915_CACHE_NONE] = 0, \
> - [I915_CACHE_LLC] = 3, \
> - [I915_CACHE_L3_LLC] = 3, \
> - [I915_CACHE_WT] = 2, \
> - }
> -
> #define MTL_CACHELEVEL \
> .cachelevel_to_pat = { \
> [I915_CACHE_NONE] = 2, \
> @@ -756,34 +748,6 @@ static const struct intel_device_info ats_m_info = {
> .tuning_thread_rr_after_dep = 1,
> };
>
> -#define XE_HPC_FEATURES \
> - XE_HP_FEATURES, \
> - .dma_mask_size = 52, \
> - .has_3d_pipeline = 0, \
> - .has_guc_deprivilege = 1, \
> - .has_l3_ccs_read = 1, \
> - .has_mslice_steering = 0, \
> - .has_one_eu_per_fuse_bit = 1
> -
> -__maybe_unused
> -static const struct intel_device_info pvc_info = {
> - XE_HPC_FEATURES,
> - DGFX_FEATURES,
> - .__runtime.graphics.ip.ver = 12,
> - .__runtime.graphics.ip.rel = 60,
> - .__runtime.media.ip.ver = 12,
> - .__runtime.media.ip.rel = 60,
> - PLATFORM(INTEL_PONTEVECCHIO),
> - .has_flat_ccs = 0,
> - .max_pat_index = 7,
> - .platform_engine_mask =
> - BIT(BCS0) |
> - BIT(VCS0) |
> - BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
> - .require_force_probe = 1,
> - PVC_CACHELEVEL,
> -};
> -
> static const struct intel_gt_definition xelpmp_extra_gt[] = {
> {
> .type = GT_MEDIA,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a120c17aafcc..f8d93bc638fd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1750,7 +1750,6 @@
>
> #define BXT_RP_STATE_CAP _MMIO(0x138170)
> #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
> -#define PVC_RP_STATE_CAP _MMIO(0x281014)
>
> #define MTL_RP_STATE_CAP _MMIO(0x138000)
> #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 93ab44190a47..be355c1fefc6 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -356,17 +356,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
> SGSI_SIDECLK_DIS);
> }
>
> -static void pvc_init_clock_gating(struct drm_i915_private *i915)
> -{
> - /* Wa_14012385139:pvc */
> - if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
> - intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
> -
> - /* Wa_22010954014:pvc */
> - if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
> - intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
> -}
> -
> static void cnp_init_clock_gating(struct drm_i915_private *i915)
> {
> if (!HAS_PCH_CNP(i915))
> @@ -755,7 +744,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs =
> .init_clock_gating = platform##_init_clock_gating, \
> }
>
> -CG_FUNCS(pvc);
> CG_FUNCS(dg2);
> CG_FUNCS(cfl);
> CG_FUNCS(skl);
> @@ -789,9 +777,7 @@ CG_FUNCS(nop);
> */
> void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
> {
> - if (IS_PONTEVECCHIO(i915))
> - i915->clock_gating_funcs = &pvc_clock_gating_funcs;
> - else if (IS_DG2(i915))
> + if (IS_DG2(i915))
> i915->clock_gating_funcs = &dg2_clock_gating_funcs;
> else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
> i915->clock_gating_funcs = &cfl_clock_gating_funcs;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index de28cbe758f7..a0a43ea07f11 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -71,7 +71,6 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(ALDERLAKE_S),
> PLATFORM_NAME(ALDERLAKE_P),
> PLATFORM_NAME(DG2),
> - PLATFORM_NAME(PONTEVECCHIO),
> PLATFORM_NAME(METEORLAKE),
> };
> #undef PLATFORM_NAME
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 2299327e59f0..d1a2abc7e513 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -88,7 +88,6 @@ enum intel_platform {
> INTEL_ALDERLAKE_S,
> INTEL_ALDERLAKE_P,
> INTEL_DG2,
> - INTEL_PONTEVECCHIO,
> INTEL_METEORLAKE,
> INTEL_MAX_PLATFORMS
> };
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index d524bfe17c27..a5adfb5d8fd2 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -146,8 +146,6 @@ static u8 gmd_to_intel_step(struct drm_i915_private *i915,
> return step;
> }
>
> -static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
> -
> void intel_step_init(struct drm_i915_private *i915)
> {
> const struct intel_step_info *revids = NULL;
> @@ -171,10 +169,7 @@ void intel_step_init(struct drm_i915_private *i915)
> return;
> }
>
> - if (IS_PONTEVECCHIO(i915)) {
> - pvc_step_init(i915, revid);
> - return;
> - } else if (IS_DG2_G10(i915)) {
> + if (IS_DG2_G10(i915)) {
> revids = dg2_g10_revid_step_tbl;
> size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
> } else if (IS_DG2_G11(i915)) {
> @@ -267,69 +262,6 @@ void intel_step_init(struct drm_i915_private *i915)
> RUNTIME_INFO(i915)->step = step;
> }
>
> -#define PVC_BD_REVID GENMASK(5, 3)
> -#define PVC_CT_REVID GENMASK(2, 0)
> -
> -static const int pvc_bd_subids[] = {
> - [0x0] = STEP_A0,
> - [0x3] = STEP_B0,
> - [0x4] = STEP_B1,
> - [0x5] = STEP_B3,
> -};
> -
> -static const int pvc_ct_subids[] = {
> - [0x3] = STEP_A0,
> - [0x5] = STEP_B0,
> - [0x6] = STEP_B1,
> - [0x7] = STEP_C0,
> -};
> -
> -static int
> -pvc_step_lookup(struct drm_i915_private *i915, const char *type,
> - const int *table, int size, int subid)
> -{
> - if (subid < size && table[subid] != STEP_NONE)
> - return table[subid];
> -
> - drm_warn(&i915->drm, "Unknown %s id 0x%02x\n", type, subid);
> -
> - /*
> - * As on other platforms, try to use the next higher ID if we land on a
> - * gap in the table.
> - */
> - while (subid < size && table[subid] == STEP_NONE)
> - subid++;
> -
> - if (subid < size) {
> - drm_dbg(&i915->drm, "Using steppings for %s id 0x%02x\n",
> - type, subid);
> - return table[subid];
> - }
> -
> - drm_dbg(&i915->drm, "Using future steppings\n");
> - return STEP_FUTURE;
> -}
> -
> -/*
> - * PVC needs special handling since we don't lookup the
> - * revid in a table, but rather specific bitfields within
> - * the revid for various components.
> - */
> -static void pvc_step_init(struct drm_i915_private *i915, int pci_revid)
> -{
> - int ct_subid, bd_subid;
> -
> - bd_subid = FIELD_GET(PVC_BD_REVID, pci_revid);
> - ct_subid = FIELD_GET(PVC_CT_REVID, pci_revid);
> -
> - RUNTIME_INFO(i915)->step.basedie_step =
> - pvc_step_lookup(i915, "Base Die", pvc_bd_subids,
> - ARRAY_SIZE(pvc_bd_subids), bd_subid);
> - RUNTIME_INFO(i915)->step.graphics_step =
> - pvc_step_lookup(i915, "Compute Tile", pvc_ct_subids,
> - ARRAY_SIZE(pvc_ct_subids), ct_subid);
> -}
> -
> #define STEP_NAME_CASE(name) \
> case STEP_##name: \
> return #name;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 0ceb4b50e349..756c44fa4462 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1106,45 +1106,6 @@ static const struct i915_range dg2_shadowed_regs[] = {
> { .start = 0x1F8510, .end = 0x1F8550 },
> };
>
> -static const struct i915_range pvc_shadowed_regs[] = {
> - { .start = 0x2030, .end = 0x2030 },
> - { .start = 0x2510, .end = 0x2550 },
> - { .start = 0xA008, .end = 0xA00C },
> - { .start = 0xA188, .end = 0xA188 },
> - { .start = 0xA278, .end = 0xA278 },
> - { .start = 0xA540, .end = 0xA56C },
> - { .start = 0xC4C8, .end = 0xC4C8 },
> - { .start = 0xC4E0, .end = 0xC4E0 },
> - { .start = 0xC600, .end = 0xC600 },
> - { .start = 0xC658, .end = 0xC658 },
> - { .start = 0x22030, .end = 0x22030 },
> - { .start = 0x22510, .end = 0x22550 },
> - { .start = 0x1C0030, .end = 0x1C0030 },
> - { .start = 0x1C0510, .end = 0x1C0550 },
> - { .start = 0x1C4030, .end = 0x1C4030 },
> - { .start = 0x1C4510, .end = 0x1C4550 },
> - { .start = 0x1C8030, .end = 0x1C8030 },
> - { .start = 0x1C8510, .end = 0x1C8550 },
> - { .start = 0x1D0030, .end = 0x1D0030 },
> - { .start = 0x1D0510, .end = 0x1D0550 },
> - { .start = 0x1D4030, .end = 0x1D4030 },
> - { .start = 0x1D4510, .end = 0x1D4550 },
> - { .start = 0x1D8030, .end = 0x1D8030 },
> - { .start = 0x1D8510, .end = 0x1D8550 },
> - { .start = 0x1E0030, .end = 0x1E0030 },
> - { .start = 0x1E0510, .end = 0x1E0550 },
> - { .start = 0x1E4030, .end = 0x1E4030 },
> - { .start = 0x1E4510, .end = 0x1E4550 },
> - { .start = 0x1E8030, .end = 0x1E8030 },
> - { .start = 0x1E8510, .end = 0x1E8550 },
> - { .start = 0x1F0030, .end = 0x1F0030 },
> - { .start = 0x1F0510, .end = 0x1F0550 },
> - { .start = 0x1F4030, .end = 0x1F4030 },
> - { .start = 0x1F4510, .end = 0x1F4550 },
> - { .start = 0x1F8030, .end = 0x1F8030 },
> - { .start = 0x1F8510, .end = 0x1F8550 },
> -};
> -
> static const struct i915_range mtl_shadowed_regs[] = {
> { .start = 0x2030, .end = 0x2030 },
> { .start = 0x2510, .end = 0x2550 },
> @@ -1626,105 +1587,6 @@ static const struct intel_forcewake_range __dg2_fw_ranges[] = {
> XEHP_FWRANGES(FORCEWAKE_RENDER)
> };
>
> -static const struct intel_forcewake_range __pvc_fw_ranges[] = {
> - GEN_FW_RANGE(0x0, 0xaff, 0),
> - GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
> - GEN_FW_RANGE(0xc00, 0xfff, 0),
> - GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
> - GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
> - GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
> - 0x4000 - 0x4aff: gt
> - 0x4b00 - 0x4fff: reserved
> - 0x5000 - 0x51ff: gt
> - 0x5200 - 0x52ff: reserved
> - 0x5300 - 0x53ff: gt
> - 0x5400 - 0x7fff: reserved
> - 0x8000 - 0x813f: gt */
> - GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x8180, 0x81ff, 0),
> - GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
> - 0x8200 - 0x82ff: gt
> - 0x8300 - 0x84ff: reserved
> - 0x8500 - 0x887f: gt
> - 0x8880 - 0x8a7f: reserved
> - 0x8a80 - 0x8aff: gt
> - 0x8b00 - 0x8fff: reserved
> - 0x9000 - 0x947f: gt
> - 0x9480 - 0x94cf: reserved */
> - GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x9560, 0x967f, 0), /*
> - 0x9560 - 0x95ff: always on
> - 0x9600 - 0x967f: reserved */
> - GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
> - 0x9680 - 0x96ff: render
> - 0x9700 - 0x97ff: reserved */
> - GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
> - 0x9800 - 0xb4ff: gt
> - 0xb500 - 0xbfff: reserved
> - 0xc000 - 0xcfff: gt */
> - GEN_FW_RANGE(0xd000, 0xd3ff, 0),
> - GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT),
> - GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
> - 0xdd00 - 0xddff: gt
> - 0xde00 - 0xde7f: reserved */
> - GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
> - 0xde80 - 0xdeff: render
> - 0xdf00 - 0xe1ff: reserved
> - 0xe200 - 0xe7ff: render
> - 0xe800 - 0xe8ff: reserved */
> - GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
> - 0xe900 - 0xe9ff: gt
> - 0xea00 - 0xebff: reserved
> - 0xec00 - 0xffff: gt
> - 0x10000 - 0x11fff: reserved */
> - GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
> - 0x12000 - 0x127ff: always on
> - 0x12800 - 0x12fff: reserved */
> - GEN_FW_RANGE(0x13000, 0x19fff, FORCEWAKE_GT), /*
> - 0x13000 - 0x135ff: gt
> - 0x13600 - 0x147ff: reserved
> - 0x14800 - 0x153ff: gt
> - 0x15400 - 0x19fff: reserved */
> - GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /*
> - 0x1a000 - 0x1ffff: render
> - 0x20000 - 0x21fff: reserved */
> - GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
> - GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
> - 24000 - 0x2407f: always on
> - 24080 - 0x2417f: reserved */
> - GEN_FW_RANGE(0x24180, 0x25fff, FORCEWAKE_GT), /*
> - 0x24180 - 0x241ff: gt
> - 0x24200 - 0x251ff: reserved
> - 0x25200 - 0x252ff: gt
> - 0x25300 - 0x25fff: reserved */
> - GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
> - 0x26000 - 0x27fff: render
> - 0x28000 - 0x2ffff: reserved */
> - GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
> - GEN_FW_RANGE(0x40000, 0x1bffff, 0),
> - GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
> - 0x1c0000 - 0x1c2bff: VD0
> - 0x1c2c00 - 0x1c2cff: reserved
> - 0x1c2d00 - 0x1c2dff: VD0
> - 0x1c2e00 - 0x1c3eff: reserved
> - 0x1c3f00 - 0x1c3fff: VD0 */
> - GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
> - 0x1c4000 - 0x1c6aff: VD1
> - 0x1c6b00 - 0x1c7eff: reserved
> - 0x1c7f00 - 0x1c7fff: VD1
> - 0x1c8000 - 0x1cffff: reserved */
> - GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
> - 0x1d0000 - 0x1d2aff: VD2
> - 0x1d2b00 - 0x1d3eff: reserved
> - 0x1d3f00 - 0x1d3fff: VD2
> - 0x1d4000 - 0x23ffff: reserved */
> - GEN_FW_RANGE(0x240000, 0x3dffff, 0),
> - GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT),
> -};
> -
> static const struct intel_forcewake_range __mtl_fw_ranges[] = {
> GEN_FW_RANGE(0x0, 0xaff, 0),
> GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
> @@ -2567,10 +2429,6 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
> ASSIGN_FW_DOMAINS_TABLE(uncore, __mtl_fw_ranges);
> ASSIGN_SHADOW_TABLE(uncore, mtl_shadowed_regs);
> ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> - } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) {
> - ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges);
> - ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs);
> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
> ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
> ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index 502bcadc5f39..41eaa9b7f67d 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -71,7 +71,6 @@ static int intel_shadow_table_check(void)
> { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
> { gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
> { dg2_shadowed_regs, ARRAY_SIZE(dg2_shadowed_regs) },
> - { pvc_shadowed_regs, ARRAY_SIZE(pvc_shadowed_regs) },
> { mtl_shadowed_regs, ARRAY_SIZE(mtl_shadowed_regs) },
> { xelpmp_shadowed_regs, ARRAY_SIZE(xelpmp_shadowed_regs) },
> };
> @@ -119,7 +118,6 @@ int intel_uncore_mock_selftests(void)
> { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
> { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
> { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
> - { __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
> { __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
> { __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
> };
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> index a7e7ec3b5db9..a01d1b869c2d 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> @@ -86,7 +86,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
> #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
> #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)
> #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
> -#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
> #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
> #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
>
> @@ -130,9 +129,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
> ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
> IS_GRAPHICS_STEP(xe, first, last))
>
> -/* XXX: No basedie stepping support yet */
> -#define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) && IS_PONTEVECCHIO(xe))
> -
> #define IS_TIGERLAKE_DISPLAY_STEP(xe, first, last) (IS_TIGERLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
#define IS_ROCKETLAKE_DISPLAY_STEP(xe, first, last) (IS_ROCKETLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
> #define IS_DG1_DISPLAY_STEP(xe, first, last) (IS_DG1(xe) && IS_DISPLAY_STEP(xe, first, last))
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/5] drm/i915: Update IP_VER(12, 50)
2024-03-11 15:18 ` Rodrigo Vivi
@ 2024-03-11 15:29 ` Lucas De Marchi
2024-03-11 16:21 ` Rodrigo Vivi
0 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-11 15:29 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, dri-devel
On Mon, Mar 11, 2024 at 11:18:03AM -0400, Rodrigo Vivi wrote:
>On Wed, Mar 06, 2024 at 11:36:41AM -0800, Lucas De Marchi wrote:
>> With no platform declaring graphics/media IP_VER(12, 50),
>
>this is not true.
>We still have
>
>#define XE_HPM_FEATURES \
> .__runtime.media.ip.ver = 12, \
> .__runtime.media.ip.rel = 50
<snip>
>> -#define XE_HPM_FEATURES \
>> - .__runtime.media.ip.ver = 12, \
>> - .__runtime.media.ip.rel = 50
>> -
^ being removed here since all the users, like below, are overriding it.
>> #define DG2_FEATURES \
>> XE_HP_FEATURES, \
>> - XE_HPM_FEATURES, \
>> DGFX_FEATURES, \
>> + .__runtime.graphics.ip.ver = 12, \
>> .__runtime.graphics.ip.rel = 55, \
>> + .__runtime.media.ip.ver = 12, \
>> .__runtime.media.ip.rel = 55, \
^^
After applying until this patch:
$ git grep -e "rel[[:space:]]*=" -- drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/i915_pci.c: .__runtime.graphics.ip.rel = 10,
drivers/gpu/drm/i915/i915_pci.c: .__runtime.graphics.ip.rel = 55, \
drivers/gpu/drm/i915/i915_pci.c: .__runtime.media.ip.rel = 55, \
drivers/gpu/drm/i915/i915_pci.c: .__runtime.graphics.ip.rel = 60,
drivers/gpu/drm/i915/i915_pci.c: .__runtime.media.ip.rel = 60,
drivers/gpu/drm/i915/i915_pci.c: .__runtime.graphics.ip.rel = 70,
should I reword anything in the commit message to make my intent
clearer?
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 4/5] drm/i915: Drop dead code for pvc
2024-03-11 15:29 ` Rodrigo Vivi
@ 2024-03-11 15:35 ` Lucas De Marchi
2024-03-11 16:22 ` Rodrigo Vivi
0 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-11 15:35 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, dri-devel
On Mon, Mar 11, 2024 at 11:29:31AM -0400, Rodrigo Vivi wrote:
>> @@ -2907,9 +2829,7 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
>> if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
>> general_render_compute_wa_init(engine, wal);
>>
>> - if (engine->class == COMPUTE_CLASS)
>> - ccs_engine_wa_init(engine, wal);
>> - else if (engine->class == RENDER_CLASS)
>
>I don't believe we need to remove this chunk since we are not deleting the ccs_engine_wa_init.
>If we want to keep that as a placeholder we should also keep the caller as well.
right... I had removed it but brought it back since I noticed the
kernel-doc mentions and forgot to bring back the caller too. I will fix
this in next rev.
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/5] drm/i915: Update IP_VER(12, 50)
2024-03-11 15:29 ` Lucas De Marchi
@ 2024-03-11 16:21 ` Rodrigo Vivi
0 siblings, 0 replies; 22+ messages in thread
From: Rodrigo Vivi @ 2024-03-11 16:21 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Mon, Mar 11, 2024 at 10:29:45AM -0500, Lucas De Marchi wrote:
> On Mon, Mar 11, 2024 at 11:18:03AM -0400, Rodrigo Vivi wrote:
> > On Wed, Mar 06, 2024 at 11:36:41AM -0800, Lucas De Marchi wrote:
> > > With no platform declaring graphics/media IP_VER(12, 50),
> >
> > this is not true.
> > We still have
> >
> > #define XE_HPM_FEATURES \
> > .__runtime.media.ip.ver = 12, \
> > .__runtime.media.ip.rel = 50
>
> <snip>
>
> > > -#define XE_HPM_FEATURES \
> > > - .__runtime.media.ip.ver = 12, \
> > > - .__runtime.media.ip.rel = 50
> > > -
>
> ^ being removed here since all the users, like below, are overriding it.
>
> > > #define DG2_FEATURES \
> > > XE_HP_FEATURES, \
> > > - XE_HPM_FEATURES, \
> > > DGFX_FEATURES, \
> > > + .__runtime.graphics.ip.ver = 12, \
> > > .__runtime.graphics.ip.rel = 55, \
> > > + .__runtime.media.ip.ver = 12, \
> > > .__runtime.media.ip.rel = 55, \
>
> ^^
>
> After applying until this patch:
>
> $ git grep -e "rel[[:space:]]*=" -- drivers/gpu/drm/i915/i915_pci.c
> drivers/gpu/drm/i915/i915_pci.c: .__runtime.graphics.ip.rel = 10,
> drivers/gpu/drm/i915/i915_pci.c: .__runtime.graphics.ip.rel = 55, \
> drivers/gpu/drm/i915/i915_pci.c: .__runtime.media.ip.rel = 55, \
> drivers/gpu/drm/i915/i915_pci.c: .__runtime.graphics.ip.rel = 60,
> drivers/gpu/drm/i915/i915_pci.c: .__runtime.media.ip.rel = 60,
> drivers/gpu/drm/i915/i915_pci.c: .__runtime.graphics.ip.rel = 70,
>
> should I reword anything in the commit message to make my intent
> clearer?
doh! sorry.. I read the first line of the commit message and stopped.
perhaps we could do that HPM removal in a separate patch before this one?
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
on the final result, whatever you decide to split or to rephrase the msg.
>
> thanks
> Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 4/5] drm/i915: Drop dead code for pvc
2024-03-11 15:35 ` Lucas De Marchi
@ 2024-03-11 16:22 ` Rodrigo Vivi
0 siblings, 0 replies; 22+ messages in thread
From: Rodrigo Vivi @ 2024-03-11 16:22 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Mon, Mar 11, 2024 at 10:35:20AM -0500, Lucas De Marchi wrote:
> On Mon, Mar 11, 2024 at 11:29:31AM -0400, Rodrigo Vivi wrote:
> > > @@ -2907,9 +2829,7 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
> > > if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
> > > general_render_compute_wa_init(engine, wal);
> > >
> > > - if (engine->class == COMPUTE_CLASS)
> > > - ccs_engine_wa_init(engine, wal);
> > > - else if (engine->class == RENDER_CLASS)
> >
> > I don't believe we need to remove this chunk since we are not deleting the ccs_engine_wa_init.
> > If we want to keep that as a placeholder we should also keep the caller as well.
>
> right... I had removed it but brought it back since I noticed the
> kernel-doc mentions and forgot to bring back the caller too. I will fix
> this in next rev.
thanks!
with that:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>
> thanks
> Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] drm/i915: cleanup dead code
2024-03-06 19:36 [PATCH 0/5] drm/i915: cleanup dead code Lucas De Marchi
` (4 preceding siblings ...)
2024-03-06 19:36 ` [PATCH 5/5] drm/i915: Remove special handling for !RCS_MASK() Lucas De Marchi
@ 2024-03-11 17:43 ` Tvrtko Ursulin
2024-03-11 19:27 ` Lucas De Marchi
5 siblings, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2024-03-11 17:43 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: dri-devel
On 06/03/2024 19:36, Lucas De Marchi wrote:
> Remove platforms that never had their PCI IDs added to the driver and
> are of course marked with requiring force_probe. Note that most of the
> code for those platforms is actually used by subsequent ones, so it's
> not a huge amount of code being removed.
I had PVC and xehpsdv back in October but could not collect all acks. :(
Last two patches from https://patchwork.freedesktop.org/series/124705/.
Regards,
Tvrtko
> drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h is also changed on the
> xe side, but that should be ok: the defines are there only for compat
> reasons while building the display side (and none of these platforms
> have display, so it's build-issue only).
>
> First patch is what motivated the others and was submitted alone
> @ 20240306144723.1826977-1-lucas.demarchi@intel.com .
> While loooking at this WA I was wondering why we still had some of that
> code around.
>
> Build-tested only for now.
>
> Lucas De Marchi (5):
> drm/i915: Drop WA 16015675438
> drm/i915: Drop dead code for xehpsdv
> drm/i915: Update IP_VER(12, 50)
> drm/i915: Drop dead code for pvc
> drm/i915: Remove special handling for !RCS_MASK()
>
> Documentation/gpu/rfc/i915_vm_bind.h | 11 +-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
> .../gpu/drm/i915/gem/selftests/huge_pages.c | 4 +-
> .../i915/gem/selftests/i915_gem_client_blt.c | 8 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 5 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40 ++--
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 43 +---
> .../drm/i915/gt/intel_execlists_submission.c | 10 +-
> drivers/gpu/drm/i915/gt/intel_gsc.c | 15 --
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 52 +----
> drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 59 ------
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 51 +----
> drivers/gpu/drm/i915/gt/intel_migrate.c | 22 +-
> drivers/gpu/drm/i915/gt/intel_mocs.c | 52 +----
> drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 13 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 193 +-----------------
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 6 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 4 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 -
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
> drivers/gpu/drm/i915/i915_debugfs.c | 12 --
> drivers/gpu/drm/i915/i915_drv.h | 13 --
> drivers/gpu/drm/i915/i915_getparam.c | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
> drivers/gpu/drm/i915/i915_hwmon.c | 6 -
> drivers/gpu/drm/i915/i915_pci.c | 61 +-----
> drivers/gpu/drm/i915/i915_perf.c | 19 +-
> drivers/gpu/drm/i915/i915_query.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 4 +-
> drivers/gpu/drm/i915/intel_clock_gating.c | 26 +--
> drivers/gpu/drm/i915/intel_device_info.c | 2 -
> drivers/gpu/drm/i915/intel_device_info.h | 2 -
> drivers/gpu/drm/i915/intel_step.c | 80 +-------
> drivers/gpu/drm/i915/intel_uncore.c | 159 +--------------
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 3 -
> .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 6 -
> 43 files changed, 110 insertions(+), 928 deletions(-)
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] drm/i915: cleanup dead code
2024-03-11 17:43 ` [PATCH 0/5] drm/i915: cleanup dead code Tvrtko Ursulin
@ 2024-03-11 19:27 ` Lucas De Marchi
2024-03-12 9:54 ` Tvrtko Ursulin
0 siblings, 1 reply; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-11 19:27 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx, dri-devel, Rodrigo Vivi
On Mon, Mar 11, 2024 at 05:43:00PM +0000, Tvrtko Ursulin wrote:
>
>On 06/03/2024 19:36, Lucas De Marchi wrote:
>>Remove platforms that never had their PCI IDs added to the driver and
>>are of course marked with requiring force_probe. Note that most of the
>>code for those platforms is actually used by subsequent ones, so it's
>>not a huge amount of code being removed.
>
>I had PVC and xehpsdv back in October but could not collect all acks. :(
>
>Last two patches from https://patchwork.freedesktop.org/series/124705/.
oh... I was actually surprised we still had xehpsdv while removing a
WA for PVC, which made me look into removing these platforms.
rebasing your series and comparing yours..my-v2, where my-v2 only has
patches 2 and 4, I have the diff below. I think it's small enough that I
can just take your commits and squash delta. Is that ok to you?
my version is a little bit more aggressive, also doing some renames
s/xehpsdv/xehp/ and dropping some more code
(engine_mask_apply_copy_fuses(), unused registers, default ctx, fw
ranges).
diff --git a/Documentation/gpu/rfc/i915_vm_bind.h b/Documentation/gpu/rfc/i915_vm_bind.h
index 8a8fcd4fceac..bc26dc126104 100644
--- a/Documentation/gpu/rfc/i915_vm_bind.h
+++ b/Documentation/gpu/rfc/i915_vm_bind.h
@@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
* Multiple VA mappings can be created to the same section of the object
* (aliasing).
*
- * The @start, @offset and @length must be 4K page aligned. However the DG2
- * and XEHPSDV has 64K page size for device local memory and has compact page
- * table. On those platforms, for binding device local-memory objects, the
- * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
- * the local memory 64K page and the system memory 4K page bindings in the same
- * 2M range.
+ * The @start, @offset and @length must be 4K page aligned. However the DG2 has
+ * 64K page size for device local memory and has compact page table. On that
+ * platform, for binding device local-memory objects, the @start, @offset and
+ * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K
+ * page and the system memory 4K page bindings in the same 2M range.
*
* Error code -EINVAL will be returned if @start, @offset and @length are not
* properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 1495b6074492..d3300ae3053f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -386,7 +386,7 @@ struct drm_i915_gem_object {
* and kernel mode driver for caching policy control after GEN12.
* In the meantime platform specific tables are created to translate
* i915_cache_level into pat index, for more details check the macros
- * defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.
+ * defined i915/i915_pci.c, e.g. MTL_CACHELEVEL.
* For backward compatibility, this field contains values exactly match
* the entries of enum i915_cache_level for pre-GEN12 platforms (See
* LEGACY_CACHELEVEL), so that the PTE encode functions for these
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index fa46d2308b0e..1bd0e041e15c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
}
static void
-xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
- struct i915_vma_resource *vma_res,
- struct sgt_dma *iter,
- unsigned int pat_index,
- u32 flags)
+xehp_ppgtt_insert_huge(struct i915_address_space *vm,
+ struct i915_vma_resource *vma_res,
+ struct sgt_dma *iter,
+ unsigned int pat_index,
+ u32 flags)
{
const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
unsigned int rem = sg_dma_len(iter->sg);
@@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
struct sgt_dma iter = sgt_dma(vma_res);
if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
- if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
- xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
+ if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
+ xehp_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
else
gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
} else {
@@ -781,11 +781,11 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
-static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
- dma_addr_t addr,
- u64 offset,
- unsigned int pat_index,
- u32 flags)
+static void xehp_ppgtt_insert_entry_lm(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ unsigned int pat_index,
+ u32 flags)
{
u64 idx = offset >> GEN8_PTE_SHIFT;
struct i915_page_directory * const pdp =
@@ -810,15 +810,15 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, pat_index, flags);
}
-static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
- dma_addr_t addr,
- u64 offset,
- unsigned int pat_index,
- u32 flags)
+static void xehp_ppgtt_insert_entry(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ unsigned int pat_index,
+ u32 flags)
{
if (flags & PTE_LM)
- return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
- pat_index, flags);
+ return xehp_ppgtt_insert_entry_lm(vm, addr, offset,
+ pat_index, flags);
return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index, flags);
}
@@ -1042,7 +1042,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
if (HAS_64K_PAGES(gt->i915))
- ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
+ ppgtt->vm.insert_page = xehp_ppgtt_insert_entry;
else
ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f553cf4e6449..423d72115af0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -839,38 +839,6 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
}
}
-static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
-{
- struct drm_i915_private *i915 = gt->i915;
- struct intel_gt_info *info = >->info;
- unsigned long meml3_mask;
- unsigned long quad;
-
- if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
- GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
- return;
-
- meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
- meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
-
- /*
- * Link Copy engines may be fused off according to meml3_mask. Each
- * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
- */
- for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
- unsigned int instance = quad * 2 + 1;
- intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
- _BCS(instance));
-
- if (mask & info->engine_mask) {
- gt_dbg(gt, "bcs%u fused off\n", instance);
- gt_dbg(gt, "bcs%u fused off\n", instance + 1);
-
- info->engine_mask &= ~mask;
- }
- }
-}
-
/*
* Determine which engines are fused off in our particular hardware.
* Note that we have a catch-22 situation where we need to be able to access
@@ -889,7 +857,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
engine_mask_apply_media_fuses(gt);
engine_mask_apply_compute_fuses(gt);
- engine_mask_apply_copy_fuses(gt);
/*
* The only use of the GSC CS is to load and communicate with the GSC
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 2f386f531c55..ee5115b12a21 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -57,7 +57,7 @@ static const struct intel_mmio_range icl_l3bank_steering_table[] = {
* are of a "GAM" subclass that has special rules. Thus we use a separate
* GAM table farther down for those.
*/
-static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
+static const struct intel_mmio_range dg2_mslice_steering_table[] = {
{ 0x00DD00, 0x00DDFF },
{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
{},
@@ -153,7 +153,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;
gt->steering_table[DSS] = xelpg_dss_steering_table;
} else if (IS_DG2(i915)) {
- gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
+ gt->steering_table[MSLICE] = dg2_mslice_steering_table;
gt->steering_table[LNCF] = dg2_lncf_steering_table;
/*
* No need to hook up the GAM table since it has a dedicated
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 0635c9288742..8d8d781b44b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -723,38 +723,6 @@
#define HSUNIT_CLKGATE_DIS REG_BIT(8)
#define VSUNIT_CLKGATE_DIS REG_BIT(3)
-#define UNSLCGCTL9440 _MMIO(0x9440)
-#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
-#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
-#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
-#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
-#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
-#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
-#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
-#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
-#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
-#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
-#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
-#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
-
-#define UNSLCGCTL9444 _MMIO(0x9444)
-#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
-#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
-#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
-#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
-#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
-#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
-#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
-#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
-#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
-#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
-#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
-#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
-#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
-#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
-#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
-#define LTCDD_CLKGATE_DIS REG_BIT(10)
-
#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
@@ -764,9 +732,6 @@
#define L3_CLKGATE_DIS REG_BIT(16)
#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
-#define SCCGCTL94DC MCR_REG(0x94dc)
-#define CG3DDISURB REG_BIT(14)
-
#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
@@ -988,10 +953,6 @@
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
#define GEN7_L3AGDIS (1 << 19)
-#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c)
-#define XEHPC_HOSTCACHEEN REG_BIT(1)
-#define XEHPC_OVRLSCCC REG_BIT(0)
-
#define GEN7_L3CNTLREG2 _MMIO(0xb020)
/* MOCS (Memory Object Control State) registers */
@@ -1045,20 +1006,9 @@
#define XEHP_L3SQCREG5 MCR_REG(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
-#define MLTICTXCTL MCR_REG(0xb170)
-#define TDONRENDER REG_BIT(2)
-
#define XEHP_L3SCQREG7 MCR_REG(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
-#define XEHPC_L3SCRUB MCR_REG(0xb18c)
-#define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12)
-#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
-#define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
-
-#define L3SQCREG1_CCS0 MCR_REG(0xb200)
-#define FLUSHALLNONCOH REG_BIT(5)
-
#define GEN11_GLBLINVL _MMIO(0xb404)
#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
@@ -1108,7 +1058,6 @@
#define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
#define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */
-#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
#define RENDER_MOD_CTRL MCR_REG(0xcf2c)
#define COMP_MOD_CTRL MCR_REG(0xcf30)
#define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */
@@ -1184,7 +1133,6 @@
#define EU_PERF_CNTL4 PERF_REG(0xe45c)
#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
-#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
@@ -1201,7 +1149,6 @@
#define FLOW_CONTROL_ENABLE REG_BIT(15)
#define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12)
-#define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
#define STALL_DOP_GATING_DISABLE REG_BIT(5)
#define THROTTLE_12_5 REG_GENMASK(4, 2)
@@ -1678,11 +1625,6 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
-#define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004)
-#define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008)
-#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
-#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
-
/*
* Standalone Media's non-engine GT registers are located at their regular GT
* offsets plus 0x380000. This extra offset is stored inside the intel_uncore
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 90644e47d261..d7784650e4d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -582,9 +582,10 @@ static ssize_t media_freq_factor_show(struct kobject *kobj,
*/
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
+
mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
- SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
- SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
+ SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
+ SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7c367ba8d9dc..7f1b00cb9924 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -546,47 +546,6 @@ static const u8 gen12_rcs_offsets[] = {
END
};
-static const u8 xehp_rcs_offsets[] = {
- NOP(1),
- LRI(13, POSTED),
- REG16(0x244),
- REG(0x034),
- REG(0x030),
- REG(0x038),
- REG(0x03c),
- REG(0x168),
- REG(0x140),
- REG(0x110),
- REG(0x1c0),
- REG(0x1c4),
- REG(0x1c8),
- REG(0x180),
- REG16(0x2b4),
-
- NOP(5),
- LRI(9, POSTED),
- REG16(0x3a8),
- REG16(0x28c),
- REG16(0x288),
- REG16(0x284),
- REG16(0x280),
- REG16(0x27c),
- REG16(0x278),
- REG16(0x274),
- REG16(0x270),
-
- LRI(3, POSTED),
- REG(0x1b0),
- REG16(0x5a8),
- REG16(0x5ac),
-
- NOP(6),
- LRI(1, 0),
- REG(0x0c8),
-
- END
-};
-
static const u8 dg2_rcs_offsets[] = {
NOP(1),
LRI(15, POSTED),
@@ -695,8 +654,6 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
return mtl_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
- else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
- return xehp_rcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_rcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 11)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 576e5ef0289b..86ba2f2e485c 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -35,9 +35,9 @@ static bool engine_supports_migration(struct intel_engine_cs *engine)
return true;
}
-static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
- struct i915_page_table *pt,
- void *data)
+static void xehp_toggle_pdes(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
{
struct insert_pte_data *d = data;
@@ -52,9 +52,9 @@ static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
d->offset += SZ_2M;
}
-static void xehpsdv_insert_pte(struct i915_address_space *vm,
- struct i915_page_table *pt,
- void *data)
+static void xehp_insert_pte(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
{
struct insert_pte_data *d = data;
@@ -120,7 +120,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
* 512 entry layout using 4K GTT pages. The other two windows just map
* lmem pages and must use the new compact 32 entry layout using 64K GTT
* pages, which ensures we can address any lmem object that the user
- * throws at us. We then also use the xehpsdv_toggle_pdes as a way of
+ * throws at us. We then also use the xehp_toggle_pdes as a way of
* just toggling the PDE bit(GEN12_PDE_64K) for us, to enable the
* compact layout for each of these page-tables, that fall within the
* [CHUNK_SIZE, 3 * CHUNK_SIZE) range.
@@ -209,12 +209,12 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
/* Now allow the GPU to rewrite the PTE via its own ppGTT */
if (HAS_64K_PAGES(gt->i915)) {
vm->vm.foreach(&vm->vm, base, d.offset - base,
- xehpsdv_insert_pte, &d);
+ xehp_insert_pte, &d);
d.offset = base + CHUNK_SZ;
vm->vm.foreach(&vm->vm,
d.offset,
2 * CHUNK_SZ,
- xehpsdv_toggle_pdes, &d);
+ xehp_toggle_pdes, &d);
} else {
vm->vm.foreach(&vm->vm, base, d.offset - base,
insert_pte, &d);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 7889147b44b7..804654ab80ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2661,6 +2661,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static void
ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
+ /* boilerplate for any CCS engine workaround */
}
/*
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f68ec0a1c17d..1637c1d235e9 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2881,7 +2881,7 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
int ret;
/*
- * Wa_1508761755:xehpsdv, dg2
+ * Wa_1508761755
* EU NOA signals behave incorrectly if EU clock gating is enabled.
* Disable thread stall DOP gating and EU DOP gating.
*/
@@ -2911,7 +2911,7 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
/*
* Initialize Super Queue Internal Cnt Register
* Set PMON Enable in order to collect valid metrics.
- * Enable byets per clock reporting in OA for XEHPSDV onward.
+ * Enable byets per clock reporting in OA.
*/
sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
@@ -2971,8 +2971,7 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
u32 sqcnt1;
/*
- * Wa_1508761755:xehpsdv, dg2
- * Enable thread stall DOP gating and EU DOP gating.
+ * Wa_1508761755: Enable thread stall DOP gating and EU DOP gating.
*/
if (IS_DG2(i915)) {
intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bdc409085b9a..f62573d48c76 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5399,7 +5399,7 @@
#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
-#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
+#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e
/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 58d6c68195e0..40d56f02b5c6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1497,17 +1497,16 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
0x13200 - 0x133ff: VD2 (DG2 only) \
0x13400 - 0x13fff: reserved */ \
- GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
+ GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), \
+ GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), \
+ GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), \
+ GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), \
GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
0x15000 - 0x15fff: gt (DG2 only) \
0x16000 - 0x16dff: reserved */ \
GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
- 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
+ GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
0x21000 - 0x21fff: reserved */ \
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
@@ -1588,10 +1587,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
0x1f6e00 - 0x1f7fff: reserved */ \
GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
-static const struct intel_forcewake_range __xehp_fw_ranges[] = {
- XEHP_FWRANGES(FORCEWAKE_GT)
-};
-
static const struct intel_forcewake_range __dg2_fw_ranges[] = {
XEHP_FWRANGES(FORCEWAKE_RENDER)
};
@@ -2442,10 +2437,6 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
- } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
- ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
- ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
} else if (GRAPHICS_VER(i915) >= 12) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index c998f15d505c..41eaa9b7f67d 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -118,7 +118,6 @@ int intel_uncore_mock_selftests(void)
{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
- { __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
{ __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
{ __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
};
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index a86d00a9758f..a01d1b869c2d 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -85,9 +85,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)
-#define IS_XEHPSDV(dev_priv) (dev_priv && 0)
#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
-#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
@@ -130,7 +128,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
#define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \
((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
IS_GRAPHICS_STEP(xe, first, last))
-#define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last) (IS_XEHPSDV(xe) && IS_GRAPHICS_STEP(xe, first, last))
#define IS_TIGERLAKE_DISPLAY_STEP(xe, first, last) (IS_TIGERLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
#define IS_ROCKETLAKE_DISPLAY_STEP(xe, first, last) (IS_ROCKETLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
Let me know what you prefer. If squashing these changes to your patches,
then I'd add the other patches in this series on top.
thanks
Lucas De Marchi
>
>Regards,
>
>Tvrtko
>
>>drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h is also changed on the
>>xe side, but that should be ok: the defines are there only for compat
>>reasons while building the display side (and none of these platforms
>>have display, so it's build-issue only).
>>
>>First patch is what motivated the others and was submitted alone
>>@ 20240306144723.1826977-1-lucas.demarchi@intel.com .
>>While loooking at this WA I was wondering why we still had some of that
>>code around.
>>
>>Build-tested only for now.
>>
>>Lucas De Marchi (5):
>> drm/i915: Drop WA 16015675438
>> drm/i915: Drop dead code for xehpsdv
>> drm/i915: Update IP_VER(12, 50)
>> drm/i915: Drop dead code for pvc
>> drm/i915: Remove special handling for !RCS_MASK()
>>
>> Documentation/gpu/rfc/i915_vm_bind.h | 11 +-
>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
>> .../gpu/drm/i915/gem/selftests/huge_pages.c | 4 +-
>> .../i915/gem/selftests/i915_gem_client_blt.c | 8 +-
>> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 5 +-
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40 ++--
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 43 +---
>> .../drm/i915/gt/intel_execlists_submission.c | 10 +-
>> drivers/gpu/drm/i915/gt/intel_gsc.c | 15 --
>> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +-
>> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 52 +----
>> drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 +-
>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 59 ------
>> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 +-
>> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_lrc.c | 51 +----
>> drivers/gpu/drm/i915/gt/intel_migrate.c | 22 +-
>> drivers/gpu/drm/i915/gt/intel_mocs.c | 52 +----
>> drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
>> drivers/gpu/drm/i915/gt/intel_sseu.c | 13 +-
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 193 +-----------------
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 6 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 4 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 -
>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
>> drivers/gpu/drm/i915/i915_debugfs.c | 12 --
>> drivers/gpu/drm/i915/i915_drv.h | 13 --
>> drivers/gpu/drm/i915/i915_getparam.c | 4 +-
>> drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
>> drivers/gpu/drm/i915/i915_hwmon.c | 6 -
>> drivers/gpu/drm/i915/i915_pci.c | 61 +-----
>> drivers/gpu/drm/i915/i915_perf.c | 19 +-
>> drivers/gpu/drm/i915/i915_query.c | 2 +-
>> drivers/gpu/drm/i915/i915_reg.h | 4 +-
>> drivers/gpu/drm/i915/intel_clock_gating.c | 26 +--
>> drivers/gpu/drm/i915/intel_device_info.c | 2 -
>> drivers/gpu/drm/i915/intel_device_info.h | 2 -
>> drivers/gpu/drm/i915/intel_step.c | 80 +-------
>> drivers/gpu/drm/i915/intel_uncore.c | 159 +--------------
>> drivers/gpu/drm/i915/selftests/intel_uncore.c | 3 -
>> .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 6 -
>> 43 files changed, 110 insertions(+), 928 deletions(-)
>>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] drm/i915: cleanup dead code
2024-03-11 19:27 ` Lucas De Marchi
@ 2024-03-12 9:54 ` Tvrtko Ursulin
2024-03-12 12:53 ` Lucas De Marchi
0 siblings, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2024-03-12 9:54 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel, Rodrigo Vivi
On 11/03/2024 19:27, Lucas De Marchi wrote:
> On Mon, Mar 11, 2024 at 05:43:00PM +0000, Tvrtko Ursulin wrote:
>>
>> On 06/03/2024 19:36, Lucas De Marchi wrote:
>>> Remove platforms that never had their PCI IDs added to the driver and
>>> are of course marked with requiring force_probe. Note that most of the
>>> code for those platforms is actually used by subsequent ones, so it's
>>> not a huge amount of code being removed.
>>
>> I had PVC and xehpsdv back in October but could not collect all acks. :(
>>
>> Last two patches from https://patchwork.freedesktop.org/series/124705/.
>
> oh... I was actually surprised we still had xehpsdv while removing a
> WA for PVC, which made me look into removing these platforms.
>
> rebasing your series and comparing yours..my-v2, where my-v2 only has
> patches 2 and 4, I have the diff below. I think it's small enough that I
> can just take your commits and squash delta. Is that ok to you?
>
> my version is a little bit more aggressive, also doing some renames
> s/xehpsdv/xehp/ and dropping some more code
> (engine_mask_apply_copy_fuses(), unused registers, default ctx, fw
> ranges).
Right, yeah I see I missed some case combos in the comments when
grepping and more.
> diff --git a/Documentation/gpu/rfc/i915_vm_bind.h
> b/Documentation/gpu/rfc/i915_vm_bind.h
> index 8a8fcd4fceac..bc26dc126104 100644
> --- a/Documentation/gpu/rfc/i915_vm_bind.h
> +++ b/Documentation/gpu/rfc/i915_vm_bind.h
> @@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
> * Multiple VA mappings can be created to the same section of the
> object
> * (aliasing).
> *
> - * The @start, @offset and @length must be 4K page aligned.
> However the DG2
> - * and XEHPSDV has 64K page size for device local memory and has
> compact page
> - * table. On those platforms, for binding device local-memory
> objects, the
> - * @start, @offset and @length must be 64K aligned. Also, UMDs
> should not mix
> - * the local memory 64K page and the system memory 4K page
> bindings in the same
> - * 2M range.
> + * The @start, @offset and @length must be 4K page aligned.
> However the DG2 has
> + * 64K page size for device local memory and has compact page
> table. On that
> + * platform, for binding device local-memory objects, the @start,
> @offset and
> + * @length must be 64K aligned. Also, UMDs should not mix the
> local memory 64K
> + * page and the system memory 4K page bindings in the same 2M range.
> *
> * Error code -EINVAL will be returned if @start, @offset and
> @length are not
> * properly aligned. In version 1 (See
> I915_PARAM_VM_BIND_VERSION), error code
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 1495b6074492..d3300ae3053f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -386,7 +386,7 @@ struct drm_i915_gem_object {
> * and kernel mode driver for caching policy control after GEN12.
> * In the meantime platform specific tables are created to
> translate
> * i915_cache_level into pat index, for more details check the
> macros
> - * defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.
> + * defined i915/i915_pci.c, e.g. MTL_CACHELEVEL.
Why this?
> * For backward compatibility, this field contains values
> exactly match
> * the entries of enum i915_cache_level for pre-GEN12 platforms
> (See
> * LEGACY_CACHELEVEL), so that the PTE encode functions for these
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index fa46d2308b0e..1bd0e041e15c 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
> }
> static void
> -xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
> - struct i915_vma_resource *vma_res,
> - struct sgt_dma *iter,
> - unsigned int pat_index,
> - u32 flags)
> +xehp_ppgtt_insert_huge(struct i915_address_space *vm,
> + struct i915_vma_resource *vma_res,
> + struct sgt_dma *iter,
> + unsigned int pat_index,
> + u32 flags)
> {
> const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
> unsigned int rem = sg_dma_len(iter->sg);
> @@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct
> i915_address_space *vm,
> struct sgt_dma iter = sgt_dma(vma_res);
> if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
> - if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
> - xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter,
> pat_index, flags);
> + if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
> + xehp_ppgtt_insert_huge(vm, vma_res, &iter, pat_index,
> flags);
> else
> gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index,
> flags);
> } else {
> @@ -781,11 +781,11 @@ static void gen8_ppgtt_insert_entry(struct
> i915_address_space *vm,
> drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)],
> sizeof(*vaddr));
> }
> -static void __xehpsdv_ppgtt_insert_entry_lm(struct
> i915_address_space *vm,
> - dma_addr_t addr,
> - u64 offset,
> - unsigned int pat_index,
> - u32 flags)
> +static void xehp_ppgtt_insert_entry_lm(struct i915_address_space *vm,
> + dma_addr_t addr,
> + u64 offset,
> + unsigned int pat_index,
> + u32 flags)
> {
> u64 idx = offset >> GEN8_PTE_SHIFT;
> struct i915_page_directory * const pdp =
> @@ -810,15 +810,15 @@ static void
> __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
> vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr,
> pat_index, flags);
> }
> -static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
> - dma_addr_t addr,
> - u64 offset,
> - unsigned int pat_index,
> - u32 flags)
> +static void xehp_ppgtt_insert_entry(struct i915_address_space *vm,
> + dma_addr_t addr,
> + u64 offset,
> + unsigned int pat_index,
> + u32 flags)
> {
> if (flags & PTE_LM)
> - return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
> - pat_index, flags);
> + return xehp_ppgtt_insert_entry_lm(vm, addr, offset,
> + pat_index, flags);
> return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index,
> flags);
> }
> @@ -1042,7 +1042,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct
> intel_gt *gt,
> ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
> ppgtt->vm.insert_entries = gen8_ppgtt_insert;
> if (HAS_64K_PAGES(gt->i915))
> - ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
> + ppgtt->vm.insert_page = xehp_ppgtt_insert_entry;
> else
> ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
> ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index f553cf4e6449..423d72115af0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -839,38 +839,6 @@ static void
> engine_mask_apply_compute_fuses(struct intel_gt *gt)
> }
> }
> -static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
> -{
> - struct drm_i915_private *i915 = gt->i915;
> - struct intel_gt_info *info = >->info;
> - unsigned long meml3_mask;
> - unsigned long quad;
> -
> - if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
> - GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
> - return;
I trust you know this is correct. :) Without a easy to reach table of
platform codenames to ip block version I give up.
> -
> - meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> - meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
> -
> - /*
> - * Link Copy engines may be fused off according to meml3_mask.
> Each
> - * bit is a quad that houses 2 Link Copy and two Sub Copy
> engines.
> - */
> - for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
> - unsigned int instance = quad * 2 + 1;
> - intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
> - _BCS(instance));
> -
> - if (mask & info->engine_mask) {
> - gt_dbg(gt, "bcs%u fused off\n", instance);
> - gt_dbg(gt, "bcs%u fused off\n", instance + 1);
> -
> - info->engine_mask &= ~mask;
> - }
> - }
> -}
> -
> /*
> * Determine which engines are fused off in our particular hardware.
> * Note that we have a catch-22 situation where we need to be able
> to access
> @@ -889,7 +857,6 @@ static intel_engine_mask_t
> init_engine_mask(struct intel_gt *gt)
> engine_mask_apply_media_fuses(gt);
> engine_mask_apply_compute_fuses(gt);
> - engine_mask_apply_copy_fuses(gt);
> /*
> * The only use of the GSC CS is to load and communicate with
> the GSC
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 2f386f531c55..ee5115b12a21 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -57,7 +57,7 @@ static const struct intel_mmio_range
> icl_l3bank_steering_table[] = {
> * are of a "GAM" subclass that has special rules. Thus we use a
> separate
> * GAM table farther down for those.
> */
> -static const struct intel_mmio_range
> xehpsdv_mslice_steering_table[] = {
> +static const struct intel_mmio_range dg2_mslice_steering_table[] = {
> { 0x00DD00, 0x00DDFF },
> { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
> {},
> @@ -153,7 +153,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;
> gt->steering_table[DSS] = xelpg_dss_steering_table;
> } else if (IS_DG2(i915)) {
> - gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> + gt->steering_table[MSLICE] = dg2_mslice_steering_table;
> gt->steering_table[LNCF] = dg2_lncf_steering_table;
> /*
> * No need to hook up the GAM table since it has a dedicated
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 0635c9288742..8d8d781b44b6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -723,38 +723,6 @@
> #define HSUNIT_CLKGATE_DIS REG_BIT(8)
> #define VSUNIT_CLKGATE_DIS REG_BIT(3)
> -#define UNSLCGCTL9440 _MMIO(0x9440)
> -#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
> -#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
> -#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
> -#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
> -#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
> -#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
> -#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
> -#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
> -#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
> -#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
> -#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
> -#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
> -
> -#define UNSLCGCTL9444 _MMIO(0x9444)
> -#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
> -#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
> -#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
> -#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
> -#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
> -#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
> -#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
> -#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
> -#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
> -#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
> -#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
> -#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
> -#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
> -#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
> -#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
> -#define LTCDD_CLKGATE_DIS REG_BIT(10)
> -
> #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> #define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
> #define SARBUNIT_CLKGATE_DIS (1 << 5)
> @@ -764,9 +732,6 @@
> #define L3_CLKGATE_DIS REG_BIT(16)
> #define L3_CR2X_CLKGATE_DIS REG_BIT(17)
> -#define SCCGCTL94DC MCR_REG(0x94dc)
> -#define CG3DDISURB REG_BIT(14)
> -
> #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
> #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
> #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
> @@ -988,10 +953,6 @@
> #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
> #define GEN7_L3AGDIS (1 << 19)
> -#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c)
> -#define XEHPC_HOSTCACHEEN REG_BIT(1)
> -#define XEHPC_OVRLSCCC REG_BIT(0)
> -
> #define GEN7_L3CNTLREG2 _MMIO(0xb020)
> /* MOCS (Memory Object Control State) registers */
> @@ -1045,20 +1006,9 @@
> #define XEHP_L3SQCREG5 MCR_REG(0xb158)
> #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
> -#define MLTICTXCTL MCR_REG(0xb170)
> -#define TDONRENDER REG_BIT(2)
> -
> #define XEHP_L3SCQREG7 MCR_REG(0xb188)
> #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
> -#define XEHPC_L3SCRUB MCR_REG(0xb18c)
> -#define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12)
> -#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
> -#define SCRUB_RATE_4B_PER_CLK
> REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
> -
> -#define L3SQCREG1_CCS0 MCR_REG(0xb200)
> -#define FLUSHALLNONCOH REG_BIT(5)
> -
> #define GEN11_GLBLINVL _MMIO(0xb404)
> #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
> #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
> @@ -1108,7 +1058,6 @@
> #define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
> #define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media
> GT only */
> -#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
> #define RENDER_MOD_CTRL MCR_REG(0xcf2c)
> #define COMP_MOD_CTRL MCR_REG(0xcf30)
> #define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media
> GT only */
> @@ -1184,7 +1133,6 @@
> #define EU_PERF_CNTL4 PERF_REG(0xe45c)
> #define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
> -#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
> #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
> #define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
> #define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
> @@ -1201,7 +1149,6 @@
> #define FLOW_CONTROL_ENABLE REG_BIT(15)
> #define UGM_BACKUP_MODE REG_BIT(13)
> #define MDQ_ARBITRATION_MODE REG_BIT(12)
> -#define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10)
> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
> #define STALL_DOP_GATING_DISABLE REG_BIT(5)
> #define THROTTLE_12_5 REG_GENMASK(4, 2)
> @@ -1678,11 +1625,6 @@
> #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
> -#define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004)
> -#define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008)
> -#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
> -#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
> -
> /*
> * Standalone Media's non-engine GT registers are located at their
> regular GT
> * offsets plus 0x380000. This extra offset is stored inside the
> intel_uncore
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index 90644e47d261..d7784650e4d9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -582,9 +582,10 @@ static ssize_t media_freq_factor_show(struct
> kobject *kobj,
> */
> with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
> +
> mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
> - SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
> - SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
> + SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
> + SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
Something is off in someone's version here.
> return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7c367ba8d9dc..7f1b00cb9924 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -546,47 +546,6 @@ static const u8 gen12_rcs_offsets[] = {
> END
> };
> -static const u8 xehp_rcs_offsets[] = {
> - NOP(1),
> - LRI(13, POSTED),
> - REG16(0x244),
> - REG(0x034),
> - REG(0x030),
> - REG(0x038),
> - REG(0x03c),
> - REG(0x168),
> - REG(0x140),
> - REG(0x110),
> - REG(0x1c0),
> - REG(0x1c4),
> - REG(0x1c8),
> - REG(0x180),
> - REG16(0x2b4),
> -
> - NOP(5),
> - LRI(9, POSTED),
> - REG16(0x3a8),
> - REG16(0x28c),
> - REG16(0x288),
> - REG16(0x284),
> - REG16(0x280),
> - REG16(0x27c),
> - REG16(0x278),
> - REG16(0x274),
> - REG16(0x270),
> -
> - LRI(3, POSTED),
> - REG(0x1b0),
> - REG16(0x5a8),
> - REG16(0x5ac),
> -
> - NOP(6),
> - LRI(1, 0),
> - REG(0x0c8),
> -
> - END
> -};
> -
> static const u8 dg2_rcs_offsets[] = {
> NOP(1),
> LRI(15, POSTED),
> @@ -695,8 +654,6 @@ static const u8 *reg_offsets(const struct
> intel_engine_cs *engine)
> return mtl_rcs_offsets;
> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_rcs_offsets;
> - else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> - return xehp_rcs_offsets;
> else if (GRAPHICS_VER(engine->i915) >= 12)
> return gen12_rcs_offsets;
> else if (GRAPHICS_VER(engine->i915) >= 11)
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
> b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 576e5ef0289b..86ba2f2e485c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -35,9 +35,9 @@ static bool engine_supports_migration(struct
> intel_engine_cs *engine)
> return true;
> }
> -static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
> - struct i915_page_table *pt,
> - void *data)
> +static void xehp_toggle_pdes(struct i915_address_space *vm,
> + struct i915_page_table *pt,
> + void *data)
> {
> struct insert_pte_data *d = data;
> @@ -52,9 +52,9 @@ static void xehpsdv_toggle_pdes(struct
> i915_address_space *vm,
> d->offset += SZ_2M;
> }
> -static void xehpsdv_insert_pte(struct i915_address_space *vm,
> - struct i915_page_table *pt,
> - void *data)
> +static void xehp_insert_pte(struct i915_address_space *vm,
> + struct i915_page_table *pt,
> + void *data)
> {
> struct insert_pte_data *d = data;
> @@ -120,7 +120,7 @@ static struct i915_address_space
> *migrate_vm(struct intel_gt *gt)
> * 512 entry layout using 4K GTT pages. The other two windows
> just map
> * lmem pages and must use the new compact 32 entry layout
> using 64K GTT
> * pages, which ensures we can address any lmem object that the
> user
> - * throws at us. We then also use the xehpsdv_toggle_pdes as a
> way of
> + * throws at us. We then also use the xehp_toggle_pdes as a
> way of
> * just toggling the PDE bit(GEN12_PDE_64K) for us, to enable the
> * compact layout for each of these page-tables, that fall
> within the
> * [CHUNK_SIZE, 3 * CHUNK_SIZE) range.
> @@ -209,12 +209,12 @@ static struct i915_address_space
> *migrate_vm(struct intel_gt *gt)
> /* Now allow the GPU to rewrite the PTE via its own ppGTT */
> if (HAS_64K_PAGES(gt->i915)) {
> vm->vm.foreach(&vm->vm, base, d.offset - base,
> - xehpsdv_insert_pte, &d);
> + xehp_insert_pte, &d);
> d.offset = base + CHUNK_SZ;
> vm->vm.foreach(&vm->vm,
> d.offset,
> 2 * CHUNK_SZ,
> - xehpsdv_toggle_pdes, &d);
> + xehp_toggle_pdes, &d);
> } else {
> vm->vm.foreach(&vm->vm, base, d.offset - base,
> insert_pte, &d);
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 7889147b44b7..804654ab80ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2661,6 +2661,7 @@ xcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> static void
> ccs_engine_wa_init(struct intel_engine_cs *engine, struct
> i915_wa_list *wal)
> {
> + /* boilerplate for any CCS engine workaround */
> }
> /*
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index f68ec0a1c17d..1637c1d235e9 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2881,7 +2881,7 @@ gen12_enable_metric_set(struct
> i915_perf_stream *stream,
> int ret;
> /*
> - * Wa_1508761755:xehpsdv, dg2
> + * Wa_1508761755
> * EU NOA signals behave incorrectly if EU clock gating is
> enabled.
> * Disable thread stall DOP gating and EU DOP gating.
> */
> @@ -2911,7 +2911,7 @@ gen12_enable_metric_set(struct
> i915_perf_stream *stream,
> /*
> * Initialize Super Queue Internal Cnt Register
> * Set PMON Enable in order to collect valid metrics.
> - * Enable byets per clock reporting in OA for XEHPSDV onward.
> + * Enable byets per clock reporting in OA.
Could you fix byets while touching the line?
> */
> sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
> (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
> @@ -2971,8 +2971,7 @@ static void gen12_disable_metric_set(struct
> i915_perf_stream *stream)
> u32 sqcnt1;
> /*
> - * Wa_1508761755:xehpsdv, dg2
> - * Enable thread stall DOP gating and EU DOP gating.
> + * Wa_1508761755: Enable thread stall DOP gating and EU DOP
> gating.
> */
> if (IS_DG2(i915)) {
> intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index bdc409085b9a..f62573d48c76 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5399,7 +5399,7 @@
> #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed
> point format */
> #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
> #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> -#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv,
> pvc */
> +#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e
> /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
> #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 58d6c68195e0..40d56f02b5c6 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1497,17 +1497,16 @@ static const struct intel_forcewake_range
> __gen12_fw_ranges[] = {
> GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2),
> /* \
> 0x13200 - 0x133ff: VD2 (DG2 only) \
> 0x13400 - 0x13fff: reserved */ \
> - GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /*
> XEHPSDV only */ \
> - GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /*
> XEHPSDV only */ \
> - GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /*
> XEHPSDV only */ \
> - GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /*
> XEHPSDV only */ \
> + GEN_FW_RANGE(0x14000, 0x141ff,
> FORCEWAKE_MEDIA_VDBOX0), \
> + GEN_FW_RANGE(0x14200, 0x143ff,
> FORCEWAKE_MEDIA_VDBOX2), \
> + GEN_FW_RANGE(0x14400, 0x145ff,
> FORCEWAKE_MEDIA_VDBOX4), \
> + GEN_FW_RANGE(0x14600, 0x147ff,
> FORCEWAKE_MEDIA_VDBOX6), \
I see Rodrigo and you were discussing this hunk so I will just skip over.
> GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
> GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
> 0x15000 - 0x15fff: gt (DG2 only) \
> 0x16000 - 0x16dff: reserved */ \
> GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
> - GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0),
> /* \
> - 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
> + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0),
> /* \
> 0x21000 - 0x21fff: reserved */ \
> GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
> GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
> @@ -1588,10 +1587,6 @@ static const struct intel_forcewake_range
> __gen12_fw_ranges[] = {
> 0x1f6e00 - 0x1f7fff: reserved */ \
> GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
> - XEHP_FWRANGES(FORCEWAKE_GT)
> -};
> -
> static const struct intel_forcewake_range __dg2_fw_ranges[] = {
> XEHP_FWRANGES(FORCEWAKE_RENDER)
> };
> @@ -2442,10 +2437,6 @@ static int uncore_forcewake_init(struct
> intel_uncore *uncore)
> ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
> ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
> ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> - } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> - ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
> - ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> } else if (GRAPHICS_VER(i915) >= 12) {
> ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
> ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index c998f15d505c..41eaa9b7f67d 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -118,7 +118,6 @@ int intel_uncore_mock_selftests(void)
> { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
> { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
> { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
> - { __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
> { __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
> { __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
> };
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> index a86d00a9758f..a01d1b869c2d 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
> @@ -85,9 +85,7 @@ static inline struct drm_i915_private
> *kdev_to_i915(struct device *kdev)
> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1)
> #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv,
> XE_ALDERLAKE_S)
> #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv,
> XE_ALDERLAKE_P)
> -#define IS_XEHPSDV(dev_priv) (dev_priv && 0)
> #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
> -#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
> #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
> #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
> @@ -130,7 +128,6 @@ static inline struct drm_i915_private
> *kdev_to_i915(struct device *kdev)
> #define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \
> ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
> IS_GRAPHICS_STEP(xe, first, last))
> -#define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last) (IS_XEHPSDV(xe)
> && IS_GRAPHICS_STEP(xe, first, last))
> #define IS_TIGERLAKE_DISPLAY_STEP(xe, first, last)
> (IS_TIGERLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
> #define IS_ROCKETLAKE_DISPLAY_STEP(xe, first, last)
> (IS_ROCKETLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
>
>
> Let me know what you prefer. If squashing these changes to your patches,
> then I'd add the other patches in this series on top.
Do what is easiest for you, which is probably to just go with yours and
that's fine since you caught more than I have. Just unfortunate we spent
duplicated effort.
Regards,
Tvrtko
>
> thanks
> Lucas De Marchi
>
>>
>> Regards,
>>
>> Tvrtko
>>
>>> drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h is also changed on the
>>> xe side, but that should be ok: the defines are there only for compat
>>> reasons while building the display side (and none of these platforms
>>> have display, so it's build-issue only).
>>>
>>> First patch is what motivated the others and was submitted alone
>>> @ 20240306144723.1826977-1-lucas.demarchi@intel.com .
>>> While loooking at this WA I was wondering why we still had some of that
>>> code around.
>>>
>>> Build-tested only for now.
>>>
>>> Lucas De Marchi (5):
>>> drm/i915: Drop WA 16015675438
>>> drm/i915: Drop dead code for xehpsdv
>>> drm/i915: Update IP_VER(12, 50)
>>> drm/i915: Drop dead code for pvc
>>> drm/i915: Remove special handling for !RCS_MASK()
>>>
>>> Documentation/gpu/rfc/i915_vm_bind.h | 11 +-
>>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
>>> .../gpu/drm/i915/gem/selftests/huge_pages.c | 4 +-
>>> .../i915/gem/selftests/i915_gem_client_blt.c | 8 +-
>>> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 5 +-
>>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40 ++--
>>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 43 +---
>>> .../drm/i915/gt/intel_execlists_submission.c | 10 +-
>>> drivers/gpu/drm/i915/gt/intel_gsc.c | 15 --
>>> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +-
>>> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 52 +----
>>> drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 59 ------
>>> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 +-
>>> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 51 +----
>>> drivers/gpu/drm/i915/gt/intel_migrate.c | 22 +-
>>> drivers/gpu/drm/i915/gt/intel_mocs.c | 52 +----
>>> drivers/gpu/drm/i915/gt/intel_rps.c | 6 +-
>>> drivers/gpu/drm/i915/gt/intel_sseu.c | 13 +-
>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 193 +-----------------
>>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 6 +-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 4 +-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 -
>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
>>> drivers/gpu/drm/i915/i915_debugfs.c | 12 --
>>> drivers/gpu/drm/i915/i915_drv.h | 13 --
>>> drivers/gpu/drm/i915/i915_getparam.c | 4 +-
>>> drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
>>> drivers/gpu/drm/i915/i915_hwmon.c | 6 -
>>> drivers/gpu/drm/i915/i915_pci.c | 61 +-----
>>> drivers/gpu/drm/i915/i915_perf.c | 19 +-
>>> drivers/gpu/drm/i915/i915_query.c | 2 +-
>>> drivers/gpu/drm/i915/i915_reg.h | 4 +-
>>> drivers/gpu/drm/i915/intel_clock_gating.c | 26 +--
>>> drivers/gpu/drm/i915/intel_device_info.c | 2 -
>>> drivers/gpu/drm/i915/intel_device_info.h | 2 -
>>> drivers/gpu/drm/i915/intel_step.c | 80 +-------
>>> drivers/gpu/drm/i915/intel_uncore.c | 159 +--------------
>>> drivers/gpu/drm/i915/selftests/intel_uncore.c | 3 -
>>> .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 6 -
>>> 43 files changed, 110 insertions(+), 928 deletions(-)
>>>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/5] drm/i915: cleanup dead code
2024-03-12 9:54 ` Tvrtko Ursulin
@ 2024-03-12 12:53 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-12 12:53 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx, dri-devel, Rodrigo Vivi
On Tue, Mar 12, 2024 at 09:54:41AM +0000, Tvrtko Ursulin wrote:
>
>On 11/03/2024 19:27, Lucas De Marchi wrote:
>>On Mon, Mar 11, 2024 at 05:43:00PM +0000, Tvrtko Ursulin wrote:
>>>
>>>On 06/03/2024 19:36, Lucas De Marchi wrote:
>>>>Remove platforms that never had their PCI IDs added to the driver and
>>>>are of course marked with requiring force_probe. Note that most of the
>>>>code for those platforms is actually used by subsequent ones, so it's
>>>>not a huge amount of code being removed.
>>>
>>>I had PVC and xehpsdv back in October but could not collect all acks. :(
>>>
>>>Last two patches from https://patchwork.freedesktop.org/series/124705/.
>>
>>oh... I was actually surprised we still had xehpsdv while removing a
>>WA for PVC, which made me look into removing these platforms.
>>
>>rebasing your series and comparing yours..my-v2, where my-v2 only has
>>patches 2 and 4, I have the diff below. I think it's small enough that I
>>can just take your commits and squash delta. Is that ok to you?
>>
>>my version is a little bit more aggressive, also doing some renames
>>s/xehpsdv/xehp/ and dropping some more code
>>(engine_mask_apply_copy_fuses(), unused registers, default ctx, fw
>>ranges).
>
>Right, yeah I see I missed some case combos in the comments when
>grepping and more.
>
>> diff --git a/Documentation/gpu/rfc/i915_vm_bind.h
>>b/Documentation/gpu/rfc/i915_vm_bind.h
>> index 8a8fcd4fceac..bc26dc126104 100644
>> --- a/Documentation/gpu/rfc/i915_vm_bind.h
>> +++ b/Documentation/gpu/rfc/i915_vm_bind.h
>> @@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
>> * Multiple VA mappings can be created to the same section of
>>the object
>> * (aliasing).
>> *
>> - * The @start, @offset and @length must be 4K page aligned.
>>However the DG2
>> - * and XEHPSDV has 64K page size for device local memory and
>>has compact page
>> - * table. On those platforms, for binding device local-memory
>>objects, the
>> - * @start, @offset and @length must be 64K aligned. Also, UMDs
>>should not mix
>> - * the local memory 64K page and the system memory 4K page
>>bindings in the same
>> - * 2M range.
>> + * The @start, @offset and @length must be 4K page aligned.
>>However the DG2 has
>> + * 64K page size for device local memory and has compact page
>>table. On that
>> + * platform, for binding device local-memory objects, the
>>@start, @offset and
>> + * @length must be 64K aligned. Also, UMDs should not mix the
>>local memory 64K
>> + * page and the system memory 4K page bindings in the same 2M range.
>> *
>> * Error code -EINVAL will be returned if @start, @offset and
>>@length are not
>> * properly aligned. In version 1 (See
>>I915_PARAM_VM_BIND_VERSION), error code
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>>b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> index 1495b6074492..d3300ae3053f 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> @@ -386,7 +386,7 @@ struct drm_i915_gem_object {
>> * and kernel mode driver for caching policy control after GEN12.
>> * In the meantime platform specific tables are created to
>>translate
>> * i915_cache_level into pat index, for more details check
>>the macros
>> - * defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.
>> + * defined i915/i915_pci.c, e.g. MTL_CACHELEVEL.
>
>Why this?
it was just our different choices while doing the search-and-replace.
It's not that I changed yours, it's that my choice was to go with MTL
and yours to go with TGL. Any of them fit the role here.
>
>> * For backward compatibility, this field contains values
>>exactly match
>> * the entries of enum i915_cache_level for pre-GEN12
>>platforms (See
>> * LEGACY_CACHELEVEL), so that the PTE encode functions for these
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index fa46d2308b0e..1bd0e041e15c 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
>> }
>> static void
>> -xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
>> - struct i915_vma_resource *vma_res,
>> - struct sgt_dma *iter,
>> - unsigned int pat_index,
>> - u32 flags)
>> +xehp_ppgtt_insert_huge(struct i915_address_space *vm,
>> + struct i915_vma_resource *vma_res,
>> + struct sgt_dma *iter,
>> + unsigned int pat_index,
>> + u32 flags)
>> {
>> const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
>> unsigned int rem = sg_dma_len(iter->sg);
>> @@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct
>>i915_address_space *vm,
>> struct sgt_dma iter = sgt_dma(vma_res);
>> if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
>> - if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
>> - xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter,
>>pat_index, flags);
>> + if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
>> + xehp_ppgtt_insert_huge(vm, vma_res, &iter,
>>pat_index, flags);
>> else
>> gen8_ppgtt_insert_huge(vm, vma_res, &iter,
>>pat_index, flags);
>> } else {
>> @@ -781,11 +781,11 @@ static void
>>gen8_ppgtt_insert_entry(struct i915_address_space *vm,
>> drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)],
>>sizeof(*vaddr));
>> }
>> -static void __xehpsdv_ppgtt_insert_entry_lm(struct
>>i915_address_space *vm,
>> - dma_addr_t addr,
>> - u64 offset,
>> - unsigned int pat_index,
>> - u32 flags)
>> +static void xehp_ppgtt_insert_entry_lm(struct i915_address_space *vm,
>> + dma_addr_t addr,
>> + u64 offset,
>> + unsigned int pat_index,
>> + u32 flags)
>> {
>> u64 idx = offset >> GEN8_PTE_SHIFT;
>> struct i915_page_directory * const pdp =
>> @@ -810,15 +810,15 @@ static void
>>__xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
>> vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr,
>>pat_index, flags);
>> }
>> -static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
>> - dma_addr_t addr,
>> - u64 offset,
>> - unsigned int pat_index,
>> - u32 flags)
>> +static void xehp_ppgtt_insert_entry(struct i915_address_space *vm,
>> + dma_addr_t addr,
>> + u64 offset,
>> + unsigned int pat_index,
>> + u32 flags)
>> {
>> if (flags & PTE_LM)
>> - return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
>> - pat_index, flags);
>> + return xehp_ppgtt_insert_entry_lm(vm, addr, offset,
>> + pat_index, flags);
>> return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index,
>>flags);
>> }
>> @@ -1042,7 +1042,7 @@ struct i915_ppgtt
>>*gen8_ppgtt_create(struct intel_gt *gt,
>> ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
>> ppgtt->vm.insert_entries = gen8_ppgtt_insert;
>> if (HAS_64K_PAGES(gt->i915))
>> - ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
>> + ppgtt->vm.insert_page = xehp_ppgtt_insert_entry;
>> else
>> ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
>> ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>>b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index f553cf4e6449..423d72115af0 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -839,38 +839,6 @@ static void
>>engine_mask_apply_compute_fuses(struct intel_gt *gt)
>> }
>> }
>> -static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
>> -{
>> - struct drm_i915_private *i915 = gt->i915;
>> - struct intel_gt_info *info = >->info;
>> - unsigned long meml3_mask;
>> - unsigned long quad;
>> -
>> - if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
>> - GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
>> - return;
>
>I trust you know this is correct. :) Without a easy to reach table of
>platform codenames to ip block version I give up.
well, xe_pci.c has the versions at least until MTL with
graphics ver 12.70. So if we remove PVC (12.60), there's nothing left.
>
>> -
>> - meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
>> - meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
>> -
>> - /*
>> - * Link Copy engines may be fused off according to
>>meml3_mask. Each
>> - * bit is a quad that houses 2 Link Copy and two Sub Copy
>>engines.
>> - */
>> - for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
>> - unsigned int instance = quad * 2 + 1;
>> - intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
>> - _BCS(instance));
>> -
>> - if (mask & info->engine_mask) {
>> - gt_dbg(gt, "bcs%u fused off\n", instance);
>> - gt_dbg(gt, "bcs%u fused off\n", instance + 1);
>> -
>> - info->engine_mask &= ~mask;
>> - }
>> - }
>> -}
>> -
>> /*
>> * Determine which engines are fused off in our particular hardware.
>> * Note that we have a catch-22 situation where we need to be
>>able to access
>> @@ -889,7 +857,6 @@ static intel_engine_mask_t
>>init_engine_mask(struct intel_gt *gt)
>> engine_mask_apply_media_fuses(gt);
>> engine_mask_apply_compute_fuses(gt);
>> - engine_mask_apply_copy_fuses(gt);
>> /*
>> * The only use of the GSC CS is to load and communicate
>>with the GSC
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> index 2f386f531c55..ee5115b12a21 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> @@ -57,7 +57,7 @@ static const struct intel_mmio_range
>>icl_l3bank_steering_table[] = {
>> * are of a "GAM" subclass that has special rules. Thus we
>>use a separate
>> * GAM table farther down for those.
>> */
>> -static const struct intel_mmio_range
>>xehpsdv_mslice_steering_table[] = {
>> +static const struct intel_mmio_range dg2_mslice_steering_table[] = {
>> { 0x00DD00, 0x00DDFF },
>> { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
>> {},
>> @@ -153,7 +153,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>> gt->steering_table[L3BANK] = xelpg_l3bank_steering_table;
>> gt->steering_table[DSS] = xelpg_dss_steering_table;
>> } else if (IS_DG2(i915)) {
>> - gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
>> + gt->steering_table[MSLICE] = dg2_mslice_steering_table;
>> gt->steering_table[LNCF] = dg2_lncf_steering_table;
>> /*
>> * No need to hook up the GAM table since it has a dedicated
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>>b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> index 0635c9288742..8d8d781b44b6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> @@ -723,38 +723,6 @@
>> #define HSUNIT_CLKGATE_DIS REG_BIT(8)
>> #define VSUNIT_CLKGATE_DIS REG_BIT(3)
>> -#define UNSLCGCTL9440 _MMIO(0x9440)
>> -#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
>> -#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
>> -#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
>> -#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
>> -#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
>> -#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
>> -#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
>> -#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
>> -#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
>> -#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
>> -#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
>> -#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
>> -
>> -#define UNSLCGCTL9444 _MMIO(0x9444)
>> -#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
>> -#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
>> -#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
>> -#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
>> -#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
>> -#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
>> -#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
>> -#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
>> -#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
>> -#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
>> -#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
>> -#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
>> -#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
>> -#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
>> -#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
>> -#define LTCDD_CLKGATE_DIS REG_BIT(10)
>> -
>> #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
>> #define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
>> #define SARBUNIT_CLKGATE_DIS (1 << 5)
>> @@ -764,9 +732,6 @@
>> #define L3_CLKGATE_DIS REG_BIT(16)
>> #define L3_CR2X_CLKGATE_DIS REG_BIT(17)
>> -#define SCCGCTL94DC MCR_REG(0x94dc)
>> -#define CG3DDISURB REG_BIT(14)
>> -
>> #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
>> #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
>> #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
>> @@ -988,10 +953,6 @@
>> #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
>> #define GEN7_L3AGDIS (1 << 19)
>> -#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c)
>> -#define XEHPC_HOSTCACHEEN REG_BIT(1)
>> -#define XEHPC_OVRLSCCC REG_BIT(0)
>> -
>> #define GEN7_L3CNTLREG2 _MMIO(0xb020)
>> /* MOCS (Memory Object Control State) registers */
>> @@ -1045,20 +1006,9 @@
>> #define XEHP_L3SQCREG5 MCR_REG(0xb158)
>> #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
>> -#define MLTICTXCTL MCR_REG(0xb170)
>> -#define TDONRENDER REG_BIT(2)
>> -
>> #define XEHP_L3SCQREG7 MCR_REG(0xb188)
>> #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
>> -#define XEHPC_L3SCRUB MCR_REG(0xb18c)
>> -#define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12)
>> -#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
>> -#define SCRUB_RATE_4B_PER_CLK
>>REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
>> -
>> -#define L3SQCREG1_CCS0 MCR_REG(0xb200)
>> -#define FLUSHALLNONCOH REG_BIT(5)
>> -
>> #define GEN11_GLBLINVL _MMIO(0xb404)
>> #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
>> #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
>> @@ -1108,7 +1058,6 @@
>> #define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
>> #define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /*
>>media GT only */
>> -#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
>> #define RENDER_MOD_CTRL MCR_REG(0xcf2c)
>> #define COMP_MOD_CTRL MCR_REG(0xcf30)
>> #define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /*
>>media GT only */
>> @@ -1184,7 +1133,6 @@
>> #define EU_PERF_CNTL4 PERF_REG(0xe45c)
>> #define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
>> -#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
>> #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
>> #define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
>> #define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
>> @@ -1201,7 +1149,6 @@
>> #define FLOW_CONTROL_ENABLE REG_BIT(15)
>> #define UGM_BACKUP_MODE REG_BIT(13)
>> #define MDQ_ARBITRATION_MODE REG_BIT(12)
>> -#define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10)
>> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
>> #define STALL_DOP_GATING_DISABLE REG_BIT(5)
>> #define THROTTLE_12_5 REG_GENMASK(4, 2)
>> @@ -1678,11 +1625,6 @@
>> #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
>> -#define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004)
>> -#define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008)
>> -#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
>> -#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
>> -
>> /*
>> * Standalone Media's non-engine GT registers are located at
>>their regular GT
>> * offsets plus 0x380000. This extra offset is stored inside
>>the intel_uncore
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
>>b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
>> index 90644e47d261..d7784650e4d9 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
>> @@ -582,9 +582,10 @@ static ssize_t
>>media_freq_factor_show(struct kobject *kobj,
>> */
>> with_intel_runtime_pm(gt->uncore->rpm, wakeref)
>> mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
>> +
>> mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
>> - SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
>> - SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
>> + SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
>> + SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
>
>Something is off in someone's version here.
yeah, I will double check before v2.
>
>> return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index 7c367ba8d9dc..7f1b00cb9924 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -546,47 +546,6 @@ static const u8 gen12_rcs_offsets[] = {
>> END
>> };
>> -static const u8 xehp_rcs_offsets[] = {
>> - NOP(1),
>> - LRI(13, POSTED),
>> - REG16(0x244),
>> - REG(0x034),
>> - REG(0x030),
>> - REG(0x038),
>> - REG(0x03c),
>> - REG(0x168),
>> - REG(0x140),
>> - REG(0x110),
>> - REG(0x1c0),
>> - REG(0x1c4),
>> - REG(0x1c8),
>> - REG(0x180),
>> - REG16(0x2b4),
>> -
>> - NOP(5),
>> - LRI(9, POSTED),
>> - REG16(0x3a8),
>> - REG16(0x28c),
>> - REG16(0x288),
>> - REG16(0x284),
>> - REG16(0x280),
>> - REG16(0x27c),
>> - REG16(0x278),
>> - REG16(0x274),
>> - REG16(0x270),
>> -
>> - LRI(3, POSTED),
>> - REG(0x1b0),
>> - REG16(0x5a8),
>> - REG16(0x5ac),
>> -
>> - NOP(6),
>> - LRI(1, 0),
>> - REG(0x0c8),
>> -
>> - END
>> -};
>> -
>> static const u8 dg2_rcs_offsets[] = {
>> NOP(1),
>> LRI(15, POSTED),
>> @@ -695,8 +654,6 @@ static const u8 *reg_offsets(const struct
>>intel_engine_cs *engine)
>> return mtl_rcs_offsets;
>> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>> return dg2_rcs_offsets;
>> - else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
>> - return xehp_rcs_offsets;
>> else if (GRAPHICS_VER(engine->i915) >= 12)
>> return gen12_rcs_offsets;
>> else if (GRAPHICS_VER(engine->i915) >= 11)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
>>b/drivers/gpu/drm/i915/gt/intel_migrate.c
>> index 576e5ef0289b..86ba2f2e485c 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
>> @@ -35,9 +35,9 @@ static bool engine_supports_migration(struct
>>intel_engine_cs *engine)
>> return true;
>> }
>> -static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
>> - struct i915_page_table *pt,
>> - void *data)
>> +static void xehp_toggle_pdes(struct i915_address_space *vm,
>> + struct i915_page_table *pt,
>> + void *data)
>> {
>> struct insert_pte_data *d = data;
>> @@ -52,9 +52,9 @@ static void xehpsdv_toggle_pdes(struct
>>i915_address_space *vm,
>> d->offset += SZ_2M;
>> }
>> -static void xehpsdv_insert_pte(struct i915_address_space *vm,
>> - struct i915_page_table *pt,
>> - void *data)
>> +static void xehp_insert_pte(struct i915_address_space *vm,
>> + struct i915_page_table *pt,
>> + void *data)
>> {
>> struct insert_pte_data *d = data;
>> @@ -120,7 +120,7 @@ static struct i915_address_space
>>*migrate_vm(struct intel_gt *gt)
>> * 512 entry layout using 4K GTT pages. The other two
>>windows just map
>> * lmem pages and must use the new compact 32 entry layout
>>using 64K GTT
>> * pages, which ensures we can address any lmem object that
>>the user
>> - * throws at us. We then also use the xehpsdv_toggle_pdes
>>as a way of
>> + * throws at us. We then also use the xehp_toggle_pdes as
>>a way of
>> * just toggling the PDE bit(GEN12_PDE_64K) for us, to enable the
>> * compact layout for each of these page-tables, that fall
>>within the
>> * [CHUNK_SIZE, 3 * CHUNK_SIZE) range.
>> @@ -209,12 +209,12 @@ static struct i915_address_space
>>*migrate_vm(struct intel_gt *gt)
>> /* Now allow the GPU to rewrite the PTE via its own ppGTT */
>> if (HAS_64K_PAGES(gt->i915)) {
>> vm->vm.foreach(&vm->vm, base, d.offset - base,
>> - xehpsdv_insert_pte, &d);
>> + xehp_insert_pte, &d);
>> d.offset = base + CHUNK_SZ;
>> vm->vm.foreach(&vm->vm,
>> d.offset,
>> 2 * CHUNK_SZ,
>> - xehpsdv_toggle_pdes, &d);
>> + xehp_toggle_pdes, &d);
>> } else {
>> vm->vm.foreach(&vm->vm, base, d.offset - base,
>> insert_pte, &d);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 7889147b44b7..804654ab80ec 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -2661,6 +2661,7 @@ xcs_engine_wa_init(struct intel_engine_cs
>>*engine, struct i915_wa_list *wal)
>> static void
>> ccs_engine_wa_init(struct intel_engine_cs *engine, struct
>>i915_wa_list *wal)
>> {
>> + /* boilerplate for any CCS engine workaround */
>> }
>> /*
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>>b/drivers/gpu/drm/i915/i915_perf.c
>> index f68ec0a1c17d..1637c1d235e9 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -2881,7 +2881,7 @@ gen12_enable_metric_set(struct
>>i915_perf_stream *stream,
>> int ret;
>> /*
>> - * Wa_1508761755:xehpsdv, dg2
>> + * Wa_1508761755
>> * EU NOA signals behave incorrectly if EU clock gating is
>>enabled.
>> * Disable thread stall DOP gating and EU DOP gating.
>> */
>> @@ -2911,7 +2911,7 @@ gen12_enable_metric_set(struct
>>i915_perf_stream *stream,
>> /*
>> * Initialize Super Queue Internal Cnt Register
>> * Set PMON Enable in order to collect valid metrics.
>> - * Enable byets per clock reporting in OA for XEHPSDV onward.
>> + * Enable byets per clock reporting in OA.
>
>Could you fix byets while touching the line?
>
>> */
>> sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
>> (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
>> @@ -2971,8 +2971,7 @@ static void
>>gen12_disable_metric_set(struct i915_perf_stream *stream)
>> u32 sqcnt1;
>> /*
>> - * Wa_1508761755:xehpsdv, dg2
>> - * Enable thread stall DOP gating and EU DOP gating.
>> + * Wa_1508761755: Enable thread stall DOP gating and EU
>>DOP gating.
>> */
>> if (IS_DG2(i915)) {
>> intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>b/drivers/gpu/drm/i915/i915_reg.h
>> index bdc409085b9a..f62573d48c76 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5399,7 +5399,7 @@
>> #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed
>>point format */
>> #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
>> #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
>> -#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /*
>>xehpsdv, pvc */
>> +#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e
>> /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
>> #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
>> #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
>>b/drivers/gpu/drm/i915/intel_uncore.c
>> index 58d6c68195e0..40d56f02b5c6 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -1497,17 +1497,16 @@ static const struct
>>intel_forcewake_range __gen12_fw_ranges[] = {
>> GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2),
>>/* \
>> 0x13200 - 0x133ff: VD2 (DG2 only) \
>> 0x13400 - 0x13fff: reserved */ \
>> - GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /*
>>XEHPSDV only */ \
>> - GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /*
>>XEHPSDV only */ \
>> - GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /*
>>XEHPSDV only */ \
>> - GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /*
>>XEHPSDV only */ \
>> + GEN_FW_RANGE(0x14000, 0x141ff,
>>FORCEWAKE_MEDIA_VDBOX0), \
>> + GEN_FW_RANGE(0x14200, 0x143ff,
>>FORCEWAKE_MEDIA_VDBOX2), \
>> + GEN_FW_RANGE(0x14400, 0x145ff,
>>FORCEWAKE_MEDIA_VDBOX4), \
>> + GEN_FW_RANGE(0x14600, 0x147ff,
>>FORCEWAKE_MEDIA_VDBOX6), \
>
>I see Rodrigo and you were discussing this hunk so I will just skip over.
>
>> GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
>> GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
>> 0x15000 - 0x15fff: gt (DG2 only) \
>> 0x16000 - 0x16dff: reserved */ \
>> GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
>> - GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0),
>>/* \
>> - 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
>> + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0),
>>/* \
>> 0x21000 - 0x21fff: reserved */ \
>> GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
>> GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
>> @@ -1588,10 +1587,6 @@ static const struct
>>intel_forcewake_range __gen12_fw_ranges[] = {
>> 0x1f6e00 - 0x1f7fff: reserved */ \
>> GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
>> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
>> - XEHP_FWRANGES(FORCEWAKE_GT)
>> -};
>> -
>> static const struct intel_forcewake_range __dg2_fw_ranges[] = {
>> XEHP_FWRANGES(FORCEWAKE_RENDER)
>> };
>> @@ -2442,10 +2437,6 @@ static int uncore_forcewake_init(struct
>>intel_uncore *uncore)
>> ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
>> ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
>> ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
>> - } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>> - ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
>> - ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
>> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
>> } else if (GRAPHICS_VER(i915) >= 12) {
>> ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
>> ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
>> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
>>b/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> index c998f15d505c..41eaa9b7f67d 100644
>> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> @@ -118,7 +118,6 @@ int intel_uncore_mock_selftests(void)
>> { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
>> { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
>> { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
>> - { __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
>> { __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
>> { __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
>> };
>> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>>b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> index a86d00a9758f..a01d1b869c2d 100644
>> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> @@ -85,9 +85,7 @@ static inline struct drm_i915_private
>>*kdev_to_i915(struct device *kdev)
>> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1)
>> #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv,
>>XE_ALDERLAKE_S)
>> #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv,
>>XE_ALDERLAKE_P)
>> -#define IS_XEHPSDV(dev_priv) (dev_priv && 0)
>> #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
>> -#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
>> #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
>> #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
>> @@ -130,7 +128,6 @@ static inline struct drm_i915_private
>>*kdev_to_i915(struct device *kdev)
>> #define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \
>> ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
>> IS_GRAPHICS_STEP(xe, first, last))
>> -#define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last)
>>(IS_XEHPSDV(xe) && IS_GRAPHICS_STEP(xe, first, last))
>> #define IS_TIGERLAKE_DISPLAY_STEP(xe, first, last)
>>(IS_TIGERLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
>> #define IS_ROCKETLAKE_DISPLAY_STEP(xe, first, last)
>>(IS_ROCKETLAKE(xe) && IS_DISPLAY_STEP(xe, first, last))
>>
>>
>>Let me know what you prefer. If squashing these changes to your patches,
>>then I'd add the other patches in this series on top.
>
>Do what is easiest for you, which is probably to just go with yours
>and that's fine since you caught more than I have. Just unfortunate we
>spent duplicated effort.
ok, sounds good.
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv
2024-03-11 15:16 ` Rodrigo Vivi
@ 2024-03-12 16:29 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-12 16:29 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, dri-devel
On Mon, Mar 11, 2024 at 11:16:06AM -0400, Rodrigo Vivi wrote:
>On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:
>> PCI IDs for XEHPSDV were never added and platform always marked with
>> force_probe. Drop what's not used and rename some places to either be
>> xehp or dg2, depending on the platform/IP checks.
>>
>> The registers not used anymore are also removed.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>
>> Potential problem here that needs a deeper look, the changes in
>> __gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
>> I removed them, but it needs to be double checked with spec and CI
>> results.
>
>I have checked the specs and your patch looks right because those
>bits should be reserved for DG2.
>
>But the main issue I see is that we were using that (wrongly?) for
>DG2 so far. So it probably deserves a separate patch anyway.
>
>With this patch only removing the comments and a separate patch
>to remove that for DG2 (and standalone CI run on that patch by itself):
After double checking I think the main issue is that the changed table
became wrong since it poke holes. From the docs:
* All platforms' forcewake tables below must be sorted by offset ranges.
* Furthermore, new forcewake tables added should be "watertight" and hav
* no gaps between ranges.
I *think* this would be the more correct change:
@@ -1533,21 +1533,16 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
0x12000 - 0x127ff: always on \
0x12800 - 0x12fff: reserved */ \
GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */ \
- GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
+ GEN_FW_RANGE(0x13200, 0x147ff, FORCEWAKE_MEDIA_VDBOX2), /* \
0x13200 - 0x133ff: VD2 (DG2 only) \
- 0x13400 - 0x13fff: reserved */ \
- GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
- GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
+ 0x13400 - 0x147ff: reserved */ \
GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
0x15000 - 0x15fff: gt (DG2 only) \
0x16000 - 0x16dff: reserved */ \
- GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
- GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
- 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
- 0x21000 - 0x21fff: reserved */ \
+ GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /* \
+ 0x16e00 - 0x1ffff: render \
+ 0x20000 - 0x21fff: reserved */ \
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
0x24000 - 0x2407f: always on \
did you find any access on DG2 within the reserved ranges?
Lucas De Marchi
>
>Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>>
>> Documentation/gpu/rfc/i915_vm_bind.h | 11 +--
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40 ++++----
>> drivers/gpu/drm/i915/gt/intel_gsc.c | 15 ---
>> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 20 +---
>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 50 ----------
>> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 ++--
>> drivers/gpu/drm/i915/gt/intel_lrc.c | 43 ---------
>> drivers/gpu/drm/i915/gt/intel_migrate.c | 18 ++--
>> drivers/gpu/drm/i915/gt/intel_mocs.c | 31 ------
>> drivers/gpu/drm/i915/gt/intel_rps.c | 2 -
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 -------------------
>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
>> drivers/gpu/drm/i915/i915_drv.h | 4 -
>> drivers/gpu/drm/i915/i915_hwmon.c | 6 --
>> drivers/gpu/drm/i915/i915_pci.c | 17 ----
>> drivers/gpu/drm/i915/i915_perf.c | 11 +--
>> drivers/gpu/drm/i915/i915_reg.h | 3 +-
>> drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
>> drivers/gpu/drm/i915/intel_device_info.c | 1 -
>> drivers/gpu/drm/i915/intel_device_info.h | 1 -
>> drivers/gpu/drm/i915/intel_step.c | 10 --
>> drivers/gpu/drm/i915/intel_uncore.c | 15 +--
>> drivers/gpu/drm/i915/selftests/intel_uncore.c | 1 -
>> .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 -
>> 24 files changed, 51 insertions(+), 380 deletions(-)
>>
>> diff --git a/Documentation/gpu/rfc/i915_vm_bind.h b/Documentation/gpu/rfc/i915_vm_bind.h
>> index 8a8fcd4fceac..bc26dc126104 100644
>> --- a/Documentation/gpu/rfc/i915_vm_bind.h
>> +++ b/Documentation/gpu/rfc/i915_vm_bind.h
>> @@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
>> * Multiple VA mappings can be created to the same section of the object
>> * (aliasing).
>> *
>> - * The @start, @offset and @length must be 4K page aligned. However the DG2
>> - * and XEHPSDV has 64K page size for device local memory and has compact page
>> - * table. On those platforms, for binding device local-memory objects, the
>> - * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
>> - * the local memory 64K page and the system memory 4K page bindings in the same
>> - * 2M range.
>> + * The @start, @offset and @length must be 4K page aligned. However the DG2 has
>> + * 64K page size for device local memory and has compact page table. On that
>> + * platform, for binding device local-memory objects, the @start, @offset and
>> + * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K
>> + * page and the system memory 4K page bindings in the same 2M range.
>> *
>> * Error code -EINVAL will be returned if @start, @offset and @length are not
>> * properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index fa46d2308b0e..1bd0e041e15c 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
>> }
>>
>> static void
>> -xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
>> - struct i915_vma_resource *vma_res,
>> - struct sgt_dma *iter,
>> - unsigned int pat_index,
>> - u32 flags)
>> +xehp_ppgtt_insert_huge(struct i915_address_space *vm,
>> + struct i915_vma_resource *vma_res,
>> + struct sgt_dma *iter,
>> + unsigned int pat_index,
>> + u32 flags)
>> {
>> const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
>> unsigned int rem = sg_dma_len(iter->sg);
>> @@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
>> struct sgt_dma iter = sgt_dma(vma_res);
>>
>> if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
>> - if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
>> - xehpsdv_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
>> + if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
>> + xehp_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
>> else
>> gen8_ppgtt_insert_huge(vm, vma_res, &iter, pat_index, flags);
>> } else {
>> @@ -781,11 +781,11 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
>> drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
>> }
>>
>> -static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
>> - dma_addr_t addr,
>> - u64 offset,
>> - unsigned int pat_index,
>> - u32 flags)
>> +static void xehp_ppgtt_insert_entry_lm(struct i915_address_space *vm,
>> + dma_addr_t addr,
>> + u64 offset,
>> + unsigned int pat_index,
>> + u32 flags)
>> {
>> u64 idx = offset >> GEN8_PTE_SHIFT;
>> struct i915_page_directory * const pdp =
>> @@ -810,15 +810,15 @@ static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm,
>> vaddr[gen8_pd_index(idx, 0) / 16] = vm->pte_encode(addr, pat_index, flags);
>> }
>>
>> -static void xehpsdv_ppgtt_insert_entry(struct i915_address_space *vm,
>> - dma_addr_t addr,
>> - u64 offset,
>> - unsigned int pat_index,
>> - u32 flags)
>> +static void xehp_ppgtt_insert_entry(struct i915_address_space *vm,
>> + dma_addr_t addr,
>> + u64 offset,
>> + unsigned int pat_index,
>> + u32 flags)
>> {
>> if (flags & PTE_LM)
>> - return __xehpsdv_ppgtt_insert_entry_lm(vm, addr, offset,
>> - pat_index, flags);
>> + return xehp_ppgtt_insert_entry_lm(vm, addr, offset,
>> + pat_index, flags);
>>
>> return gen8_ppgtt_insert_entry(vm, addr, offset, pat_index, flags);
>> }
>> @@ -1042,7 +1042,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
>> ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
>> ppgtt->vm.insert_entries = gen8_ppgtt_insert;
>> if (HAS_64K_PAGES(gt->i915))
>> - ppgtt->vm.insert_page = xehpsdv_ppgtt_insert_entry;
>> + ppgtt->vm.insert_page = xehp_ppgtt_insert_entry;
>> else
>> ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
>> ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
>> index 6d440de8ba01..1e925c75fb08 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
>> @@ -103,19 +103,6 @@ static const struct gsc_def gsc_def_dg1[] = {
>> }
>> };
>>
>> -static const struct gsc_def gsc_def_xehpsdv[] = {
>> - {
>> - /* HECI1 not enabled on the device. */
>> - },
>> - {
>> - .name = "mei-gscfi",
>> - .bar = DG1_GSC_HECI2_BASE,
>> - .bar_size = GSC_BAR_LENGTH,
>> - .use_polling = true,
>> - .slow_firmware = true,
>> - }
>> -};
>> -
>> static const struct gsc_def gsc_def_dg2[] = {
>> {
>> .name = "mei-gsc",
>> @@ -188,8 +175,6 @@ static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
>>
>> if (IS_DG1(i915)) {
>> def = &gsc_def_dg1[intf_id];
>> - } else if (IS_XEHPSDV(i915)) {
>> - def = &gsc_def_xehpsdv[intf_id];
>> } else if (IS_DG2(i915)) {
>> def = &gsc_def_dg2[intf_id];
>> } else {
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> index e253750a51c5..5a2bd8de155a 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> @@ -57,24 +57,12 @@ static const struct intel_mmio_range icl_l3bank_steering_table[] = {
>> * are of a "GAM" subclass that has special rules. Thus we use a separate
>> * GAM table farther down for those.
>> */
>> -static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
>> +static const struct intel_mmio_range dg2_mslice_steering_table[] = {
>> { 0x00DD00, 0x00DDFF },
>> { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
>> {},
>> };
>>
>> -static const struct intel_mmio_range xehpsdv_gam_steering_table[] = {
>> - { 0x004000, 0x004AFF },
>> - { 0x00C800, 0x00CFFF },
>> - {},
>> -};
>> -
>> -static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
>> - { 0x00B000, 0x00B0FF },
>> - { 0x00D800, 0x00D8FF },
>> - {},
>> -};
>> -
>> static const struct intel_mmio_range dg2_lncf_steering_table[] = {
>> { 0x00B000, 0x00B0FF },
>> { 0x00D880, 0x00D8FF },
>> @@ -188,17 +176,13 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>> } else if (IS_PONTEVECCHIO(i915)) {
>> gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
>> } else if (IS_DG2(i915)) {
>> - gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
>> + gt->steering_table[MSLICE] = dg2_mslice_steering_table;
>> gt->steering_table[LNCF] = dg2_lncf_steering_table;
>> /*
>> * No need to hook up the GAM table since it has a dedicated
>> * steering control register on DG2 and can use implicit
>> * steering.
>> */
>> - } else if (IS_XEHPSDV(i915)) {
>> - gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
>> - gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
>> - gt->steering_table[GAM] = xehpsdv_gam_steering_table;
>> } else if (GRAPHICS_VER(i915) >= 11 &&
>> GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
>> gt->steering_table[L3BANK] = icl_l3bank_steering_table;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> index 50962cfd1353..919c07903767 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> @@ -718,44 +718,11 @@
>>
>> #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
>> #define VFUNIT_CLKGATE_DIS REG_BIT(20)
>> -#define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */
>> #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */
>> #define GAMEDIA_CLKGATE_DIS REG_BIT(11)
>> #define HSUNIT_CLKGATE_DIS REG_BIT(8)
>> #define VSUNIT_CLKGATE_DIS REG_BIT(3)
>>
>> -#define UNSLCGCTL9440 _MMIO(0x9440)
>> -#define GAMTLBOACS_CLKGATE_DIS REG_BIT(28)
>> -#define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27)
>> -#define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26)
>> -#define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24)
>> -#define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23)
>> -#define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22)
>> -#define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21)
>> -#define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17)
>> -#define GAMTLBKCR_CLKGATE_DIS REG_BIT(16)
>> -#define GAMTLBGUC_CLKGATE_DIS REG_BIT(15)
>> -#define GAMTLBBLT_CLKGATE_DIS REG_BIT(14)
>> -#define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6)
>> -
>> -#define UNSLCGCTL9444 _MMIO(0x9444)
>> -#define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30)
>> -#define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29)
>> -#define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28)
>> -#define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27)
>> -#define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26)
>> -#define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25)
>> -#define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24)
>> -#define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23)
>> -#define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22)
>> -#define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21)
>> -#define GAMTLBMERT_CLKGATE_DIS REG_BIT(20)
>> -#define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19)
>> -#define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18)
>> -#define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17)
>> -#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
>> -#define LTCDD_CLKGATE_DIS REG_BIT(10)
>> -
>> #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
>> #define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
>> #define SARBUNIT_CLKGATE_DIS (1 << 5)
>> @@ -765,9 +732,6 @@
>> #define L3_CLKGATE_DIS REG_BIT(16)
>> #define L3_CR2X_CLKGATE_DIS REG_BIT(17)
>>
>> -#define SCCGCTL94DC MCR_REG(0x94dc)
>> -#define CG3DDISURB REG_BIT(14)
>> -
>> #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
>> #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
>> #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
>> @@ -1046,9 +1010,6 @@
>> #define XEHP_L3SQCREG5 MCR_REG(0xb158)
>> #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
>>
>> -#define MLTICTXCTL MCR_REG(0xb170)
>> -#define TDONRENDER REG_BIT(2)
>> -
>> #define XEHP_L3SCQREG7 MCR_REG(0xb188)
>> #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
>>
>> @@ -1057,9 +1018,6 @@
>> #define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
>> #define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
>>
>> -#define L3SQCREG1_CCS0 MCR_REG(0xb200)
>> -#define FLUSHALLNONCOH REG_BIT(5)
>> -
>> #define GEN11_GLBLINVL _MMIO(0xb404)
>> #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
>> #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
>> @@ -1109,7 +1067,6 @@
>> #define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
>> #define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */
>>
>> -#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
>> #define RENDER_MOD_CTRL MCR_REG(0xcf2c)
>> #define COMP_MOD_CTRL MCR_REG(0xcf30)
>> #define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */
>> @@ -1185,7 +1142,6 @@
>> #define EU_PERF_CNTL4 PERF_REG(0xe45c)
>>
>> #define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
>> -#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
>> #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
>> #define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
>> #define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
>> @@ -1202,7 +1158,6 @@
>> #define FLOW_CONTROL_ENABLE REG_BIT(15)
>> #define UGM_BACKUP_MODE REG_BIT(13)
>> #define MDQ_ARBITRATION_MODE REG_BIT(12)
>> -#define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10)
>> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
>> #define STALL_DOP_GATING_DISABLE REG_BIT(5)
>> #define THROTTLE_12_5 REG_GENMASK(4, 2)
>> @@ -1679,11 +1634,6 @@
>>
>> #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
>>
>> -#define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004)
>> -#define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008)
>> -#define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068)
>> -#define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c)
>> -
>> /*
>> * Standalone Media's non-engine GT registers are located at their regular GT
>> * offsets plus 0x380000. This extra offset is stored inside the intel_uncore
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
>> index eca4a6a65556..d7784650e4d9 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
>> @@ -573,7 +573,6 @@ static ssize_t media_freq_factor_show(struct kobject *kobj,
>> char *buff)
>> {
>> struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
>> - struct intel_guc_slpc *slpc = >_to_guc(gt)->slpc;
>> intel_wakeref_t wakeref;
>> u32 mode;
>>
>> @@ -581,20 +580,12 @@ static ssize_t media_freq_factor_show(struct kobject *kobj,
>> * Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
>> * GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
>> */
>> - if (IS_XEHPSDV(gt->i915) &&
>> - slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
>> - /*
>> - * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
>> - * the media_ratio_mode, just return the cached media ratio
>> - */
>> - mode = slpc->media_ratio_mode;
>> - } else {
>> - with_intel_runtime_pm(gt->uncore->rpm, wakeref)
>> - mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
>> - mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
>> - SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
>> - SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
>> - }
>> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
>> + mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
>> +
>> + mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
>> + SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
>> + SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
>>
>> return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index 7c367ba8d9dc..7f1b00cb9924 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -546,47 +546,6 @@ static const u8 gen12_rcs_offsets[] = {
>> END
>> };
>>
>> -static const u8 xehp_rcs_offsets[] = {
>> - NOP(1),
>> - LRI(13, POSTED),
>> - REG16(0x244),
>> - REG(0x034),
>> - REG(0x030),
>> - REG(0x038),
>> - REG(0x03c),
>> - REG(0x168),
>> - REG(0x140),
>> - REG(0x110),
>> - REG(0x1c0),
>> - REG(0x1c4),
>> - REG(0x1c8),
>> - REG(0x180),
>> - REG16(0x2b4),
>> -
>> - NOP(5),
>> - LRI(9, POSTED),
>> - REG16(0x3a8),
>> - REG16(0x28c),
>> - REG16(0x288),
>> - REG16(0x284),
>> - REG16(0x280),
>> - REG16(0x27c),
>> - REG16(0x278),
>> - REG16(0x274),
>> - REG16(0x270),
>> -
>> - LRI(3, POSTED),
>> - REG(0x1b0),
>> - REG16(0x5a8),
>> - REG16(0x5ac),
>> -
>> - NOP(6),
>> - LRI(1, 0),
>> - REG(0x0c8),
>> -
>> - END
>> -};
>> -
>> static const u8 dg2_rcs_offsets[] = {
>> NOP(1),
>> LRI(15, POSTED),
>> @@ -695,8 +654,6 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>> return mtl_rcs_offsets;
>> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
>> return dg2_rcs_offsets;
>> - else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
>> - return xehp_rcs_offsets;
>> else if (GRAPHICS_VER(engine->i915) >= 12)
>> return gen12_rcs_offsets;
>> else if (GRAPHICS_VER(engine->i915) >= 11)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
>> index 576e5ef0289b..86ba2f2e485c 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
>> @@ -35,9 +35,9 @@ static bool engine_supports_migration(struct intel_engine_cs *engine)
>> return true;
>> }
>>
>> -static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
>> - struct i915_page_table *pt,
>> - void *data)
>> +static void xehp_toggle_pdes(struct i915_address_space *vm,
>> + struct i915_page_table *pt,
>> + void *data)
>> {
>> struct insert_pte_data *d = data;
>>
>> @@ -52,9 +52,9 @@ static void xehpsdv_toggle_pdes(struct i915_address_space *vm,
>> d->offset += SZ_2M;
>> }
>>
>> -static void xehpsdv_insert_pte(struct i915_address_space *vm,
>> - struct i915_page_table *pt,
>> - void *data)
>> +static void xehp_insert_pte(struct i915_address_space *vm,
>> + struct i915_page_table *pt,
>> + void *data)
>> {
>> struct insert_pte_data *d = data;
>>
>> @@ -120,7 +120,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
>> * 512 entry layout using 4K GTT pages. The other two windows just map
>> * lmem pages and must use the new compact 32 entry layout using 64K GTT
>> * pages, which ensures we can address any lmem object that the user
>> - * throws at us. We then also use the xehpsdv_toggle_pdes as a way of
>> + * throws at us. We then also use the xehp_toggle_pdes as a way of
>> * just toggling the PDE bit(GEN12_PDE_64K) for us, to enable the
>> * compact layout for each of these page-tables, that fall within the
>> * [CHUNK_SIZE, 3 * CHUNK_SIZE) range.
>> @@ -209,12 +209,12 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
>> /* Now allow the GPU to rewrite the PTE via its own ppGTT */
>> if (HAS_64K_PAGES(gt->i915)) {
>> vm->vm.foreach(&vm->vm, base, d.offset - base,
>> - xehpsdv_insert_pte, &d);
>> + xehp_insert_pte, &d);
>> d.offset = base + CHUNK_SZ;
>> vm->vm.foreach(&vm->vm,
>> d.offset,
>> 2 * CHUNK_SZ,
>> - xehpsdv_toggle_pdes, &d);
>> + xehp_toggle_pdes, &d);
>> } else {
>> vm->vm.foreach(&vm->vm, base, d.offset - base,
>> insert_pte, &d);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> index 25c1023eb5f9..c931c56945bd 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> @@ -367,31 +367,6 @@ static const struct drm_i915_mocs_entry gen12_mocs_table[] = {
>> L3_3_WB),
>> };
>>
>> -static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
>> - /* wa_1608975824 */
>> - MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
>> -
>> - /* UC - Coherent; GO:L3 */
>> - MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
>> - /* UC - Coherent; GO:Memory */
>> - MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
>> - /* UC - Non-Coherent; GO:Memory */
>> - MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
>> - /* UC - Non-Coherent; GO:L3 */
>> - MOCS_ENTRY(4, 0, L3_1_UC),
>> -
>> - /* WB */
>> - MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
>> -
>> - /* HW Reserved - SW program but never use. */
>> - MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
>> - MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
>> - MOCS_ENTRY(60, 0, L3_1_UC),
>> - MOCS_ENTRY(61, 0, L3_1_UC),
>> - MOCS_ENTRY(62, 0, L3_1_UC),
>> - MOCS_ENTRY(63, 0, L3_1_UC),
>> -};
>> -
>> static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
>> /* UC - Coherent; GO:L3 */
>> MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
>> @@ -514,12 +489,6 @@ static unsigned int get_mocs_settings(struct drm_i915_private *i915,
>> table->uc_index = 1;
>> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> table->unused_entries_index = 3;
>> - } else if (IS_XEHPSDV(i915)) {
>> - table->size = ARRAY_SIZE(xehpsdv_mocs_table);
>> - table->table = xehpsdv_mocs_table;
>> - table->uc_index = 2;
>> - table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> - table->unused_entries_index = 5;
>> } else if (IS_DG1(i915)) {
>> table->size = ARRAY_SIZE(dg1_mocs_table);
>> table->table = dg1_mocs_table;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index 9c6812257ac2..2a6a8134782d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -1088,8 +1088,6 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
>>
>> if (IS_PONTEVECCHIO(i915))
>> return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
>> - else if (IS_XEHPSDV(i915))
>> - return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);
>> else if (IS_GEN9_LP(i915))
>> return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
>> else
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 7f812409c30a..33d543d9bf44 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -922,8 +922,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>> ; /* noop; none at this time */
>> else if (IS_DG2(i915))
>> dg2_ctx_workarounds_init(engine, wal);
>> - else if (IS_XEHPSDV(i915))
>> - ; /* noop; none at this time */
>> else if (IS_DG1(i915))
>> dg1_ctx_workarounds_init(engine, wal);
>> else if (GRAPHICS_VER(i915) == 12)
>> @@ -1350,9 +1348,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
>> gt->steering_table[MSLICE] = NULL;
>> }
>>
>> - if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0))
>> - gt->steering_table[GAM] = NULL;
>> -
>> slice = __ffs(slice_mask);
>> subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
>> GEN_DSS_PER_GSLICE;
>> @@ -1519,76 +1514,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>> wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
>> }
>>
>> -static void
>> -xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>> -{
>> - struct drm_i915_private *i915 = gt->i915;
>> -
>> - xehp_init_mcr(gt, wal);
>> -
>> - /* Wa_1409757795:xehpsdv */
>> - wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB);
>> -
>> - /* Wa_18011725039:xehpsdv */
>> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
>> - wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
>> - wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
>> - }
>> -
>> - /* Wa_16011155590:xehpsdv */
>> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>> - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
>> - TSGUNIT_CLKGATE_DIS);
>> -
>> - /* Wa_14011780169:xehpsdv */
>> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) {
>> - wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
>> - GAMTLBVDBOX7_CLKGATE_DIS |
>> - GAMTLBVDBOX6_CLKGATE_DIS |
>> - GAMTLBVDBOX5_CLKGATE_DIS |
>> - GAMTLBVDBOX4_CLKGATE_DIS |
>> - GAMTLBVDBOX3_CLKGATE_DIS |
>> - GAMTLBVDBOX2_CLKGATE_DIS |
>> - GAMTLBVDBOX1_CLKGATE_DIS |
>> - GAMTLBVDBOX0_CLKGATE_DIS |
>> - GAMTLBKCR_CLKGATE_DIS |
>> - GAMTLBGUC_CLKGATE_DIS |
>> - GAMTLBBLT_CLKGATE_DIS);
>> - wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS |
>> - GAMTLBGFXA1_CLKGATE_DIS |
>> - GAMTLBCOMPA0_CLKGATE_DIS |
>> - GAMTLBCOMPA1_CLKGATE_DIS |
>> - GAMTLBCOMPB0_CLKGATE_DIS |
>> - GAMTLBCOMPB1_CLKGATE_DIS |
>> - GAMTLBCOMPC0_CLKGATE_DIS |
>> - GAMTLBCOMPC1_CLKGATE_DIS |
>> - GAMTLBCOMPD0_CLKGATE_DIS |
>> - GAMTLBCOMPD1_CLKGATE_DIS |
>> - GAMTLBMERT_CLKGATE_DIS |
>> - GAMTLBVEBOX3_CLKGATE_DIS |
>> - GAMTLBVEBOX2_CLKGATE_DIS |
>> - GAMTLBVEBOX1_CLKGATE_DIS |
>> - GAMTLBVEBOX0_CLKGATE_DIS);
>> - }
>> -
>> - /* Wa_16012725990:xehpsdv */
>> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER))
>> - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS);
>> -
>> - /* Wa_14011060649:xehpsdv */
>> - wa_14011060649(gt, wal);
>> -
>> - /* Wa_14012362059:xehpsdv */
>> - wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
>> -
>> - /* Wa_14014368820:xehpsdv */
>> - wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
>> - INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
>> -
>> - /* Wa_14010670810:xehpsdv */
>> - wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
>> -}
>> -
>> static void
>> dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>> {
>> @@ -1758,8 +1683,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
>> pvc_gt_workarounds_init(gt, wal);
>> else if (IS_DG2(i915))
>> dg2_gt_workarounds_init(gt, wal);
>> - else if (IS_XEHPSDV(i915))
>> - xehpsdv_gt_workarounds_init(gt, wal);
>> else if (IS_DG1(i915))
>> dg1_gt_workarounds_init(gt, wal);
>> else if (GRAPHICS_VER(i915) == 12)
>> @@ -2231,8 +2154,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>> pvc_whitelist_build(engine);
>> else if (IS_DG2(i915))
>> dg2_whitelist_build(engine);
>> - else if (IS_XEHPSDV(i915))
>> - ; /* none needed */
>> else if (GRAPHICS_VER(i915) == 12)
>> tgl_whitelist_build(engine);
>> else if (GRAPHICS_VER(i915) == 11)
>> @@ -2968,22 +2889,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>> 0 /* write-only, so skip validation */,
>> true);
>> }
>> -
>> - if (IS_XEHPSDV(i915)) {
>> - /* Wa_1409954639 */
>> - wa_mcr_masked_en(wal,
>> - GEN8_ROW_CHICKEN,
>> - SYSTOLIC_DOP_CLOCK_GATING_DIS);
>> -
>> - /* Wa_1607196519 */
>> - wa_mcr_masked_en(wal,
>> - GEN9_ROW_CHICKEN4,
>> - GEN12_DISABLE_GRF_CLEAR);
>> -
>> - /* Wa_14010449647:xehpsdv */
>> - wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
>> - GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>> - }
>> }
>>
>> static void
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> index 6dfe5d9456c6..28277321d9ca 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> @@ -51,8 +51,8 @@ static void uc_expand_default_options(struct intel_uc *uc)
>> /* Default: enable HuC authentication and GuC submission */
>> i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
>>
>> - /* XEHPSDV and PVC do not use HuC */
>> - if (IS_XEHPSDV(i915) || IS_PONTEVECCHIO(i915))
>> + /* PVC does not use HuC */
>> + if (IS_PONTEVECCHIO(i915))
>> i915->params.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index e81b3b2858ac..dff056587459 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -544,7 +544,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
>> #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
>> #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
>> -#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
>> #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
>> #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
>> #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
>> @@ -621,9 +620,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define IS_TIGERLAKE_UY(i915) \
>> IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
>>
>> -#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>> - (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>> -
>> #define IS_PVC_BD_STEP(__i915, since, until) \
>> (IS_PONTEVECCHIO(__i915) && \
>> IS_BASEDIE_STEP(__i915, since, until))
>> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
>> index 8c3f443c8347..11bd42e03b73 100644
>> --- a/drivers/gpu/drm/i915/i915_hwmon.c
>> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
>> @@ -738,12 +738,6 @@ hwm_get_preregistration_info(struct drm_i915_private *i915)
>> hwmon->rg.pkg_rapl_limit = PCU_PACKAGE_RAPL_LIMIT;
>> hwmon->rg.energy_status_all = PCU_PACKAGE_ENERGY_STATUS;
>> hwmon->rg.energy_status_tile = INVALID_MMIO_REG;
>> - } else if (IS_XEHPSDV(i915)) {
>> - hwmon->rg.pkg_power_sku_unit = GT0_PACKAGE_POWER_SKU_UNIT;
>> - hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
>> - hwmon->rg.pkg_rapl_limit = GT0_PACKAGE_RAPL_LIMIT;
>> - hwmon->rg.energy_status_all = GT0_PLATFORM_ENERGY_STATUS;
>> - hwmon->rg.energy_status_tile = GT0_PACKAGE_ENERGY_STATUS;
>> } else {
>> hwmon->rg.pkg_power_sku_unit = INVALID_MMIO_REG;
>> hwmon->rg.pkg_power_sku = INVALID_MMIO_REG;
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 8b4fdeabb12a..b318b7c6bf73 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -734,23 +734,6 @@ static const struct intel_device_info adl_p_info = {
>> .__runtime.media.ip.ver = 12, \
>> .__runtime.media.ip.rel = 50
>>
>> -__maybe_unused
>> -static const struct intel_device_info xehpsdv_info = {
>> - XE_HP_FEATURES,
>> - XE_HPM_FEATURES,
>> - DGFX_FEATURES,
>> - PLATFORM(INTEL_XEHPSDV),
>> - .has_64k_pages = 1,
>> - .has_media_ratio_mode = 1,
>> - .platform_engine_mask =
>> - BIT(RCS0) | BIT(BCS0) |
>> - BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
>> - BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
>> - BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
>> - BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
>> - .require_force_probe = 1,
>> -};
>> -
>> #define DG2_FEATURES \
>> XE_HP_FEATURES, \
>> XE_HPM_FEATURES, \
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> index bd9d812b1afa..1637c1d235e9 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -2881,11 +2881,11 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
>> int ret;
>>
>> /*
>> - * Wa_1508761755:xehpsdv, dg2
>> + * Wa_1508761755
>> * EU NOA signals behave incorrectly if EU clock gating is enabled.
>> * Disable thread stall DOP gating and EU DOP gating.
>> */
>> - if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
>> + if (IS_DG2(i915)) {
>> intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
>> _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
>> intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
>> @@ -2911,7 +2911,7 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
>> /*
>> * Initialize Super Queue Internal Cnt Register
>> * Set PMON Enable in order to collect valid metrics.
>> - * Enable byets per clock reporting in OA for XEHPSDV onward.
>> + * Enable byets per clock reporting in OA.
>> */
>> sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
>> (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
>> @@ -2971,10 +2971,9 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
>> u32 sqcnt1;
>>
>> /*
>> - * Wa_1508761755:xehpsdv, dg2
>> - * Enable thread stall DOP gating and EU DOP gating.
>> + * Wa_1508761755: Enable thread stall DOP gating and EU DOP gating.
>> */
>> - if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
>> + if (IS_DG2(i915)) {
>> intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
>> _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
>> intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e00557e1a57f..a120c17aafcc 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1750,7 +1750,6 @@
>>
>> #define BXT_RP_STATE_CAP _MMIO(0x138170)
>> #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
>> -#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
>> #define PVC_RP_STATE_CAP _MMIO(0x281014)
>>
>> #define MTL_RP_STATE_CAP _MMIO(0x138000)
>> @@ -5401,7 +5400,7 @@
>> #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
>> #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
>> #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
>> -#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
>> +#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
>> /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
>> #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
>> #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
>> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
>> index 9c21ce69bd98..93ab44190a47 100644
>> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
>> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
>> @@ -349,13 +349,6 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
>> intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);
>> }
>>
>> -static void xehpsdv_init_clock_gating(struct drm_i915_private *i915)
>> -{
>> - /* Wa_22010146351:xehpsdv */
>> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
>> - intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
>> -}
>> -
>> static void dg2_init_clock_gating(struct drm_i915_private *i915)
>> {
>> /* Wa_22010954014:dg2 */
>> @@ -764,7 +757,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs =
>>
>> CG_FUNCS(pvc);
>> CG_FUNCS(dg2);
>> -CG_FUNCS(xehpsdv);
>> CG_FUNCS(cfl);
>> CG_FUNCS(skl);
>> CG_FUNCS(kbl);
>> @@ -801,8 +793,6 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
>> i915->clock_gating_funcs = &pvc_clock_gating_funcs;
>> else if (IS_DG2(i915))
>> i915->clock_gating_funcs = &dg2_clock_gating_funcs;
>> - else if (IS_XEHPSDV(i915))
>> - i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
>> else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
>> i915->clock_gating_funcs = &cfl_clock_gating_funcs;
>> else if (IS_SKYLAKE(i915))
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 59bea1398c91..de28cbe758f7 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -70,7 +70,6 @@ static const char * const platform_names[] = {
>> PLATFORM_NAME(DG1),
>> PLATFORM_NAME(ALDERLAKE_S),
>> PLATFORM_NAME(ALDERLAKE_P),
>> - PLATFORM_NAME(XEHPSDV),
>> PLATFORM_NAME(DG2),
>> PLATFORM_NAME(PONTEVECCHIO),
>> PLATFORM_NAME(METEORLAKE),
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index eba2f0b919c8..2299327e59f0 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -87,7 +87,6 @@ enum intel_platform {
>> INTEL_DG1,
>> INTEL_ALDERLAKE_S,
>> INTEL_ALDERLAKE_P,
>> - INTEL_XEHPSDV,
>> INTEL_DG2,
>> INTEL_PONTEVECCHIO,
>> INTEL_METEORLAKE,
>> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
>> index b4162f1be765..d524bfe17c27 100644
>> --- a/drivers/gpu/drm/i915/intel_step.c
>> +++ b/drivers/gpu/drm/i915/intel_step.c
>> @@ -102,13 +102,6 @@ static const struct intel_step_info adlp_revids[] = {
>> [0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
>> };
>>
>> -static const struct intel_step_info xehpsdv_revids[] = {
>> - [0x0] = { COMMON_GT_MEDIA_STEP(A0) },
>> - [0x1] = { COMMON_GT_MEDIA_STEP(A1) },
>> - [0x4] = { COMMON_GT_MEDIA_STEP(B0) },
>> - [0x8] = { COMMON_GT_MEDIA_STEP(C0) },
>> -};
>> -
>> static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
>> [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
>> [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 },
>> @@ -190,9 +183,6 @@ void intel_step_init(struct drm_i915_private *i915)
>> } else if (IS_DG2_G12(i915)) {
>> revids = dg2_g12_revid_step_tbl;
>> size = ARRAY_SIZE(dg2_g12_revid_step_tbl);
>> - } else if (IS_XEHPSDV(i915)) {
>> - revids = xehpsdv_revids;
>> - size = ARRAY_SIZE(xehpsdv_revids);
>> } else if (IS_ALDERLAKE_P_N(i915)) {
>> revids = adlp_n_revids;
>> size = ARRAY_SIZE(adlp_n_revids);
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 76400e9c40f0..4f1e56187442 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -1536,17 +1536,12 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
>> GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
>> 0x13200 - 0x133ff: VD2 (DG2 only) \
>> 0x13400 - 0x13fff: reserved */ \
>> - GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
>> - GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
>> - GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
>> - GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
>> GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
>> GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
>> 0x15000 - 0x15fff: gt (DG2 only) \
>> 0x16000 - 0x16dff: reserved */ \
>> GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
>> - GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
>> - 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
>> + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
>> 0x21000 - 0x21fff: reserved */ \
>> GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
>> GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
>> @@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
>> 0x1f6e00 - 0x1f7fff: reserved */ \
>> GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
>>
>> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
>> - XEHP_FWRANGES(FORCEWAKE_GT)
>> -};
>> -
>> static const struct intel_forcewake_range __dg2_fw_ranges[] = {
>> XEHP_FWRANGES(FORCEWAKE_RENDER)
>> };
>> @@ -2584,10 +2575,6 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
>> ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
>> ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
>> ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
>> - } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>> - ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
>> - ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
>> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
>> } else if (GRAPHICS_VER(i915) >= 12) {
>> ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
>> ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
>> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> index 4f98aa8a861e..502bcadc5f39 100644
>> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> @@ -119,7 +119,6 @@ int intel_uncore_mock_selftests(void)
>> { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
>> { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
>> { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
>> - { __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
>> { __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
>> { __mtl_fw_ranges, ARRAY_SIZE(__mtl_fw_ranges), true },
>> { __xelpmp_fw_ranges, ARRAY_SIZE(__xelpmp_fw_ranges), true },
>> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> index fef969112b1d..a7e7ec3b5db9 100644
>> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> @@ -85,7 +85,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
>> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1)
>> #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)
>> #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)
>> -#define IS_XEHPSDV(dev_priv) (dev_priv && 0)
>> #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2)
>> #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)
>> #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
>> @@ -130,7 +129,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
>> #define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \
>> ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \
>> IS_GRAPHICS_STEP(xe, first, last))
>> -#define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last) (IS_XEHPSDV(xe) && IS_GRAPHICS_STEP(xe, first, last))
>>
>> /* XXX: No basedie stepping support yet */
>> #define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) && IS_PONTEVECCHIO(xe))
>> --
>> 2.43.0
>>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] drm/i915: Drop WA 16015675438
2024-03-06 19:36 ` [PATCH 1/5] drm/i915: Drop WA 16015675438 Lucas De Marchi
@ 2024-03-12 22:54 ` Matt Roper
2024-03-12 23:47 ` Lucas De Marchi
0 siblings, 1 reply; 22+ messages in thread
From: Matt Roper @ 2024-03-12 22:54 UTC (permalink / raw)
To: Lucas De Marchi
Cc: intel-gfx, dri-devel, Mateusz Jablonski, Michal Mrozek, Rodrigo Vivi
On Wed, Mar 06, 2024 at 11:36:39AM -0800, Lucas De Marchi wrote:
> With dynamic load-balancing disabled on the compute side, there's no
> reason left to enable WA 16015675438. Drop it from both PVC and DG2.
> Note that this can be done because now the driver always set a fixed
> partition of EUs during initialization via the ccs_mode configuration.
>
> The flag to GuC is still needed because of 18020744125, so update
> the comment accordingly.
>
> Cc: Mateusz Jablonski <mateusz.jablonski@intel.com>
> Cc: Michal Mrozek <michal.mrozek@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Dynamic load-balancing disable hasn't landed in i915 yet (although it
probably will soon). Assuming we wait for that to happen first before
applying this,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +-----
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
> 2 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d67d44611c28..7f812409c30a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2928,14 +2928,10 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> }
>
> - if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) {
> + if (IS_PONTEVECCHIO(i915) || IS_DG2(i915))
> /* Wa_14015227452:dg2,pvc */
> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
>
> - /* Wa_16015675438:dg2,pvc */
> - wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
> - }
> -
> if (IS_DG2(i915)) {
> /*
> * Wa_16011620976:dg2_g11
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index d2b7425bbdcc..c6603793af89 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -315,7 +315,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> if (IS_DG2_G11(gt->i915))
> flags |= GUC_WA_CONTEXT_ISOLATION;
>
> - /* Wa_16015675438 */
> + /* Wa_18020744125 */
> if (!RCS_MASK(gt))
> flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
>
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv
2024-03-06 19:36 ` [PATCH 2/5] drm/i915: Drop dead code for xehpsdv Lucas De Marchi
2024-03-11 15:16 ` Rodrigo Vivi
@ 2024-03-12 22:58 ` Matt Roper
2024-03-12 23:07 ` Lucas De Marchi
1 sibling, 1 reply; 22+ messages in thread
From: Matt Roper @ 2024-03-12 22:58 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:
> PCI IDs for XEHPSDV were never added and platform always marked with
> force_probe. Drop what's not used and rename some places to either be
> xehp or dg2, depending on the platform/IP checks.
>
> The registers not used anymore are also removed.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>
> Potential problem here that needs a deeper look, the changes in
> __gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
> I removed them, but it needs to be double checked with spec and CI
> results.
>
...
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 76400e9c40f0..4f1e56187442 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1536,17 +1536,12 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
> GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
> 0x13200 - 0x133ff: VD2 (DG2 only) \
> 0x13400 - 0x13fff: reserved */ \
> - GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
> - GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
> - GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
> - GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
We can't just remove ranges in the middle of the table since that breaks
the "watertight" table requirement that our selftests check for. We
need to either roll the now-unused ranges into an adjacent range, or add
a new "reserved" range.
> GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
> GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
> 0x15000 - 0x15fff: gt (DG2 only) \
> 0x16000 - 0x16dff: reserved */ \
> GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
> - GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
> - 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
> + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
> 0x21000 - 0x21fff: reserved */ \
> GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
> GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
> @@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
> 0x1f6e00 - 0x1f7fff: reserved */ \
> GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
>
> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
> - XEHP_FWRANGES(FORCEWAKE_GT)
> -};
> -
> static const struct intel_forcewake_range __dg2_fw_ranges[] = {
> XEHP_FWRANGES(FORCEWAKE_RENDER)
We can drop the macro here now and just make this a normal table like
everything else.
Matt
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv
2024-03-12 22:58 ` Matt Roper
@ 2024-03-12 23:07 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-12 23:07 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Tue, Mar 12, 2024 at 03:58:19PM -0700, Matt Roper wrote:
>On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:
>> PCI IDs for XEHPSDV were never added and platform always marked with
>> force_probe. Drop what's not used and rename some places to either be
>> xehp or dg2, depending on the platform/IP checks.
>>
>> The registers not used anymore are also removed.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>
>> Potential problem here that needs a deeper look, the changes in
>> __gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
>> I removed them, but it needs to be double checked with spec and CI
>> results.
>>
>...
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 76400e9c40f0..4f1e56187442 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -1536,17 +1536,12 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
>> GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
>> 0x13200 - 0x133ff: VD2 (DG2 only) \
>> 0x13400 - 0x13fff: reserved */ \
>> - GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
>> - GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
>> - GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
>> - GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
>
>We can't just remove ranges in the middle of the table since that breaks
>the "watertight" table requirement that our selftests check for. We
>need to either roll the now-unused ranges into an adjacent range, or add
>a new "reserved" range.
see 23n224gu57lfd4wbroqflav4pih6usrkf53q2ve4ntekhueylb@eqigxyktri6b
>
>> GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
>> GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
>> 0x15000 - 0x15fff: gt (DG2 only) \
>> 0x16000 - 0x16dff: reserved */ \
>> GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
>> - GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
>> - 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
>> + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
>> 0x21000 - 0x21fff: reserved */ \
>> GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
>> GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
>> @@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
>> 0x1f6e00 - 0x1f7fff: reserved */ \
>> GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
>>
>> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
>> - XEHP_FWRANGES(FORCEWAKE_GT)
>> -};
>> -
>> static const struct intel_forcewake_range __dg2_fw_ranges[] = {
>> XEHP_FWRANGES(FORCEWAKE_RENDER)
>
>We can drop the macro here now and just make this a normal table like
>everything else.
will add that in v2 too, thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] drm/i915: Drop WA 16015675438
2024-03-12 22:54 ` Matt Roper
@ 2024-03-12 23:47 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2024-03-12 23:47 UTC (permalink / raw)
To: Matt Roper
Cc: intel-gfx, dri-devel, Mateusz Jablonski, Michal Mrozek, Rodrigo Vivi
On Tue, Mar 12, 2024 at 03:54:09PM -0700, Matt Roper wrote:
>On Wed, Mar 06, 2024 at 11:36:39AM -0800, Lucas De Marchi wrote:
>> With dynamic load-balancing disabled on the compute side, there's no
>> reason left to enable WA 16015675438. Drop it from both PVC and DG2.
>> Note that this can be done because now the driver always set a fixed
>> partition of EUs during initialization via the ccs_mode configuration.
>>
>> The flag to GuC is still needed because of 18020744125, so update
>> the comment accordingly.
>>
>> Cc: Mateusz Jablonski <mateusz.jablonski@intel.com>
>> Cc: Michal Mrozek <michal.mrozek@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>Dynamic load-balancing disable hasn't landed in i915 yet (although it
>probably will soon). Assuming we wait for that to happen first before
>applying this,
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Humn... I probably grepped the wrong tree for this one since I was
seeing ccs_mode being set. Indeed it isn't :-/, so I will have to land a
fix or revert since this patch already landed a few days ago.
Lucas De Marchi
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2024-03-12 23:48 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-06 19:36 [PATCH 0/5] drm/i915: cleanup dead code Lucas De Marchi
2024-03-06 19:36 ` [PATCH 1/5] drm/i915: Drop WA 16015675438 Lucas De Marchi
2024-03-12 22:54 ` Matt Roper
2024-03-12 23:47 ` Lucas De Marchi
2024-03-06 19:36 ` [PATCH 2/5] drm/i915: Drop dead code for xehpsdv Lucas De Marchi
2024-03-11 15:16 ` Rodrigo Vivi
2024-03-12 16:29 ` Lucas De Marchi
2024-03-12 22:58 ` Matt Roper
2024-03-12 23:07 ` Lucas De Marchi
2024-03-06 19:36 ` [PATCH 3/5] drm/i915: Update IP_VER(12, 50) Lucas De Marchi
2024-03-11 15:18 ` Rodrigo Vivi
2024-03-11 15:29 ` Lucas De Marchi
2024-03-11 16:21 ` Rodrigo Vivi
2024-03-06 19:36 ` [PATCH 4/5] drm/i915: Drop dead code for pvc Lucas De Marchi
2024-03-11 15:29 ` Rodrigo Vivi
2024-03-11 15:35 ` Lucas De Marchi
2024-03-11 16:22 ` Rodrigo Vivi
2024-03-06 19:36 ` [PATCH 5/5] drm/i915: Remove special handling for !RCS_MASK() Lucas De Marchi
2024-03-11 17:43 ` [PATCH 0/5] drm/i915: cleanup dead code Tvrtko Ursulin
2024-03-11 19:27 ` Lucas De Marchi
2024-03-12 9:54 ` Tvrtko Ursulin
2024-03-12 12:53 ` Lucas De Marchi
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