From: Maxime Ripard <maxime@cerno.tech>
To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Eric Anholt <eric@anholt.net>
Cc: Tim Gover <tim.gover@raspberrypi.com>,
Dave Stevenson <dave.stevenson@raspberrypi.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
bcm-kernel-feedback-list@broadcom.com,
linux-rpi-kernel@lists.infradead.org,
Phil Elwell <phil@raspberrypi.com>,
linux-arm-kernel@lists.infradead.org,
Maxime Ripard <maxime@cerno.tech>
Subject: [PATCH v3 033/105] drm/vc4: crtc: Assign output to channel automatically
Date: Wed, 27 May 2020 17:48:03 +0200 [thread overview]
Message-ID: <5186409a2b5d290b78f6b518a2eb8e407bf1e83e.1590594512.git-series.maxime@cerno.tech> (raw)
In-Reply-To: <cover.aaf2100bd7da4609f8bcb8216247d4b4e4379639.1590594512.git-series.maxime@cerno.tech>
The HVS found in the BCM2711 has 6 outputs and 3 FIFOs, with each output
being connected to a pixelvalve, and some muxing between the FIFOs and
outputs.
Any output cannot feed from any FIFO though, and they all have a bunch of
constraints.
In order to support this, let's store the possible FIFOs each output can be
assigned to in the vc4_crtc_data, and use that information at atomic_check
time to iterate over all the CRTCs enabled and assign them FIFOs.
The channel assigned is then set in the vc4_crtc_state so that the rest of
the driver can use it.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 37 +++++----
drivers/gpu/drm/vc4/vc4_drv.h | 7 +-
drivers/gpu/drm/vc4/vc4_kms.c | 142 ++++++++++++++++++++++++++++++++--
drivers/gpu/drm/vc4/vc4_regs.h | 10 ++-
4 files changed, 172 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 580b37ad514d..a6c3f2f907bd 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -88,6 +88,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
unsigned int cob_size;
u32 val;
int fifo_lines;
@@ -104,7 +105,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
* Read vertical scanline which is currently composed for our
* pixelvalve by the HVS, and also the scaler status.
*/
- val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
+ val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
/* Get optional system timestamp after query. */
if (etime)
@@ -124,7 +125,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
*hpos += mode->crtc_htotal / 2;
}
- cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc->channel);
+ cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
/* This is the offset we need for translating hvs -> pv scanout pos. */
fifo_lines = cob_size / mode->crtc_hdisplay;
@@ -211,6 +212,7 @@ vc4_crtc_lut_load(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
u32 i;
/* The LUT memory is laid out with each HVS channel in order,
@@ -219,7 +221,7 @@ vc4_crtc_lut_load(struct drm_crtc *crtc)
*/
HVS_WRITE(SCALER_GAMADDR,
SCALER_GAMADDR_AUTOINC |
- (vc4_crtc->channel * 3 * crtc->gamma_size));
+ (vc4_crtc_state->assigned_channel * 3 * crtc->gamma_size));
for (i = 0; i < crtc->gamma_size; i++)
HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
@@ -392,7 +394,7 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
drm_print_regset32(&p, &vc4_crtc->regset);
}
- if (vc4_crtc->channel == 2) {
+ if (vc4_crtc->data->hvs_output == 2) {
u32 dispctrl;
u32 dsp3_mux;
@@ -419,7 +421,7 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
if (!vc4_state->feed_txp)
vc4_crtc_config_pv(crtc);
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
SCALER_DISPBKGND_AUTOHS |
SCALER_DISPBKGND_GAMMA |
(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
@@ -451,7 +453,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- u32 chan = vc4_crtc->channel;
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(old_state);
+ u32 chan = vc4_crtc_state->assigned_channel;
int ret;
require_hvs_enabled(dev);
@@ -530,12 +533,12 @@ static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
crtc->state->event = NULL;
}
- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
+ HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
vc4_state->mm.start);
spin_unlock_irqrestore(&dev->event_lock, flags);
} else {
- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
+ HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
vc4_state->mm.start);
}
}
@@ -584,7 +587,7 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
(vc4_state->feed_txp ?
SCALER5_DISPCTRLX_ONESHOT : 0);
- HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
+ HVS_WRITE(SCALER_DISPCTRLX(vc4_state->assigned_channel), dispctrl);
/* When feeding the transposer block the pixelvalve is unneeded and
* should not be enabled.
@@ -700,7 +703,6 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
struct drm_plane *plane;
struct vc4_plane_state *vc4_plane_state;
@@ -742,8 +744,8 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
/* This sets a black background color fill, as is the case
* with other DRM drivers.
*/
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
- HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
+ HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel)) |
SCALER_DISPBKGND_FILL);
/* Only update DISPLIST if the CRTC was already running and is not
@@ -757,7 +759,7 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
vc4_crtc_update_dlist(crtc);
if (crtc->state->color_mgmt_changed) {
- u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
+ u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel));
if (crtc->state->gamma_lut) {
vc4_crtc_update_gamma_lut(crtc);
@@ -769,7 +771,7 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
*/
dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
}
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
+ HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel), dispbkgndx);
}
if (debug_dump_regs) {
@@ -800,7 +802,7 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
- u32 chan = vc4_crtc->channel;
+ u32 chan = vc4_state->assigned_channel;
unsigned long flags;
spin_lock_irqsave(&dev->event_lock, flags);
@@ -999,6 +1001,7 @@ static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
old_vc4_state = to_vc4_crtc_state(crtc->state);
vc4_state->feed_txp = old_vc4_state->feed_txp;
vc4_state->margins = old_vc4_state->margins;
+ vc4_state->assigned_channel = old_vc4_state->assigned_channel;
__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
return &vc4_state->base;
@@ -1060,6 +1063,7 @@ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
};
static const struct vc4_crtc_data bcm2835_pv0_data = {
+ .hvs_available_channels = BIT(0),
.hvs_output = 0,
.debugfs_name = "crtc0_regs",
.pixels_per_clock = 1,
@@ -1070,6 +1074,7 @@ static const struct vc4_crtc_data bcm2835_pv0_data = {
};
static const struct vc4_crtc_data bcm2835_pv1_data = {
+ .hvs_available_channels = BIT(2),
.hvs_output = 2,
.debugfs_name = "crtc1_regs",
.pixels_per_clock = 1,
@@ -1080,6 +1085,7 @@ static const struct vc4_crtc_data bcm2835_pv1_data = {
};
static const struct vc4_crtc_data bcm2835_pv2_data = {
+ .hvs_available_channels = BIT(1),
.hvs_output = 1,
.debugfs_name = "crtc2_regs",
.pixels_per_clock = 1,
@@ -1171,7 +1177,6 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
&vc4_crtc_funcs, NULL);
drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
- vc4_crtc->channel = vc4_crtc->data->hvs_output;
drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 9d120aae4af9..73156a53822f 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -450,6 +450,9 @@ to_vc4_encoder(struct drm_encoder *encoder)
}
struct vc4_crtc_data {
+ /* Which channels of the HVS can the output source from */
+ unsigned int hvs_available_channels;
+
/* Which output of the HVS this pixelvalve sources from. */
int hvs_output;
@@ -469,9 +472,6 @@ struct vc4_crtc {
/* Timestamp at start of vblank irq - unaffected by lock delays. */
ktime_t t_vblank;
- /* Which HVS channel we're using for our CRTC. */
- int channel;
-
u8 lut_r[256];
u8 lut_g[256];
u8 lut_b[256];
@@ -493,6 +493,7 @@ struct vc4_crtc_state {
struct drm_mm_node mm;
bool feed_txp;
bool txp_armed;
+ unsigned int assigned_channel;
struct {
unsigned int left;
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 29b75b60d858..db00625c61dd 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -11,6 +11,8 @@
* crtc, HDMI encoder).
*/
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
#include <linux/clk.h>
#include <drm/drm_atomic.h>
@@ -146,6 +148,72 @@ vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
}
+static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
+ struct drm_atomic_state *state)
+{
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+ unsigned char dsp2_mux = 0;
+ unsigned char dsp3_mux = 3;
+ unsigned char dsp4_mux = 3;
+ unsigned char dsp5_mux = 3;
+ unsigned int i;
+ u32 reg;
+
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+
+ if (!crtc_state->active)
+ continue;
+
+ switch (vc4_crtc->data->hvs_output) {
+ case 2:
+ dsp2_mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
+ break;
+
+ case 3:
+ dsp3_mux = vc4_state->assigned_channel;
+ break;
+
+ case 4:
+ dsp4_mux = vc4_state->assigned_channel;
+ break;
+
+ case 5:
+ dsp5_mux = vc4_state->assigned_channel;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ reg = HVS_READ(SCALER_DISPECTRL);
+ if (FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg) != dsp2_mux)
+ HVS_WRITE(SCALER_DISPECTRL,
+ (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
+ VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX));
+
+ reg = HVS_READ(SCALER_DISPCTRL);
+ if (FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg) != dsp3_mux)
+ HVS_WRITE(SCALER_DISPCTRL,
+ (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
+ VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX));
+
+ reg = HVS_READ(SCALER_DISPEOLN);
+ if (FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg) != dsp4_mux)
+ HVS_WRITE(SCALER_DISPEOLN,
+ (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
+ VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX));
+
+ reg = HVS_READ(SCALER_DISPDITHER);
+ if (FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg) != dsp5_mux)
+ HVS_WRITE(SCALER_DISPDITHER,
+ (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
+ VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX));
+}
+
static void
vc4_atomic_complete_commit(struct drm_atomic_state *state)
{
@@ -156,11 +224,15 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
int i;
for (i = 0; i < dev->mode_config.num_crtc; i++) {
- if (!state->crtcs[i].ptr || !state->crtcs[i].commit)
+ struct __drm_crtcs_state *_state = &state->crtcs[i];
+ struct vc4_crtc_state *vc4_crtc_state;
+
+ if (!_state->ptr || !_state->commit)
continue;
- vc4_crtc = to_vc4_crtc(state->crtcs[i].ptr);
- vc4_hvs_mask_underrun(dev, vc4_crtc->channel);
+ vc4_crtc = to_vc4_crtc(_state->ptr);
+ vc4_crtc_state = to_vc4_crtc_state(_state->state);
+ vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
}
clk_set_rate(hvs->core_clk, 500000000);
@@ -172,6 +244,7 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
drm_atomic_helper_commit_modeset_disables(dev, state);
vc4_ctm_commit(vc4, state);
+ vc4_hvs_pv_muxing_commit(vc4, state);
drm_atomic_helper_commit_planes(dev, state, 0);
@@ -381,8 +454,11 @@ vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
/* CTM is being enabled or the matrix changed. */
if (new_crtc_state->ctm) {
+ struct vc4_crtc_state *vc4_crtc_state =
+ to_vc4_crtc_state(new_crtc_state);
+
/* fifo is 1-based since 0 disables CTM. */
- int fifo = to_vc4_crtc(crtc)->channel + 1;
+ int fifo = vc4_crtc_state->assigned_channel + 1;
/* Check userland isn't trying to turn on CTM for more
* than one CRTC at a time.
@@ -495,10 +571,66 @@ static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
.atomic_destroy_state = vc4_load_tracker_destroy_state,
};
+#define NUM_OUTPUTS 6
+#define NUM_CHANNELS 3
+
static int
vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
{
- int ret;
+ unsigned long unassigned_channels = GENMASK(NUM_CHANNELS - 1, 0);
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+ int i, ret;
+
+ for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+ struct vc4_crtc_state *vc4_crtc_state =
+ to_vc4_crtc_state(crtc_state);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ bool is_assigned = false;
+ unsigned int channel;
+
+ if (!crtc_state->active)
+ continue;
+
+ /*
+ * The problem we have to solve here is that we have
+ * up to 7 encoders, connected to up to 6 CRTCs.
+ *
+ * Those CRTCs, depending on the instance, can be
+ * routed to 1, 2 or 3 HVS FIFOs, and we need to set
+ * the change the muxing between FIFOs and outputs in
+ * the HVS accordingly.
+ *
+ * It would be pretty hard to come up with an
+ * algorithm that would generically solve
+ * this. However, the current routing trees we support
+ * allow us to simplify a bit the problem.
+ *
+ * Indeed, with the current supported layouts, if we
+ * try to assign in the ascending crtc index order the
+ * FIFOs, we can't fall into the situation where an
+ * earlier CRTC that had multiple routes is assigned
+ * one that was the only option for a later CRTC.
+ *
+ * If the layout changes and doesn't give us that in
+ * the future, we will need to have something smarter,
+ * but it works so far.
+ */
+ for_each_set_bit(channel, &unassigned_channels,
+ sizeof(unassigned_channels)) {
+
+ if (!(BIT(channel) & vc4_crtc->data->hvs_available_channels))
+ continue;
+
+ vc4_crtc_state->assigned_channel = channel;
+ unassigned_channels &= ~BIT(channel);
+ is_assigned = true;
+ break;
+ }
+
+ if (!is_assigned)
+ return -EINVAL;
+ }
ret = vc4_ctm_atomic_check(dev, state);
if (ret < 0)
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 8a51baf681fe..b96ebbb1354b 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -287,9 +287,19 @@
#define SCALER_DISPID 0x00000008
#define SCALER_DISPECTRL 0x0000000c
+# define SCALER_DISPECTRL_DSP2_MUX_SHIFT 31
+# define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31)
+
#define SCALER_DISPPROF 0x00000010
+
#define SCALER_DISPDITHER 0x00000014
+# define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
+# define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
+
#define SCALER_DISPEOLN 0x00000018
+# define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
+# define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
+
#define SCALER_DISPLIST0 0x00000020
#define SCALER_DISPLIST1 0x00000024
#define SCALER_DISPLIST2 0x00000028
--
git-series 0.9.1
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next prev parent reply other threads:[~2020-05-28 7:46 UTC|newest]
Thread overview: 151+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-27 15:47 [PATCH v3 000/105] drm/vc4: Support BCM2711 Display Pipeline Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 001/105] reset: Move reset-simple header out of drivers/reset Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 002/105] reset: simple: Add reset callback Maxime Ripard
2020-05-27 16:03 ` Philipp Zabel
2020-05-27 15:47 ` [PATCH v3 003/105] dt-bindings: clock: Add BCM2711 DVP binding Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 004/105] clk: bcm: Add BCM2711 DVP driver Maxime Ripard
2020-06-04 17:26 ` Nicolas Saenz Julienne
2020-06-05 17:43 ` Maxime Ripard
2020-06-05 18:11 ` Nicolas Saenz Julienne
2020-06-05 17:56 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 005/105] ARM: dts: bcm2711: Add HDMI DVP Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 006/105] dt-bindings: display: Convert VC4 bindings to schemas Maxime Ripard
2020-05-27 19:12 ` Rob Herring
2020-06-02 15:00 ` Maxime Ripard
2020-06-17 20:21 ` Rob Herring
2020-05-27 15:47 ` [PATCH v3 007/105] dt-bindings: display: vc4: dpi: Add missing clock-names property Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 008/105] dt-bindings: display: vc4: dsi: Add missing clock properties Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 009/105] dt-bindings: display: vc4: hdmi: Add missing clock-names property Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 010/105] dt-bindings: display: vc4: Document BCM2711 VC5 Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 011/105] drm/vc4: drv: Add include guards Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 012/105] drm/vc4: drv: Support BCM2711 Maxime Ripard
2020-05-27 16:27 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 013/105] dt-bindings: display: Add support for the BCM2711 HVS Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 014/105] drm/vc4: Add support for the BCM2711 HVS5 Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 015/105] drm/vc4: hvs: Boost the core clock during modeset Maxime Ripard
2020-05-27 16:33 ` Eric Anholt
2020-06-02 12:52 ` Maxime Ripard
2020-06-02 17:52 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 016/105] drm/vc4: plane: Improve LBM usage Maxime Ripard
2020-05-27 16:44 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 017/105] drm/vc4: plane: Move planes creation to its own function Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 018/105] drm/vc4: plane: Move additional planes creation to driver Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 019/105] drm/vc4: plane: Register all the planes at once Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 020/105] drm/vc4: plane: Create overlays for any CRTC Maxime Ripard
2020-05-27 16:52 ` Eric Anholt
2020-05-27 15:47 ` [PATCH v3 021/105] drm/vc4: plane: Create more planes Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 022/105] drm/vc4: crtc: Rename SoC data structures Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 023/105] drm/vc4: crtc: Switch to of_device_get_match_data Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 024/105] drm/vc4: crtc: Move crtc state to common header Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 025/105] drm/vc4: crtc: Deal with different number of pixel per clock Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 026/105] drm/vc4: crtc: Use a shared interrupt Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 027/105] drm/vc4: crtc: Turn static const variable into a define Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 028/105] drm/vc4: crtc: Restrict HACT_ACT setup to DSI Maxime Ripard
2020-05-27 15:47 ` [PATCH v3 029/105] drm/vc4: crtc: Move the cob allocation outside of bind Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 030/105] drm/vc4: crtc: Rename HVS channel to output Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 031/105] drm/vc4: crtc: Use local chan variable Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 032/105] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable Maxime Ripard
2020-05-27 16:54 ` Eric Anholt
2020-06-02 14:12 ` Maxime Ripard
2020-06-02 15:02 ` Dave Stevenson
2020-06-02 19:31 ` Eric Anholt
2020-06-02 20:03 ` Stefan Wahren
2020-06-03 13:14 ` Maxime Ripard
2020-06-03 15:26 ` Stefan Wahren
2020-06-12 15:35 ` Maxime Ripard
2020-05-27 15:48 ` Maxime Ripard [this message]
2020-05-27 17:23 ` [PATCH v3 033/105] drm/vc4: crtc: Assign output to channel automatically Eric Anholt
2020-06-16 15:04 ` Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 034/105] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 035/105] drm/vc4: crtc: Add function to compute FIFO level bits Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 036/105] drm/vc4: crtc: Rename HDMI encoder type to HDMI0 Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 037/105] drm/vc4: crtc: Add HDMI1 encoder type Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 038/105] drm/vc4: crtc: Remove redundant call to drm_crtc_enable_color_mgmt Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 039/105] drm/vc4: crtc: Disable color management for HVS5 Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 040/105] drm/vc4: crtc: Turn pixelvalve reset into a function Maxime Ripard
2020-05-27 17:30 ` Eric Anholt
2020-05-27 15:48 ` [PATCH v3 041/105] drm/vc4: crtc: Move HVS mode config to HVS file Maxime Ripard
2020-05-27 18:26 ` Eric Anholt
2020-05-27 15:48 ` [PATCH v3 042/105] drm/vc4: crtc: Move PV dump to config_pv Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 043/105] drm/vc4: crtc: Move HVS init and close to a function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 044/105] drm/vc4: crtc: Move the HVS gamma LUT setup to our init function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 045/105] drm/vc4: hvs: Make sure our channel is reset Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 046/105] drm/vc4: hvs: Remove mode_set_nofb Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 047/105] drm/vc4: crtc: " Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 048/105] drm/vc4: crtc: Remove redundant pixelvalve reset Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 049/105] drm/vc4: crtc: Move HVS channel init before the PV initialisation Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 050/105] drm/vc4: encoder: Add finer-grained encoder callbacks Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 051/105] drm/vc4: crtc: Add a delay after disabling the PixelValve output Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 052/105] drm/vc4: crtc: Clear the PixelValve FIFO on disable Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 053/105] drm/vc4: crtc: Clear the PixelValve FIFO during configuration Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 054/105] drm/vc4: hvs: Make the stop_channel function public Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 055/105] drm/vc4: hvs: Introduce a function to get the assigned FIFO Maxime Ripard
2020-05-27 19:40 ` Eric Anholt
2020-06-03 9:43 ` Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 056/105] drm/vc4: crtc: Move the CRTC disable out Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 057/105] drm/vc4: drv: Disable the CRTC at boot time Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 058/105] dt-bindings: display: vc4: pv: Add BCM2711 pixel valves Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 059/105] drm/vc4: crtc: Add BCM2711 pixelvalves Maxime Ripard
2020-05-27 19:24 ` Eric Anholt
2020-05-27 15:48 ` [PATCH v3 060/105] drm/vc4: crtc: Make state functions public Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 061/105] drm/vc4: crtc: Split CRTC data in two Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 062/105] drm/vc4: crtc: Only access the PixelValve registers if we have to Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 063/105] drm/vc4: crtc: Move the CRTC initialisation to a separate function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 064/105] drm/vc4: crtc: Change the HVS5 test for of_device_is_compatible Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 065/105] drm/vc4: crtc: Move the txp_armed function to the TXP Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 066/105] drm/vc4: txp: Turn the TXP into a CRTC of its own Maxime Ripard
2020-05-28 15:51 ` Emil Velikov
2020-06-10 18:40 ` Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 067/105] drm/vc4: crtc: Remove the feed_txp tests Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 068/105] drm/vc4: hdmi: Use debugfs private field Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 069/105] drm/vc4: hdmi: Move structure to header Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 070/105] drm/vc4: hdmi: rework connectors and encoders Maxime Ripard
2020-05-27 18:41 ` Eric Anholt
2020-06-02 15:54 ` Maxime Ripard
2020-06-03 17:32 ` Stefan Wahren
2020-06-05 14:35 ` Maxime Ripard
2020-06-06 8:06 ` Stefan Wahren
2020-06-11 13:34 ` Maxime Ripard
2020-06-14 16:16 ` Stefan Wahren
2020-06-16 12:30 ` Maxime Ripard
2020-06-16 19:09 ` Stefan Wahren
2020-05-27 15:48 ` [PATCH v3 071/105] drm/vc4: hdmi: Remove DDC argument to connector_init Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 072/105] drm/vc4: hdmi: Rename hdmi to vc4_hdmi Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 073/105] drm/vc4: hdmi: Move accessors " Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 074/105] drm/vc4: hdmi: Use local vc4_hdmi directly Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 075/105] drm/vc4: hdmi: Add container_of macros for encoders and connectors Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 076/105] drm/vc4: hdmi: Pass vc4_hdmi to CEC code Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 077/105] drm/vc4: hdmi: Remove vc4_dev hdmi pointer Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 078/105] drm/vc4: hdmi: Remove vc4_hdmi_connector Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 079/105] drm/vc4: hdmi: Introduce resource init and variant Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 080/105] drm/vc4: hdmi: Implement a register layout abstraction Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 081/105] drm/vc4: hdmi: Add reset callback Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 082/105] drm/vc4: hdmi: Add PHY init and disable function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 083/105] drm/vc4: hdmi: Add PHY RNG enable / " Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 084/105] drm/vc4: hdmi: Add a CSC setup callback Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 085/105] drm/vc4: hdmi: Store the encoder type in the variant structure Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 086/105] drm/vc4: hdmi: Deal with multiple debugfs files Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 087/105] drm/vc4: hdmi: Move CEC init to its own function Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 088/105] drm/vc4: hdmi: Add CEC support flag Maxime Ripard
2020-05-27 15:48 ` [PATCH v3 089/105] drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 090/105] drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 091/105] drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 092/105] drm/vc4: hdmi: Use clk_set_min_rate instead Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 093/105] drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 094/105] drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 095/105] drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 096/105] drm/vc4: hdmi: Add audio-related callbacks Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 097/105] drm/vc4: hdmi: Deal with multiple ALSA cards Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 098/105] drm/vc4: hdmi: Remove register dumps in enable Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 099/105] drm/vc4: hdmi: Always recenter the HDMI FIFO Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 100/105] drm/vc4: hdmi: Implement finer-grained hooks Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 101/105] drm/vc4: hdmi: Do the VID_CTL configuration at once Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 102/105] drm/vc4: hdmi: Switch to blank pixels when disabled Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 103/105] drm/vc4: hdmi: Support the BCM2711 HDMI controllers Maxime Ripard
2020-05-27 15:49 ` [PATCH v3 104/105] dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings Maxime Ripard
2020-05-29 18:18 ` Rob Herring
2020-06-02 15:08 ` Maxime Ripard
2020-06-08 23:01 ` Rob Herring
2020-05-27 15:49 ` [PATCH v3 105/105] ARM: dts: bcm2711: Enable the display pipeline Maxime Ripard
2020-06-03 20:11 ` Stefan Wahren
2020-06-02 20:12 ` [PATCH v3 000/105] drm/vc4: Support BCM2711 Display Pipeline Stefan Wahren
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