From: Dmitry Osipenko <digetx@gmail.com>
To: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org, "Mikko Perttunen" <cyndis@kapsi.fi>,
linux-pm@vger.kernel.org, "Stephen Boyd" <sboyd@kernel.org>,
linux-kernel@vger.kernel.org,
"Peter De Schrijver" <pdeschrijver@nvidia.com>,
"Artur Świgoń" <a.swigon@samsung.com>,
dri-devel@lists.freedesktop.org,
"Georgi Djakov" <georgi.djakov@linaro.org>,
"Chanwoo Choi" <cw00.choi@samsung.com>,
"Kyungmin Park" <kyungmin.park@samsung.com>,
"Thierry Reding" <thierry.reding@gmail.com>,
"MyungJoo Ham" <myungjoo.ham@samsung.com>,
linux-tegra@vger.kernel.org,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Michael Turquette" <mturquette@baylibre.com>
Subject: Re: [PATCH v4 22/37] dt-bindings: host1x: Document new interconnect properties
Date: Thu, 18 Jun 2020 00:44:47 +0300 [thread overview]
Message-ID: <5303317a-2cb6-d7a8-361a-30867fc6eab7@gmail.com> (raw)
In-Reply-To: <20200617213726.GA2837398@bogus>
18.06.2020 00:37, Rob Herring пишет:
> On Tue, Jun 09, 2020 at 04:13:49PM +0300, Dmitry Osipenko wrote:
>> Most of Host1x devices have at least one memory client. These clients
>> are directly connected to the memory controller. The new interconnect
>> properties represent the memory client's connection to the memory
>> controller.
>>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
>> .../display/tegra/nvidia,tegra20-host1x.txt | 68 +++++++++++++++++++
>> 1 file changed, 68 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
>> index 47319214b5f6..ab4fbee7bccf 100644
>> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
>> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
>> @@ -20,6 +20,10 @@ Required properties:
>> - reset-names: Must include the following entries:
>> - host1x
>>
>> +Each host1x client module having to perform DMA through the Memory Controller
>> +should have the interconnect endpoints set to the Memory Client and External
>> +Memory respectively.
>> +
>> The host1x top-level node defines a number of children, each representing one
>> of the following host1x client modules:
>>
>> @@ -36,6 +40,12 @@ of the following host1x client modules:
>> - reset-names: Must include the following entries:
>> - mpe
>>
>> + Optional properties:
>> + - interconnects: Must contain entry for the MPE memory clients.
>> + - interconnect-names: Must include name of the interconnect path for each
>> + interconnect entry. Consult TRM documentation for information about
>> + available memory clients, see MEMORY CONTROLLER section.
>> +
>> - vi: video input
>>
>> Required properties:
>> @@ -65,6 +75,12 @@ of the following host1x client modules:
>> - power-domains: Must include sor powergate node as csicil is in
>> SOR partition.
>>
>> + Optional properties:
>> + - interconnects: Must contain entry for the VI memory clients.
>> + - interconnect-names: Must include name of the interconnect path for each
>> + interconnect entry. Consult TRM documentation for information about
>> + available memory clients, see MEMORY CONTROLLER section.
>> +
>> - epp: encoder pre-processor
>>
>> Required properties:
>> @@ -78,6 +94,12 @@ of the following host1x client modules:
>> - reset-names: Must include the following entries:
>> - epp
>>
>> + Optional properties:
>> + - interconnects: Must contain entry for the EPP memory clients.
>> + - interconnect-names: Must include name of the interconnect path for each
>> + interconnect entry. Consult TRM documentation for information about
>> + available memory clients, see MEMORY CONTROLLER section.
>> +
>> - isp: image signal processor
>>
>> Required properties:
>> @@ -91,6 +113,12 @@ of the following host1x client modules:
>> - reset-names: Must include the following entries:
>> - isp
>>
>> + Optional properties:
>> + - interconnects: Must contain entry for the ISP memory clients.
>> + - interconnect-names: Must include name of the interconnect path for each
>> + interconnect entry. Consult TRM documentation for information about
>> + available memory clients, see MEMORY CONTROLLER section.
>> +
>> - gr2d: 2D graphics engine
>>
>> Required properties:
>> @@ -104,6 +132,12 @@ of the following host1x client modules:
>> - reset-names: Must include the following entries:
>> - 2d
>>
>> + Optional properties:
>> + - interconnects: Must contain entry for the GR2D memory clients.
>> + - interconnect-names: Must include name of the interconnect path for each
>> + interconnect entry. Consult TRM documentation for information about
>> + available memory clients, see MEMORY CONTROLLER section.
>> +
>> - gr3d: 3D graphics engine
>>
>> Required properties:
>> @@ -122,6 +156,12 @@ of the following host1x client modules:
>> - 3d
>> - 3d2 (Only required on SoCs with two 3D clocks)
>>
>> + Optional properties:
>> + - interconnects: Must contain entry for the GR3D memory clients.
>> + - interconnect-names: Must include name of the interconnect path for each
>> + interconnect entry. Consult TRM documentation for information about
>> + available memory clients, see MEMORY CONTROLLER section.
>> +
>> - dc: display controller
>>
>> Required properties:
>> @@ -149,6 +189,10 @@ of the following host1x client modules:
>> - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
>> - nvidia,edid: supplies a binary EDID blob
>> - nvidia,panel: phandle of a display panel
>> + - interconnects: Must contain entry for the DC memory clients.
>> + - interconnect-names: Must include name of the interconnect path for each
>> + interconnect entry. Consult TRM documentation for information about
>> + available memory clients, see MEMORY CONTROLLER section.
>>
>> - hdmi: High Definition Multimedia Interface
>>
>> @@ -297,6 +341,12 @@ of the following host1x client modules:
>> - reset-names: Must include the following entries:
>> - vic
>>
>> + Optional properties:
>> + - interconnects: Must contain entry for the VIC memory clients.
>> + - interconnect-names: Must include name of the interconnect path for each
>> + interconnect entry. Consult TRM documentation for information about
>> + available memory clients, see MEMORY CONTROLLER section.
>> +
>> Example:
>>
>> / {
>> @@ -410,6 +460,15 @@ Example:
>> resets = <&tegra_car 27>;
>> reset-names = "dc";
>>
>> + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
>> + <&mc TEGRA20_MC_DISPLAY0B &emc>,
>> + <&mc TEGRA20_MC_DISPLAY0C &emc>,
>> + <&mc TEGRA20_MC_DISPLAY1B &emc>;
>
> This looks odd or wrong. Each entry has 2 phandles?
Each entry defines interconnect path, where MC is the start of the path
and EMC is the end. So yes, 2 phandles for each path.
Please see arm/boot/dts/qcom-msm8974.dtsi for another example [1].
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/qcom-msm8974.dtsi?h=v5.8-rc1#n1448
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next prev parent reply other threads:[~2020-06-18 7:18 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-09 13:13 [PATCH v4 00/37] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 01/37] clk: Export clk_hw_reparent() Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 02/37] clk: tegra: Remove Memory Controller lock Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 03/37] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 04/37] memory: tegra20-emc: Make driver modular Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 05/37] memory: tegra30-emc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 06/37] memory: tegra124-emc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 07/37] memory: tegra124-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 08/37] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 09/37] memory: tegra20-emc: Initialize MC timings Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 10/37] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko
2020-07-02 0:56 ` Chanwoo Choi
2020-07-02 1:35 ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 11/37] PM / devfreq: tegra30: " Dmitry Osipenko
2020-07-02 0:59 ` Chanwoo Choi
2020-07-02 1:20 ` Dmitry Osipenko
2020-07-02 1:34 ` Chanwoo Choi
2020-07-02 1:25 ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 12/37] PM / devfreq: tegra20: Use MC timings for building OPP table Dmitry Osipenko
2020-07-02 4:18 ` Chanwoo Choi
2020-07-02 5:07 ` Dmitry Osipenko
2020-07-02 5:30 ` Chanwoo Choi
2020-07-02 5:43 ` Dmitry Osipenko
2020-07-02 5:53 ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 13/37] PM / devfreq: tegra30: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 14/37] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() Dmitry Osipenko
2020-07-02 1:12 ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 15/37] PM / devfreq: tegra30: " Dmitry Osipenko
2020-07-02 1:12 ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 16/37] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval Dmitry Osipenko
2020-07-02 1:37 ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 17/37] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko
2020-07-02 2:10 ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 18/37] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 19/37] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 20/37] dt-bindings: memory: tegra30: mc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 21/37] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 22/37] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko
2020-06-17 21:37 ` Rob Herring
2020-06-17 21:44 ` Dmitry Osipenko [this message]
2020-06-17 21:48 ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 23/37] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 24/37] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 25/37] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 26/37] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 27/37] interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko
2020-07-01 17:10 ` Georgi Djakov
2020-07-01 23:41 ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 28/37] memory: tegra: Register as interconnect provider Dmitry Osipenko
2020-07-01 17:12 ` Georgi Djakov
2020-07-01 23:36 ` Dmitry Osipenko
2020-07-02 12:36 ` Georgi Djakov
2020-07-03 8:41 ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 29/37] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 30/37] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 31/37] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 32/37] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 33/37] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 34/37] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 35/37] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 36/37] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 37/37] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko
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