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From: Dmitry Osipenko <digetx@gmail.com>
To: Georgi Djakov <georgi.djakov@linaro.org>
Cc: devicetree@vger.kernel.org, "Mikko Perttunen" <cyndis@kapsi.fi>,
	dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org,
	"Stephen Boyd" <sboyd@kernel.org>,
	linux-kernel@vger.kernel.org,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Artur Świgoń" <a.swigon@samsung.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Chanwoo Choi" <cw00.choi@samsung.com>,
	"Kyungmin Park" <kyungmin.park@samsung.com>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"MyungJoo Ham" <myungjoo.ham@samsung.com>,
	linux-tegra@vger.kernel.org,
	"Peter De Schrijver" <pdeschrijver@nvidia.com>
Subject: Re: [PATCH v4 28/37] memory: tegra: Register as interconnect provider
Date: Thu, 2 Jul 2020 02:36:40 +0300	[thread overview]
Message-ID: <82d27a47-f189-6609-a584-c9ca1b35a76c@gmail.com> (raw)
In-Reply-To: <aec831a6-a7ad-6bcc-4e15-c44582f7568e@linaro.org>

01.07.2020 20:12, Georgi Djakov пишет:
> Hi Dmitry,
> 
> Thank you for updating the patches!

Hello, Georgi!

Thank you for the review!

> On 6/9/20 16:13, Dmitry Osipenko wrote:
>> Now memory controller is a memory interconnection provider. This allows us
>> to use interconnect API in order to change memory configuration.
>>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
>>  drivers/memory/tegra/Kconfig |   1 +
>>  drivers/memory/tegra/mc.c    | 114 +++++++++++++++++++++++++++++++++++
>>  drivers/memory/tegra/mc.h    |   8 +++
>>  include/soc/tegra/mc.h       |   3 +
>>  4 files changed, 126 insertions(+)
>>
>> diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
>> index 5bf75b316a2f..7055fdef2c32 100644
>> --- a/drivers/memory/tegra/Kconfig
>> +++ b/drivers/memory/tegra/Kconfig
>> @@ -3,6 +3,7 @@ config TEGRA_MC
>>  	bool "NVIDIA Tegra Memory Controller support"
>>  	default y
>>  	depends on ARCH_TEGRA
>> +	select INTERCONNECT
>>  	help
>>  	  This driver supports the Memory Controller (MC) hardware found on
>>  	  NVIDIA Tegra SoCs.
>> diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
>> index 772aa021b5f6..7ef7ac9e103e 100644
>> --- a/drivers/memory/tegra/mc.c
>> +++ b/drivers/memory/tegra/mc.c
>> @@ -594,6 +594,118 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
>>  	return IRQ_HANDLED;
>>  }
>>  
>> +static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst)
>> +{
>> +	return 0;
>> +}
>> +
>> +static int tegra_mc_icc_aggregate(struct icc_node *node,
>> +				  u32 tag, u32 avg_bw, u32 peak_bw,
>> +				  u32 *agg_avg, u32 *agg_peak)
>> +{
>> +	*agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX);
>> +	*agg_peak = max(*agg_peak, peak_bw);
>> +
>> +	return 0;
>> +}
>> +
>> +/*
>> + * Memory Controller (MC) has few Memory Clients that are issuing memory
>> + * bandwidth allocation requests to the MC interconnect provider. The MC
>> + * provider aggregates the requests and then sends the aggregated request
>> + * up to the External Memory Controller (EMC) interconnect provider which
>> + * re-configures hardware interface to External Memory (EMEM) in accordance
>> + * to the required bandwidth. Each MC interconnect node represents an
>> + * individual Memory Client.
>> + *
>> + * Memory interconnect topology:
>> + *
>> + *               +----+
>> + * +--------+    |    |
>> + * | TEXSRD +--->+    |
>> + * +--------+    |    |
>> + *               |    |    +-----+    +------+
>> + *    ...        | MC +--->+ EMC +--->+ EMEM |
>> + *               |    |    +-----+    +------+
>> + * +--------+    |    |
>> + * | DISP.. +--->+    |
>> + * +--------+    |    |
>> + *               +----+
>> + */
>> +static int tegra_mc_interconnect_setup(struct tegra_mc *mc)
>> +{
>> +	struct icc_onecell_data *data;
>> +	struct icc_node *node;
>> +	unsigned int num_nodes;
>> +	unsigned int i;
>> +	int err;
>> +
>> +	/* older device-trees don't have interconnect properties */
>> +	if (!of_find_property(mc->dev->of_node, "#interconnect-cells", NULL))
>> +		return 0;
>> +
>> +	num_nodes = mc->soc->num_clients;
>> +
>> +	data = devm_kzalloc(mc->dev, struct_size(data, nodes, num_nodes),
>> +			    GFP_KERNEL);
>> +	if (!data)
>> +		return -ENOMEM;
>> +
>> +	mc->provider.dev = mc->dev;
>> +	mc->provider.set = tegra_mc_icc_set;
> 
> Hmm, maybe the core should not require a set() implementation and we can
> just make it optional instead. Then the dummy function would not be needed.

Eventually this dummy function might become populated with a memory
latency allowness programming. I could add a comment into that function
in the next version, saying that it's to-be-done for now.

>> +	mc->provider.data = data;
>> +	mc->provider.xlate = of_icc_xlate_onecell;
>> +	mc->provider.aggregate = tegra_mc_icc_aggregate;
>> +
>> +	err = icc_provider_add(&mc->provider);
>> +	if (err)
>> +		goto err_msg;
> 
> Nit: I am planning to re-organize some of the existing drivers to call
> icc_provider_add() after the topology is populated. Could you please move
> this after the nodes are created and linked.

Are you planning to remove the provider's list-head initialization from
the icc_provider_add() [1] and move it to the individual provider
drivers, correct?

[1]
https://elixir.bootlin.com/linux/v5.8-rc3/source/drivers/interconnect/core.c#L977

If yes, then it should be easy to move the icc_provider_add() in the
case of this driver. Otherwise, please give some more clarification.

Please notice that the same "node" variable is used for both creation
and linking of the nodes to the provider here, making code nice and
clean. And thus, the provider's list-head should be initialized before
the linking.

...
> The rest looks good to me!

Thanks!
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  reply	other threads:[~2020-07-02  7:24 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-09 13:13 [PATCH v4 00/37] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 01/37] clk: Export clk_hw_reparent() Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 02/37] clk: tegra: Remove Memory Controller lock Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 03/37] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 04/37] memory: tegra20-emc: Make driver modular Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 05/37] memory: tegra30-emc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 06/37] memory: tegra124-emc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 07/37] memory: tegra124-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 08/37] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 09/37] memory: tegra20-emc: Initialize MC timings Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 10/37] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko
2020-07-02  0:56   ` Chanwoo Choi
2020-07-02  1:35     ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 11/37] PM / devfreq: tegra30: " Dmitry Osipenko
2020-07-02  0:59   ` Chanwoo Choi
2020-07-02  1:20     ` Dmitry Osipenko
2020-07-02  1:34       ` Chanwoo Choi
2020-07-02  1:25         ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 12/37] PM / devfreq: tegra20: Use MC timings for building OPP table Dmitry Osipenko
2020-07-02  4:18   ` Chanwoo Choi
2020-07-02  5:07     ` Dmitry Osipenko
2020-07-02  5:30       ` Chanwoo Choi
2020-07-02  5:43         ` Dmitry Osipenko
2020-07-02  5:53           ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 13/37] PM / devfreq: tegra30: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 14/37] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() Dmitry Osipenko
2020-07-02  1:12   ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 15/37] PM / devfreq: tegra30: " Dmitry Osipenko
2020-07-02  1:12   ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 16/37] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval Dmitry Osipenko
2020-07-02  1:37   ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 17/37] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko
2020-07-02  2:10   ` Chanwoo Choi
2020-06-09 13:13 ` [PATCH v4 18/37] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 19/37] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 20/37] dt-bindings: memory: tegra30: mc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 21/37] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 22/37] dt-bindings: host1x: Document new interconnect properties Dmitry Osipenko
2020-06-17 21:37   ` Rob Herring
2020-06-17 21:44     ` Dmitry Osipenko
2020-06-17 21:48       ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 23/37] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 24/37] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 25/37] ARM: tegra: Add interconnect properties to Tegra20 device-tree Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 26/37] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 27/37] interconnect: Relax requirement in of_icc_get_from_provider() Dmitry Osipenko
2020-07-01 17:10   ` Georgi Djakov
2020-07-01 23:41     ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 28/37] memory: tegra: Register as interconnect provider Dmitry Osipenko
2020-07-01 17:12   ` Georgi Djakov
2020-07-01 23:36     ` Dmitry Osipenko [this message]
2020-07-02 12:36       ` Georgi Djakov
2020-07-03  8:41         ` Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 29/37] memory: tegra20-emc: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 30/37] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 31/37] memory: tegra20-emc: Register as interconnect provider Dmitry Osipenko
2020-06-09 13:13 ` [PATCH v4 32/37] memory: tegra20-emc: Create tegra20-devfreq device Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 33/37] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 34/37] memory: tegra30-emc: Register as interconnect provider Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 35/37] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 36/37] drm/tegra: dc: Tune up high priority request controls for Tegra20 Dmitry Osipenko
2020-06-09 13:14 ` [PATCH v4 37/37] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko

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