[PATCH v3] pci: Handle 5-bit and 8-bit tag field

[PATCH v3] pci: Handle 5-bit and 8-bit tag field

[Pierre Moreau]

If the hardware supports extended tag field (8-bit ones), then enabled it. This
is usually done by the VBIOS, but not on some MBPs (see fdo#86537).
In case extended tag field is not supported, 5-bit tag field is used which
limits the possible values to 32. Apparently bits 7:0 of 0x8841c stores some
number of outstanding requests, so cap it to 32 if extended tag is unsupported.

Fixes: fdo#86537

v2: Restrict changes to chipsets >= 0x84
v3:
  * Add nvkm_pci_mask to pci.h
  * Mask bit 8 before setting it

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
---
 drm/nouveau/include/nvkm/subdev/pci.h |  1 +
 drm/nouveau/nvkm/subdev/pci/base.c    | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/drm/nouveau/include/nvkm/subdev/pci.h b/drm/nouveau/include/nvkm/subdev/pci.h
index 5b3c054..774ca66 100644
--- a/drm/nouveau/include/nvkm/subdev/pci.h
+++ b/drm/nouveau/include/nvkm/subdev/pci.h
@@ -24,6 +24,7 @@ struct nvkm_pci {
 u32 nvkm_pci_rd32(struct nvkm_pci *, u16 addr);
 void nvkm_pci_wr08(struct nvkm_pci *, u16 addr, u8 data);
 void nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data);
+u32 nvkm_pci_mask(struct nvkm_pci *, u16 addr, u32 mask, u32 add);
 void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow);
 
 int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
diff --git a/drm/nouveau/nvkm/subdev/pci/base.c b/drm/nouveau/nvkm/subdev/pci/base.c
index d1c148e..cb2835b 100644
--- a/drm/nouveau/nvkm/subdev/pci/base.c
+++ b/drm/nouveau/nvkm/subdev/pci/base.c
@@ -46,6 +46,14 @@ nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data)
 	pci->func->wr32(pci, addr, data);
 }
 
+u32
+nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32 add)
+{
+	u32 data = pci->func->rd32(pci, addr);
+	pci->func->wr32(pci, addr, (data & ~mask) | add);
+	return data;
+}
+
 void
 nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow)
 {
@@ -115,6 +123,23 @@ nvkm_pci_init(struct nvkm_subdev *subdev)
 	if (ret)
 		return ret;
 
+	if (pci_is_pcie(pdev) && subdev->device->chipset >= 0x84) {
+		/* Tag field is 8-bit long, regardless of EXT_TAG.
+		 * However, if EXT_TAG is disabled, only the lower 5 bits of the tag
+		 * field should be used, limiting the number of request to 32.
+		 *
+		 * Apparently, 0x041c stores some limit on the number of requests
+		 * possible, so if EXT_TAG is disabled, limit that requests number to
+		 * 32
+		 *
+		 * Fixes fdo#86537
+		 */
+		if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020)
+			nvkm_pci_mask(pci, 0x0080, 0x00000100, 0x00000100);
+		else
+			nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000);
+	}
+
 	pci->irq = pdev->irq;
 	return ret;
 }
-- 
2.5.2

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Re: [PATCH v3] pci: Handle 5-bit and 8-bit tag field

[Pierre Moreau]

----- Mail original -----
> If the hardware supports extended tag field (8-bit ones), then
> enabled it. This
> is usually done by the VBIOS, but not on some MBPs (see fdo#86537).
> In case extended tag field is not supported, 5-bit tag field is used
> which
> limits the possible values to 32. Apparently bits 7:0 of 0x8841c
> stores some
> number of outstanding requests, so cap it to 32 if extended tag is
> unsupported.
> 
> Fixes: fdo#86537
> 
> v2: Restrict changes to chipsets >= 0x84
> v3:
>   * Add nvkm_pci_mask to pci.h
>   * Mask bit 8 before setting it
> 
> Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>

Tested-by: Karol Herbst <freedesktop@karolherbst.de>

> ---
>  drm/nouveau/include/nvkm/subdev/pci.h |  1 +
>  drm/nouveau/nvkm/subdev/pci/base.c    | 25 +++++++++++++++++++++++++
>  2 files changed, 26 insertions(+)
> 
> diff --git a/drm/nouveau/include/nvkm/subdev/pci.h
> b/drm/nouveau/include/nvkm/subdev/pci.h
> index 5b3c054..774ca66 100644
> --- a/drm/nouveau/include/nvkm/subdev/pci.h
> +++ b/drm/nouveau/include/nvkm/subdev/pci.h
> @@ -24,6 +24,7 @@ struct nvkm_pci {
>  u32 nvkm_pci_rd32(struct nvkm_pci *, u16 addr);
>  void nvkm_pci_wr08(struct nvkm_pci *, u16 addr, u8 data);
>  void nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data);
> +u32 nvkm_pci_mask(struct nvkm_pci *, u16 addr, u32 mask, u32 add);
>  void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow);
>  
>  int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
> diff --git a/drm/nouveau/nvkm/subdev/pci/base.c
> b/drm/nouveau/nvkm/subdev/pci/base.c
> index d1c148e..cb2835b 100644
> --- a/drm/nouveau/nvkm/subdev/pci/base.c
> +++ b/drm/nouveau/nvkm/subdev/pci/base.c
> @@ -46,6 +46,14 @@ nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32
> data)
>  	pci->func->wr32(pci, addr, data);
>  }
>  
> +u32
> +nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32 add)
> +{
> +	u32 data = pci->func->rd32(pci, addr);
> +	pci->func->wr32(pci, addr, (data & ~mask) | add);
> +	return data;
> +}
> +
>  void
>  nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow)
>  {
> @@ -115,6 +123,23 @@ nvkm_pci_init(struct nvkm_subdev *subdev)
>  	if (ret)
>  		return ret;
>  
> +	if (pci_is_pcie(pdev) && subdev->device->chipset >= 0x84) {
> +		/* Tag field is 8-bit long, regardless of EXT_TAG.
> +		 * However, if EXT_TAG is disabled, only the lower 5 bits of the
> tag
> +		 * field should be used, limiting the number of request to 32.
> +		 *
> +		 * Apparently, 0x041c stores some limit on the number of requests
> +		 * possible, so if EXT_TAG is disabled, limit that requests number
> to
> +		 * 32
> +		 *
> +		 * Fixes fdo#86537
> +		 */
> +		if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020)
> +			nvkm_pci_mask(pci, 0x0080, 0x00000100, 0x00000100);
> +		else
> +			nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000);
> +	}
> +
>  	pci->irq = pdev->irq;
>  	return ret;
>  }
> --
> 2.5.2
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
> 
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Re: [PATCH v3] pci: Handle 5-bit and 8-bit tag field

[Ben Skeggs]

On 09/17/2015 06:26 AM, Pierre Moreau wrote:
> If the hardware supports extended tag field (8-bit ones), then
> enabled it. This is usually done by the VBIOS, but not on some MBPs
> (see fdo#86537). In case extended tag field is not supported, 5-bit
> tag field is used which limits the possible values to 32.
> Apparently bits 7:0 of 0x8841c stores some number of outstanding
> requests, so cap it to 32 if extended tag is unsupported.
> 
> Fixes: fdo#86537
> 
> v2: Restrict changes to chipsets >= 0x84 v3: * Add nvkm_pci_mask to
> pci.h * Mask bit 8 before setting it
> 
> Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> --- 
> drm/nouveau/include/nvkm/subdev/pci.h |  1 + 
> drm/nouveau/nvkm/subdev/pci/base.c    | 25
> +++++++++++++++++++++++++ 2 files changed, 26 insertions(+)
> 
> diff --git a/drm/nouveau/include/nvkm/subdev/pci.h
> b/drm/nouveau/include/nvkm/subdev/pci.h index 5b3c054..774ca66
> 100644 --- a/drm/nouveau/include/nvkm/subdev/pci.h +++
> b/drm/nouveau/include/nvkm/subdev/pci.h @@ -24,6 +24,7 @@ struct
> nvkm_pci { u32 nvkm_pci_rd32(struct nvkm_pci *, u16 addr); void
> nvkm_pci_wr08(struct nvkm_pci *, u16 addr, u8 data); void
> nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data); +u32
> nvkm_pci_mask(struct nvkm_pci *, u16 addr, u32 mask, u32 add); void
> nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow);
> 
> int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **); 
> diff --git a/drm/nouveau/nvkm/subdev/pci/base.c
> b/drm/nouveau/nvkm/subdev/pci/base.c index d1c148e..cb2835b 100644 
> --- a/drm/nouveau/nvkm/subdev/pci/base.c +++
> b/drm/nouveau/nvkm/subdev/pci/base.c @@ -46,6 +46,14 @@
> nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data) 
> pci->func->wr32(pci, addr, data); }
> 
> +u32 +nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32
> add) +{ +	u32 data = pci->func->rd32(pci, addr); +
> pci->func->wr32(pci, addr, (data & ~mask) | add); +	return data; 
> +} + void nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow) { 
> @@ -115,6 +123,23 @@ nvkm_pci_init(struct nvkm_subdev *subdev) if
> (ret) return ret;
> 
> +	if (pci_is_pcie(pdev) && subdev->device->chipset >= 0x84) { +		/*
> Tag field is 8-bit long, regardless of EXT_TAG. +		 * However, if
> EXT_TAG is disabled, only the lower 5 bits of the tag +		 * field
> should be used, limiting the number of request to 32. +		 * +		 *
> Apparently, 0x041c stores some limit on the number of requests +
> * possible, so if EXT_TAG is disabled, limit that requests number
> to +		 * 32 +		 * +		 * Fixes fdo#86537 +		 */ +		if
> (nvkm_pci_rd32(pci, 0x007c) & 0x00000020) +			nvkm_pci_mask(pci,
> 0x0080, 0x00000100, 0x00000100); +		else +			nvkm_pci_mask(pci,
> 0x041c, 0x00000060, 0x00000000); +	}
Please introduce a .init() to nvkm_pci_func(), and implement a g84.c
that handles this (gf100.c can use g84_pci_init() from there).

The check for PCI-E is redundant too, all these boards are PCI-E.

Other than the above nit-picking, looks fine.

Thanks,
Ben.

> + pci->irq = pdev->irq; return ret; }
> 

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