* [PATCH] drm/i915/guc: Update guc shim control programming on newer platforms
@ 2022-01-20 22:24 Daniele Ceraolo Spurio
2022-01-25 18:36 ` Belgaumkar, Vinay
0 siblings, 1 reply; 2+ messages in thread
From: Daniele Ceraolo Spurio @ 2022-01-20 22:24 UTC (permalink / raw)
To: intel-gfx
Cc: Stuart Summers, Vinay Belgaumkar, Daniele Ceraolo Spurio, dri-devel
Starting from xehpsdv, bit 0 of of the GuC shim control register has
been repurposed, while bit 2 is now reserved, so we need to avoid
setting those for their old meaning on newer platforms.
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index f773e7f35bc1a..40f7d4779c9ec 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -15,13 +15,15 @@
static void guc_prepare_xfer(struct intel_uncore *uncore)
{
- u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
- GUC_ENABLE_READ_CACHE_LOGIC |
- GUC_ENABLE_MIA_CACHING |
+ u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
GUC_ENABLE_MIA_CLOCK_GATING;
+ if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
+ shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
+ GUC_ENABLE_MIA_CACHING;
+
/* Must program this register before loading the ucode with DMA */
intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/i915/guc: Update guc shim control programming on newer platforms
2022-01-20 22:24 [PATCH] drm/i915/guc: Update guc shim control programming on newer platforms Daniele Ceraolo Spurio
@ 2022-01-25 18:36 ` Belgaumkar, Vinay
0 siblings, 0 replies; 2+ messages in thread
From: Belgaumkar, Vinay @ 2022-01-25 18:36 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Stuart Summers, dri-devel
On 1/20/2022 2:24 PM, Daniele Ceraolo Spurio wrote:
> Starting from xehpsdv, bit 0 of of the GuC shim control register has
> been repurposed, while bit 2 is now reserved, so we need to avoid
> setting those for their old meaning on newer platforms.
>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index f773e7f35bc1a..40f7d4779c9ec 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -15,13 +15,15 @@
>
> static void guc_prepare_xfer(struct intel_uncore *uncore)
> {
> - u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
> - GUC_ENABLE_READ_CACHE_LOGIC |
> - GUC_ENABLE_MIA_CACHING |
> + u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
> GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
> GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
> GUC_ENABLE_MIA_CLOCK_GATING;
>
> + if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
> + shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
> + GUC_ENABLE_MIA_CACHING;
> +
LGTM.
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> /* Must program this register before loading the ucode with DMA */
> intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-01-25 18:37 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-20 22:24 [PATCH] drm/i915/guc: Update guc shim control programming on newer platforms Daniele Ceraolo Spurio
2022-01-25 18:36 ` Belgaumkar, Vinay
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).