From: Giulio Benetti <giulio.benetti@benettiengineering.com>
To: Marjan Pascolo <marjan.pascolo@trexom.it>,
Maxime Ripard <maxime@cerno.tech>
Cc: Jernej Skrabec <jernej.skrabec@siol.net>,
airlied@linux.ie, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, wens@csie.org,
treding@nvidia.com,
Giulio Benetti <giulio.benetti@micronovasrl.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling
Date: Fri, 8 Jan 2021 15:46:15 +0100 [thread overview]
Message-ID: <88789919-6f46-55f2-d432-d83c91b6e73f@benettiengineering.com> (raw)
In-Reply-To: <00f21d15-7a88-2d01-dd48-dc49e9295e34@trexom.it>
Hi Marjan,
On 1/8/21 10:32 AM, Marjan Pascolo wrote:
> Hi,
please don't top post, answer in-line as we do, and please use
plain-test instead of HTML. These are the standards in Mailing Lists(ML).
> Quote "
>
> I'm not really sure why we need the first patch of this series here?
> That patch only seem to undo what you did in patch 1
>
> "
Already answered to Maxime
>
> And another question (probably could be a stupid one):
>
> in "/[PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling/" I
> see you deleted:
>
> - clk_set_phase(tcon->dclk, 0);
>
> Is safe to assume that phase register will be always set to 0?
We always assumed it is set to 0 by default.
>
> Or maybe will be safer manually set it to 0 in every condition to avoid
> surprises (dirt values due to previous condition)?
That would be a good idea, so something like this:
'''
int phase = 0;
if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
phase = 240;
clk_set_phase(tcon->dclk, phase);
'''
because now DRM_BUS_FLAG_PIXDATA_SAMPLE_ and DRM_BUS_FLAG_PIXDATA_DRIVE_
are exclusive, while before not.
But then if bit 26 solution works everything gets easier.
Best Regards
Giulio
>
> Marjan
>
> Il 08/01/2021 10:23, Maxime Ripard ha scritto:
>> Hi,
>>
>> Thanks for those patches
>>
>> On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote:
>>> From: Giulio Benetti<giulio.benetti@micronovasrl.com>
>>>
>>> It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is
>>> dedicated to invert DCLK polarity and this makes thing really easier than
>>> before. So let's handle DCLK polarity by adding
>>> SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to
>>> bus_flags the same way is done for all the other signals.
>>>
>>> Cc: Maxime Ripard<maxime@cerno.tech>
>> Suggested-by would be nice here :)
>>
>>> Signed-off-by: Giulio Benetti<giulio.benetti@micronovasrl.com>
>>> ---
>>> drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +-------------------
>>> drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
>>> 2 files changed, 2 insertions(+), 19 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
>>> index 52598bb0fb0b..30171ccd87e5 100644
>>> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
>>> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
>>> @@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
>>> if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
>>> val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
>>>
>>> - /*
>>> - * On A20 and similar SoCs, the only way to achieve Positive Edge
>>> - * (Rising Edge), is setting dclk clock phase to 2/3(240°).
>>> - * By default TCON works in Negative Edge(Falling Edge),
>>> - * this is why phase is set to 0 in that case.
>>> - * Unfortunately there's no way to logically invert dclk through
>>> - * IO_POL register.
>>> - * The only acceptable way to work, triple checked with scope,
>>> - * is using clock phase set to 0° for Negative Edge and set to 240°
>>> - * for Positive Edge.
>>> - * On A33 and similar SoCs there would be a 90° phase option,
>>> - * but it divides also dclk by 2.
>>> - * Following code is a way to avoid quirks all around TCON
>>> - * and DOTCLOCK drivers.
>>> - */
>>> if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
>>> - clk_set_phase(tcon->dclk, 0);
>>> -
>>> - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
>>> - clk_set_phase(tcon->dclk, 240);
>>> + val |= SUN4I_TCON0_IO_POL_DCLK_POSITIVE;
>> I'm not really sure why we need the first patch of this series here?
>> That patch only seem to undo what you did in patch 1
>>
>> Maxime
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next prev parent reply other threads:[~2021-01-09 11:47 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-06 19:27 [PATCH 0/2] drm/sun4i: fix DCLK and improve its handling Giulio Benetti
2021-01-06 19:27 ` [PATCH 1/2] drm/sun4i: tcon: fix inverted DCLK polarity Giulio Benetti
2021-01-06 21:00 ` Jernej Škrabec
2021-01-07 2:30 ` [PATCH v2 0/2] drm/sun4i: fix DCLK and improve its handling Giulio Benetti
2021-01-07 2:30 ` [PATCH v2 1/2] drm/sun4i: tcon: fix inverted DCLK polarity Giulio Benetti
2021-01-07 2:30 ` [PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling Giulio Benetti
2021-01-08 9:23 ` Maxime Ripard
2021-01-08 9:32 ` Marjan Pascolo
2021-01-08 14:46 ` Giulio Benetti [this message]
2021-01-08 14:34 ` Giulio Benetti
2021-01-11 17:20 ` Maxime Ripard
2021-01-11 17:37 ` Giulio Benetti
2021-01-11 17:46 ` [PATCH v3] drm/sun4i: tcon: fix inverted DCLK polarity Giulio Benetti
2021-01-13 9:42 ` Maxime Ripard
2021-01-13 10:47 ` [PATCH v4] " Giulio Benetti
2021-01-13 16:05 ` [PATCH v5] " Giulio Benetti
2021-01-14 1:32 ` kernel test robot
2021-01-14 7:58 ` Marjan Pascolo
2021-01-14 8:12 ` Giulio Benetti
2021-01-14 8:17 ` [PATCH v6] " Giulio Benetti
2021-01-14 11:40 ` Marjan Pascolo
2021-01-14 11:42 ` Maxime Ripard
2021-02-10 16:22 ` [PATCH] pinctrl/sunxi: adding input-debounce-ns property Marjan Pascolo
2021-02-17 11:03 ` Maxime Ripard
2021-02-26 12:53 ` Marjan Pascolo
2021-03-04 15:51 ` Maxime Ripard
2021-01-13 10:48 ` [PATCH v3] drm/sun4i: tcon: fix inverted DCLK polarity Giulio Benetti
2021-01-06 19:28 ` [PATCH 2/2] drm/sun4i: tcon: improve DCLK polarity handling Giulio Benetti
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