[PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi

[PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi

[David Francis]

This patchset enables Display Stream Compression (DSC) on DP
connectors on Navi ASICs, both SST and DSC.

8k60 and 4k144 support requires ODM combine, an AMD internal
feature that may be a bit buggy right now.

Patches 1 through 5 enable DSC for SST. Most of the work was
already done in the Navi promotion patches; this just hooks
it up to the atomic interface. The first two reverts are of temporary
changes to block off DSC. The third is of a commit that was
accidentally promoted twice. The fourth and last revert fixes a
potential issue with ODM combine.

Patches 6, 7 and 8 are fixes for bugs that would be exposed by
MST DSC. Patches 6 and 7 add and use a new DRM helper for MST
calculations. Patch 8 fixes a silly use-uninitialized

Patches 9, 10, and 11 are small DRM changes required for DSC MST:
FEC, a new bit in the standard; MST DPCD from drivers; and
a previously uninitialized variable.

Patches 12 through 16 are the DSC MST policy itself. Patch 12
adds DSC aux access helpers to DRM, and patches 13 and 14 make
use of those helpers. Patch 15 deals with dividing bandwidth
fairly between multiple streams, and patch 16 ensures
that MST CRTC that may change DSC config are reprogrammed

v2: Updating patches 6 and 14 in respoinse to Nick's feedback
v3: Add return value to patch 6 and split it (now patches 6 & 7)
    New patch 10 adding MST DPCD read/write support
    Minor fix (num_ports--) to patch 11
    Add DRM helpers (patch 12)

David Francis (16):
  Revert "drm/amd/display: skip dsc config for navi10 bring up"
  Revert "drm/amd/display: navi10 bring up skip dsc encoder config"
  Revert "drm/amd/display: add global master update lock for DCN2"
  Revert "drm/amd/display: Fix underscan not using proper scaling"
  drm/amd/display: Enable SST DSC in DM
  drm/dp-mst: Add PBN calculation for DSC modes
  drm/amd/display: Use correct helpers to compute timeslots
  drm/amd/display: Initialize DSC PPS variables to 0
  drm/dp-mst: Parse FEC capability on MST ports
  drm/dp-mst: Add MST support to DP DPCD R/W functions
  drm/dp-mst: Fill branch->num_ports
  drm/dp-mst: Add helpers for querying and enabling MST DSC
  drm/amd/display: Validate DSC caps on MST endpoints
  drm/amd/display: Write DSC enable to MST DPCD
  drm/amd/display: MST DSC compute fair share
  drm/amd/display: Trigger modesets on MST DSC connectors

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 113 ++++-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  33 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 402 +++++++++++++++++-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   4 +
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  12 +-
 .../drm/amd/display/dc/core/dc_link_hwss.c    |   3 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |   3 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   4 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  72 +---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   3 -
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
 .../display/dc/dcn20/dcn20_stream_encoder.c   |   8 -
 .../amd/display/dc/inc/hw/timing_generator.h  |   2 -
 drivers/gpu/drm/drm_dp_aux_dev.c              |  12 +-
 drivers/gpu/drm/drm_dp_helper.c               |  10 +-
 drivers/gpu/drm/drm_dp_mst_topology.c         | 240 +++++++++++
 include/drm/drm_dp_mst_helper.h               |   8 +-
 18 files changed, 806 insertions(+), 131 deletions(-)

-- 
2.17.1

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[PATCH v3 01/16] Revert "drm/amd/display: skip dsc config for navi10 bring up"

[David Francis]

This reverts commit 55ad81f3510ec1a1c19e6a4d8a6319812d07d256.

optc dsc config was causing warnings due to missing register
definitions. With the registers restored, the function can
be re-enabled

The reverted commit also disabled sanity checks and dsc
power gating. The sanity check warnings are not associated
with dsc, and power gating on dsc still has an issue on
non-dsc monitors where the dsc hardware block is never init
and so cannot respond to power gating requests. Therefore,
those are left as is

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index aedf9de1c947..99070e93020b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -191,15 +191,6 @@ void optc2_set_dsc_config(struct timing_generator *optc,
 					uint32_t dsc_slice_width)
 {
 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
-	uint32_t data_format = 0;
-	/* skip if dsc mode is not changed */
-	data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL));
-
-	data_format = data_format & 0x30; /* bit5:4 */
-	data_format = data_format >> 4;
-
-	if (data_format == dsc_mode)
-		return;
 
 	REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
 		OPTC_DSC_MODE, dsc_mode);
-- 
2.17.1

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[PATCH v3 02/16] Revert "drm/amd/display: navi10 bring up skip dsc encoder config"

[David Francis]

This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c.

Re-enable enc2_dp_set_dsc_config. This function caused warnings
due to missing register definitions. With the registers added,
this now works

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c   | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 6d54942ab98b..a4e67286cdad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -277,14 +277,6 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
 					uint32_t dsc_slice_width)
 {
 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
-	uint32_t dsc_value = 0;
-
-	dsc_value = REG_READ(DP_DSC_CNTL);
-
-	/* dsc disable skip */
-	if ((dsc_value & 0x3) == 0x0)
-		return;
-
 
 	REG_UPDATE_2(DP_DSC_CNTL,
 			DP_DSC_MODE, dsc_mode,
-- 
2.17.1

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[PATCH v3 03/16] Revert "drm/amd/display: add global master update lock for DCN2"

[David Francis]

This reverts commit 55a6f5bbcf00a49565946c0a9b8c716313dc6c05.

This commit was accidentally promoted twice

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  4 --
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 63 +------------------
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |  3 -
 .../amd/display/dc/inc/hw/timing_generator.h  |  2 -
 4 files changed, 1 insertion(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fa8a73f6c8e3..e146d1d8d45e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -575,10 +575,6 @@ enum dc_status dcn20_enable_stream_timing(
 			pipe_ctx->stream->signal,
 			true);
 
-	if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
-		pipe_ctx->stream_res.tg->funcs->setup_global_lock(
-				pipe_ctx->stream_res.tg);
-
 	if (odm_pipe)
 		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 				odm_pipe->stream_res.opp,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 99070e93020b..2137e2be2140 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -333,65 +333,6 @@ void optc2_triplebuffer_unlock(struct timing_generator *optc)
 
 }
 
-
-void optc2_setup_global_lock(struct timing_generator *optc)
-{
-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
-	uint32_t v_blank_start = 0;
-	uint32_t h_blank_start = 0, h_total = 0;
-
-	REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1);
-
-	REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20);
-
-	REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
-
-	REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
-
-	REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &h_total);
-	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
-			MASTER_UPDATE_LOCK_DB_X,
-			h_blank_start - 200 - 1,
-			MASTER_UPDATE_LOCK_DB_Y,
-			v_blank_start - 1);
-}
-
-void optc2_lock_global(struct timing_generator *optc)
-{
-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
-
-	REG_SET(OTG_GLOBAL_CONTROL0, 0,
-			OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-			OTG_MASTER_UPDATE_LOCK, 1);
-
-	/* Should be fast, status does not update on maximus */
-	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-				UPDATE_LOCK_STATUS, 1,
-				1, 10);
-}
-
-void optc2_lock(struct timing_generator *optc)
-{
-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
-
-	REG_SET(OTG_GLOBAL_CONTROL0, 0,
-			OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-			OTG_MASTER_UPDATE_LOCK, 1);
-
-	/* Should be fast, status does not update on maximus */
-	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-				UPDATE_LOCK_STATUS, 1,
-				1, 10);
-}
-
 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
 {
 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -486,10 +427,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
 		.triplebuffer_lock = optc2_triplebuffer_lock,
 		.triplebuffer_unlock = optc2_triplebuffer_unlock,
 		.disable_reset_trigger = optc1_disable_reset_trigger,
-		.lock = optc2_lock,
+		.lock = optc1_lock,
 		.unlock = optc1_unlock,
-		.lock_global = optc2_lock_global,
-		.setup_global_lock = optc2_setup_global_lock,
 		.lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
 		.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
 		.enable_optc_clock = optc1_enable_optc_clock,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index 47cb4de1564c..32a58431fd09 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -106,9 +106,6 @@ void optc2_get_optc_source(struct timing_generator *optc,
 
 void optc2_triplebuffer_lock(struct timing_generator *optc);
 void optc2_triplebuffer_unlock(struct timing_generator *optc);
-void optc2_lock(struct timing_generator *optc);
-void optc2_lock_global(struct timing_generator *optc);
-void optc2_setup_global_lock(struct timing_generator *optc);
 void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
 void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
 void optc2_program_manual_trigger(struct timing_generator *optc);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index f607ef24c766..e0713d6d6c8d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -189,10 +189,8 @@ struct timing_generator_funcs {
 	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
 	void (*setup_global_swap_lock)(struct timing_generator *tg,
 							const struct dcp_gsl_params *gsl_params);
-	void (*setup_global_lock)(struct timing_generator *tg);
 	void (*unlock)(struct timing_generator *tg);
 	void (*lock)(struct timing_generator *tg);
-	void (*lock_global)(struct timing_generator *tg);
 	void (*lock_doublebuffer_disable)(struct timing_generator *tg);
 	void (*lock_doublebuffer_enable)(struct timing_generator *tg);
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
-- 
2.17.1

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[PATCH v3 04/16] Revert "drm/amd/display: Fix underscan not using proper scaling"

[David Francis]

This reverts commit 80e80ec817f161560b4159608fb41bd289abede3.

This commit fixed an issue with underscan commits not updating all
needed timing values, but through various refactors it is no longer
necessary. It causes corruption on odm combine by
overwriting the halved h_active in the stream timing

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 77ac7f707ec5..1189e320062b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2127,7 +2127,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
 	enum surface_update_type update_type;
 	struct dc_state *context;
 	struct dc_context *dc_ctx = dc->ctx;
-	int i, j;
+	int i;
 
 	stream_status = dc_stream_get_status(stream);
 	context = dc->current_state;
@@ -2165,16 +2165,6 @@ void dc_commit_updates_for_stream(struct dc *dc,
 
 		copy_surface_update_to_plane(surface, &srf_updates[i]);
 
-		if (update_type >= UPDATE_TYPE_MED) {
-			for (j = 0; j < dc->res_pool->pipe_count; j++) {
-				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-
-				if (pipe_ctx->plane_state != surface)
-					continue;
-
-				resource_build_scaling_params(pipe_ctx);
-			}
-		}
 	}
 
 	copy_stream_update_to_stream(dc, context, stream, stream_update);
-- 
2.17.1

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[PATCH v3 05/16] drm/amd/display: Enable SST DSC in DM

[David Francis]

In create_stream_for_sink, check for SST DP connectors

Parse DSC caps to DC format, then, if DSC is supported,
compute the config

DSC hardware will be programmed by dc_commit_state

Tested-by: Mikita Lipski <Mikita.Lipski@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++++++++++++-------
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  4 ++-
 2 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 911fe78b47c1..84249057e181 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3576,6 +3576,10 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 	bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
 	int mode_refresh;
 	int preferred_refresh = 0;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+	struct dsc_dec_dpcd_caps dsc_caps;
+	uint32_t link_bandwidth_kbps;
+#endif
 
 	struct dc_sink *sink = NULL;
 	if (aconnector == NULL) {
@@ -3648,17 +3652,23 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 			&mode, &aconnector->base, con_state, old_stream);
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-	/* stream->timing.flags.DSC = 0; */
-        /*  */
-	/* if (aconnector->dc_link && */
-	/* 		aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */
-	/* 		aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */
-	/* 	if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */
-	/* 			&aconnector->dc_link->dpcd_caps.dsc_caps, */
-	/* 			dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */
-	/* 			&stream->timing, */
-	/* 			&stream->timing.dsc_cfg)) */
-	/* 		stream->timing.flags.DSC = 1; */
+	stream->timing.flags.DSC = 0;
+
+	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
+		dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
+				      &dsc_caps);
+		link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
+							     dc_link_get_link_cap(aconnector->dc_link));
+
+		if (dsc_caps.is_dsc_supported)
+			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
+						  &dsc_caps,
+						  link_bandwidth_kbps,
+						  &stream->timing,
+						  &stream->timing.dsc_cfg))
+				stream->timing.flags.DSC = 1;
+	}
 #endif
 
 	update_stream_scaling_settings(&mode, dm_state, stream);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 7cf0573ab25f..5f2c315b18ba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -549,7 +549,9 @@ bool dm_helpers_dp_write_dsc_enable(
 		bool enable
 )
 {
-	return false;
+	uint8_t enable_dsc = enable ? 1 : 0;
+
+	return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
 }
 #endif
 
-- 
2.17.1

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[PATCH v3 06/16] drm/dp-mst: Add PBN calculation for DSC modes

[David Francis]

With DSC, bpp can be a multiple of 1/16, so
drm_dp_calc_pbn_mode is insufficient.

Add drm_dp_calc_pbn_mode_dsc, a function which is
the same as drm_dp_calc_pbn_mode, but the bpp is
in units of 1/16.

Cc: Lyude Paul <lyude@redhat.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 43 +++++++++++++++++++++++++++
 include/drm/drm_dp_mst_helper.h       |  2 +-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 398e7314ea8b..34a5bdfc598b 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3588,6 +3588,49 @@ static int test_calc_pbn_mode(void)
 	return 0;
 }
 
+/**
+ * drm_dp_calc_pbn_mode_dsc() - Calculate the PBN for a mode with DSC enabled.
+ * @clock: dot clock for the mode
+ * @dsc_bpp: dsc bits per pixel x16 (e.g. dsc_bpp = 136 is 8.5 bpp)
+ *
+ * This uses the formula in the spec to calculate the PBN value for a mode,
+ * given that the mode is using DSC
+ * Returns:
+ * PBN required for this mode
+ */
+int drm_dp_calc_pbn_mode_dsc(int clock, int dsc_bpp)
+{
+	u64 kbps;
+	s64 peak_kbps;
+	u32 numerator;
+	u32 denominator;
+
+	kbps = clock * dsc_bpp;
+
+	/*
+	 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+	 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
+	 * common multiplier to render an integer PBN for all link rate/lane
+	 * counts combinations
+	 * calculate
+	 * peak_kbps *= (1/16) bppx16 to bpp
+	 * peak_kbps *= (1006/1000)
+	 * peak_kbps *= (64/54)
+	 * peak_kbps *= 8    convert to bytes
+	 *
+	 * Divide numerator and denominator by 16 to avoid overflow
+	 */
+
+	numerator = 64 * 1006 / 16;
+	denominator = 54 * 8 * 1000 * 1000;
+
+	kbps *= numerator;
+	peak_kbps = drm_fixp_from_fraction(kbps, denominator);
+
+	return drm_fixp2int_ceil(peak_kbps);
+}
+EXPORT_SYMBOL(drm_dp_calc_pbn_mode_dsc);
+
 /* we want to kick the TX after we've ack the up/down IRQs. */
 static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr)
 {
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 2ba6253ea6d3..ddb518f2157a 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -611,7 +611,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_
 
 
 int drm_dp_calc_pbn_mode(int clock, int bpp);
-
+int drm_dp_calc_pbn_mode_dsc(int clock, int dsc_bpp);
 
 bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr,
 			      struct drm_dp_mst_port *port, int pbn, int slots);
-- 
2.17.1

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[PATCH v3 07/16] drm/amd/display: Use correct helpers to compute timeslots

[David Francis]

We were using drm helpers to convert a timing into its
bandwidth, its bandwidth into pbn, and its pbn into timeslots

These helpers
-Did not take DSC timings into account
-Used the link rate and lane count of the link's aux device,
which are not the same as the link's current cap
-Did not take FEC into account (FEC reduces the PBN per timeslot)

For converting timing into PBN, use the new function
drm_dp_calc_pbn_mode_dsc that handles the DSC case

For converting PBN into time slots, amdgpu doesn't use the
'correct' atomic method (drm_dp_atomic_find_vcpi_slots), so
don't add a new helper to cover our approach. Use the same
means of calculating pbn per time slot as the DSC code.

Cc: Jerry Zuo <Jerry.Zuo@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c   | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 5f2c315b18ba..716d6577cdbd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
 	int slots = 0;
 	bool ret;
 	int clock;
-	int bpp = 0;
 	int pbn = 0;
+	int pbn_per_timeslot, bpp = 0;
 
 	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 
@@ -234,11 +234,18 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
 
 		bpp = bpp * 3;
 
-		/* TODO need to know link rate */
-
-		pbn = drm_dp_calc_pbn_mode(clock, bpp);
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+		if (stream->timing.flags.DSC)
+			pbn = drm_dp_calc_pbn_mode_dsc(clock,
+					stream->timing.dsc_cfg.bits_per_pixel);
+		else
+#endif
+			pbn = drm_dp_calc_pbn_mode(clock, bpp);
 
-		slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
+		/* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */
+		pbn_per_timeslot = dc_link_bandwidth_kbps(
+				stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54);
+		slots = DIV_ROUND_UP(pbn, pbn_per_timeslot);
 		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
 
 		if (!ret)
-- 
2.17.1

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[PATCH v3 08/16] drm/amd/display: Initialize DSC PPS variables to 0

[David Francis]

For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.

memset to 0 to avoid this

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c   | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 35c5467e60e8..619ac48edd05 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -491,6 +491,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
 		struct dsc_config dsc_cfg;
 		uint8_t dsc_packed_pps[128];
 
+		memset(&dsc_cfg, 0, sizeof(dsc_cfg));
+		memset(dsc_packed_pps, 0, 128);
+
 		/* Enable DSC hw block */
 		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 379c9e4ac63b..16debe6d89f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
 	struct dsc_reg_values dsc_reg_vals;
 	struct dsc_optc_config dsc_optc_cfg;
 
+	memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
+	memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
+
 	DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
 	dsc_config_log(dsc, dsc_cfg);
 	DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
-- 
2.17.1

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[PATCH v3 09/16] drm/dp-mst: Parse FEC capability on MST ports

[David Francis]

As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.

The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)

That value is needed for FEC and DSC support

Store it on drm_dp_mst_port

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
 include/drm/drm_dp_mst_helper.h       | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 34a5bdfc598b..ad5ccc08c40a 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -552,6 +552,7 @@ static bool drm_dp_sideband_parse_enum_path_resources_ack(struct drm_dp_sideband
 {
 	int idx = 1;
 	repmsg->u.path_resources.port_number = (raw->msg[idx] >> 4) & 0xf;
+	repmsg->u.path_resources.fec_capable = raw->msg[idx] & 0x1;
 	idx++;
 	if (idx > raw->curlen)
 		goto fail_len;
@@ -2180,6 +2181,7 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr,
 			DRM_DEBUG_KMS("enum path resources %d: %d %d\n", txmsg->reply.u.path_resources.port_number, txmsg->reply.u.path_resources.full_payload_bw_number,
 			       txmsg->reply.u.path_resources.avail_payload_bw_number);
 			port->available_pbn = txmsg->reply.u.path_resources.avail_payload_bw_number;
+			port->fec_capable = txmsg->reply.u.path_resources.fec_capable;
 		}
 	}
 
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index ddb518f2157a..fa973773a4a7 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -108,6 +108,8 @@ struct drm_dp_mst_port {
 	 * audio-capable.
 	 */
 	bool has_audio;
+
+	bool fec_capable;
 };
 
 /**
@@ -312,6 +314,7 @@ struct drm_dp_port_number_req {
 
 struct drm_dp_enum_path_resources_ack_reply {
 	u8 port_number;
+	bool fec_capable;
 	u16 full_payload_bw_number;
 	u16 avail_payload_bw_number;
 };
-- 
2.17.1

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[PATCH v3 10/16] drm/dp-mst: Add MST support to DP DPCD R/W functions

[David Francis]

Instead of having drm_dp_dpcd_read/write and
drm_dp_mst_dpcd_read/write as entry points into the
aux code, have drm_dp_dpcd_read/write handle both.

This means that DRM drivers can make MST DPCD read/writes.

Cc: Leo Li <sunpeng.li@amd.com>
Cc: Lyude Paul <lyude@redhat.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/drm_dp_aux_dev.c | 12 ++----------
 drivers/gpu/drm/drm_dp_helper.c  | 10 ++++++++--
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c b/drivers/gpu/drm/drm_dp_aux_dev.c
index 00610bd8d6c1..0780fc358389 100644
--- a/drivers/gpu/drm/drm_dp_aux_dev.c
+++ b/drivers/gpu/drm/drm_dp_aux_dev.c
@@ -162,11 +162,7 @@ static ssize_t auxdev_read_iter(struct kiocb *iocb, struct iov_iter *to)
 			break;
 		}
 
-		if (aux_dev->aux->is_remote)
-			res = drm_dp_mst_dpcd_read(aux_dev->aux, pos, buf,
-						   todo);
-		else
-			res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
+		res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
 
 		if (res <= 0)
 			break;
@@ -214,11 +210,7 @@ static ssize_t auxdev_write_iter(struct kiocb *iocb, struct iov_iter *from)
 			break;
 		}
 
-		if (aux_dev->aux->is_remote)
-			res = drm_dp_mst_dpcd_write(aux_dev->aux, pos, buf,
-						    todo);
-		else
-			res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
+		res = drm_dp_mst_dpcd_write(aux_dev->aux, pos, buf, todo);
 
 		if (res <= 0)
 			break;
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 54a6414c5d96..9f976b90c53a 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -29,6 +29,7 @@
 #include <linux/i2c.h>
 #include <linux/seq_file.h>
 #include <drm/drm_dp_helper.h>
+#include <drm/drm_dp_mst_helper.h>
 #include <drm/drmP.h>
 
 #include "drm_crtc_helper_internal.h"
@@ -272,7 +273,7 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
 
 /**
  * drm_dp_dpcd_read() - read a series of bytes from the DPCD
- * @aux: DisplayPort AUX channel
+ * @aux: DisplayPort AUX channel (SST or MST)
  * @offset: address of the (first) register to read
  * @buffer: buffer to store the register values
  * @size: number of bytes in @buffer
@@ -289,6 +290,8 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
 {
 	int ret;
 
+        if (aux->is_remote)
+                return drm_dp_mst_dpcd_read(aux, offset, buffer, size);
 	/*
 	 * HP ZR24w corrupts the first DPCD access after entering power save
 	 * mode. Eg. on a read, the entire buffer will be filled with the same
@@ -317,7 +320,7 @@ EXPORT_SYMBOL(drm_dp_dpcd_read);
 
 /**
  * drm_dp_dpcd_write() - write a series of bytes to the DPCD
- * @aux: DisplayPort AUX channel
+ * @aux: DisplayPort AUX channel (SST or MST)
  * @offset: address of the (first) register to write
  * @buffer: buffer containing the values to write
  * @size: number of bytes in @buffer
@@ -334,6 +337,9 @@ ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
 {
 	int ret;
 
+        if (aux->is_remote)
+                return drm_dp_mst_dpcd_write(aux, offset, buffer, size);
+
 	ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
 				 size);
 	drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
-- 
2.17.1

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[PATCH v3 11/16] drm/dp-mst: Fill branch->num_ports

[David Francis]

This field on drm_dp_mst_branch was never filled

Initialize it to zero when the list of ports is created.
When a port is added to the list, increment num_ports,
and when a port is removed from the list, decrement num_ports.

v2: remember to decrement on port removal

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index ad5ccc08c40a..7decb5bef062 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -918,6 +918,7 @@ static struct drm_dp_mst_branch *drm_dp_add_mst_branch_device(u8 lct, u8 *rad)
 	INIT_LIST_HEAD(&mstb->ports);
 	kref_init(&mstb->topology_kref);
 	kref_init(&mstb->malloc_kref);
+	mstb->num_ports = 0;
 	return mstb;
 }
 
@@ -1670,6 +1671,7 @@ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
 		mutex_lock(&mstb->mgr->lock);
 		drm_dp_mst_topology_get_port(port);
 		list_add(&port->next, &mstb->ports);
+		mstb->num_ports++;
 		mutex_unlock(&mstb->mgr->lock);
 	}
 
@@ -1704,6 +1706,7 @@ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
 			/* remove it from the port list */
 			mutex_lock(&mstb->mgr->lock);
 			list_del(&port->next);
+			mstb->num_ports--;
 			mutex_unlock(&mstb->mgr->lock);
 			/* drop port list reference */
 			drm_dp_mst_topology_put_port(port);
-- 
2.17.1

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[PATCH v3 12/16] drm/dp-mst: Add helpers for querying and enabling MST DSC

[David Francis]

Add drm_dp_mst_dsc_caps_for_port and drm_dp_mst_dsc_enable,
two helper functions for MST DSC

The former, given a port, returns the raw DPCD DSC caps off
that port.

The latter, given a port, enables or disables DSC on that port.

In both cases, the port given as input should be a leaf of
the MST tree with an attached display.

The logic for this is somewhat complicated, as DSC can be
enabled in 4 different ways.

Case 1: DP-to-DP peer device
if the branch immediately upstream has
 - PDT = DP_PEER_DEVICE_DP_MST_BRANCHING (2)
 - DPCD rev. >= DP 1.4
 - Exactly one input and one output
 - The output has PDT = DP_PEER_DEVICE_SST_SINK (3)

In this case, DSC could be possible either on the endpoint
or the peer device. Prefer the endpoint, which is possible if
 - The endpoint has DP_DSC_DECOMPRESSION_IS_SUPPORTED bit set
 - The endpoint has DP_FEC_CAPABLE bit set
 - The peer device has DSC_PASSTHROUGH_CAPABILITY bit set (from DP v2.0)

Otherwise, use the peer device

Case 2: DP-to-HDMI peer device
If the output port has
 - PDT = DP_PEER_DEVICE_DP_LEGACY_CONV (4)
 - DPCD rev. >= DP 1.4
 - LDPS = true
 - MCS = false

In this case, DSC can only be attempted on the peer device
(the output port)

Case 3: Virtual DP Sink (Internal Display Panel)
If the output port has
 - DPCD rev. >= DP 1.4
 - port_num >= 8

In this case, DSC can only be attempted on the peer device
(the output port)

Case 4: Synaptix Workaround
If the output has
 - link DPCD rev. >= DP 1.4
 - link branch_dev_id = 0x90CC24 (Synaptix)
 - There is exactly one branch device between the link and output

In this case, DSC can be attempted, but only using the *link*
aux device's caps. This is a quirk.

Cc: Lyude Paul <lyude@redhat.com>
Cc: Wenjing Liu <Wenjing.Liu@amd.com>
Cc: Nikola Cornij <Nikola.Cornij@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 192 ++++++++++++++++++++++++++
 include/drm/drm_dp_mst_helper.h       |   3 +
 2 files changed, 195 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 7decb5bef062..94742538551e 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4183,3 +4183,195 @@ static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux)
 {
 	i2c_del_adapter(&aux->ddc);
 }
+
+/**
+ * drm_dp_mst_is_virtual_dpcd() - Is the given port a virtual DPCD device?
+ * @port: The port to check
+ *
+ * Returns:
+ * true if the port is a virtual DPCD peer device, false otherwise
+ */
+static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port)
+{
+	struct drm_dp_mst_port *downstream_port;
+
+	if (!port)
+		return false;
+
+	/* Virtual DP Sink (Internal Display Panel) */
+	if (port->port_num >= 8 && port->dpcd_rev >= DP_DPCD_REV_14)
+		return true;
+
+	/* DP-to-HDMI Protocol Converter */
+	if (port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV &&
+			!port->mcs &&
+			port->ldps &&
+			port->dpcd_rev >= DP_DPCD_REV_14)
+		return true;
+
+	/* DP-to-DP */
+	if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
+			port->mstb &&
+			port->dpcd_rev >= DP_DPCD_REV_14 &&
+			port->mstb->num_ports == 2) {
+		list_for_each_entry(downstream_port, &port->mstb->ports, next) {
+			if (!downstream_port->input &&
+				downstream_port->pdt == DP_PEER_DEVICE_SST_SINK)
+				return true;
+		}
+	}
+
+	return false;
+}
+
+/**
+ * drm_dp_mst_is_virtual_dpcd() - Does this port require Synaptix DSC workaround?
+ * @port: The port to check
+ *
+ * Some Synaptix MST hubs support DSC even though they do not support virtual
+ * DPCD. This is a quirk.
+ *
+ * Returns:
+ * true if the Synaptix workaround is required, false otherwise
+ */
+static bool drm_dp_mst_dsc_synaptix_workaround(struct drm_dp_mst_port *port)
+{
+	u8 data[3] = { 0 };
+	u32 dev_id;
+	struct drm_dp_aux *phys_aux;
+
+	/* The hub must be directly connected to the connector */
+	if (port->mgr->mst_primary != port->parent)
+		return false;
+
+	phys_aux = port->mgr->aux;
+	if (drm_dp_dpcd_read(phys_aux, DP_BRANCH_OUI, data, 3) < 0)
+		return false;
+	dev_id = (data[0] << 16) & (data[1] << 8) & data[3];
+	/* Synaptix device ID */
+	if (dev_id != 0x90CC24)
+		return false;
+
+	if (drm_dp_dpcd_read(phys_aux, DP_DPCD_REV, data, 1) < 0)
+		return false;
+	/* Must be DPCD rev. 1.4 or later */
+	if (data[0] < DP_DPCD_REV_14)
+		return false;
+
+	if (drm_dp_dpcd_read(&port->aux, DP_DOWNSTREAMPORT_PRESENT, data, 1) < 0)
+		return false;
+	/* Must not be a VGA converter */
+	if ((data[0] & 7) == 3)
+		return false;
+
+	return true;
+}
+
+/**
+ * drm_dp_mst_dsc_aux_for_port() - Find the correct aux for DSC
+ * @port: The port to check. A leaf of the MST tree with an attached display.
+ *
+ * Depending on the situation, DSC may be enabled via the endpoint aux,
+ * the immediately upstream aux, or the connector's physical aux.
+ *
+ * Returns:
+ * NULL if DSC cannot be enabled on this port, otherwise the aux device
+ */
+struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
+{
+	u8 upstream_dsc_caps = 0;
+	u8 endpoint_dsc_caps = 0;
+	u8 endpoint_fec_caps = 0;
+	struct drm_dp_mst_port *immediate_upstream_port;
+	struct drm_dp_mst_port *fec_port;
+
+	if (port && port->parent)
+		immediate_upstream_port = port->parent->port_parent;
+	else
+		immediate_upstream_port = NULL;
+
+	fec_port = immediate_upstream_port;
+	while (fec_port) {
+		if (!fec_port->fec_capable)
+			return NULL;
+
+		fec_port = fec_port->parent->port_parent;
+	}
+
+	if (immediate_upstream_port) {
+		if (drm_dp_dpcd_read(&immediate_upstream_port->aux,
+				DP_DSC_SUPPORT, &upstream_dsc_caps, 1) < 0)
+			return NULL;
+	}
+
+	if (drm_dp_dpcd_read(&port->aux, DP_DSC_SUPPORT, &endpoint_dsc_caps, 1) < 0)
+		return NULL;
+	if (drm_dp_dpcd_read(&port->aux, DP_FEC_CAPABILITY, &endpoint_fec_caps, 1) < 0)
+		return NULL;
+
+	/* Enpoint decompression with DP-to-DP peer device */
+	if (drm_dp_mst_is_virtual_dpcd(immediate_upstream_port)
+			&& (upstream_dsc_caps & 0x2) /* DSC passthrough capability */
+			&& (endpoint_fec_caps & DP_FEC_CAPABLE)
+			&& (endpoint_dsc_caps & DP_DSC_DECOMPRESSION_IS_SUPPORTED))
+		return &port->aux;
+
+	/* Virtual DPCD decompression with DP-to-DP peer device */
+	if (drm_dp_mst_is_virtual_dpcd(immediate_upstream_port))
+		return &immediate_upstream_port->aux;
+
+	/* Virtual DPCD decompression with DP-to-HDMI or Virtual DP Sink */
+	if (drm_dp_mst_is_virtual_dpcd(port))
+		return &port->aux;
+
+	/* Synaptix workaround */
+	if (drm_dp_mst_dsc_synaptix_workaround(port))
+		return port->mgr->aux;
+
+	return NULL;
+}
+
+/**
+ * drm_dp_mst_dsc_aux_for_port() - Retrieve the DSC capability registers
+ * @port: The port to check. A leaf of the MST tree with an attached display.
+ * @caps: Output.  A pointer to an array at least 16 bytes long
+ *
+ * Reads the DSC capability registers (DSC_SUPPORT through
+ * BITS_PER_PIXEL_INCREMENT) and store them in the given pointer. Use
+ * the correct aux for DSC on the given port.
+ *
+ * Returns:
+ * The number of bytes read on success, or a negative error code on failure
+ */
+int drm_dp_mst_dsc_caps_for_port(struct drm_dp_mst_port *port, u8 *caps)
+{
+	struct drm_dp_aux *aux = drm_dp_mst_dsc_aux_for_port(port);
+
+	if (!aux)
+		return -EINVAL;
+
+	return drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, caps, 16);
+}
+EXPORT_SYMBOL(drm_dp_mst_dsc_caps_for_port);
+
+/**
+ * drm_dp_mst_dsc_aux_for_port() - Enable DSC on an MST endpoint
+ * @port: The port to check. A leaf of the MST tree with an attached display.
+ * @enable: true for turn on DSC, false for turn off DSC
+ *
+ * Writes DP_DSC_ENABLE on the correct aux for the given port.
+ *
+ * Returns:
+ * The number of bytes written on success, or a negative error code on failure
+ */
+int drm_dp_mst_dsc_enable(struct drm_dp_mst_port *port, bool enable)
+{
+	struct drm_dp_aux *aux = drm_dp_mst_dsc_aux_for_port(port);
+	u8 enable_dsc = enable ? 1 : 0;
+
+	if (!aux)
+		return -EINVAL;
+
+	return drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable_dsc, 1);
+}
+EXPORT_SYMBOL(drm_dp_mst_dsc_enable);
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index fa973773a4a7..0f70dc8dfbeb 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -674,6 +674,9 @@ int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);
 void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port);
 void drm_dp_mst_put_port_malloc(struct drm_dp_mst_port *port);
 
+int drm_dp_mst_dsc_caps_for_port(struct drm_dp_mst_port *port, u8 *caps);
+int drm_dp_mst_dsc_enable(struct drm_dp_mst_port *port, bool enable);
+
 extern const struct drm_private_state_funcs drm_dp_mst_topology_state_funcs;
 
 /**
-- 
2.17.1

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[PATCH v3 13/16] drm/amd/display: Validate DSC caps on MST endpoints

[David Francis]

During MST mode enumeration, if a new dc_sink is created,
populate it with dsc caps as appropriate.

Use drm_dp_mst_dsc_caps_for_port to get the raw caps,
then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.

Cc: Wenjing Liu <Wenjing.Liu@amd.com>
Cc: Nikola Cornij <Nikola.Cornij@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 27 ++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 16218a202b59..9978c1a01eb7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -25,6 +25,7 @@
 
 #include <linux/version.h>
 #include <drm/drm_atomic_helper.h>
+#include <drm/drm_dp_mst_helper.h>
 #include "dm_services.h"
 #include "amdgpu.h"
 #include "amdgpu_dm.h"
@@ -189,6 +190,24 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 	.early_unregister = amdgpu_dm_mst_connector_early_unregister,
 };
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
+{
+	struct dc_sink *dc_sink = aconnector->dc_sink;
+	struct drm_dp_mst_port *port = aconnector->port;
+	u8 dsc_caps[16] = { 0 };
+
+	if (drm_dp_mst_dsc_caps_for_port(port, dsc_caps) < 0)
+		return false;
+
+	printk("Validated DSC caps 0x%x", dsc_caps[0]);
+	if (!dc_dsc_parse_dsc_dpcd(dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps))
+		return false;
+
+	return true;
+}
+#endif
+
 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 {
 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
@@ -231,10 +250,16 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
 		/* dc_link_add_remote_sink returns a new reference */
 		aconnector->dc_sink = dc_sink;
 
-		if (aconnector->dc_sink)
+		if (aconnector->dc_sink) {
 			amdgpu_dm_update_freesync_caps(
 					connector, aconnector->edid);
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+			if (!validate_dsc_caps_on_connector(aconnector))
+				memset(&aconnector->dc_sink->sink_dsc_caps,
+				       0, sizeof(aconnector->dc_sink->sink_dsc_caps));
+#endif
+		}
 	}
 
 	drm_connector_update_edid_property(
-- 
2.17.1

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[PATCH v3 14/16] drm/amd/display: Write DSC enable to MST DPCD

[David Francis]

Rework the dm_helpers_write_dsc_enable callback to
handle the MST case.

Use the drm_dp_mst_dsc_enable helper.

Cc: Wenjing Liu <Wenjing.Liu@amd.com>
Cc: Nikola Cornij <Nikola.Cornij@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c    | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 716d6577cdbd..6ef680fa2875 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -38,6 +38,7 @@
 #include "dc.h"
 #include "amdgpu_dm.h"
 #include "amdgpu_dm_irq.h"
+#include "amdgpu_dm_mst_types.h"
 
 #include "dm_helpers.h"
 
@@ -557,8 +558,21 @@ bool dm_helpers_dp_write_dsc_enable(
 )
 {
 	uint8_t enable_dsc = enable ? 1 : 0;
+	struct amdgpu_dm_connector *aconnector;
+
+	if (!stream)
+		return false;
+
+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+		aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+
+		return (drm_dp_mst_dsc_enable(aconnector->port, enable) >= 0);
+	}
+
+	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)
+		return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 
-	return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
+	return false;
 }
 #endif
 
-- 
2.17.1

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[PATCH v3 15/16] drm/amd/display: MST DSC compute fair share

[David Francis]

If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network

Implement an algorithm to determine the correct DSC config
for each stream

The algorithm:
This
     [                   ]          ( )
represents the range of bandwidths possible for a given stream.
The [] area represents the range of DSC configs, and the ()
represents no DSC. The bandwidth used increases from left to right.

First, try disabling DSC on all streams
     [                  ]          (|)
     [                     ]            (|)
Check this against the bandwidth limits of the link and each branch
(including each endpoint). If it passes, the job is done

Second, try maximum DSC compression on all streams
that support DSC
     [|         ]        ( )
     [|                ]         ( )
If this does not pass, then enabling this combination of streams
is impossible

Otherwise, divide the remaining bandwidth evenly amongst the streams
     [        |  ]         ( )
     [        |      ]        ( )

If one or more of the streams reach minimum compression, evenly
divide the reamining bandwidth amongst the remaining streams
     [    |] ( )
     [       |]   ( )
     [                 |   ]               ( )
     [                 |      ]                  ( )

If all streams can reach minimum compression, disable compression
greedily
     [      |]  ( )
     [        |]    ( )
     [                 ]                                (|)

Perform this algorithm on each full update, on each MST link
with at least one DSC stream on it

After the configs are computed, call
dcn20_add_dsc_to_stream_resource on each stream with DSC enabled.
It is only after all streams are created that we can know which
of them will need DSC.

Do all of this at the end of amdgpu atomic check.  If it fails,
fail check; This combination of timings cannot be supported.

Cc: Wenjing Liu <Wenjing.Liu@amd.com>
Cc: Nikola Cornij <Nikola.Cornij@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   4 +
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 375 ++++++++++++++++++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   4 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
 5 files changed, 389 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 84249057e181..145fd73025dc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7331,6 +7331,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 		if (ret)
 			goto fail;
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+		if (!compute_mst_dsc_configs_for_state(dm_state->context))
+			goto fail;
+#endif
 		if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
 			ret = -EINVAL;
 			goto fail;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 9978c1a01eb7..57b5a711c336 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -38,6 +38,8 @@
 
 #include "i2caux_interface.h"
 
+#include "dc/dcn20/dcn20_resource.h"
+
 /* #define TRACE_DPCD */
 
 #ifdef TRACE_DPCD
@@ -452,3 +454,376 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 		aconnector->connector_id);
 }
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+struct dsc_mst_fairness_params {
+	struct dc_crtc_timing *timing;
+	struct dc_sink *sink;
+	struct dc_dsc_bw_range bw_range;
+	bool compression_possible;
+	struct drm_dp_mst_port *port;
+};
+
+struct dsc_mst_fairness_vars {
+	int pbn;
+	bool dsc_enabled;
+	int bpp_x16;
+};
+
+static bool port_downstream_of_branch(struct drm_dp_mst_port *port,
+		struct drm_dp_mst_branch *branch)
+{
+	while (port->parent) {
+		if (port->parent == branch)
+			return true;
+
+		if (port->parent->port_parent)
+			port = port->parent->port_parent;
+		else
+			break;
+	}
+	return false;
+}
+
+static bool check_pbn_limit_on_branch(struct drm_dp_mst_branch *branch,
+		struct dsc_mst_fairness_params *params,
+		struct dsc_mst_fairness_vars *vars, int count)
+{
+	struct drm_dp_mst_port *port;
+	int i;
+	int pbn_limit = 0;
+	int pbn_used = 0;
+
+	list_for_each_entry(port, &branch->ports, next) {
+		if (port->mstb)
+			if (!check_pbn_limit_on_branch(port->mstb, params, vars, count))
+				return false;
+
+		if (port->available_pbn > 0)
+			pbn_limit = port->available_pbn;
+	}
+
+	for (i = 0; i < count; i++) {
+		if (port_downstream_of_branch(params[i].port, branch))
+			pbn_used += vars[i].pbn;
+	}
+
+	if (pbn_used > pbn_limit)
+		return false;
+
+	return true;
+}
+
+static bool check_bandwidth_limits(struct dc_link *dc_link,
+		struct dsc_mst_fairness_params *params,
+		struct dsc_mst_fairness_vars *vars,
+		int count)
+{
+	int link_timeslot_limit = 63;
+	int link_timeslots_used = 0;
+	int pbn_per_timeslot;
+	int i;
+	struct drm_dp_mst_topology_mgr *mst_mgr;
+
+	/* kbits to pbn, dividing by 64 */
+	pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
+			dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
+
+	/* Check link bandwidth limit */
+	for (i = 0; i < count; i++)
+		link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
+
+	if (link_timeslots_used > link_timeslot_limit)
+		return false;
+
+	/* Check branch bandwidth limit for each port on each branch */
+	mst_mgr = params[0].port->mgr;
+	if (!check_pbn_limit_on_branch(mst_mgr->mst_primary, params, vars, count))
+		return false;
+
+	return true;
+}
+
+static int kbps_to_peak_pbn(int kbps)
+{
+	u64 peak_kbps = kbps;
+
+	peak_kbps *= 1006;
+	peak_kbps /= 1000;
+	return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
+}
+
+static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
+		struct dsc_mst_fairness_vars *vars,
+		int count)
+{
+	int i;
+
+	for (i = 0; i < count; i++) {
+		memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
+		if (vars[i].dsc_enabled && dc_dsc_compute_config(params[i].sink->ctx->dc,
+					&params[i].sink->sink_dsc_caps.dsc_dec_caps,
+					0,
+					params[i].timing,
+					&params[i].timing->dsc_cfg)) {
+			params[i].timing->flags.DSC = 1;
+			params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
+		} else {
+			params[i].timing->flags.DSC = 0;
+		}
+
+	}
+
+}
+
+static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
+{
+	struct dc_dsc_config dsc_config;
+	u64 kbps;
+
+	kbps = (u64)pbn * 994 * 8 * 54 / 64;
+	dc_dsc_compute_config(param.sink->ctx->dc,
+			&param.sink->sink_dsc_caps.dsc_dec_caps,
+			(int) kbps, param.timing, &dsc_config);
+
+	return dsc_config.bits_per_pixel;
+}
+
+static void increase_dsc_bpp(struct dc_link *dc_link,
+		struct dsc_mst_fairness_params *params,
+		struct dsc_mst_fairness_vars *vars,
+		int count)
+{
+	int i;
+	bool bpp_increased[MAX_PIPES];
+	int initial_slack[MAX_PIPES];
+	int min_initial_slack;
+	int next_index;
+	int remaining_to_increase = 0;
+	int pbn_per_timeslot;
+	int link_timeslots_used;
+	int fair_pbn_alloc;
+
+	for (i = 0; i < count; i++) {
+		if (vars[i].dsc_enabled) {
+			initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
+			bpp_increased[i] = false;
+			remaining_to_increase += 1;
+		} else {
+			initial_slack[i] = 0;
+			bpp_increased[i] = true;
+		}
+	}
+
+	pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
+			dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
+
+	while (remaining_to_increase) {
+		next_index = -1;
+		min_initial_slack = -1;
+		for (i = 0; i < count; i++) {
+			if (!bpp_increased[i]) {
+				if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
+					min_initial_slack = initial_slack[i];
+					next_index = i;
+				}
+			}
+		}
+
+		if (next_index == -1)
+			break;
+
+		link_timeslots_used = 0;
+
+		for (i = 0; i < count; i++)
+			link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
+
+		fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
+
+		if (initial_slack[next_index] > fair_pbn_alloc) {
+			vars[next_index].pbn += fair_pbn_alloc;
+			if (check_bandwidth_limits(dc_link, params, vars, count))
+				vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
+			else
+				vars[next_index].pbn -= fair_pbn_alloc;
+		} else {
+			vars[next_index].pbn += initial_slack[next_index];
+			if (check_bandwidth_limits(dc_link, params, vars, count))
+				vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
+			else
+				vars[next_index].pbn -= initial_slack[next_index];
+		}
+
+		bpp_increased[next_index] = true;
+		remaining_to_increase--;
+	}
+}
+
+static void try_disable_dsc(struct dc_link *dc_link,
+		struct dsc_mst_fairness_params *params,
+		struct dsc_mst_fairness_vars *vars,
+		int count)
+{
+	int i;
+	bool tried[MAX_PIPES];
+	int kbps_increase[MAX_PIPES];
+	int max_kbps_increase;
+	int next_index;
+	int remaining_to_try = 0;
+
+	for (i = 0; i < count; i++) {
+		if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
+			kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
+			tried[i] = false;
+			remaining_to_try += 1;
+		} else {
+			kbps_increase[i] = 0;
+			tried[i] = true;
+		}
+	}
+
+	while (remaining_to_try) {
+		next_index = -1;
+		max_kbps_increase = -1;
+		for (i = 0; i < count; i++) {
+			if (!tried[i]) {
+				if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
+					max_kbps_increase = kbps_increase[i];
+					next_index = i;
+				}
+			}
+		}
+
+		if (next_index == -1)
+			break;
+
+		vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
+
+		if (check_bandwidth_limits(dc_link, params, vars, count)) {
+			vars[next_index].dsc_enabled = false;
+			vars[next_index].bpp_x16 = 0;
+		} else {
+			vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
+		}
+
+		tried[next_index] = true;
+		remaining_to_try--;
+	}
+}
+
+static bool compute_mst_dsc_configs_for_link(struct dc_state *dc_state, struct dc_link *dc_link)
+{
+	int i;
+	struct dc_stream_state *stream;
+	struct dsc_mst_fairness_params params[MAX_PIPES];
+	struct dsc_mst_fairness_vars vars[MAX_PIPES];
+	struct amdgpu_dm_connector *aconnector;
+	int count = 0;
+
+	memset(params, 0, sizeof(params));
+
+	/* Set up params */
+	for (i = 0; i < dc_state->stream_count; i++) {
+		stream = dc_state->streams[i];
+
+		if (stream->link != dc_link)
+			continue;
+
+		stream->timing.flags.DSC = 0;
+
+		params[count].timing = &stream->timing;
+		params[count].sink = stream->sink;
+		aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+		params[count].port = aconnector->port;
+		params[count].compression_possible = stream->sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported;
+		if (!dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc, 8, 16,
+				&stream->sink->sink_dsc_caps.dsc_dec_caps,
+				&stream->timing, &params[count].bw_range))
+			params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
+
+		count++;
+	}
+
+	/* Try no compression */
+	for (i = 0; i < count; i++) {
+		vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
+		vars[i].dsc_enabled = false;
+		vars[i].bpp_x16 = 0;
+	}
+
+	if (check_bandwidth_limits(dc_link, params, vars, count)) {
+		set_dsc_configs_from_fairness_vars(params, vars, count);
+		return true;
+	}
+
+	/* Try max compression */
+	for (i = 0; i < count; i++) {
+		if (params[i].compression_possible) {
+			vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
+			vars[i].dsc_enabled = true;
+			vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
+		} else {
+			vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
+			vars[i].dsc_enabled = false;
+			vars[i].bpp_x16 = 0;
+		}
+	}
+
+	if (!check_bandwidth_limits(dc_link, params, vars, count))
+		return false;
+
+	/* Optimize degree of compression */
+	increase_dsc_bpp(dc_link, params, vars, count);
+
+	try_disable_dsc(dc_link, params, vars, count);
+
+	set_dsc_configs_from_fairness_vars(params, vars, count);
+
+	return true;
+}
+
+bool compute_mst_dsc_configs_for_state(struct dc_state *dc_state)
+{
+	int i, j;
+	struct dc_stream_state *stream;
+	bool computed_streams[MAX_PIPES];
+	struct amdgpu_dm_connector *aconnector;
+
+	for (i = 0; i < dc_state->stream_count; i++)
+		computed_streams[i] = false;
+
+	for (i = 0; i < dc_state->stream_count; i++) {
+		stream = dc_state->streams[i];
+
+		if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
+			continue;
+
+		aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+
+		if (!aconnector || !aconnector->dc_sink)
+			continue;
+
+		if (!aconnector->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
+			continue;
+
+		if (computed_streams[i])
+			continue;
+
+		if (!compute_mst_dsc_configs_for_link(dc_state, stream->link))
+			return false;
+
+		for (j = 0; j < dc_state->stream_count; j++) {
+			if (dc_state->streams[j]->link == stream->link)
+				computed_streams[j] = true;
+		}
+	}
+
+	for (i = 0; i < dc_state->stream_count; i++) {
+		stream = dc_state->streams[i];
+
+		if (stream->timing.flags.DSC == 1)
+			dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);
+	}
+
+	return true;
+}
+#endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 2da851b40042..da957611214a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -32,4 +32,8 @@ struct amdgpu_dm_connector;
 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 				       struct amdgpu_dm_connector *aconnector);
 
+
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+bool compute_mst_dsc_configs_for_state(struct dc_state *dc_state);
+#endif
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index c59f31dcdc0d..22511b047837 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1439,7 +1439,7 @@ static void release_dsc(struct resource_context *res_ctx,
 
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
 		struct dc_state *dc_ctx,
 		struct dc_stream_state *dc_stream)
 {
@@ -1454,6 +1454,9 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
 		if (pipe_ctx->stream != dc_stream)
 			continue;
 
+		if (pipe_ctx->stream_res.dsc)
+			continue;
+
 		acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
 
 		/* The number of DSCs can be less than the number of pipes */
@@ -1511,7 +1514,7 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx,
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 	/* Get a DSC if required and available */
 	if (result == DC_OK && dc_stream->timing.flags.DSC)
-		result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
+		result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
 #endif
 
 	if (result == DC_OK)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index 44f95aa0d61e..2209ebda6ef6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -131,6 +131,7 @@ void dcn20_calculate_dlg_params(
 
 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);
 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state);
 
-- 
2.17.1

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[PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC connectors

[David Francis]

Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not change timing.

Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
for each crtc that shares a MST topology with that stream and
supports DSC, add that crtc (and all affected connectors and
planes) to the atomic state and set mode_changed on its state

v2: Do this check only on Navi and before adding connectors
and planes on modesetting crtcs

Cc: Leo Li <sunpeng.li@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: Lyude Paul <lyude@redhat.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 145fd73025dc..702fb0e29053 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6475,7 +6475,73 @@ static int do_aquire_global_lock(struct drm_device *dev,
 
 	return ret < 0 ? ret : 0;
 }
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+/*
+ * TODO: This logic should at some point be moved into DRM
+ */
+static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
+{
+	struct drm_connector *connector;
+	struct drm_connector_state *conn_state;
+	struct drm_connector_list_iter conn_iter;
+	struct drm_crtc_state *new_crtc_state;
+	struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
+	int i, j;
+	struct drm_crtc *crtcs_affected[AMDGPU_MAX_CRTCS] = { 0 };
+
+	for_each_new_connector_in_state(state, connector, conn_state, i) {
+		if (conn_state->crtc != crtc)
+			continue;
+
+		aconnector = to_amdgpu_dm_connector(connector);
+		if (!aconnector->port)
+			aconnector = NULL;
+		else
+			break;
+	}
+
+	if (!aconnector)
+		return 0;
+
+	i = 0;
+	drm_connector_list_iter_begin(state->dev, &conn_iter);
+	drm_for_each_connector_iter(connector, &conn_iter) {
+		if (!connector->state || !connector->state->crtc)
+			continue;
+
+		aconnector_to_add = to_amdgpu_dm_connector(connector);
+		if (!aconnector_to_add->port)
+			continue;
+
+		if (aconnector_to_add->port->mgr != aconnector->port->mgr)
+			continue;
+
+		if (!aconnector_to_add->dc_sink)
+			continue;
+
+		if (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
+			continue;
+
+		if (i >= AMDGPU_MAX_CRTCS)
+			continue;
+
+		crtcs_affected[i] = connector->state->crtc;
+		i++;
+	}
+	drm_connector_list_iter_end(&conn_iter);
+
+	for (j = 0; j < i; j++) {
+		new_crtc_state = drm_atomic_get_crtc_state(state, crtcs_affected[j]);
+		if (IS_ERR(new_crtc_state))
+			return PTR_ERR(new_crtc_state);
 
+		new_crtc_state->mode_changed = true;
+	}
+
+	return 0;
+
+}
+#endif
 static void get_freesync_config_for_crtc(
 	struct dm_crtc_state *new_crtc_state,
 	struct dm_connector_state *new_con_state)
@@ -7160,6 +7226,17 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 	if (ret)
 		goto fail;
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+	if (adev->asic_type >= CHIP_NAVI10) {
+		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+			if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
+				ret = add_affected_mst_dsc_crtcs(state, crtc);
+				if (ret)
+					goto fail;
+			}
+		}
+	}
+#endif
 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
 		    !new_crtc_state->color_mgmt_changed &&
-- 
2.17.1

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Re: [PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC connectors

[Francis, David]

I know this looks like it could be a DRM helper, but
 - That would require a DRM-generic way of knowing if a
   connector supports DSC, and current precedent is that
   DSC functionality is stored on a driver-specific basis
 - This function, by necessity, locks global state. Other
   hardware may be able to solve this problem with more fine-
   grained locking, for example by recalculating DSC configs
   and then adding to the state all CRTCs for which the config
   has changed
 - AMD is currently the only user of MST DSC, so if this needs
   to be in DRM, it would be easier to do so once it is
   clear what functionality is common between drivers

________________________________________
From: dri-devel <dri-devel-bounces@lists.freedesktop.org> on behalf of David Francis <David.Francis@amd.com>
Sent: August 21, 2019 4:01 PM
To: dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Li, Sun peng (Leo); Francis, David; Kazlauskas, Nicholas
Subject: [PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC connectors

Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not change timing.

Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
for each crtc that shares a MST topology with that stream and
supports DSC, add that crtc (and all affected connectors and
planes) to the atomic state and set mode_changed on its state

v2: Do this check only on Navi and before adding connectors
and planes on modesetting crtcs

Cc: Leo Li <sunpeng.li@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: Lyude Paul <lyude@redhat.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 145fd73025dc..702fb0e29053 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6475,7 +6475,73 @@ static int do_aquire_global_lock(struct drm_device *dev,

        return ret < 0 ? ret : 0;
 }
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+/*
+ * TODO: This logic should at some point be moved into DRM
+ */
+static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
+{
+       struct drm_connector *connector;
+       struct drm_connector_state *conn_state;
+       struct drm_connector_list_iter conn_iter;
+       struct drm_crtc_state *new_crtc_state;
+       struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
+       int i, j;
+       struct drm_crtc *crtcs_affected[AMDGPU_MAX_CRTCS] = { 0 };
+
+       for_each_new_connector_in_state(state, connector, conn_state, i) {
+               if (conn_state->crtc != crtc)
+                       continue;
+
+               aconnector = to_amdgpu_dm_connector(connector);
+               if (!aconnector->port)
+                       aconnector = NULL;
+               else
+                       break;
+       }
+
+       if (!aconnector)
+               return 0;
+
+       i = 0;
+       drm_connector_list_iter_begin(state->dev, &conn_iter);
+       drm_for_each_connector_iter(connector, &conn_iter) {
+               if (!connector->state || !connector->state->crtc)
+                       continue;
+
+               aconnector_to_add = to_amdgpu_dm_connector(connector);
+               if (!aconnector_to_add->port)
+                       continue;
+
+               if (aconnector_to_add->port->mgr != aconnector->port->mgr)
+                       continue;
+
+               if (!aconnector_to_add->dc_sink)
+                       continue;
+
+               if (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
+                       continue;
+
+               if (i >= AMDGPU_MAX_CRTCS)
+                       continue;
+
+               crtcs_affected[i] = connector->state->crtc;
+               i++;
+       }
+       drm_connector_list_iter_end(&conn_iter);
+
+       for (j = 0; j < i; j++) {
+               new_crtc_state = drm_atomic_get_crtc_state(state, crtcs_affected[j]);
+               if (IS_ERR(new_crtc_state))
+                       return PTR_ERR(new_crtc_state);

+               new_crtc_state->mode_changed = true;
+       }
+
+       return 0;
+
+}
+#endif
 static void get_freesync_config_for_crtc(
        struct dm_crtc_state *new_crtc_state,
        struct dm_connector_state *new_con_state)
@@ -7160,6 +7226,17 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
        if (ret)
                goto fail;

+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+       if (adev->asic_type >= CHIP_NAVI10) {
+               for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+                       if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
+                               ret = add_affected_mst_dsc_crtcs(state, crtc);
+                               if (ret)
+                                       goto fail;
+                       }
+               }
+       }
+#endif
        for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
                if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
                    !new_crtc_state->color_mgmt_changed &&
--
2.17.1

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Re: [PATCH v3 06/16] drm/dp-mst: Add PBN calculation for DSC modes

[Lyude Paul]

Reviewed-by: Lyude Paul <lyude@redhat.com>
Thanks!

On Wed, 2019-08-21 at 16:01 -0400, David Francis wrote:
> With DSC, bpp can be a multiple of 1/16, so
> drm_dp_calc_pbn_mode is insufficient.
> 
> Add drm_dp_calc_pbn_mode_dsc, a function which is
> the same as drm_dp_calc_pbn_mode, but the bpp is
> in units of 1/16.
> 
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 43 +++++++++++++++++++++++++++
>  include/drm/drm_dp_mst_helper.h       |  2 +-
>  2 files changed, 44 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 398e7314ea8b..34a5bdfc598b 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3588,6 +3588,49 @@ static int test_calc_pbn_mode(void)
>  	return 0;
>  }
>  
> +/**
> + * drm_dp_calc_pbn_mode_dsc() - Calculate the PBN for a mode with DSC
> enabled.
> + * @clock: dot clock for the mode
> + * @dsc_bpp: dsc bits per pixel x16 (e.g. dsc_bpp = 136 is 8.5 bpp)
> + *
> + * This uses the formula in the spec to calculate the PBN value for a mode,
> + * given that the mode is using DSC
> + * Returns:
> + * PBN required for this mode
> + */
> +int drm_dp_calc_pbn_mode_dsc(int clock, int dsc_bpp)
> +{
> +	u64 kbps;
> +	s64 peak_kbps;
> +	u32 numerator;
> +	u32 denominator;
> +
> +	kbps = clock * dsc_bpp;
> +
> +	/*
> +	 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> +	 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
> +	 * common multiplier to render an integer PBN for all link rate/lane
> +	 * counts combinations
> +	 * calculate
> +	 * peak_kbps *= (1/16) bppx16 to bpp
> +	 * peak_kbps *= (1006/1000)
> +	 * peak_kbps *= (64/54)
> +	 * peak_kbps *= 8    convert to bytes
> +	 *
> +	 * Divide numerator and denominator by 16 to avoid overflow
> +	 */
> +
> +	numerator = 64 * 1006 / 16;
> +	denominator = 54 * 8 * 1000 * 1000;
> +
> +	kbps *= numerator;
> +	peak_kbps = drm_fixp_from_fraction(kbps, denominator);
> +
> +	return drm_fixp2int_ceil(peak_kbps);
> +}
> +EXPORT_SYMBOL(drm_dp_calc_pbn_mode_dsc);
> +
>  /* we want to kick the TX after we've ack the up/down IRQs. */
>  static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr)
>  {
> diff --git a/include/drm/drm_dp_mst_helper.h
> b/include/drm/drm_dp_mst_helper.h
> index 2ba6253ea6d3..ddb518f2157a 100644
> --- a/include/drm/drm_dp_mst_helper.h
> +++ b/include/drm/drm_dp_mst_helper.h
> @@ -611,7 +611,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector
> *connector, struct drm_dp_
>  
>  
>  int drm_dp_calc_pbn_mode(int clock, int bpp);
> -
> +int drm_dp_calc_pbn_mode_dsc(int clock, int dsc_bpp);
>  
>  bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr,
>  			      struct drm_dp_mst_port *port, int pbn, int
> slots);
-- 
Cheers,
	Lyude Paul

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Re: [PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC connectors

[Lyude Paul]

On Wed, 2019-08-21 at 20:02 +0000, Francis, David wrote:
> I know this looks like it could be a DRM helper, but
>  - That would require a DRM-generic way of knowing if a
>    connector supports DSC, and current precedent is that
>    DSC functionality is stored on a driver-specific basis

Don't mistake a lack of foresight for precedence. As well we already have a
bunch of dsc helpers in drm_dp_dsc.c, so it would seem reasonable to add more.

>  - This function, by necessity, locks global state. Other
>    hardware may be able to solve this problem with more fine-
>    grained locking, for example by recalculating DSC configs
>    and then adding to the state all CRTCs for which the config
>    has changed
This function doesn't nessecarily need to be copy-pasted into DRM as is,
rather I'd like to see us come up with an actual design that can be used with
multiple drivers like we said. If AMD were moved to use the newer atomic
helpers, drm_dp_mst_atomic_check(). Note that when adding this I didn't move
over amd because at the time I looked at amdgpu's MST code for DM it didn't
look like any of it was really prepared for basic atomic state checking at
all, I don't know if this has changed or if maybe I missed something in the
confusing DM/DC layer.

A lot of the information you're looking at in this function could be done
entirely from just looking at the atomic topology state and adding properties
to it as needed, along with using that topology state to infer precisely which
connectors (and thus, which CRTCs) need locking. All that needs to be done is
adding whatever information you need to that atomic state.

Note as well I've already changed a lot of the MST helpers already, so if we
end up having to modify these helpers down the line so that other drivers can
use them it's really not a problem.

>  - AMD is currently the only user of MST DSC, so if this needs
>    to be in DRM, it would be easier to do so once it is
>    clear what functionality is common between drivers

Currently yes, but Intel is planning on adding support for this as well very
soon (I just discussed this with so collaborating with them and figuring out a
design that works for everyone shouldn't be too difficult. Talking with Dave
Airlie he pointed out, and tbh I agree with him, that we really should land
this as helpers first as there's less motivation to do so after it's been
added to a driver. As well, we also can move things out of intel's driver and
into common helpers as need be.

> 
> ________________________________________
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> on behalf of David
> Francis <David.Francis@amd.com>
> Sent: August 21, 2019 4:01 PM
> To: dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> Cc: Li, Sun peng (Leo); Francis, David; Kazlauskas, Nicholas
> Subject: [PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC
> connectors
> 
> Whenever a connector on an MST network is attached, detached, or
> undergoes a modeset, the DSC configs for each stream on that
> topology will be recalculated. This can change their required
> bandwidth, requiring a full reprogramming, as though a modeset
> was performed, even if that stream did not change timing.
> 
> Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
> for each crtc that shares a MST topology with that stream and
> supports DSC, add that crtc (and all affected connectors and
> planes) to the atomic state and set mode_changed on its state
> 
> v2: Do this check only on Navi and before adding connectors
> and planes on modesetting crtcs
> 
> Cc: Leo Li <sunpeng.li@amd.com>
> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 77 +++++++++++++++++++
>  1 file changed, 77 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 145fd73025dc..702fb0e29053 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -6475,7 +6475,73 @@ static int do_aquire_global_lock(struct drm_device
> *dev,
> 
>         return ret < 0 ? ret : 0;
>  }
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> +/*
> + * TODO: This logic should at some point be moved into DRM
> + */
> +static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state,
> struct drm_crtc *crtc)
> +{
> +       struct drm_connector *connector;
> +       struct drm_connector_state *conn_state;
> +       struct drm_connector_list_iter conn_iter;
> +       struct drm_crtc_state *new_crtc_state;
> +       struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
> +       int i, j;
> +       struct drm_crtc *crtcs_affected[AMDGPU_MAX_CRTCS] = { 0 };
> +
> +       for_each_new_connector_in_state(state, connector, conn_state, i) {
> +               if (conn_state->crtc != crtc)
> +                       continue;
> +
> +               aconnector = to_amdgpu_dm_connector(connector);
> +               if (!aconnector->port)
> +                       aconnector = NULL;
> +               else
> +                       break;
> +       }
> +
> +       if (!aconnector)
> +               return 0;
> +
> +       i = 0;
> +       drm_connector_list_iter_begin(state->dev, &conn_iter);
> +       drm_for_each_connector_iter(connector, &conn_iter) {
> +               if (!connector->state || !connector->state->crtc)
> +                       continue;
> +
> +               aconnector_to_add = to_amdgpu_dm_connector(connector);
> +               if (!aconnector_to_add->port)
> +                       continue;
> +
> +               if (aconnector_to_add->port->mgr != aconnector->port->mgr)
> +                       continue;
> +
> +               if (!aconnector_to_add->dc_sink)
> +                       continue;
> +
> +               if (!aconnector_to_add->dc_sink-
> >sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
> +                       continue;
> +
> +               if (i >= AMDGPU_MAX_CRTCS)
> +                       continue;
> +
> +               crtcs_affected[i] = connector->state->crtc;
> +               i++;
> +       }
> +       drm_connector_list_iter_end(&conn_iter);
> +
> +       for (j = 0; j < i; j++) {
> +               new_crtc_state = drm_atomic_get_crtc_state(state,
> crtcs_affected[j]);
> +               if (IS_ERR(new_crtc_state))
> +                       return PTR_ERR(new_crtc_state);
> 
> +               new_crtc_state->mode_changed = true;
> +       }
> +
> +       return 0;
> +
> +}
> +#endif
>  static void get_freesync_config_for_crtc(
>         struct dm_crtc_state *new_crtc_state,
>         struct dm_connector_state *new_con_state)
> @@ -7160,6 +7226,17 @@ static int amdgpu_dm_atomic_check(struct drm_device
> *dev,
>         if (ret)
>                 goto fail;
> 
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> +       if (adev->asic_type >= CHIP_NAVI10) {
> +               for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> +                       if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
> +                               ret = add_affected_mst_dsc_crtcs(state,
> crtc);
> +                               if (ret)
> +                                       goto fail;
> +                       }
> +               }
> +       }
> +#endif
>         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
>                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
>                     !new_crtc_state->color_mgmt_changed &&
> --
> 2.17.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
-- 
Cheers,
	Lyude Paul

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Re: [PATCH v3 10/16] drm/dp-mst: Add MST support to DP DPCD R/W functions

[Lyude Paul]

On Wed, 2019-08-21 at 16:01 -0400, David Francis wrote:
> Instead of having drm_dp_dpcd_read/write and
> drm_dp_mst_dpcd_read/write as entry points into the
> aux code, have drm_dp_dpcd_read/write handle both.
> 
> This means that DRM drivers can make MST DPCD read/writes.
> 
> Cc: Leo Li <sunpeng.li@amd.com>
> Cc: Lyude Paul <lyude@redhat.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
>  drivers/gpu/drm/drm_dp_aux_dev.c | 12 ++----------
>  drivers/gpu/drm/drm_dp_helper.c  | 10 ++++++++--
>  2 files changed, 10 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c
> b/drivers/gpu/drm/drm_dp_aux_dev.c
> index 00610bd8d6c1..0780fc358389 100644
> --- a/drivers/gpu/drm/drm_dp_aux_dev.c
> +++ b/drivers/gpu/drm/drm_dp_aux_dev.c
> @@ -162,11 +162,7 @@ static ssize_t auxdev_read_iter(struct kiocb *iocb,
> struct iov_iter *to)
>  			break;
>  		}
>  
> -		if (aux_dev->aux->is_remote)
> -			res = drm_dp_mst_dpcd_read(aux_dev->aux, pos, buf,
> -						   todo);
> -		else
> -			res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
> +		res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
>  
>  		if (res <= 0)
>  			break;
> @@ -214,11 +210,7 @@ static ssize_t auxdev_write_iter(struct kiocb *iocb,
> struct iov_iter *from)
>  			break;
>  		}
>  
> -		if (aux_dev->aux->is_remote)
> -			res = drm_dp_mst_dpcd_write(aux_dev->aux, pos, buf,
> -						    todo);
> -		else
> -			res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
> +		res = drm_dp_mst_dpcd_write(aux_dev->aux, pos, buf, todo);
>  
>  		if (res <= 0)
>  			break;
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index 54a6414c5d96..9f976b90c53a 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -29,6 +29,7 @@
>  #include <linux/i2c.h>
>  #include <linux/seq_file.h>
>  #include <drm/drm_dp_helper.h>
> +#include <drm/drm_dp_mst_helper.h>
>  #include <drm/drmP.h>
>  
>  #include "drm_crtc_helper_internal.h"
> @@ -272,7 +273,7 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8
> request,
>  
>  /**
>   * drm_dp_dpcd_read() - read a series of bytes from the DPCD
> - * @aux: DisplayPort AUX channel
> + * @aux: DisplayPort AUX channel (SST or MST)
>   * @offset: address of the (first) register to read
>   * @buffer: buffer to store the register values
>   * @size: number of bytes in @buffer
> @@ -289,6 +290,8 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux,
> unsigned int offset,
>  {
>  	int ret;
>  
> +        if (aux->is_remote)
> +                return drm_dp_mst_dpcd_read(aux, offset, buffer, size);

Please follow the kernel style guidelines. We indent with tabs first, not
spaces.

>  	/*
>  	 * HP ZR24w corrupts the first DPCD access after entering power save
>  	 * mode. Eg. on a read, the entire buffer will be filled with the same
> @@ -317,7 +320,7 @@ EXPORT_SYMBOL(drm_dp_dpcd_read);
>  
>  /**
>   * drm_dp_dpcd_write() - write a series of bytes to the DPCD
> - * @aux: DisplayPort AUX channel
> + * @aux: DisplayPort AUX channel (SST or MST)
>   * @offset: address of the (first) register to write
>   * @buffer: buffer containing the values to write
>   * @size: number of bytes in @buffer
> @@ -334,6 +337,9 @@ ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux,
> unsigned int offset,
>  {
>  	int ret;
>  
> +        if (aux->is_remote)
> +                return drm_dp_mst_dpcd_write(aux, offset, buffer, size);
> +
Same here

>  	ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
>  				 size);
>  	drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
-- 
Cheers,
	Lyude Paul

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Re: [PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi

[Lyude Paul]

What branch does this patch series actually apply to? I've been trying to
apply this locally, but it doesn't appear to apply against drm-tip/drm-tip,
amdgpu-next/drm-next, or origin (e.g. kernel.org) /master. Is there any chance
we could have this go against drm-tip instead (and even better, split out the
DRM-specific bits into their own patch series?)

On Wed, 2019-08-21 at 16:01 -0400, David Francis wrote:
> This patchset enables Display Stream Compression (DSC) on DP
> connectors on Navi ASICs, both SST and DSC.
> 
> 8k60 and 4k144 support requires ODM combine, an AMD internal
> feature that may be a bit buggy right now.
> 
> Patches 1 through 5 enable DSC for SST. Most of the work was
> already done in the Navi promotion patches; this just hooks
> it up to the atomic interface. The first two reverts are of temporary
> changes to block off DSC. The third is of a commit that was
> accidentally promoted twice. The fourth and last revert fixes a
> potential issue with ODM combine.
> 
> Patches 6, 7 and 8 are fixes for bugs that would be exposed by
> MST DSC. Patches 6 and 7 add and use a new DRM helper for MST
> calculations. Patch 8 fixes a silly use-uninitialized
> 
> Patches 9, 10, and 11 are small DRM changes required for DSC MST:
> FEC, a new bit in the standard; MST DPCD from drivers; and
> a previously uninitialized variable.
> 
> Patches 12 through 16 are the DSC MST policy itself. Patch 12
> adds DSC aux access helpers to DRM, and patches 13 and 14 make
> use of those helpers. Patch 15 deals with dividing bandwidth
> fairly between multiple streams, and patch 16 ensures
> that MST CRTC that may change DSC config are reprogrammed
> 
> v2: Updating patches 6 and 14 in respoinse to Nick's feedback
> v3: Add return value to patch 6 and split it (now patches 6 & 7)
>     New patch 10 adding MST DPCD read/write support
>     Minor fix (num_ports--) to patch 11
>     Add DRM helpers (patch 12)
> 
> David Francis (16):
>   Revert "drm/amd/display: skip dsc config for navi10 bring up"
>   Revert "drm/amd/display: navi10 bring up skip dsc encoder config"
>   Revert "drm/amd/display: add global master update lock for DCN2"
>   Revert "drm/amd/display: Fix underscan not using proper scaling"
>   drm/amd/display: Enable SST DSC in DM
>   drm/dp-mst: Add PBN calculation for DSC modes
>   drm/amd/display: Use correct helpers to compute timeslots
>   drm/amd/display: Initialize DSC PPS variables to 0
>   drm/dp-mst: Parse FEC capability on MST ports
>   drm/dp-mst: Add MST support to DP DPCD R/W functions
>   drm/dp-mst: Fill branch->num_ports
>   drm/dp-mst: Add helpers for querying and enabling MST DSC
>   drm/amd/display: Validate DSC caps on MST endpoints
>   drm/amd/display: Write DSC enable to MST DPCD
>   drm/amd/display: MST DSC compute fair share
>   drm/amd/display: Trigger modesets on MST DSC connectors
> 
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 113 ++++-
>  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  33 +-
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 402 +++++++++++++++++-
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   4 +
>  drivers/gpu/drm/amd/display/dc/core/dc.c      |  12 +-
>  .../drm/amd/display/dc/core/dc_link_hwss.c    |   3 +
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |   3 +
>  .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   4 -
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  72 +---
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   3 -
>  .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
>  .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
>  .../display/dc/dcn20/dcn20_stream_encoder.c   |   8 -
>  .../amd/display/dc/inc/hw/timing_generator.h  |   2 -
>  drivers/gpu/drm/drm_dp_aux_dev.c              |  12 +-
>  drivers/gpu/drm/drm_dp_helper.c               |  10 +-
>  drivers/gpu/drm/drm_dp_mst_topology.c         | 240 +++++++++++
>  include/drm/drm_dp_mst_helper.h               |   8 +-
>  18 files changed, 806 insertions(+), 131 deletions(-)
> 
-- 
Cheers,
	Lyude Paul

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Re: [PATCH v3 13/16] drm/amd/display: Validate DSC caps on MST endpoints

[Francis, David]

Whoops, left in a test print.  Ignore this patch

________________________________________
From: David Francis <David.Francis@amd.com>
Sent: August 21, 2019 4:01 PM
To: dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Francis, David; Liu, Wenjing; Cornij, Nikola
Subject: [PATCH v3 13/16] drm/amd/display: Validate DSC caps on MST endpoints

During MST mode enumeration, if a new dc_sink is created,
populate it with dsc caps as appropriate.

Use drm_dp_mst_dsc_caps_for_port to get the raw caps,
then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.

Cc: Wenjing Liu <Wenjing.Liu@amd.com>
Cc: Nikola Cornij <Nikola.Cornij@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 27 ++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 16218a202b59..9978c1a01eb7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -25,6 +25,7 @@

 #include <linux/version.h>
 #include <drm/drm_atomic_helper.h>
+#include <drm/drm_dp_mst_helper.h>
 #include "dm_services.h"
 #include "amdgpu.h"
 #include "amdgpu_dm.h"
@@ -189,6 +190,24 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
        .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 };

+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
+{
+       struct dc_sink *dc_sink = aconnector->dc_sink;
+       struct drm_dp_mst_port *port = aconnector->port;
+       u8 dsc_caps[16] = { 0 };
+
+       if (drm_dp_mst_dsc_caps_for_port(port, dsc_caps) < 0)
+               return false;
+
+       printk("Validated DSC caps 0x%x", dsc_caps[0]);
+       if (!dc_dsc_parse_dsc_dpcd(dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps))
+               return false;
+
+       return true;
+}
+#endif
+
 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 {
        struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
@@ -231,10 +250,16 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
                /* dc_link_add_remote_sink returns a new reference */
                aconnector->dc_sink = dc_sink;

-               if (aconnector->dc_sink)
+               if (aconnector->dc_sink) {
                        amdgpu_dm_update_freesync_caps(
                                        connector, aconnector->edid);

+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+                       if (!validate_dsc_caps_on_connector(aconnector))
+                               memset(&aconnector->dc_sink->sink_dsc_caps,
+                                      0, sizeof(aconnector->dc_sink->sink_dsc_caps));
+#endif
+               }
        }

        drm_connector_update_edid_property(
--
2.17.1

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Re: [PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi

[Francis, David]

I was building against amd-staging-drm-next (commit e4a67e6cf14c).

v4 will contain just the drm-mst patches and will apply on latest drm-tip/drm-tip (commit 018886de4726)

________________________________________
From: Lyude Paul <lyude@redhat.com>
Sent: August 21, 2019 5:20 PM
To: Francis, David; dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi

What branch does this patch series actually apply to? I've been trying to
apply this locally, but it doesn't appear to apply against drm-tip/drm-tip,
amdgpu-next/drm-next, or origin (e.g. kernel.org) /master. Is there any chance
we could have this go against drm-tip instead (and even better, split out the
DRM-specific bits into their own patch series?)

On Wed, 2019-08-21 at 16:01 -0400, David Francis wrote:
> This patchset enables Display Stream Compression (DSC) on DP
> connectors on Navi ASICs, both SST and DSC.
>
> 8k60 and 4k144 support requires ODM combine, an AMD internal
> feature that may be a bit buggy right now.
>
> Patches 1 through 5 enable DSC for SST. Most of the work was
> already done in the Navi promotion patches; this just hooks
> it up to the atomic interface. The first two reverts are of temporary
> changes to block off DSC. The third is of a commit that was
> accidentally promoted twice. The fourth and last revert fixes a
> potential issue with ODM combine.
>
> Patches 6, 7 and 8 are fixes for bugs that would be exposed by
> MST DSC. Patches 6 and 7 add and use a new DRM helper for MST
> calculations. Patch 8 fixes a silly use-uninitialized
>
> Patches 9, 10, and 11 are small DRM changes required for DSC MST:
> FEC, a new bit in the standard; MST DPCD from drivers; and
> a previously uninitialized variable.
>
> Patches 12 through 16 are the DSC MST policy itself. Patch 12
> adds DSC aux access helpers to DRM, and patches 13 and 14 make
> use of those helpers. Patch 15 deals with dividing bandwidth
> fairly between multiple streams, and patch 16 ensures
> that MST CRTC that may change DSC config are reprogrammed
>
> v2: Updating patches 6 and 14 in respoinse to Nick's feedback
> v3: Add return value to patch 6 and split it (now patches 6 & 7)
>     New patch 10 adding MST DPCD read/write support
>     Minor fix (num_ports--) to patch 11
>     Add DRM helpers (patch 12)
>
> David Francis (16):
>   Revert "drm/amd/display: skip dsc config for navi10 bring up"
>   Revert "drm/amd/display: navi10 bring up skip dsc encoder config"
>   Revert "drm/amd/display: add global master update lock for DCN2"
>   Revert "drm/amd/display: Fix underscan not using proper scaling"
>   drm/amd/display: Enable SST DSC in DM
>   drm/dp-mst: Add PBN calculation for DSC modes
>   drm/amd/display: Use correct helpers to compute timeslots
>   drm/amd/display: Initialize DSC PPS variables to 0
>   drm/dp-mst: Parse FEC capability on MST ports
>   drm/dp-mst: Add MST support to DP DPCD R/W functions
>   drm/dp-mst: Fill branch->num_ports
>   drm/dp-mst: Add helpers for querying and enabling MST DSC
>   drm/amd/display: Validate DSC caps on MST endpoints
>   drm/amd/display: Write DSC enable to MST DPCD
>   drm/amd/display: MST DSC compute fair share
>   drm/amd/display: Trigger modesets on MST DSC connectors
>
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 113 ++++-
>  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  33 +-
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 402 +++++++++++++++++-
>  .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   4 +
>  drivers/gpu/drm/amd/display/dc/core/dc.c      |  12 +-
>  .../drm/amd/display/dc/core/dc_link_hwss.c    |   3 +
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |   3 +
>  .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   4 -
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  72 +---
>  .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   3 -
>  .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
>  .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
>  .../display/dc/dcn20/dcn20_stream_encoder.c   |   8 -
>  .../amd/display/dc/inc/hw/timing_generator.h  |   2 -
>  drivers/gpu/drm/drm_dp_aux_dev.c              |  12 +-
>  drivers/gpu/drm/drm_dp_helper.c               |  10 +-
>  drivers/gpu/drm/drm_dp_mst_topology.c         | 240 +++++++++++
>  include/drm/drm_dp_mst_helper.h               |   8 +-
>  18 files changed, 806 insertions(+), 131 deletions(-)
>
--
Cheers,
        Lyude Paul

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