* [PATCH 0/5] drm/msm/adreno: Introduce/rework device hw catalog
@ 2023-12-05 22:03 Rob Clark
2023-12-05 22:03 ` [PATCH 1/5] drm/msm/adreno: Split up giant device table Rob Clark
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Rob Clark @ 2023-12-05 22:03 UTC (permalink / raw)
To: dri-devel
Cc: Rob Clark, open list:SUSPEND TO RAM, Akhil P Oommen,
linux-arm-msm, Bjorn Andersson, Rafael J. Wysocki,
Douglas Anderson, open list, Konrad Dybcio,
Joel Fernandes (Google),
Dmitry Baryshkov, Marijn Suijten, Sean Paul, Stephen Boyd,
freedreno, Johan Hovold
From: Rob Clark <robdclark@chromium.org>
Split the single flat gpulist table into per-gen tables that exist in
their own per-gen files, and start moving more info into the device
table. This at least gets all the big tables of register settings out
of the heart of the a6xx_gpu code. Probably more could be moved, to
remove at least some of the per-gen if/else ladders, but this seemed
like a reasonably good start.
Rob Clark (5):
drm/msm/adreno: Split up giant device table
drm/msm/adreno: Split catalog into separate files
drm/msm/adreno: Move hwcg regs to a6xx hw catalog
drm/msm/adreno: Move hwcg table into a6xx specific info
drm/msm/adreno: Move CP_PROTECT settings to hw catalog
drivers/gpu/drm/msm/Makefile | 5 +
drivers/gpu/drm/msm/adreno/a2xx_catalog.c | 53 +
drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 75 ++
drivers/gpu/drm/msm/adreno/a4xx_catalog.c | 51 +
drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 145 +++
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1118 ++++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 817 +-------------
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 11 +
drivers/gpu/drm/msm/adreno/adreno_device.c | 559 +---------
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 22 +-
10 files changed, 1506 insertions(+), 1350 deletions(-)
create mode 100644 drivers/gpu/drm/msm/adreno/a2xx_catalog.c
create mode 100644 drivers/gpu/drm/msm/adreno/a3xx_catalog.c
create mode 100644 drivers/gpu/drm/msm/adreno/a4xx_catalog.c
create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_catalog.c
create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_catalog.c
--
2.42.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/5] drm/msm/adreno: Split up giant device table
2023-12-05 22:03 [PATCH 0/5] drm/msm/adreno: Introduce/rework device hw catalog Rob Clark
@ 2023-12-05 22:03 ` Rob Clark
2023-12-06 9:10 ` Dmitry Baryshkov
2023-12-06 12:28 ` Konrad Dybcio
2023-12-05 22:03 ` [PATCH 2/5] drm/msm/adreno: Split catalog into separate files Rob Clark
` (3 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Rob Clark @ 2023-12-05 22:03 UTC (permalink / raw)
To: dri-devel
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, Abhinav Kumar,
open list, Konrad Dybcio, Sean Paul, Dmitry Baryshkov,
Marijn Suijten, freedreno, Johan Hovold
From: Rob Clark <robdclark@chromium.org>
Split into a separate table per generation, in preparation to move each
gen's device table to it's own file.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 59 +++++++++++++++++++---
1 file changed, 51 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 41b13dec9bef..36392801f929 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -20,7 +20,7 @@ bool allow_vram_carveout = false;
MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
-static const struct adreno_info gpulist[] = {
+static const struct adreno_info a2xx_gpus[] = {
{
.chip_ids = ADRENO_CHIP_IDS(0x02000000),
.family = ADRENO_2XX_GEN1,
@@ -55,6 +55,12 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a2xx_gpu_init,
}, {
+ /* sentinal */
+ }
+};
+
+static const struct adreno_info a3xx_gpus[] = {
+ {
.chip_ids = ADRENO_CHIP_IDS(
0x03000512,
0x03000520
@@ -110,6 +116,12 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a3xx_gpu_init,
}, {
+ /* sentinal */
+ }
+};
+
+static const struct adreno_info a4xx_gpus[] = {
+ {
.chip_ids = ADRENO_CHIP_IDS(0x04000500),
.family = ADRENO_4XX,
.revn = 405,
@@ -143,6 +155,12 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a4xx_gpu_init,
}, {
+ /* sentinal */
+ }
+};
+
+static const struct adreno_info a5xx_gpus[] = {
+ {
.chip_ids = ADRENO_CHIP_IDS(0x05000600),
.family = ADRENO_5XX,
.revn = 506,
@@ -268,6 +286,12 @@ static const struct adreno_info gpulist[] = {
.init = a5xx_gpu_init,
.zapfw = "a540_zap.mdt",
}, {
+ /* sentinal */
+ }
+};
+
+static const struct adreno_info a6xx_gpus[] = {
+ {
.chip_ids = ADRENO_CHIP_IDS(0x06010000),
.family = ADRENO_6XX_GEN1,
.revn = 610,
@@ -493,6 +517,12 @@ static const struct adreno_info gpulist[] = {
.hwcg = a690_hwcg,
.address_space_size = SZ_16G,
}, {
+ /* sentinal */
+ }
+};
+
+static const struct adreno_info a7xx_gpus[] = {
+ {
.chip_ids = ADRENO_CHIP_IDS(0x07030001),
.family = ADRENO_7XX_GEN1,
.fw = {
@@ -522,7 +552,18 @@ static const struct adreno_info gpulist[] = {
.zapfw = "a740_zap.mdt",
.hwcg = a740_hwcg,
.address_space_size = SZ_16G,
- },
+ }, {
+ /* sentinal */
+ }
+};
+
+static const struct adreno_info *gpulist[] = {
+ a2xx_gpus,
+ a3xx_gpus,
+ a4xx_gpus,
+ a5xx_gpus,
+ a6xx_gpus,
+ a7xx_gpus,
};
MODULE_FIRMWARE("qcom/a300_pm4.fw");
@@ -557,12 +598,14 @@ static const struct adreno_info *adreno_info(uint32_t chip_id)
{
/* identify gpu: */
for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
- const struct adreno_info *info = &gpulist[i];
- if (info->machine && !of_machine_is_compatible(info->machine))
- continue;
- for (int j = 0; info->chip_ids[j]; j++)
- if (info->chip_ids[j] == chip_id)
- return info;
+ for (int j = 0; gpulist[i][j].chip_ids; j++) {
+ const struct adreno_info *info = &gpulist[i][j];
+ if (info->machine && !of_machine_is_compatible(info->machine))
+ continue;
+ for (int k = 0; info->chip_ids[k]; k++)
+ if (info->chip_ids[k] == chip_id)
+ return info;
+ }
}
return NULL;
--
2.42.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/5] drm/msm/adreno: Split catalog into separate files
2023-12-05 22:03 [PATCH 0/5] drm/msm/adreno: Introduce/rework device hw catalog Rob Clark
2023-12-05 22:03 ` [PATCH 1/5] drm/msm/adreno: Split up giant device table Rob Clark
@ 2023-12-05 22:03 ` Rob Clark
2023-12-06 9:11 ` Dmitry Baryshkov
2023-12-05 22:03 ` [PATCH 3/5] drm/msm/adreno: Move hwcg regs to a6xx hw catalog Rob Clark
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Rob Clark @ 2023-12-05 22:03 UTC (permalink / raw)
To: dri-devel
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, Abhinav Kumar,
open list, Konrad Dybcio, Sean Paul, Dmitry Baryshkov,
Marijn Suijten, freedreno, Johan Hovold
From: Rob Clark <robdclark@chromium.org>
Split each gen's gpu table into it's own file. Only code-motion, no
functional change.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/Makefile | 5 +
drivers/gpu/drm/msm/adreno/a2xx_catalog.c | 53 ++
drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 75 +++
drivers/gpu/drm/msm/adreno/a4xx_catalog.c | 51 ++
drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 145 ++++++
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 285 +++++++++++
drivers/gpu/drm/msm/adreno/adreno_device.c | 570 +--------------------
7 files changed, 620 insertions(+), 564 deletions(-)
create mode 100644 drivers/gpu/drm/msm/adreno/a2xx_catalog.c
create mode 100644 drivers/gpu/drm/msm/adreno/a3xx_catalog.c
create mode 100644 drivers/gpu/drm/msm/adreno/a4xx_catalog.c
create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_catalog.c
create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_catalog.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 49671364fdcf..32f2fd980452 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -7,12 +7,17 @@ ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
msm-y := \
adreno/adreno_device.o \
adreno/adreno_gpu.o \
+ adreno/a2xx_catalog.o \
adreno/a2xx_gpu.o \
+ adreno/a3xx_catalog.o \
adreno/a3xx_gpu.o \
+ adreno/a4xx_catalog.o \
adreno/a4xx_gpu.o \
+ adreno/a5xx_catalog.o \
adreno/a5xx_gpu.o \
adreno/a5xx_power.o \
adreno/a5xx_preempt.o \
+ adreno/a6xx_catalog.o \
adreno/a6xx_gpu.o \
adreno/a6xx_gmu.o \
adreno/a6xx_hfi.o \
diff --git a/drivers/gpu/drm/msm/adreno/a2xx_catalog.c b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c
new file mode 100644
index 000000000000..1a4d182279fc
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013-2014 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
+ */
+
+#include "adreno_gpu.h"
+
+const struct adreno_info a2xx_gpus[] = {
+ {
+ .chip_ids = ADRENO_CHIP_IDS(0x02000000),
+ .family = ADRENO_2XX_GEN1,
+ .revn = 200,
+ .fw = {
+ [ADRENO_FW_PM4] = "yamato_pm4.fw",
+ [ADRENO_FW_PFP] = "yamato_pfp.fw",
+ },
+ .gmem = SZ_256K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a2xx_gpu_init,
+ }, { /* a200 on i.mx51 has only 128kib gmem */
+ .chip_ids = ADRENO_CHIP_IDS(0x02000001),
+ .family = ADRENO_2XX_GEN1,
+ .revn = 201,
+ .fw = {
+ [ADRENO_FW_PM4] = "yamato_pm4.fw",
+ [ADRENO_FW_PFP] = "yamato_pfp.fw",
+ },
+ .gmem = SZ_128K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a2xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x02020000),
+ .family = ADRENO_2XX_GEN2,
+ .revn = 220,
+ .fw = {
+ [ADRENO_FW_PM4] = "leia_pm4_470.fw",
+ [ADRENO_FW_PFP] = "leia_pfp_470.fw",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a2xx_gpu_init,
+ }, {
+ /* sentinal */
+ }
+};
+
+MODULE_FIRMWARE("qcom/leia_pfp_470.fw");
+MODULE_FIRMWARE("qcom/leia_pm4_470.fw");
+MODULE_FIRMWARE("qcom/yamato_pfp.fw");
+MODULE_FIRMWARE("qcom/yamato_pm4.fw");
\ No newline at end of file
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
new file mode 100644
index 000000000000..1f1fa70c5e5e
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013-2014 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
+ */
+
+#include "adreno_gpu.h"
+
+const struct adreno_info a3xx_gpus[] = {
+ {
+ .chip_ids = ADRENO_CHIP_IDS(
+ 0x03000512,
+ 0x03000520
+ ),
+ .family = ADRENO_3XX,
+ .revn = 305,
+ .fw = {
+ [ADRENO_FW_PM4] = "a300_pm4.fw",
+ [ADRENO_FW_PFP] = "a300_pfp.fw",
+ },
+ .gmem = SZ_256K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a3xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x03000600),
+ .family = ADRENO_3XX,
+ .revn = 307, /* because a305c is revn==306 */
+ .fw = {
+ [ADRENO_FW_PM4] = "a300_pm4.fw",
+ [ADRENO_FW_PFP] = "a300_pfp.fw",
+ },
+ .gmem = SZ_128K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a3xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(
+ 0x03020000,
+ 0x03020001,
+ 0x03020002
+ ),
+ .family = ADRENO_3XX,
+ .revn = 320,
+ .fw = {
+ [ADRENO_FW_PM4] = "a300_pm4.fw",
+ [ADRENO_FW_PFP] = "a300_pfp.fw",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a3xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(
+ 0x03030000,
+ 0x03030001,
+ 0x03030002
+ ),
+ .family = ADRENO_3XX,
+ .revn = 330,
+ .fw = {
+ [ADRENO_FW_PM4] = "a330_pm4.fw",
+ [ADRENO_FW_PFP] = "a330_pfp.fw",
+ },
+ .gmem = SZ_1M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a3xx_gpu_init,
+ }, {
+ /* sentinal */
+ }
+};
+
+MODULE_FIRMWARE("qcom/a300_pm4.fw");
+MODULE_FIRMWARE("qcom/a300_pfp.fw");
+MODULE_FIRMWARE("qcom/a330_pm4.fw");
+MODULE_FIRMWARE("qcom/a330_pfp.fw");
\ No newline at end of file
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_catalog.c b/drivers/gpu/drm/msm/adreno/a4xx_catalog.c
new file mode 100644
index 000000000000..39d92cb4bcf5
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a4xx_catalog.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013-2014 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
+ */
+
+#include "adreno_gpu.h"
+
+const struct adreno_info a4xx_gpus[] = {
+ {
+ .chip_ids = ADRENO_CHIP_IDS(0x04000500),
+ .family = ADRENO_4XX,
+ .revn = 405,
+ .fw = {
+ [ADRENO_FW_PM4] = "a420_pm4.fw",
+ [ADRENO_FW_PFP] = "a420_pfp.fw",
+ },
+ .gmem = SZ_256K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a4xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x04020000),
+ .family = ADRENO_4XX,
+ .revn = 420,
+ .fw = {
+ [ADRENO_FW_PM4] = "a420_pm4.fw",
+ [ADRENO_FW_PFP] = "a420_pfp.fw",
+ },
+ .gmem = (SZ_1M + SZ_512K),
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a4xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x04030002),
+ .family = ADRENO_4XX,
+ .revn = 430,
+ .fw = {
+ [ADRENO_FW_PM4] = "a420_pm4.fw",
+ [ADRENO_FW_PFP] = "a420_pfp.fw",
+ },
+ .gmem = (SZ_1M + SZ_512K),
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a4xx_gpu_init,
+ }, {
+ /* sentinal */
+ }
+};
+
+MODULE_FIRMWARE("qcom/a420_pm4.fw");
+MODULE_FIRMWARE("qcom/a420_pfp.fw");
\ No newline at end of file
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
new file mode 100644
index 000000000000..80d70ee8c1f2
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013-2014 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
+ */
+
+#include "adreno_gpu.h"
+
+const struct adreno_info a5xx_gpus[] = {
+ {
+ .chip_ids = ADRENO_CHIP_IDS(0x05000600),
+ .family = ADRENO_5XX,
+ .revn = 506,
+ .fw = {
+ [ADRENO_FW_PM4] = "a530_pm4.fw",
+ [ADRENO_FW_PFP] = "a530_pfp.fw",
+ },
+ .gmem = (SZ_128K + SZ_8K),
+ /*
+ * Increase inactive period to 250 to avoid bouncing
+ * the GDSC which appears to make it grumpy
+ */
+ .inactive_period = 250,
+ .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
+ ADRENO_QUIRK_LMLOADKILL_DISABLE,
+ .init = a5xx_gpu_init,
+ .zapfw = "a506_zap.mdt",
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x05000800),
+ .family = ADRENO_5XX,
+ .revn = 508,
+ .fw = {
+ [ADRENO_FW_PM4] = "a530_pm4.fw",
+ [ADRENO_FW_PFP] = "a530_pfp.fw",
+ },
+ .gmem = (SZ_128K + SZ_8K),
+ /*
+ * Increase inactive period to 250 to avoid bouncing
+ * the GDSC which appears to make it grumpy
+ */
+ .inactive_period = 250,
+ .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
+ .init = a5xx_gpu_init,
+ .zapfw = "a508_zap.mdt",
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x05000900),
+ .family = ADRENO_5XX,
+ .revn = 509,
+ .fw = {
+ [ADRENO_FW_PM4] = "a530_pm4.fw",
+ [ADRENO_FW_PFP] = "a530_pfp.fw",
+ },
+ .gmem = (SZ_256K + SZ_16K),
+ /*
+ * Increase inactive period to 250 to avoid bouncing
+ * the GDSC which appears to make it grumpy
+ */
+ .inactive_period = 250,
+ .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
+ .init = a5xx_gpu_init,
+ /* Adreno 509 uses the same ZAP as 512 */
+ .zapfw = "a512_zap.mdt",
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x05010000),
+ .family = ADRENO_5XX,
+ .revn = 510,
+ .fw = {
+ [ADRENO_FW_PM4] = "a530_pm4.fw",
+ [ADRENO_FW_PFP] = "a530_pfp.fw",
+ },
+ .gmem = SZ_256K,
+ /*
+ * Increase inactive period to 250 to avoid bouncing
+ * the GDSC which appears to make it grumpy
+ */
+ .inactive_period = 250,
+ .init = a5xx_gpu_init,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x05010200),
+ .family = ADRENO_5XX,
+ .revn = 512,
+ .fw = {
+ [ADRENO_FW_PM4] = "a530_pm4.fw",
+ [ADRENO_FW_PFP] = "a530_pfp.fw",
+ },
+ .gmem = (SZ_256K + SZ_16K),
+ /*
+ * Increase inactive period to 250 to avoid bouncing
+ * the GDSC which appears to make it grumpy
+ */
+ .inactive_period = 250,
+ .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
+ .init = a5xx_gpu_init,
+ .zapfw = "a512_zap.mdt",
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(
+ 0x05030002,
+ 0x05030004
+ ),
+ .family = ADRENO_5XX,
+ .revn = 530,
+ .fw = {
+ [ADRENO_FW_PM4] = "a530_pm4.fw",
+ [ADRENO_FW_PFP] = "a530_pfp.fw",
+ [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
+ },
+ .gmem = SZ_1M,
+ /*
+ * Increase inactive period to 250 to avoid bouncing
+ * the GDSC which appears to make it grumpy
+ */
+ .inactive_period = 250,
+ .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
+ ADRENO_QUIRK_FAULT_DETECT_MASK,
+ .init = a5xx_gpu_init,
+ .zapfw = "a530_zap.mdt",
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x05040001),
+ .family = ADRENO_5XX,
+ .revn = 540,
+ .fw = {
+ [ADRENO_FW_PM4] = "a530_pm4.fw",
+ [ADRENO_FW_PFP] = "a530_pfp.fw",
+ [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
+ },
+ .gmem = SZ_1M,
+ /*
+ * Increase inactive period to 250 to avoid bouncing
+ * the GDSC which appears to make it grumpy
+ */
+ .inactive_period = 250,
+ .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
+ .init = a5xx_gpu_init,
+ .zapfw = "a540_zap.mdt",
+ }, {
+ /* sentinal */
+ }
+};
+
+MODULE_FIRMWARE("qcom/a530_pm4.fw");
+MODULE_FIRMWARE("qcom/a530_pfp.fw");
+MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
+MODULE_FIRMWARE("qcom/a540_gpmu.fw2");
\ No newline at end of file
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
new file mode 100644
index 000000000000..5c1199eab82b
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2013-2014 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ *
+ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
+ */
+
+#include "adreno_gpu.h"
+
+const struct adreno_info a6xx_gpus[] = {
+ {
+ .chip_ids = ADRENO_CHIP_IDS(0x06010000),
+ .family = ADRENO_6XX_GEN1,
+ .revn = 610,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ },
+ .gmem = (SZ_128K + SZ_4K),
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a6xx_gpu_init,
+ .zapfw = "a610_zap.mdt",
+ .hwcg = a612_hwcg,
+ /*
+ * There are (at least) three SoCs implementing A610: SM6125
+ * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
+ * not have speedbinning, as only a single SKU exists and we
+ * don't support khaje upstream yet. Hence, this matching
+ * table is only valid for bengal.
+ */
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 206, 1 },
+ { 200, 2 },
+ { 157, 3 },
+ { 127, 4 },
+ ),
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x06010800),
+ .family = ADRENO_6XX_GEN1,
+ .revn = 618,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a630_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
+ .init = a6xx_gpu_init,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 169, 1 },
+ { 174, 2 },
+ ),
+ }, {
+ .machine = "qcom,sm4350",
+ .chip_ids = ADRENO_CHIP_IDS(0x06010900),
+ .family = ADRENO_6XX_GEN1,
+ .revn = 619,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a619_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a6xx_gpu_init,
+ .zapfw = "a615_zap.mdt",
+ .hwcg = a615_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 138, 1 },
+ { 92, 2 },
+ ),
+ }, {
+ .machine = "qcom,sm6375",
+ .chip_ids = ADRENO_CHIP_IDS(0x06010901),
+ .family = ADRENO_6XX_GEN1,
+ .revn = 619,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a619_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a6xx_gpu_init,
+ .zapfw = "a615_zap.mdt",
+ .hwcg = a615_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 190, 1 },
+ { 177, 2 },
+ ),
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x06010900),
+ .family = ADRENO_6XX_GEN1,
+ .revn = 619,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a619_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
+ .init = a6xx_gpu_init,
+ .zapfw = "a615_zap.mdt",
+ .hwcg = a615_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 120, 4 },
+ { 138, 3 },
+ { 169, 2 },
+ { 180, 1 },
+ ),
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(
+ 0x06030001,
+ 0x06030002
+ ),
+ .family = ADRENO_6XX_GEN1,
+ .revn = 630,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a630_gmu.bin",
+ },
+ .gmem = SZ_1M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
+ .init = a6xx_gpu_init,
+ .zapfw = "a630_zap.mdt",
+ .hwcg = a630_hwcg,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x06040001),
+ .family = ADRENO_6XX_GEN2,
+ .revn = 640,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a640_gmu.bin",
+ },
+ .gmem = SZ_1M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
+ .init = a6xx_gpu_init,
+ .zapfw = "a640_zap.mdt",
+ .hwcg = a640_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 1, 1 },
+ ),
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x06050002),
+ .family = ADRENO_6XX_GEN3,
+ .revn = 650,
+ .fw = {
+ [ADRENO_FW_SQE] = "a650_sqe.fw",
+ [ADRENO_FW_GMU] = "a650_gmu.bin",
+ },
+ .gmem = SZ_1M + SZ_128K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
+ .init = a6xx_gpu_init,
+ .zapfw = "a650_zap.mdt",
+ .hwcg = a650_hwcg,
+ .address_space_size = SZ_16G,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 1, 1 },
+ { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */
+ { 3, 2 },
+ ),
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x06060001),
+ .family = ADRENO_6XX_GEN4,
+ .revn = 660,
+ .fw = {
+ [ADRENO_FW_SQE] = "a660_sqe.fw",
+ [ADRENO_FW_GMU] = "a660_gmu.bin",
+ },
+ .gmem = SZ_1M + SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
+ .init = a6xx_gpu_init,
+ .zapfw = "a660_zap.mdt",
+ .hwcg = a660_hwcg,
+ .address_space_size = SZ_16G,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x06030500),
+ .family = ADRENO_6XX_GEN4,
+ .fw = {
+ [ADRENO_FW_SQE] = "a660_sqe.fw",
+ [ADRENO_FW_GMU] = "a660_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
+ .init = a6xx_gpu_init,
+ .zapfw = "a660_zap.mbn",
+ .hwcg = a660_hwcg,
+ .address_space_size = SZ_16G,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 117, 0 },
+ { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */
+ { 190, 1 },
+ ),
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x06080000),
+ .family = ADRENO_6XX_GEN2,
+ .revn = 680,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a640_gmu.bin",
+ },
+ .gmem = SZ_2M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
+ .init = a6xx_gpu_init,
+ .zapfw = "a640_zap.mdt",
+ .hwcg = a640_hwcg,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x06090000),
+ .family = ADRENO_6XX_GEN4,
+ .fw = {
+ [ADRENO_FW_SQE] = "a660_sqe.fw",
+ [ADRENO_FW_GMU] = "a660_gmu.bin",
+ },
+ .gmem = SZ_4M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
+ .init = a6xx_gpu_init,
+ .zapfw = "a690_zap.mdt",
+ .hwcg = a690_hwcg,
+ .address_space_size = SZ_16G,
+ }, {
+ /* sentinal */
+ }
+};
+
+MODULE_FIRMWARE("qcom/a619_gmu.bin");
+MODULE_FIRMWARE("qcom/a630_sqe.fw");
+MODULE_FIRMWARE("qcom/a630_gmu.bin");
+MODULE_FIRMWARE("qcom/a640_gmu.bin");
+MODULE_FIRMWARE("qcom/a650_gmu.bin");
+MODULE_FIRMWARE("qcom/a650_sqe.fw");
+MODULE_FIRMWARE("qcom/a660_gmu.bin");
+MODULE_FIRMWARE("qcom/a660_sqe.fw");
+
+const struct adreno_info a7xx_gpus[] = {
+ {
+ .chip_ids = ADRENO_CHIP_IDS(0x07030001),
+ .family = ADRENO_7XX_GEN1,
+ .fw = {
+ [ADRENO_FW_SQE] = "a730_sqe.fw",
+ [ADRENO_FW_GMU] = "gmu_gen70000.bin",
+ },
+ .gmem = SZ_2M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
+ .init = a6xx_gpu_init,
+ .zapfw = "a730_zap.mdt",
+ .hwcg = a730_hwcg,
+ .address_space_size = SZ_16G,
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
+ .family = ADRENO_7XX_GEN2,
+ .fw = {
+ [ADRENO_FW_SQE] = "a740_sqe.fw",
+ [ADRENO_FW_GMU] = "gmu_gen70200.bin",
+ },
+ .gmem = 3 * SZ_1M,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV,
+ .init = a6xx_gpu_init,
+ .zapfw = "a740_zap.mdt",
+ .hwcg = a740_hwcg,
+ .address_space_size = SZ_16G,
+ }, {
+ /* sentinal */
+ }
+};
\ No newline at end of file
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 36392801f929..8af921193f1e 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -20,542 +20,12 @@ bool allow_vram_carveout = false;
MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
-static const struct adreno_info a2xx_gpus[] = {
- {
- .chip_ids = ADRENO_CHIP_IDS(0x02000000),
- .family = ADRENO_2XX_GEN1,
- .revn = 200,
- .fw = {
- [ADRENO_FW_PM4] = "yamato_pm4.fw",
- [ADRENO_FW_PFP] = "yamato_pfp.fw",
- },
- .gmem = SZ_256K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a2xx_gpu_init,
- }, { /* a200 on i.mx51 has only 128kib gmem */
- .chip_ids = ADRENO_CHIP_IDS(0x02000001),
- .family = ADRENO_2XX_GEN1,
- .revn = 201,
- .fw = {
- [ADRENO_FW_PM4] = "yamato_pm4.fw",
- [ADRENO_FW_PFP] = "yamato_pfp.fw",
- },
- .gmem = SZ_128K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a2xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x02020000),
- .family = ADRENO_2XX_GEN2,
- .revn = 220,
- .fw = {
- [ADRENO_FW_PM4] = "leia_pm4_470.fw",
- [ADRENO_FW_PFP] = "leia_pfp_470.fw",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a2xx_gpu_init,
- }, {
- /* sentinal */
- }
-};
-
-static const struct adreno_info a3xx_gpus[] = {
- {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x03000512,
- 0x03000520
- ),
- .family = ADRENO_3XX,
- .revn = 305,
- .fw = {
- [ADRENO_FW_PM4] = "a300_pm4.fw",
- [ADRENO_FW_PFP] = "a300_pfp.fw",
- },
- .gmem = SZ_256K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x03000600),
- .family = ADRENO_3XX,
- .revn = 307, /* because a305c is revn==306 */
- .fw = {
- [ADRENO_FW_PM4] = "a300_pm4.fw",
- [ADRENO_FW_PFP] = "a300_pfp.fw",
- },
- .gmem = SZ_128K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x03020000,
- 0x03020001,
- 0x03020002
- ),
- .family = ADRENO_3XX,
- .revn = 320,
- .fw = {
- [ADRENO_FW_PM4] = "a300_pm4.fw",
- [ADRENO_FW_PFP] = "a300_pfp.fw",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x03030000,
- 0x03030001,
- 0x03030002
- ),
- .family = ADRENO_3XX,
- .revn = 330,
- .fw = {
- [ADRENO_FW_PM4] = "a330_pm4.fw",
- [ADRENO_FW_PFP] = "a330_pfp.fw",
- },
- .gmem = SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- /* sentinal */
- }
-};
-
-static const struct adreno_info a4xx_gpus[] = {
- {
- .chip_ids = ADRENO_CHIP_IDS(0x04000500),
- .family = ADRENO_4XX,
- .revn = 405,
- .fw = {
- [ADRENO_FW_PM4] = "a420_pm4.fw",
- [ADRENO_FW_PFP] = "a420_pfp.fw",
- },
- .gmem = SZ_256K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a4xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x04020000),
- .family = ADRENO_4XX,
- .revn = 420,
- .fw = {
- [ADRENO_FW_PM4] = "a420_pm4.fw",
- [ADRENO_FW_PFP] = "a420_pfp.fw",
- },
- .gmem = (SZ_1M + SZ_512K),
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a4xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x04030002),
- .family = ADRENO_4XX,
- .revn = 430,
- .fw = {
- [ADRENO_FW_PM4] = "a420_pm4.fw",
- [ADRENO_FW_PFP] = "a420_pfp.fw",
- },
- .gmem = (SZ_1M + SZ_512K),
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a4xx_gpu_init,
- }, {
- /* sentinal */
- }
-};
-
-static const struct adreno_info a5xx_gpus[] = {
- {
- .chip_ids = ADRENO_CHIP_IDS(0x05000600),
- .family = ADRENO_5XX,
- .revn = 506,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_128K + SZ_8K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
- ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a506_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05000800),
- .family = ADRENO_5XX,
- .revn = 508,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_128K + SZ_8K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a508_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05000900),
- .family = ADRENO_5XX,
- .revn = 509,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_256K + SZ_16K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- /* Adreno 509 uses the same ZAP as 512 */
- .zapfw = "a512_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05010000),
- .family = ADRENO_5XX,
- .revn = 510,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = SZ_256K,
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .init = a5xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05010200),
- .family = ADRENO_5XX,
- .revn = 512,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_256K + SZ_16K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a512_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x05030002,
- 0x05030004
- ),
- .family = ADRENO_5XX,
- .revn = 530,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
- },
- .gmem = SZ_1M,
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
- ADRENO_QUIRK_FAULT_DETECT_MASK,
- .init = a5xx_gpu_init,
- .zapfw = "a530_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05040001),
- .family = ADRENO_5XX,
- .revn = 540,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
- },
- .gmem = SZ_1M,
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a540_zap.mdt",
- }, {
- /* sentinal */
- }
-};
-
-static const struct adreno_info a6xx_gpus[] = {
- {
- .chip_ids = ADRENO_CHIP_IDS(0x06010000),
- .family = ADRENO_6XX_GEN1,
- .revn = 610,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- },
- .gmem = (SZ_128K + SZ_4K),
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a610_zap.mdt",
- .hwcg = a612_hwcg,
- /*
- * There are (at least) three SoCs implementing A610: SM6125
- * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
- * not have speedbinning, as only a single SKU exists and we
- * don't support khaje upstream yet. Hence, this matching
- * table is only valid for bengal.
- */
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 206, 1 },
- { 200, 2 },
- { 157, 3 },
- { 127, 4 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06010800),
- .family = ADRENO_6XX_GEN1,
- .revn = 618,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a630_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 169, 1 },
- { 174, 2 },
- ),
- }, {
- .machine = "qcom,sm4350",
- .chip_ids = ADRENO_CHIP_IDS(0x06010900),
- .family = ADRENO_6XX_GEN1,
- .revn = 619,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a619_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 138, 1 },
- { 92, 2 },
- ),
- }, {
- .machine = "qcom,sm6375",
- .chip_ids = ADRENO_CHIP_IDS(0x06010901),
- .family = ADRENO_6XX_GEN1,
- .revn = 619,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a619_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 190, 1 },
- { 177, 2 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06010900),
- .family = ADRENO_6XX_GEN1,
- .revn = 619,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a619_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 120, 4 },
- { 138, 3 },
- { 169, 2 },
- { 180, 1 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x06030001,
- 0x06030002
- ),
- .family = ADRENO_6XX_GEN1,
- .revn = 630,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a630_gmu.bin",
- },
- .gmem = SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .zapfw = "a630_zap.mdt",
- .hwcg = a630_hwcg,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06040001),
- .family = ADRENO_6XX_GEN2,
- .revn = 640,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a640_gmu.bin",
- },
- .gmem = SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .zapfw = "a640_zap.mdt",
- .hwcg = a640_hwcg,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 1, 1 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06050002),
- .family = ADRENO_6XX_GEN3,
- .revn = 650,
- .fw = {
- [ADRENO_FW_SQE] = "a650_sqe.fw",
- [ADRENO_FW_GMU] = "a650_gmu.bin",
- },
- .gmem = SZ_1M + SZ_128K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .zapfw = "a650_zap.mdt",
- .hwcg = a650_hwcg,
- .address_space_size = SZ_16G,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 1, 1 },
- { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */
- { 3, 2 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06060001),
- .family = ADRENO_6XX_GEN4,
- .revn = 660,
- .fw = {
- [ADRENO_FW_SQE] = "a660_sqe.fw",
- [ADRENO_FW_GMU] = "a660_gmu.bin",
- },
- .gmem = SZ_1M + SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .zapfw = "a660_zap.mdt",
- .hwcg = a660_hwcg,
- .address_space_size = SZ_16G,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06030500),
- .family = ADRENO_6XX_GEN4,
- .fw = {
- [ADRENO_FW_SQE] = "a660_sqe.fw",
- [ADRENO_FW_GMU] = "a660_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .zapfw = "a660_zap.mbn",
- .hwcg = a660_hwcg,
- .address_space_size = SZ_16G,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 117, 0 },
- { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */
- { 190, 1 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06080000),
- .family = ADRENO_6XX_GEN2,
- .revn = 680,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a640_gmu.bin",
- },
- .gmem = SZ_2M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .zapfw = "a640_zap.mdt",
- .hwcg = a640_hwcg,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06090000),
- .family = ADRENO_6XX_GEN4,
- .fw = {
- [ADRENO_FW_SQE] = "a660_sqe.fw",
- [ADRENO_FW_GMU] = "a660_gmu.bin",
- },
- .gmem = SZ_4M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .zapfw = "a690_zap.mdt",
- .hwcg = a690_hwcg,
- .address_space_size = SZ_16G,
- }, {
- /* sentinal */
- }
-};
-
-static const struct adreno_info a7xx_gpus[] = {
- {
- .chip_ids = ADRENO_CHIP_IDS(0x07030001),
- .family = ADRENO_7XX_GEN1,
- .fw = {
- [ADRENO_FW_SQE] = "a730_sqe.fw",
- [ADRENO_FW_GMU] = "gmu_gen70000.bin",
- },
- .gmem = SZ_2M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .zapfw = "a730_zap.mdt",
- .hwcg = a730_hwcg,
- .address_space_size = SZ_16G,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
- .family = ADRENO_7XX_GEN2,
- .fw = {
- [ADRENO_FW_SQE] = "a740_sqe.fw",
- [ADRENO_FW_GMU] = "gmu_gen70200.bin",
- },
- .gmem = 3 * SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .zapfw = "a740_zap.mdt",
- .hwcg = a740_hwcg,
- .address_space_size = SZ_16G,
- }, {
- /* sentinal */
- }
-};
+extern const struct adreno_info a2xx_gpus[];
+extern const struct adreno_info a3xx_gpus[];
+extern const struct adreno_info a4xx_gpus[];
+extern const struct adreno_info a5xx_gpus[];
+extern const struct adreno_info a6xx_gpus[];
+extern const struct adreno_info a7xx_gpus[];
static const struct adreno_info *gpulist[] = {
a2xx_gpus,
@@ -566,34 +36,6 @@ static const struct adreno_info *gpulist[] = {
a7xx_gpus,
};
-MODULE_FIRMWARE("qcom/a300_pm4.fw");
-MODULE_FIRMWARE("qcom/a300_pfp.fw");
-MODULE_FIRMWARE("qcom/a330_pm4.fw");
-MODULE_FIRMWARE("qcom/a330_pfp.fw");
-MODULE_FIRMWARE("qcom/a420_pm4.fw");
-MODULE_FIRMWARE("qcom/a420_pfp.fw");
-MODULE_FIRMWARE("qcom/a530_pm4.fw");
-MODULE_FIRMWARE("qcom/a530_pfp.fw");
-MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
-MODULE_FIRMWARE("qcom/a530_zap.mdt");
-MODULE_FIRMWARE("qcom/a530_zap.b00");
-MODULE_FIRMWARE("qcom/a530_zap.b01");
-MODULE_FIRMWARE("qcom/a530_zap.b02");
-MODULE_FIRMWARE("qcom/a540_gpmu.fw2");
-MODULE_FIRMWARE("qcom/a619_gmu.bin");
-MODULE_FIRMWARE("qcom/a630_sqe.fw");
-MODULE_FIRMWARE("qcom/a630_gmu.bin");
-MODULE_FIRMWARE("qcom/a630_zap.mbn");
-MODULE_FIRMWARE("qcom/a640_gmu.bin");
-MODULE_FIRMWARE("qcom/a650_gmu.bin");
-MODULE_FIRMWARE("qcom/a650_sqe.fw");
-MODULE_FIRMWARE("qcom/a660_gmu.bin");
-MODULE_FIRMWARE("qcom/a660_sqe.fw");
-MODULE_FIRMWARE("qcom/leia_pfp_470.fw");
-MODULE_FIRMWARE("qcom/leia_pm4_470.fw");
-MODULE_FIRMWARE("qcom/yamato_pfp.fw");
-MODULE_FIRMWARE("qcom/yamato_pm4.fw");
-
static const struct adreno_info *adreno_info(uint32_t chip_id)
{
/* identify gpu: */
--
2.42.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/5] drm/msm/adreno: Move hwcg regs to a6xx hw catalog
2023-12-05 22:03 [PATCH 0/5] drm/msm/adreno: Introduce/rework device hw catalog Rob Clark
2023-12-05 22:03 ` [PATCH 1/5] drm/msm/adreno: Split up giant device table Rob Clark
2023-12-05 22:03 ` [PATCH 2/5] drm/msm/adreno: Split catalog into separate files Rob Clark
@ 2023-12-05 22:03 ` Rob Clark
2023-12-06 9:12 ` Dmitry Baryshkov
2023-12-05 22:03 ` [PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info Rob Clark
2023-12-05 22:03 ` [PATCH 5/5] drm/msm/adreno: Move CP_PROTECT settings to hw catalog Rob Clark
4 siblings, 1 reply; 13+ messages in thread
From: Rob Clark @ 2023-12-05 22:03 UTC (permalink / raw)
To: dri-devel
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, Bjorn Andersson,
Abhinav Kumar, Douglas Anderson, Konrad Dybcio, Sean Paul,
Dmitry Baryshkov, Marijn Suijten, freedreno, open list
From: Rob Clark <robdclark@chromium.org>
Move the hwcg tables into the hw catalog.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 560 ++++++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 558 ---------------------
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 -
3 files changed, 560 insertions(+), 561 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 5c1199eab82b..a35d4c112a61 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -7,6 +7,451 @@
*/
#include "adreno_gpu.h"
+#include "a6xx.xml.h"
+#include "a6xx_gmu.xml.h"
+
+static const struct adreno_reglist a612_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {},
+};
+
+/* For a615 family (a615, a616, a618 and a619) */
+static const struct adreno_reglist a615_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {},
+};
+
+static const struct adreno_reglist a630_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {},
+};
+
+static const struct adreno_reglist a640_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {},
+};
+
+static const struct adreno_reglist a650_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {},
+};
+
+static const struct adreno_reglist a660_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {},
+};
+
+static const struct adreno_reglist a690_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+ {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
+ {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
+ {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
+ {}
+};
const struct adreno_info a6xx_gpus[] = {
{
@@ -248,6 +693,121 @@ MODULE_FIRMWARE("qcom/a650_sqe.fw");
MODULE_FIRMWARE("qcom/a660_gmu.bin");
MODULE_FIRMWARE("qcom/a660_sqe.fw");
+static const struct adreno_reglist a730_hwcg[] = {
+ { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
+ { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
+ { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
+ { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
+ { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
+ { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
+ { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
+ { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
+ { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
+ { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
+ { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
+ { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
+ { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
+ { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
+ { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
+ { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
+ { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
+ { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
+ { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
+ { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
+ { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
+ { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
+ { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
+ { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
+ {},
+};
+
+static const struct adreno_reglist a740_hwcg[] = {
+ { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
+ { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
+ { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
+ { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
+ { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
+ { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
+ { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
+ { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
+ { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
+ { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
+ { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
+ { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
+ { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
+ { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
+ { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
+ { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
+ { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
+ { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
+ { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
+ { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
+ { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
+ { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
+ { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
+ { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
+ {},
+};
+
const struct adreno_info a7xx_gpus[] = {
{
.chip_ids = ADRENO_CHIP_IDS(0x07030001),
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 7784d7d39192..e0414d0753ad 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -394,564 +394,6 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
a6xx_flush(gpu, ring);
}
-const struct adreno_reglist a612_hwcg[] = {
- {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
- {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
- {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
- {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
- {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
- {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
- {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
- {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
- {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
- {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
- {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
- {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
- {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
- {},
-};
-
-/* For a615 family (a615, a616, a618 and a619) */
-const struct adreno_reglist a615_hwcg[] = {
- {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
- {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
- {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
- {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
- {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
- {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
- {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
- {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
- {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
- {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
- {},
-};
-
-const struct adreno_reglist a630_hwcg[] = {
- {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
- {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
- {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
- {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
- {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
- {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
- {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
- {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
- {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
- {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
- {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
- {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
- {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
- {},
-};
-
-const struct adreno_reglist a640_hwcg[] = {
- {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
- {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
- {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
- {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
- {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
- {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
- {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
- {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
- {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
- {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
- {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
- {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
- {},
-};
-
-const struct adreno_reglist a650_hwcg[] = {
- {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
- {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
- {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
- {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
- {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
- {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
- {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
- {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
- {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
- {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
- {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
- {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
- {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
- {},
-};
-
-const struct adreno_reglist a660_hwcg[] = {
- {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
- {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
- {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
- {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
- {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
- {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
- {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
- {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
- {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
- {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
- {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
- {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
- {},
-};
-
-const struct adreno_reglist a690_hwcg[] = {
- {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
- {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
- {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
- {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
- {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
- {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
- {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
- {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
- {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
- {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
- {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
- {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
- {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
- {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
- {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
- {}
-};
-
-const struct adreno_reglist a730_hwcg[] = {
- { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
- { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
- { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
- { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
- { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
- { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
- { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
- { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
- { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
- { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
- { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
- { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
- { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
- { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
- { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
- { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
- { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
- { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
- { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
- { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
- { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
- { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
- { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
- { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
- { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
- { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
- { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
- { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
- { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
- { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
- { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
- { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
- { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
- { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
- { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
- { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
- { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
- { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
- { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
- { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
- { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
- { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
- { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
- { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
- {},
-};
-
-const struct adreno_reglist a740_hwcg[] = {
- { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
- { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
- { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
- { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
- { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
- { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
- { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
- { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
- { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
- { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
- { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
- { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
- { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
- { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
- { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
- { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
- { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
- { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
- { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
- { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
- { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
- { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
- { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
- { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
- { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
- { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
- { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
- { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
- { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
- { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
- { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
- { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
- { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
- { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
- { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
- { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
- { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
- { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
- { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
- { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
- { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
- { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
- { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
- { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
- { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
- {},
-};
-
static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 80b3f6312116..5d094c5ec363 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -76,9 +76,6 @@ struct adreno_reglist {
u32 value;
};
-extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
-extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a730_hwcg[], a740_hwcg[];
-
struct adreno_speedbin {
uint16_t fuse;
uint16_t speedbin;
--
2.42.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info
2023-12-05 22:03 [PATCH 0/5] drm/msm/adreno: Introduce/rework device hw catalog Rob Clark
` (2 preceding siblings ...)
2023-12-05 22:03 ` [PATCH 3/5] drm/msm/adreno: Move hwcg regs to a6xx hw catalog Rob Clark
@ 2023-12-05 22:03 ` Rob Clark
2023-12-06 9:14 ` Dmitry Baryshkov
2023-12-05 22:03 ` [PATCH 5/5] drm/msm/adreno: Move CP_PROTECT settings to hw catalog Rob Clark
4 siblings, 1 reply; 13+ messages in thread
From: Rob Clark @ 2023-12-05 22:03 UTC (permalink / raw)
To: dri-devel
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, Bjorn Andersson,
Abhinav Kumar, Douglas Anderson, Konrad Dybcio, Sean Paul,
Dmitry Baryshkov, Marijn Suijten, freedreno, open list
From: Rob Clark <robdclark@chromium.org>
Introduce a6xx_info where we can stash gen specific stuff without
polluting the toplevel adreno_info struct.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 55 +++++++++++++++++------
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++-
4 files changed, 58 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index a35d4c112a61..3fb9e249567a 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -7,6 +7,7 @@
*/
#include "adreno_gpu.h"
+#include "a6xx_gpu.h"
#include "a6xx.xml.h"
#include "a6xx_gmu.xml.h"
@@ -465,7 +466,9 @@ const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a610_zap.mdt",
- .hwcg = a612_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a612_hwcg,
+ },
/*
* There are (at least) three SoCs implementing A610: SM6125
* (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
@@ -492,6 +495,8 @@ const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
+ .a6xx = &(struct a6xx_info) {
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 169, 1 },
@@ -510,7 +515,9 @@ const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a615_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 138, 1 },
@@ -529,7 +536,9 @@ const struct adreno_info a6xx_gpus[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a615_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 190, 1 },
@@ -548,7 +557,9 @@ const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a615_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 120, 4 },
@@ -572,7 +583,9 @@ const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a630_zap.mdt",
- .hwcg = a630_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a630_hwcg,
+ },
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06040001),
.family = ADRENO_6XX_GEN2,
@@ -586,7 +599,9 @@ const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
- .hwcg = a640_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a640_hwcg,
+ },
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
{ 1, 1 },
@@ -605,7 +620,9 @@ const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a650_zap.mdt",
- .hwcg = a650_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a650_hwcg,
+ },
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -627,7 +644,9 @@ const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a660_zap.mdt",
- .hwcg = a660_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a660_hwcg,
+ },
.address_space_size = SZ_16G,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06030500),
@@ -642,7 +661,9 @@ const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a660_zap.mbn",
- .hwcg = a660_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a660_hwcg,
+ },
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -663,7 +684,9 @@ const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
- .hwcg = a640_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a640_hwcg,
+ },
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06090000),
.family = ADRENO_6XX_GEN4,
@@ -677,7 +700,9 @@ const struct adreno_info a6xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a690_zap.mdt",
- .hwcg = a690_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a690_hwcg,
+ },
.address_space_size = SZ_16G,
}, {
/* sentinal */
@@ -822,7 +847,9 @@ const struct adreno_info a7xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a730_zap.mdt",
- .hwcg = a730_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a730_hwcg,
+ },
.address_space_size = SZ_16G,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
@@ -837,7 +864,9 @@ const struct adreno_info a7xx_gpus[] = {
ADRENO_QUIRK_HAS_HW_APRIV,
.init = a6xx_gpu_init,
.zapfw = "a740_zap.mdt",
- .hwcg = a740_hwcg,
+ .a6xx = &(struct a6xx_info) {
+ .hwcg = a740_hwcg,
+ },
.address_space_size = SZ_16G,
}, {
/* sentinal */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index e0414d0753ad..a064eb42eedd 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -403,7 +403,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
unsigned int i;
u32 val, clock_cntl_on, cgc_mode;
- if (!adreno_gpu->info->hwcg)
+ if (!adreno_gpu->info->a6xx->hwcg)
return;
if (adreno_is_a630(adreno_gpu))
@@ -434,7 +434,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
- for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
+ for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++)
gpu_write(gpu, reg->offset, state ? reg->value : 0);
/* Enable SP clock */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 34822b080759..1840c1f3308e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -12,6 +12,15 @@
extern bool hang_debug;
+/**
+ * struct a6xx_info - a6xx specific information from device table
+ *
+ * @hwcg: hw clock gating register sequence
+ */
+struct a6xx_info {
+ const struct adreno_reglist *hwcg;
+};
+
struct a6xx_gpu {
struct adreno_gpu base;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 5d094c5ec363..cba53203de98 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -81,6 +81,8 @@ struct adreno_speedbin {
uint16_t speedbin;
};
+struct a6xx_info;
+
struct adreno_info {
const char *machine;
/**
@@ -97,7 +99,9 @@ struct adreno_info {
struct msm_gpu *(*init)(struct drm_device *dev);
const char *zapfw;
u32 inactive_period;
- const struct adreno_reglist *hwcg;
+ union {
+ const struct a6xx_info *a6xx;
+ };
u64 address_space_size;
/**
* @speedbins: Optional table of fuse to speedbin mappings
--
2.42.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/5] drm/msm/adreno: Move CP_PROTECT settings to hw catalog
2023-12-05 22:03 [PATCH 0/5] drm/msm/adreno: Introduce/rework device hw catalog Rob Clark
` (3 preceding siblings ...)
2023-12-05 22:03 ` [PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info Rob Clark
@ 2023-12-05 22:03 ` Rob Clark
4 siblings, 0 replies; 13+ messages in thread
From: Rob Clark @ 2023-12-05 22:03 UTC (permalink / raw)
To: dri-devel
Cc: Rob Clark, Akhil P Oommen, linux-arm-msm, Bjorn Andersson,
Abhinav Kumar, Douglas Anderson, Konrad Dybcio, Sean Paul,
Dmitry Baryshkov, Marijn Suijten, freedreno, open list
From: Rob Clark <robdclark@chromium.org>
Move the CP_PROTECT settings into the hw catalog.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 246 ++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 255 +---------------------
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 ++
4 files changed, 266 insertions(+), 250 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 3fb9e249567a..b56e43282ce6 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -454,6 +454,173 @@ static const struct adreno_reglist a690_hwcg[] = {
{}
};
+/* For a615, a616, a618, a619, a630, a640 and a680 */
+static const u32 a630_protect_regs[] = {
+ A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
+ A6XX_PROTECT_RDONLY(0x00501, 0x0005),
+ A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
+ A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00510, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00534, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00800, 0x0082),
+ A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
+ A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
+ A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
+ A6XX_PROTECT_NORDWR(0x00900, 0x004d),
+ A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
+ A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
+ A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
+ A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
+ A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
+ A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
+ A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
+ A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
+ A6XX_PROTECT_NORDWR(0x09624, 0x01db),
+ A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
+ A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
+ A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
+ A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
+ A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
+ A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
+ A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
+ A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
+ A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
+ A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
+};
+DECLARE_ADRENO_PROTECT(a630_protect, 32);
+
+/* These are for a620 and a650 */
+static const u32 a650_protect_regs[] = {
+ A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
+ A6XX_PROTECT_RDONLY(0x00501, 0x0005),
+ A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
+ A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00510, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00534, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00800, 0x0082),
+ A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
+ A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
+ A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
+ A6XX_PROTECT_NORDWR(0x00900, 0x004d),
+ A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
+ A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
+ A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
+ A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
+ A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
+ A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
+ A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
+ A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
+ A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
+ A6XX_PROTECT_NORDWR(0x09624, 0x01db),
+ A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
+ A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
+ A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
+ A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
+ A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
+ A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
+ A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
+ A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
+ A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
+ A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
+ A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
+ A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
+ A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
+ A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
+};
+DECLARE_ADRENO_PROTECT(a650_protect, 48);
+
+/* These are for a635 and a660 */
+static const u32 a660_protect_regs[] = {
+ A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
+ A6XX_PROTECT_RDONLY(0x00501, 0x0005),
+ A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
+ A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00510, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00534, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00800, 0x0082),
+ A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
+ A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
+ A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
+ A6XX_PROTECT_NORDWR(0x00900, 0x004d),
+ A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
+ A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
+ A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
+ A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
+ A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
+ A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
+ A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
+ A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
+ A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
+ A6XX_PROTECT_NORDWR(0x09624, 0x01db),
+ A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
+ A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
+ A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
+ A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
+ A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
+ A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
+ A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
+ A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
+ A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
+ A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
+ A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
+ A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
+ A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
+ A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
+ A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
+ A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
+};
+DECLARE_ADRENO_PROTECT(a660_protect, 48);
+
+/* These are for a690 */
+static const u32 a690_protect_regs[] = {
+ A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
+ A6XX_PROTECT_RDONLY(0x00501, 0x00001),
+ A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
+ A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
+ A6XX_PROTECT_NORDWR(0x00510, 0x00000),
+ A6XX_PROTECT_NORDWR(0x00534, 0x00000),
+ A6XX_PROTECT_NORDWR(0x00800, 0x00082),
+ A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
+ A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
+ A6XX_PROTECT_RDONLY(0x008de, 0x000ae),
+ A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
+ A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
+ A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
+ A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
+ A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
+ A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
+ A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
+ A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
+ A6XX_PROTECT_NORDWR(0x08e08, 0x00007),
+ A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
+ A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
+ A6XX_PROTECT_NORDWR(0x09624, 0x001db),
+ A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
+ A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
+ A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
+ A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
+ A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
+ A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
+ A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
+ A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
+ A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
+ A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
+ A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
+ A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
+ A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
+};
+DECLARE_ADRENO_PROTECT(a690_protect, 48);
+
const struct adreno_info a6xx_gpus[] = {
{
.chip_ids = ADRENO_CHIP_IDS(0x06010000),
@@ -468,6 +635,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a610_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a612_hwcg,
+ .protect = &a630_protect,
},
/*
* There are (at least) three SoCs implementing A610: SM6125
@@ -496,6 +664,7 @@ const struct adreno_info a6xx_gpus[] = {
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
.init = a6xx_gpu_init,
.a6xx = &(struct a6xx_info) {
+ .protect = &a630_protect,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -517,6 +686,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a615_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a615_hwcg,
+ .protect = &a630_protect,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -538,6 +708,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a615_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a615_hwcg,
+ .protect = &a630_protect,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -559,6 +730,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a615_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a615_hwcg,
+ .protect = &a630_protect,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -585,6 +757,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a630_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a630_hwcg,
+ .protect = &a630_protect,
},
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06040001),
@@ -601,6 +774,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a640_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a640_hwcg,
+ .protect = &a630_protect,
},
.speedbins = ADRENO_SPEEDBINS(
{ 0, 0 },
@@ -622,6 +796,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a650_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a650_hwcg,
+ .protect = &a650_protect,
},
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
@@ -646,6 +821,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a660_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a660_hwcg,
+ .protect = &a660_protect,
},
.address_space_size = SZ_16G,
}, {
@@ -663,6 +839,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a660_zap.mbn",
.a6xx = &(struct a6xx_info) {
.hwcg = a660_hwcg,
+ .protect = &a660_protect,
},
.address_space_size = SZ_16G,
.speedbins = ADRENO_SPEEDBINS(
@@ -686,6 +863,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a640_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a640_hwcg,
+ .protect = &a630_protect,
},
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06090000),
@@ -702,6 +880,7 @@ const struct adreno_info a6xx_gpus[] = {
.zapfw = "a690_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a690_hwcg,
+ .protect = &a690_protect,
},
.address_space_size = SZ_16G,
}, {
@@ -833,6 +1012,60 @@ static const struct adreno_reglist a740_hwcg[] = {
{},
};
+static const u32 a730_protect_regs[] = {
+ A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
+ A6XX_PROTECT_RDONLY(0x0050b, 0x0058),
+ A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00510, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00534, 0x0000),
+ A6XX_PROTECT_RDONLY(0x005fb, 0x009d),
+ A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
+ A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
+ A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
+ /* 0x008d0-0x008dd are unprotected on purpose for tools like perfetto */
+ A6XX_PROTECT_RDONLY(0x008de, 0x0154),
+ A6XX_PROTECT_NORDWR(0x00900, 0x004d),
+ A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
+ A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
+ A6XX_PROTECT_NORDWR(0x00df0, 0x0001),
+ A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00e07, 0x0008),
+ A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
+ A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
+ A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
+ A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
+ A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
+ A6XX_PROTECT_NORDWR(0x08e80, 0x0280),
+ A6XX_PROTECT_NORDWR(0x09624, 0x01db),
+ A6XX_PROTECT_NORDWR(0x09e40, 0x0000),
+ A6XX_PROTECT_NORDWR(0x09e64, 0x000d),
+ A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
+ A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
+ A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
+ A6XX_PROTECT_NORDWR(0x0ae50, 0x000f),
+ A6XX_PROTECT_NORDWR(0x0ae66, 0x0003),
+ A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003),
+ A6XX_PROTECT_NORDWR(0x0b604, 0x0003),
+ A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff),
+ A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x18400, 0x0053),
+ A6XX_PROTECT_RDONLY(0x18454, 0x0004),
+ A6XX_PROTECT_NORDWR(0x18459, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x1a459, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x1c459, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
+ A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
+ A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
+ A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
+ /* CP_PROTECT_REG[44, 46] are left untouched! */
+ 0,
+ 0,
+ 0,
+ A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
+};
+DECLARE_ADRENO_PROTECT(a730_protect, 48);
+
const struct adreno_info a7xx_gpus[] = {
{
.chip_ids = ADRENO_CHIP_IDS(0x07030001),
@@ -849,6 +1082,7 @@ const struct adreno_info a7xx_gpus[] = {
.zapfw = "a730_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a730_hwcg,
+ .protect = &a730_protect,
},
.address_space_size = SZ_16G,
}, {
@@ -866,9 +1100,19 @@ const struct adreno_info a7xx_gpus[] = {
.zapfw = "a740_zap.mdt",
.a6xx = &(struct a6xx_info) {
.hwcg = a740_hwcg,
+ .protect = &a730_protect,
},
.address_space_size = SZ_16G,
}, {
/* sentinal */
}
-};
\ No newline at end of file
+};
+
+static inline void __build_asserts(void)
+{
+ BUILD_BUG_ON(a630_protect.count > a630_protect.count_max);
+ BUILD_BUG_ON(a650_protect.count > a650_protect.count_max);
+ BUILD_BUG_ON(a660_protect.count > a660_protect.count_max);
+ BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
+ BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
+}
\ No newline at end of file
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index a064eb42eedd..227149476b24 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -444,254 +444,11 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
}
-/* For a615, a616, a618, a619, a630, a640 and a680 */
-static const u32 a6xx_protect[] = {
- A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
- A6XX_PROTECT_RDONLY(0x00501, 0x0005),
- A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
- A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
- A6XX_PROTECT_NORDWR(0x00510, 0x0000),
- A6XX_PROTECT_NORDWR(0x00534, 0x0000),
- A6XX_PROTECT_NORDWR(0x00800, 0x0082),
- A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
- A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
- A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
- A6XX_PROTECT_NORDWR(0x00900, 0x004d),
- A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
- A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
- A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
- A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
- A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
- A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
- A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
- A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
- A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
- A6XX_PROTECT_NORDWR(0x09624, 0x01db),
- A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
- A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
- A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
- A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
- A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
- A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
- A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
- A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
-};
-
-/* These are for a620 and a650 */
-static const u32 a650_protect[] = {
- A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
- A6XX_PROTECT_RDONLY(0x00501, 0x0005),
- A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
- A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
- A6XX_PROTECT_NORDWR(0x00510, 0x0000),
- A6XX_PROTECT_NORDWR(0x00534, 0x0000),
- A6XX_PROTECT_NORDWR(0x00800, 0x0082),
- A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
- A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
- A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
- A6XX_PROTECT_NORDWR(0x00900, 0x004d),
- A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
- A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
- A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
- A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
- A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
- A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
- A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
- A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
- A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
- A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
- A6XX_PROTECT_NORDWR(0x09624, 0x01db),
- A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
- A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
- A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
- A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
- A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
- A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
- A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
- A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
- A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
- A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
- A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
- A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
-};
-
-/* These are for a635 and a660 */
-static const u32 a660_protect[] = {
- A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
- A6XX_PROTECT_RDONLY(0x00501, 0x0005),
- A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
- A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
- A6XX_PROTECT_NORDWR(0x00510, 0x0000),
- A6XX_PROTECT_NORDWR(0x00534, 0x0000),
- A6XX_PROTECT_NORDWR(0x00800, 0x0082),
- A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
- A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
- A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
- A6XX_PROTECT_NORDWR(0x00900, 0x004d),
- A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
- A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
- A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
- A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
- A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
- A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
- A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
- A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
- A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
- A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
- A6XX_PROTECT_NORDWR(0x09624, 0x01db),
- A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
- A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
- A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
- A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
- A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
- A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
- A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
- A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
- A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
- A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
- A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
- A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
- A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
- A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
-};
-
-/* These are for a690 */
-static const u32 a690_protect[] = {
- A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
- A6XX_PROTECT_RDONLY(0x00501, 0x00001),
- A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
- A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
- A6XX_PROTECT_NORDWR(0x00510, 0x00000),
- A6XX_PROTECT_NORDWR(0x00534, 0x00000),
- A6XX_PROTECT_NORDWR(0x00800, 0x00082),
- A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
- A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
- A6XX_PROTECT_RDONLY(0x008de, 0x000ae),
- A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
- A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
- A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
- A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
- A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
- A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
- A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
- A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
- A6XX_PROTECT_NORDWR(0x08e08, 0x00007),
- A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
- A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
- A6XX_PROTECT_NORDWR(0x09624, 0x001db),
- A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
- A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
- A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
- A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
- A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
- A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
- A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
- A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
- A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
- A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
- A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
- A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
-};
-
-static const u32 a730_protect[] = {
- A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
- A6XX_PROTECT_RDONLY(0x0050b, 0x0058),
- A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
- A6XX_PROTECT_NORDWR(0x00510, 0x0000),
- A6XX_PROTECT_NORDWR(0x00534, 0x0000),
- A6XX_PROTECT_RDONLY(0x005fb, 0x009d),
- A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
- A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
- A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
- /* 0x008d0-0x008dd are unprotected on purpose for tools like perfetto */
- A6XX_PROTECT_RDONLY(0x008de, 0x0154),
- A6XX_PROTECT_NORDWR(0x00900, 0x004d),
- A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
- A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
- A6XX_PROTECT_NORDWR(0x00df0, 0x0001),
- A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
- A6XX_PROTECT_NORDWR(0x00e07, 0x0008),
- A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
- A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
- A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
- A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
- A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
- A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
- A6XX_PROTECT_NORDWR(0x08e80, 0x0280),
- A6XX_PROTECT_NORDWR(0x09624, 0x01db),
- A6XX_PROTECT_NORDWR(0x09e40, 0x0000),
- A6XX_PROTECT_NORDWR(0x09e64, 0x000d),
- A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
- A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
- A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
- A6XX_PROTECT_NORDWR(0x0ae50, 0x000f),
- A6XX_PROTECT_NORDWR(0x0ae66, 0x0003),
- A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003),
- A6XX_PROTECT_NORDWR(0x0b604, 0x0003),
- A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff),
- A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
- A6XX_PROTECT_NORDWR(0x18400, 0x0053),
- A6XX_PROTECT_RDONLY(0x18454, 0x0004),
- A6XX_PROTECT_NORDWR(0x18459, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1a459, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1c459, 0x1fff),
- A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
- A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
- A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
- A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
- /* CP_PROTECT_REG[44, 46] are left untouched! */
- 0,
- 0,
- 0,
- A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
-};
-
static void a6xx_set_cp_protect(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
- const u32 *regs = a6xx_protect;
- unsigned i, count, count_max;
-
- if (adreno_is_a650(adreno_gpu)) {
- regs = a650_protect;
- count = ARRAY_SIZE(a650_protect);
- count_max = 48;
- BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
- } else if (adreno_is_a690(adreno_gpu)) {
- regs = a690_protect;
- count = ARRAY_SIZE(a690_protect);
- count_max = 48;
- BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48);
- } else if (adreno_is_a660_family(adreno_gpu)) {
- regs = a660_protect;
- count = ARRAY_SIZE(a660_protect);
- count_max = 48;
- BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48);
- } else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) {
- regs = a730_protect;
- count = ARRAY_SIZE(a730_protect);
- count_max = 48;
- BUILD_BUG_ON(ARRAY_SIZE(a730_protect) > 48);
- } else {
- regs = a6xx_protect;
- count = ARRAY_SIZE(a6xx_protect);
- count_max = 32;
- BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
- }
+ const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect;
+ unsigned i;
/*
* Enable access protection to privileged registers, fault on an access
@@ -703,13 +460,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN |
A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE);
- for (i = 0; i < count - 1; i++) {
+ for (i = 0; i < protect->count - 1; i++) {
/* Intentionally skip writing to some registers */
- if (regs[i])
- gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
+ if (protect->regs[i])
+ gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]);
}
/* last CP_PROTECT to have "infinite" length on the last entry */
- gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
+ gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
}
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 1840c1f3308e..0c433ff0b494 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -16,9 +16,11 @@ extern bool hang_debug;
* struct a6xx_info - a6xx specific information from device table
*
* @hwcg: hw clock gating register sequence
+ * @protect: CP_PROTECT settings
*/
struct a6xx_info {
const struct adreno_reglist *hwcg;
+ const struct adreno_protect *protect;
};
struct a6xx_gpu {
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index cba53203de98..cacf9e1e399f 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -132,6 +132,19 @@ struct adreno_info {
*/
#define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} }
+struct adreno_protect {
+ const uint32_t *regs;
+ uint32_t count;
+ uint32_t count_max;
+};
+
+#define DECLARE_ADRENO_PROTECT(name, __count_max) \
+static const struct adreno_protect name = { \
+ .regs = name ## _regs, \
+ .count = ARRAY_SIZE(name ## _regs), \
+ .count_max = __count_max, \
+};
+
struct adreno_gpu {
struct msm_gpu base;
const struct adreno_info *info;
--
2.42.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/5] drm/msm/adreno: Split up giant device table
2023-12-05 22:03 ` [PATCH 1/5] drm/msm/adreno: Split up giant device table Rob Clark
@ 2023-12-06 9:10 ` Dmitry Baryshkov
2023-12-06 12:28 ` Konrad Dybcio
1 sibling, 0 replies; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-12-06 9:10 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, freedreno, linux-arm-msm, Bjorn Andersson,
Abhinav Kumar, dri-devel, open list, Konrad Dybcio,
Marijn Suijten, Sean Paul, Johan Hovold
On Wed, 6 Dec 2023 at 00:05, Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> Split into a separate table per generation, in preparation to move each
> gen's device table to it's own file.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 59 +++++++++++++++++++---
> 1 file changed, 51 insertions(+), 8 deletions(-)
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/5] drm/msm/adreno: Split catalog into separate files
2023-12-05 22:03 ` [PATCH 2/5] drm/msm/adreno: Split catalog into separate files Rob Clark
@ 2023-12-06 9:11 ` Dmitry Baryshkov
0 siblings, 0 replies; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-12-06 9:11 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, freedreno, linux-arm-msm, Bjorn Andersson,
Abhinav Kumar, dri-devel, open list, Konrad Dybcio,
Marijn Suijten, Sean Paul, Johan Hovold
On Wed, 6 Dec 2023 at 00:06, Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> Split each gen's gpu table into it's own file. Only code-motion, no
> functional change.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/Makefile | 5 +
> drivers/gpu/drm/msm/adreno/a2xx_catalog.c | 53 ++
> drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 75 +++
> drivers/gpu/drm/msm/adreno/a4xx_catalog.c | 51 ++
> drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 145 ++++++
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 285 +++++++++++
> drivers/gpu/drm/msm/adreno/adreno_device.c | 570 +--------------------
> 7 files changed, 620 insertions(+), 564 deletions(-)
> create mode 100644 drivers/gpu/drm/msm/adreno/a2xx_catalog.c
> create mode 100644 drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> create mode 100644 drivers/gpu/drm/msm/adreno/a4xx_catalog.c
> create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_catalog.c
> create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_catalog.c
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index 49671364fdcf..32f2fd980452 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -7,12 +7,17 @@ ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
> msm-y := \
> adreno/adreno_device.o \
> adreno/adreno_gpu.o \
> + adreno/a2xx_catalog.o \
> adreno/a2xx_gpu.o \
> + adreno/a3xx_catalog.o \
> adreno/a3xx_gpu.o \
> + adreno/a4xx_catalog.o \
> adreno/a4xx_gpu.o \
> + adreno/a5xx_catalog.o \
> adreno/a5xx_gpu.o \
> adreno/a5xx_power.o \
> adreno/a5xx_preempt.o \
> + adreno/a6xx_catalog.o \
> adreno/a6xx_gpu.o \
> adreno/a6xx_gmu.o \
> adreno/a6xx_hfi.o \
> diff --git a/drivers/gpu/drm/msm/adreno/a2xx_catalog.c b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c
> new file mode 100644
> index 000000000000..1a4d182279fc
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/adreno/a2xx_catalog.c
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2013-2014 Red Hat
> + * Author: Rob Clark <robdclark@gmail.com>
> + *
> + * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
> + */
> +
> +#include "adreno_gpu.h"
> +
> +const struct adreno_info a2xx_gpus[] = {
> + {
> + .chip_ids = ADRENO_CHIP_IDS(0x02000000),
> + .family = ADRENO_2XX_GEN1,
> + .revn = 200,
> + .fw = {
> + [ADRENO_FW_PM4] = "yamato_pm4.fw",
> + [ADRENO_FW_PFP] = "yamato_pfp.fw",
> + },
> + .gmem = SZ_256K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a2xx_gpu_init,
> + }, { /* a200 on i.mx51 has only 128kib gmem */
> + .chip_ids = ADRENO_CHIP_IDS(0x02000001),
> + .family = ADRENO_2XX_GEN1,
> + .revn = 201,
> + .fw = {
> + [ADRENO_FW_PM4] = "yamato_pm4.fw",
> + [ADRENO_FW_PFP] = "yamato_pfp.fw",
> + },
> + .gmem = SZ_128K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a2xx_gpu_init,
> + }, {
> + .chip_ids = ADRENO_CHIP_IDS(0x02020000),
> + .family = ADRENO_2XX_GEN2,
> + .revn = 220,
> + .fw = {
> + [ADRENO_FW_PM4] = "leia_pm4_470.fw",
> + [ADRENO_FW_PFP] = "leia_pfp_470.fw",
> + },
> + .gmem = SZ_512K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .init = a2xx_gpu_init,
> + }, {
> + /* sentinal */
> + }
> +};
> +
> +MODULE_FIRMWARE("qcom/leia_pfp_470.fw");
> +MODULE_FIRMWARE("qcom/leia_pm4_470.fw");
> +MODULE_FIRMWARE("qcom/yamato_pfp.fw");
> +MODULE_FIRMWARE("qcom/yamato_pm4.fw");
> \ No newline at end of file
Nit: you might want to fix newlines (here and in other catalog files).
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/5] drm/msm/adreno: Move hwcg regs to a6xx hw catalog
2023-12-05 22:03 ` [PATCH 3/5] drm/msm/adreno: Move hwcg regs to a6xx hw catalog Rob Clark
@ 2023-12-06 9:12 ` Dmitry Baryshkov
0 siblings, 0 replies; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-12-06 9:12 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, freedreno, Akhil P Oommen, linux-arm-msm,
Bjorn Andersson, Abhinav Kumar, dri-devel, Douglas Anderson,
Konrad Dybcio, Marijn Suijten, Sean Paul, open list
On Wed, 6 Dec 2023 at 00:06, Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> Move the hwcg tables into the hw catalog.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 560 ++++++++++++++++++++++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 558 ---------------------
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 -
> 3 files changed, 560 insertions(+), 561 deletions(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info
2023-12-05 22:03 ` [PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info Rob Clark
@ 2023-12-06 9:14 ` Dmitry Baryshkov
0 siblings, 0 replies; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-12-06 9:14 UTC (permalink / raw)
To: Rob Clark
Cc: Rob Clark, freedreno, Akhil P Oommen, linux-arm-msm,
Bjorn Andersson, Abhinav Kumar, dri-devel, Douglas Anderson,
Konrad Dybcio, Marijn Suijten, Sean Paul, open list
On Wed, 6 Dec 2023 at 00:06, Rob Clark <robdclark@gmail.com> wrote:
>
> From: Rob Clark <robdclark@chromium.org>
>
> Introduce a6xx_info where we can stash gen specific stuff without
> polluting the toplevel adreno_info struct.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 55 +++++++++++++++++------
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++-
> 4 files changed, 58 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index a35d4c112a61..3fb9e249567a 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -7,6 +7,7 @@
> */
>
> #include "adreno_gpu.h"
> +#include "a6xx_gpu.h"
> #include "a6xx.xml.h"
> #include "a6xx_gmu.xml.h"
>
> @@ -465,7 +466,9 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> .zapfw = "a610_zap.mdt",
> - .hwcg = a612_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a612_hwcg,
> + },
> /*
> * There are (at least) three SoCs implementing A610: SM6125
> * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
> @@ -492,6 +495,8 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> + .a6xx = &(struct a6xx_info) {
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 169, 1 },
> @@ -510,7 +515,9 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> - .hwcg = a615_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a615_hwcg,
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 138, 1 },
> @@ -529,7 +536,9 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> - .hwcg = a615_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a615_hwcg,
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 190, 1 },
> @@ -548,7 +557,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> - .hwcg = a615_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a615_hwcg,
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 120, 4 },
> @@ -572,7 +583,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a630_zap.mdt",
> - .hwcg = a630_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a630_hwcg,
> + },
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x06040001),
> .family = ADRENO_6XX_GEN2,
> @@ -586,7 +599,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> - .hwcg = a640_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a640_hwcg,
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 1, 1 },
> @@ -605,7 +620,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a650_zap.mdt",
> - .hwcg = a650_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a650_hwcg,
> + },
> .address_space_size = SZ_16G,
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> @@ -627,7 +644,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a660_zap.mdt",
> - .hwcg = a660_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a660_hwcg,
> + },
> .address_space_size = SZ_16G,
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x06030500),
> @@ -642,7 +661,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a660_zap.mbn",
> - .hwcg = a660_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a660_hwcg,
> + },
> .address_space_size = SZ_16G,
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> @@ -663,7 +684,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> - .hwcg = a640_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a640_hwcg,
> + },
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x06090000),
> .family = ADRENO_6XX_GEN4,
> @@ -677,7 +700,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a690_zap.mdt",
> - .hwcg = a690_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a690_hwcg,
> + },
> .address_space_size = SZ_16G,
> }, {
> /* sentinal */
> @@ -822,7 +847,9 @@ const struct adreno_info a7xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a730_zap.mdt",
> - .hwcg = a730_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a730_hwcg,
> + },
> .address_space_size = SZ_16G,
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
> @@ -837,7 +864,9 @@ const struct adreno_info a7xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a740_zap.mdt",
> - .hwcg = a740_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a740_hwcg,
> + },
> .address_space_size = SZ_16G,
> }, {
> /* sentinal */
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index e0414d0753ad..a064eb42eedd 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -403,7 +403,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> unsigned int i;
> u32 val, clock_cntl_on, cgc_mode;
>
> - if (!adreno_gpu->info->hwcg)
> + if (!adreno_gpu->info->a6xx->hwcg)
> return;
>
> if (adreno_is_a630(adreno_gpu))
> @@ -434,7 +434,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
> gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
>
> - for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
> + for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++)
> gpu_write(gpu, reg->offset, state ? reg->value : 0);
>
> /* Enable SP clock */
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index 34822b080759..1840c1f3308e 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -12,6 +12,15 @@
>
> extern bool hang_debug;
>
> +/**
> + * struct a6xx_info - a6xx specific information from device table
> + *
> + * @hwcg: hw clock gating register sequence
> + */
> +struct a6xx_info {
> + const struct adreno_reglist *hwcg;
> +};
> +
> struct a6xx_gpu {
> struct adreno_gpu base;
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 5d094c5ec363..cba53203de98 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -81,6 +81,8 @@ struct adreno_speedbin {
> uint16_t speedbin;
> };
>
> +struct a6xx_info;
> +
> struct adreno_info {
> const char *machine;
> /**
> @@ -97,7 +99,9 @@ struct adreno_info {
> struct msm_gpu *(*init)(struct drm_device *dev);
> const char *zapfw;
> u32 inactive_period;
> - const struct adreno_reglist *hwcg;
> + union {
> + const struct a6xx_info *a6xx;
> + };
I think the usual pattern is to subclass the common structure rather
than adding a polymorphic field.
So, from my point of view, it should be:
struct a6xx_info {
struct adreno_info base;
struct areno_reglist *hwcg;
};
> u64 address_space_size;
> /**
> * @speedbins: Optional table of fuse to speedbin mappings
> --
> 2.42.0
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/5] drm/msm/adreno: Split up giant device table
2023-12-05 22:03 ` [PATCH 1/5] drm/msm/adreno: Split up giant device table Rob Clark
2023-12-06 9:10 ` Dmitry Baryshkov
@ 2023-12-06 12:28 ` Konrad Dybcio
2023-12-06 12:49 ` Dmitry Baryshkov
2023-12-06 17:08 ` Rob Clark
1 sibling, 2 replies; 13+ messages in thread
From: Konrad Dybcio @ 2023-12-06 12:28 UTC (permalink / raw)
To: Rob Clark, dri-devel
Cc: Rob Clark, freedreno, linux-arm-msm, Bjorn Andersson,
Abhinav Kumar, open list, Dmitry Baryshkov, Marijn Suijten,
Sean Paul, Johan Hovold
On 12/5/23 23:03, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Split into a separate table per generation, in preparation to move each
> gen's device table to it's own file.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 59 +++++++++++++++++++---
> 1 file changed, 51 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 41b13dec9bef..36392801f929 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -20,7 +20,7 @@ bool allow_vram_carveout = false;
> MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
> module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
>
> -static const struct adreno_info gpulist[] = {
> +static const struct adreno_info a2xx_gpus[] = {
> {
> .chip_ids = ADRENO_CHIP_IDS(0x02000000),
> .family = ADRENO_2XX_GEN1,
> @@ -55,6 +55,12 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a2xx_gpu_init,
> }, {
> + /* sentinal */
sentinel?
> + }
> +};
> +
> +static const struct adreno_info a3xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(
> 0x03000512,
> 0x03000520
> @@ -110,6 +116,12 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a3xx_gpu_init,
> }, {
> + /* sentinal */
> + }
> +};
> +
> +static const struct adreno_info a4xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(0x04000500),
> .family = ADRENO_4XX,
> .revn = 405,
> @@ -143,6 +155,12 @@ static const struct adreno_info gpulist[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a4xx_gpu_init,
> }, {
> + /* sentinal */
> + }
> +};
> +
> +static const struct adreno_info a5xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(0x05000600),
> .family = ADRENO_5XX,
> .revn = 506,
> @@ -268,6 +286,12 @@ static const struct adreno_info gpulist[] = {
> .init = a5xx_gpu_init,
> .zapfw = "a540_zap.mdt",
> }, {
> + /* sentinal */
> + }
> +};
> +
> +static const struct adreno_info a6xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(0x06010000),
> .family = ADRENO_6XX_GEN1,
> .revn = 610,
> @@ -493,6 +517,12 @@ static const struct adreno_info gpulist[] = {
> .hwcg = a690_hwcg,
> .address_space_size = SZ_16G,
> }, {
> + /* sentinal */
> + }
> +};
> +
> +static const struct adreno_info a7xx_gpus[] = {
> + {
> .chip_ids = ADRENO_CHIP_IDS(0x07030001),
> .family = ADRENO_7XX_GEN1,
> .fw = {
> @@ -522,7 +552,18 @@ static const struct adreno_info gpulist[] = {
> .zapfw = "a740_zap.mdt",
> .hwcg = a740_hwcg,
> .address_space_size = SZ_16G,
> - },
> + }, {
> + /* sentinal */
> + }
> +};
> +
> +static const struct adreno_info *gpulist[] = {
> + a2xx_gpus,
> + a3xx_gpus,
> + a4xx_gpus,
> + a5xx_gpus,
> + a6xx_gpus,
> + a7xx_gpus,
> };
>
> MODULE_FIRMWARE("qcom/a300_pm4.fw");
> @@ -557,12 +598,14 @@ static const struct adreno_info *adreno_info(uint32_t chip_id)
> {
> /* identify gpu: */
> for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> - const struct adreno_info *info = &gpulist[i];
> - if (info->machine && !of_machine_is_compatible(info->machine))
> - continue;
> - for (int j = 0; info->chip_ids[j]; j++)
I'm not sure using sentinels here is a good idea, it adds a
whole lot of stack size. Perhaps gpulist could be a struct
of array pointers and an array of sizes?
Konrad
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/5] drm/msm/adreno: Split up giant device table
2023-12-06 12:28 ` Konrad Dybcio
@ 2023-12-06 12:49 ` Dmitry Baryshkov
2023-12-06 17:08 ` Rob Clark
1 sibling, 0 replies; 13+ messages in thread
From: Dmitry Baryshkov @ 2023-12-06 12:49 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, Abhinav Kumar,
dri-devel, open list, Sean Paul, Marijn Suijten, freedreno,
Johan Hovold
On Wed, 6 Dec 2023 at 14:29, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 12/5/23 23:03, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Split into a separate table per generation, in preparation to move each
> > gen's device table to it's own file.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 59 +++++++++++++++++++---
> > 1 file changed, 51 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index 41b13dec9bef..36392801f929 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -20,7 +20,7 @@ bool allow_vram_carveout = false;
> > MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
> > module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
> >
> > -static const struct adreno_info gpulist[] = {
> > +static const struct adreno_info a2xx_gpus[] = {
> > {
> > .chip_ids = ADRENO_CHIP_IDS(0x02000000),
> > .family = ADRENO_2XX_GEN1,
> > @@ -55,6 +55,12 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a2xx_gpu_init,
> > }, {
> > + /* sentinal */
> sentinel?
>
> > + }
> > +};
> > +
> > +static const struct adreno_info a3xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(
> > 0x03000512,
> > 0x03000520
> > @@ -110,6 +116,12 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a3xx_gpu_init,
> > }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info a4xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(0x04000500),
> > .family = ADRENO_4XX,
> > .revn = 405,
> > @@ -143,6 +155,12 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a4xx_gpu_init,
> > }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info a5xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(0x05000600),
> > .family = ADRENO_5XX,
> > .revn = 506,
> > @@ -268,6 +286,12 @@ static const struct adreno_info gpulist[] = {
> > .init = a5xx_gpu_init,
> > .zapfw = "a540_zap.mdt",
> > }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info a6xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(0x06010000),
> > .family = ADRENO_6XX_GEN1,
> > .revn = 610,
> > @@ -493,6 +517,12 @@ static const struct adreno_info gpulist[] = {
> > .hwcg = a690_hwcg,
> > .address_space_size = SZ_16G,
> > }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info a7xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(0x07030001),
> > .family = ADRENO_7XX_GEN1,
> > .fw = {
> > @@ -522,7 +552,18 @@ static const struct adreno_info gpulist[] = {
> > .zapfw = "a740_zap.mdt",
> > .hwcg = a740_hwcg,
> > .address_space_size = SZ_16G,
> > - },
> > + }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info *gpulist[] = {
> > + a2xx_gpus,
> > + a3xx_gpus,
> > + a4xx_gpus,
> > + a5xx_gpus,
> > + a6xx_gpus,
> > + a7xx_gpus,
> > };
> >
> > MODULE_FIRMWARE("qcom/a300_pm4.fw");
> > @@ -557,12 +598,14 @@ static const struct adreno_info *adreno_info(uint32_t chip_id)
> > {
> > /* identify gpu: */
> > for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > - const struct adreno_info *info = &gpulist[i];
> > - if (info->machine && !of_machine_is_compatible(info->machine))
> > - continue;
> > - for (int j = 0; info->chip_ids[j]; j++)
> I'm not sure using sentinels here is a good idea, it adds a
> whole lot of stack size. Perhaps gpulist could be a struct
> of array pointers and an array of sizes?
My 2c would be to reimplement it as a of_device_id.data and thus the
device_match_data.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/5] drm/msm/adreno: Split up giant device table
2023-12-06 12:28 ` Konrad Dybcio
2023-12-06 12:49 ` Dmitry Baryshkov
@ 2023-12-06 17:08 ` Rob Clark
1 sibling, 0 replies; 13+ messages in thread
From: Rob Clark @ 2023-12-06 17:08 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, Abhinav Kumar,
dri-devel, open list, Sean Paul, Dmitry Baryshkov,
Marijn Suijten, freedreno, Johan Hovold
On Wed, Dec 6, 2023 at 4:29 AM Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 12/5/23 23:03, Rob Clark wrote:
> > From: Rob Clark <robdclark@chromium.org>
> >
> > Split into a separate table per generation, in preparation to move each
> > gen's device table to it's own file.
> >
> > Signed-off-by: Rob Clark <robdclark@chromium.org>
> > ---
> > drivers/gpu/drm/msm/adreno/adreno_device.c | 59 +++++++++++++++++++---
> > 1 file changed, 51 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > index 41b13dec9bef..36392801f929 100644
> > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> > @@ -20,7 +20,7 @@ bool allow_vram_carveout = false;
> > MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
> > module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
> >
> > -static const struct adreno_info gpulist[] = {
> > +static const struct adreno_info a2xx_gpus[] = {
> > {
> > .chip_ids = ADRENO_CHIP_IDS(0x02000000),
> > .family = ADRENO_2XX_GEN1,
> > @@ -55,6 +55,12 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a2xx_gpu_init,
> > }, {
> > + /* sentinal */
> sentinel?
>
> > + }
> > +};
> > +
> > +static const struct adreno_info a3xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(
> > 0x03000512,
> > 0x03000520
> > @@ -110,6 +116,12 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a3xx_gpu_init,
> > }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info a4xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(0x04000500),
> > .family = ADRENO_4XX,
> > .revn = 405,
> > @@ -143,6 +155,12 @@ static const struct adreno_info gpulist[] = {
> > .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> > .init = a4xx_gpu_init,
> > }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info a5xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(0x05000600),
> > .family = ADRENO_5XX,
> > .revn = 506,
> > @@ -268,6 +286,12 @@ static const struct adreno_info gpulist[] = {
> > .init = a5xx_gpu_init,
> > .zapfw = "a540_zap.mdt",
> > }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info a6xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(0x06010000),
> > .family = ADRENO_6XX_GEN1,
> > .revn = 610,
> > @@ -493,6 +517,12 @@ static const struct adreno_info gpulist[] = {
> > .hwcg = a690_hwcg,
> > .address_space_size = SZ_16G,
> > }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info a7xx_gpus[] = {
> > + {
> > .chip_ids = ADRENO_CHIP_IDS(0x07030001),
> > .family = ADRENO_7XX_GEN1,
> > .fw = {
> > @@ -522,7 +552,18 @@ static const struct adreno_info gpulist[] = {
> > .zapfw = "a740_zap.mdt",
> > .hwcg = a740_hwcg,
> > .address_space_size = SZ_16G,
> > - },
> > + }, {
> > + /* sentinal */
> > + }
> > +};
> > +
> > +static const struct adreno_info *gpulist[] = {
> > + a2xx_gpus,
> > + a3xx_gpus,
> > + a4xx_gpus,
> > + a5xx_gpus,
> > + a6xx_gpus,
> > + a7xx_gpus,
> > };
> >
> > MODULE_FIRMWARE("qcom/a300_pm4.fw");
> > @@ -557,12 +598,14 @@ static const struct adreno_info *adreno_info(uint32_t chip_id)
> > {
> > /* identify gpu: */
> > for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
> > - const struct adreno_info *info = &gpulist[i];
> > - if (info->machine && !of_machine_is_compatible(info->machine))
> > - continue;
> > - for (int j = 0; info->chip_ids[j]; j++)
> I'm not sure using sentinels here is a good idea, it adds a
> whole lot of stack size. Perhaps gpulist could be a struct
> of array pointers and an array of sizes?
I guess you meant text size..
But with 30 devices currently, that array would be (30 + 7) * 8 = 296
bytes.. each sentinel is ~112 bytes (and arguably we could move a bit
more out of adreno_info). So it isn't that big of a difference.
Being able to have aNxx_info subclass adreno_effort might be a more
compelling reason to go for an array of pointers. I'd have to see how
awkward that looks.
BR,
-R
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-12-06 17:08 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-12-05 22:03 [PATCH 0/5] drm/msm/adreno: Introduce/rework device hw catalog Rob Clark
2023-12-05 22:03 ` [PATCH 1/5] drm/msm/adreno: Split up giant device table Rob Clark
2023-12-06 9:10 ` Dmitry Baryshkov
2023-12-06 12:28 ` Konrad Dybcio
2023-12-06 12:49 ` Dmitry Baryshkov
2023-12-06 17:08 ` Rob Clark
2023-12-05 22:03 ` [PATCH 2/5] drm/msm/adreno: Split catalog into separate files Rob Clark
2023-12-06 9:11 ` Dmitry Baryshkov
2023-12-05 22:03 ` [PATCH 3/5] drm/msm/adreno: Move hwcg regs to a6xx hw catalog Rob Clark
2023-12-06 9:12 ` Dmitry Baryshkov
2023-12-05 22:03 ` [PATCH 4/5] drm/msm/adreno: Move hwcg table into a6xx specific info Rob Clark
2023-12-06 9:14 ` Dmitry Baryshkov
2023-12-05 22:03 ` [PATCH 5/5] drm/msm/adreno: Move CP_PROTECT settings to hw catalog Rob Clark
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