* [PATCH v3 01/43] drm/rockchip: Get rid of unnecessary struct fields
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
@ 2018-01-30 20:28 ` Thierry Escande
2018-02-18 10:50 ` Heiko Stuebner
2018-01-30 20:28 ` [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind Thierry Escande
` (27 subsequent siblings)
28 siblings, 1 reply; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
This patch removes unused fields from vop structure.
Signed-off-by: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index ba7505292b78..7a137bc5708c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -95,9 +95,6 @@ struct vop {
struct drm_device *drm_dev;
bool is_enabled;
- /* mutex vsync_ work */
- struct mutex vsync_mutex;
- bool vsync_work_pending;
struct completion dsp_hold_completion;
/* protected by dev->event_lock */
@@ -1567,8 +1564,6 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
spin_lock_init(&vop->reg_lock);
spin_lock_init(&vop->irq_lock);
- mutex_init(&vop->vsync_mutex);
-
ret = devm_request_irq(dev, vop->irq, vop_isr,
IRQF_SHARED, dev_name(dev), vop);
if (ret)
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 01/43] drm/rockchip: Get rid of unnecessary struct fields
2018-01-30 20:28 ` [PATCH v3 01/43] drm/rockchip: Get rid of unnecessary struct fields Thierry Escande
@ 2018-02-18 10:50 ` Heiko Stuebner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stuebner @ 2018-02-18 10:50 UTC (permalink / raw)
To: linux-rockchip
Cc: Thierry Escande, Archit Taneja, Inki Dae, Thierry Reding,
Sandy Huang, Sean Paul, David Airlie, Tomasz Figa,
Enric Balletbo i Serra, Zain Wang, Lin Huang, Douglas Anderson,
dri-devel, linux-kernel, Yakir Yang, Ørjan Eide, Mark Yao,
Haixia Shi
Am Dienstag, 30. Januar 2018, 21:28:31 CET schrieb Thierry Escande:
> From: Tomasz Figa <tfiga@chromium.org>
>
> This patch removes unused fields from vop structure.
>
> Signed-off-by: Tomasz Figa <tfiga@chromium.org>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
applied to drm-misc
Thanks
Heiko
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2018-01-30 20:28 ` [PATCH v3 01/43] drm/rockchip: Get rid of unnecessary struct fields Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-02-28 14:37 ` Heiko Stübner
` (2 more replies)
2018-01-30 20:28 ` [PATCH v3 06/43] drm/rockchip: Don't use atomic constructs for psr Thierry Escande
` (26 subsequent siblings)
28 siblings, 3 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz@rock-chips.com>
The bridge does not need to be powered in analogix_dp_bind(), so
remove the calls to pm_runtime_get()/phy_power_on()/analogix_dp_init_dp()
as well as their power-off counterparts.
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
[the patch originally just removed the power_on portion, seanpaul removed
the power off code as well as improved the commit message]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index cb5e18d6ba04..1477ea9ba85d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1382,11 +1382,6 @@ analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
pm_runtime_enable(dev);
- pm_runtime_get_sync(dev);
- phy_power_on(dp->phy);
-
- analogix_dp_init_dp(dp);
-
ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
analogix_dp_hardirq,
analogix_dp_irq_thread,
@@ -1414,15 +1409,10 @@ analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
goto err_disable_pm_runtime;
}
- phy_power_off(dp->phy);
- pm_runtime_put(dev);
-
return dp;
err_disable_pm_runtime:
- phy_power_off(dp->phy);
- pm_runtime_put(dev);
pm_runtime_disable(dev);
return ERR_PTR(ret);
--
2.14.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind
2018-01-30 20:28 ` [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind Thierry Escande
@ 2018-02-28 14:37 ` Heiko Stübner
2018-02-28 14:54 ` Marc Zyngier
2018-02-28 15:20 ` Heiko Stübner
2018-03-01 13:37 ` Marek Szyprowski
2 siblings, 1 reply; 62+ messages in thread
From: Heiko Stübner @ 2018-02-28 14:37 UTC (permalink / raw)
To: linux-rockchip, Marc Zyngier
Cc: Douglas Anderson, Thierry Escande, Lin Huang, David Airlie,
linux-kernel, dri-devel, Tomasz Figa, Thierry Reding, Yakir Yang,
Enric Balletbo i Serra, Ørjan Eide, Haixia Shi, Zain Wang,
Mark Yao
Am Dienstag, 30. Januar 2018, 21:28:35 CET schrieb Thierry Escande:
> From: zain wang <wzz@rock-chips.com>
>
> The bridge does not need to be powered in analogix_dp_bind(), so
> remove the calls to pm_runtime_get()/phy_power_on()/analogix_dp_init_dp()
> as well as their power-off counterparts.
>
> Cc: Stéphane Marchesin <marcheu@chromium.org>
> Signed-off-by: zain wang <wzz@rock-chips.com>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> [the patch originally just removed the power_on portion, seanpaul removed
> the power off code as well as improved the commit message]
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
> ---
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index
> cb5e18d6ba04..1477ea9ba85d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -1382,11 +1382,6 @@ analogix_dp_bind(struct device *dev, struct
> drm_device *drm_dev,
>
> pm_runtime_enable(dev);
>
> - pm_runtime_get_sync(dev);
> - phy_power_on(dp->phy);
> -
> - analogix_dp_init_dp(dp);
> -
> ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
> analogix_dp_hardirq,
> analogix_dp_irq_thread,
Not 100% sure here, as the driver has the request-irq + disable-irq hack
here. So a pending interrupt could possibly fire between request and
disable.
Right now the block should be on, but can it still handle such an irq
when the power is removed?
So before removing the power here, we might want something
similar to what Marc posted for the vop [0] for the analogix-dp?
Heiko
[0] https://patchwork.kernel.org/patch/10210513/
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind
2018-02-28 14:37 ` Heiko Stübner
@ 2018-02-28 14:54 ` Marc Zyngier
2018-02-28 14:56 ` Heiko Stübner
0 siblings, 1 reply; 62+ messages in thread
From: Marc Zyngier @ 2018-02-28 14:54 UTC (permalink / raw)
To: Heiko Stübner, linux-rockchip
Cc: Thierry Escande, Archit Taneja, Inki Dae, Thierry Reding,
Sandy Huang, Sean Paul, David Airlie, Tomasz Figa,
Enric Balletbo i Serra, Zain Wang, Lin Huang, Douglas Anderson,
dri-devel, linux-kernel, Yakir Yang, Ørjan Eide, Mark Yao,
Haixia Shi
On 28/02/18 14:37, Heiko Stübner wrote:
> Am Dienstag, 30. Januar 2018, 21:28:35 CET schrieb Thierry Escande:
>> From: zain wang <wzz@rock-chips.com>
>>
>> The bridge does not need to be powered in analogix_dp_bind(), so
>> remove the calls to pm_runtime_get()/phy_power_on()/analogix_dp_init_dp()
>> as well as their power-off counterparts.
>>
>> Cc: Stéphane Marchesin <marcheu@chromium.org>
>> Signed-off-by: zain wang <wzz@rock-chips.com>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> [the patch originally just removed the power_on portion, seanpaul removed
>> the power off code as well as improved the commit message]
>> Signed-off-by: Sean Paul <seanpaul@chromium.org>
>> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
>> ---
>> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ----------
>> 1 file changed, 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index
>> cb5e18d6ba04..1477ea9ba85d 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -1382,11 +1382,6 @@ analogix_dp_bind(struct device *dev, struct
>> drm_device *drm_dev,
>>
>> pm_runtime_enable(dev);
>>
>> - pm_runtime_get_sync(dev);
>> - phy_power_on(dp->phy);
>> -
>> - analogix_dp_init_dp(dp);
>> -
>> ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
>> analogix_dp_hardirq,
>> analogix_dp_irq_thread,
>
> Not 100% sure here, as the driver has the request-irq + disable-irq hack
> here. So a pending interrupt could possibly fire between request and
> disable.
>
> Right now the block should be on, but can it still handle such an irq
> when the power is removed?
Probably not (see below).
> So before removing the power here, we might want something
> similar to what Marc posted for the vop [0] for the analogix-dp?
You can do that trick only if the interrupt is not shared. In the VOP
case, it is shared with the IOMMU, which makes it more... interesting.
And when it comes to power and the analogix-dp driver, I've been
carrying this[1] for a while. Fully exploitable from userspace. I know
it is about to be replaced by this series, but at least 4.15 and 4.16
are affected.
M.
[1] https://www.spinics.net/lists/arm-kernel/msg623892.html
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind
2018-02-28 14:54 ` Marc Zyngier
@ 2018-02-28 14:56 ` Heiko Stübner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2018-02-28 14:56 UTC (permalink / raw)
To: Marc Zyngier
Cc: Douglas Anderson, Thierry Escande, Lin Huang, David Airlie,
linux-kernel, dri-devel, Tomasz Figa, linux-rockchip,
Thierry Reding, Yakir Yang, Enric Balletbo i Serra,
Ørjan Eide, Haixia Shi, Zain Wang, Mark Yao
Am Mittwoch, 28. Februar 2018, 15:54:30 CET schrieb Marc Zyngier:
> On 28/02/18 14:37, Heiko Stübner wrote:
> > Am Dienstag, 30. Januar 2018, 21:28:35 CET schrieb Thierry Escande:
> >> From: zain wang <wzz@rock-chips.com>
> >>
> >> The bridge does not need to be powered in analogix_dp_bind(), so
> >> remove the calls to pm_runtime_get()/phy_power_on()/analogix_dp_init_dp()
> >> as well as their power-off counterparts.
> >>
> >> Cc: Stéphane Marchesin <marcheu@chromium.org>
> >> Signed-off-by: zain wang <wzz@rock-chips.com>
> >> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> >> [the patch originally just removed the power_on portion, seanpaul removed
> >> the power off code as well as improved the commit message]
> >> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> >> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
> >> ---
> >>
> >> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ----------
> >> 1 file changed, 10 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> >> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index
> >> cb5e18d6ba04..1477ea9ba85d 100644
> >> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> >> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> >> @@ -1382,11 +1382,6 @@ analogix_dp_bind(struct device *dev, struct
> >> drm_device *drm_dev,
> >>
> >> pm_runtime_enable(dev);
> >>
> >> - pm_runtime_get_sync(dev);
> >> - phy_power_on(dp->phy);
> >> -
> >> - analogix_dp_init_dp(dp);
> >> -
> >>
> >> ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
> >>
> >> analogix_dp_hardirq,
> >> analogix_dp_irq_thread,
> >
> > Not 100% sure here, as the driver has the request-irq + disable-irq hack
> > here. So a pending interrupt could possibly fire between request and
> > disable.
> >
> > Right now the block should be on, but can it still handle such an irq
> > when the power is removed?
>
> Probably not (see below).
>
> > So before removing the power here, we might want something
> > similar to what Marc posted for the vop [0] for the analogix-dp?
>
> You can do that trick only if the interrupt is not shared. In the VOP
> case, it is shared with the IOMMU, which makes it more... interesting.
Yep, which is why I mentioned it, as the dp-irq should not be shared
I'd think :-)
Heiko
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind
2018-01-30 20:28 ` [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind Thierry Escande
2018-02-28 14:37 ` Heiko Stübner
@ 2018-02-28 15:20 ` Heiko Stübner
2018-03-01 8:19 ` Marek Szyprowski
2018-03-01 13:37 ` Marek Szyprowski
2 siblings, 1 reply; 62+ messages in thread
From: Heiko Stübner @ 2018-02-28 15:20 UTC (permalink / raw)
To: linux-rockchip, Marek Szyprowski
Cc: Douglas Anderson, Thierry Escande, Lin Huang, David Airlie,
linux-kernel, dri-devel, Tomasz Figa, Thierry Reding, Yakir Yang,
Enric Balletbo i Serra, Ørjan Eide, Haixia Shi, Zain Wang,
Mark Yao
Am Dienstag, 30. Januar 2018, 21:28:35 CET schrieb Thierry Escande:
> From: zain wang <wzz@rock-chips.com>
>
> The bridge does not need to be powered in analogix_dp_bind(), so
> remove the calls to pm_runtime_get()/phy_power_on()/analogix_dp_init_dp()
> as well as their power-off counterparts.
>
> Cc: Stéphane Marchesin <marcheu@chromium.org>
> Signed-off-by: zain wang <wzz@rock-chips.com>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> [the patch originally just removed the power_on portion, seanpaul removed
> the power off code as well as improved the commit message]
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
> ---
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index
> cb5e18d6ba04..1477ea9ba85d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -1382,11 +1382,6 @@ analogix_dp_bind(struct device *dev, struct
> drm_device *drm_dev,
>
> pm_runtime_enable(dev);
>
> - pm_runtime_get_sync(dev);
> - phy_power_on(dp->phy);
> -
> - analogix_dp_init_dp(dp);
> -
> ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
> analogix_dp_hardirq,
> analogix_dp_irq_thread,
> @@ -1414,15 +1409,10 @@ analogix_dp_bind(struct device *dev, struct
> drm_device *drm_dev, goto err_disable_pm_runtime;
> }
>
> - phy_power_off(dp->phy);
> - pm_runtime_put(dev);
> -
> return dp;
>
> err_disable_pm_runtime:
>
> - phy_power_off(dp->phy);
> - pm_runtime_put(dev);
> pm_runtime_disable(dev);
>
> return ERR_PTR(ret);
In general, this patch seems to also create the opposite than
"drm/bridge: analogix_dp: Keep PHY powered between driver bind/unbind" [0]
posted on monday?
[0] https://patchwork.kernel.org/patch/10242493/
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind
2018-02-28 15:20 ` Heiko Stübner
@ 2018-03-01 8:19 ` Marek Szyprowski
0 siblings, 0 replies; 62+ messages in thread
From: Marek Szyprowski @ 2018-03-01 8:19 UTC (permalink / raw)
To: Heiko Stübner, linux-rockchip
Cc: Douglas Anderson, Thierry Escande, Lin Huang, David Airlie,
linux-kernel, dri-devel, Tomasz Figa, Thierry Reding, Yakir Yang,
Enric Balletbo i Serra, Ørjan Eide, Haixia Shi, Zain Wang,
Mark Yao
Hi Heiko,
Thanks for adding me to this thread.
On 2018-02-28 16:20, Heiko Stübner wrote:
> Am Dienstag, 30. Januar 2018, 21:28:35 CET schrieb Thierry Escande:
>> From: zain wang <wzz@rock-chips.com>
>>
>> The bridge does not need to be powered in analogix_dp_bind(), so
>> remove the calls to pm_runtime_get()/phy_power_on()/analogix_dp_init_dp()
>> as well as their power-off counterparts.
>>
>> Cc: Stéphane Marchesin <marcheu@chromium.org>
>> Signed-off-by: zain wang <wzz@rock-chips.com>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> [the patch originally just removed the power_on portion, seanpaul removed
>> the power off code as well as improved the commit message]
>> Signed-off-by: Sean Paul <seanpaul@chromium.org>
>> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
>> ---
>> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ----------
>> 1 file changed, 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index
>> cb5e18d6ba04..1477ea9ba85d 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -1382,11 +1382,6 @@ analogix_dp_bind(struct device *dev, struct
>> drm_device *drm_dev,
>>
>> pm_runtime_enable(dev);
>>
>> - pm_runtime_get_sync(dev);
>> - phy_power_on(dp->phy);
>> -
>> - analogix_dp_init_dp(dp);
>> -
>> ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
>> analogix_dp_hardirq,
>> analogix_dp_irq_thread,
>> @@ -1414,15 +1409,10 @@ analogix_dp_bind(struct device *dev, struct
>> drm_device *drm_dev, goto err_disable_pm_runtime;
>> }
>>
>> - phy_power_off(dp->phy);
>> - pm_runtime_put(dev);
>> -
>> return dp;
>>
>> err_disable_pm_runtime:
>>
>> - phy_power_off(dp->phy);
>> - pm_runtime_put(dev);
>> pm_runtime_disable(dev);
>>
>> return ERR_PTR(ret);
> In general, this patch seems to also create the opposite than
> "drm/bridge: analogix_dp: Keep PHY powered between driver bind/unbind" [0]
>
> posted on monday?
>
> [0] https://patchwork.kernel.org/patch/10242493/
Well, my patch was a quick workaround to avoid board freeze.
This patch looks like a proper fix. Besides removing runtime pm and phy
power calls from dp_bind, it also removes dp register access done in
analogix_dp_init_dp, as there is really no need to touch registers in bind
operation.
The patchset however suffers from other issues on Exynos hardware. I
will post
them in that thread.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind
2018-01-30 20:28 ` [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind Thierry Escande
2018-02-28 14:37 ` Heiko Stübner
2018-02-28 15:20 ` Heiko Stübner
@ 2018-03-01 13:37 ` Marek Szyprowski
2 siblings, 0 replies; 62+ messages in thread
From: Marek Szyprowski @ 2018-03-01 13:37 UTC (permalink / raw)
To: Thierry Escande, Archit Taneja, Inki Dae, Thierry Reding,
Sandy Huang, Sean Paul, David Airlie, Tomasz Figa,
Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, linux-kernel, dri-devel, Douglas Anderson,
linux-rockchip, Yakir Yang, Ørjan Eide, Haixia Shi,
Mark Yao
Hi,
On 2018-01-30 21:28, Thierry Escande wrote:
> From: zain wang <wzz@rock-chips.com>
>
> The bridge does not need to be powered in analogix_dp_bind(), so
> remove the calls to pm_runtime_get()/phy_power_on()/analogix_dp_init_dp()
> as well as their power-off counterparts.
>
> Cc: Stéphane Marchesin <marcheu@chromium.org>
> Signed-off-by: zain wang <wzz@rock-chips.com>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> [the patch originally just removed the power_on portion, seanpaul removed
> the power off code as well as improved the commit message]
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
> ---
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index cb5e18d6ba04..1477ea9ba85d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -1382,11 +1382,6 @@ analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
>
> pm_runtime_enable(dev);
>
> - pm_runtime_get_sync(dev);
> - phy_power_on(dp->phy);
> -
> - analogix_dp_init_dp(dp);
> -
> ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
> analogix_dp_hardirq,
> analogix_dp_irq_thread,
> @@ -1414,15 +1409,10 @@ analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> goto err_disable_pm_runtime;
> }
>
> - phy_power_off(dp->phy);
> - pm_runtime_put(dev);
> -
> return dp;
>
> err_disable_pm_runtime:
>
> - phy_power_off(dp->phy);
> - pm_runtime_put(dev);
> pm_runtime_disable(dev);
>
> return ERR_PTR(ret);
Once this change is applied, there is also no need to keep dp->clock
prepared & enabled between bind/unbind.
analogix_dp_set_bridge() and analogix_dp_bridge_disable() properly manage
dp->clock on their own.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 06/43] drm/rockchip: Don't use atomic constructs for psr
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2018-01-30 20:28 ` [PATCH v3 01/43] drm/rockchip: Get rid of unnecessary struct fields Thierry Escande
2018-01-30 20:28 ` [PATCH v3 05/43] drm/bridge: analogix_dp: Don't power bridge in analogix_dp_bind Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 07/43] drm/bridge: analogix_dp: detect Sink PSR state after configuring the PSR Thierry Escande
` (25 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Sean Paul <seanpaul@chromium.org>
Instead of using timer and spinlocks, use delayed_work and
mutexes for rockchip psr. This allows us to make blocking
calls when enabling/disabling psr (which is sort of important
given we're talking over dpcd to the display).
Cc: Caesar Wang <wxt@rock-chips.com>
Cc: 征增 王 <wzz@rock-chips.com>
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_psr.c | 68 ++++++++++++-----------------
3 files changed, 31 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index 88084ca15115..0609113d6a71 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -134,7 +134,7 @@ static int rockchip_drm_bind(struct device *dev)
drm_dev->dev_private = private;
INIT_LIST_HEAD(&private->psr_list);
- spin_lock_init(&private->psr_list_lock);
+ mutex_init(&private->psr_list_lock);
ret = rockchip_drm_init_iommu(drm_dev);
if (ret)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index 498dfbc52cec..9c064a40458b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -55,7 +55,7 @@ struct rockchip_drm_private {
struct mutex mm_lock;
struct drm_mm mm;
struct list_head psr_list;
- spinlock_t psr_list_lock;
+ struct mutex psr_list_lock;
};
int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c b/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
index b3fb99c5b1fd..b339ca943139 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
@@ -18,7 +18,7 @@
#include "rockchip_drm_drv.h"
#include "rockchip_drm_psr.h"
-#define PSR_FLUSH_TIMEOUT msecs_to_jiffies(100)
+#define PSR_FLUSH_TIMEOUT_MS 100
enum psr_state {
PSR_FLUSH,
@@ -30,11 +30,11 @@ struct psr_drv {
struct list_head list;
struct drm_encoder *encoder;
- spinlock_t lock;
+ struct mutex lock;
bool active;
enum psr_state state;
- struct timer_list flush_timer;
+ struct delayed_work flush_work;
void (*set)(struct drm_encoder *encoder, bool enable);
};
@@ -43,9 +43,8 @@ static struct psr_drv *find_psr_by_crtc(struct drm_crtc *crtc)
{
struct rockchip_drm_private *drm_drv = crtc->dev->dev_private;
struct psr_drv *psr;
- unsigned long flags;
- spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+ mutex_lock(&drm_drv->psr_list_lock);
list_for_each_entry(psr, &drm_drv->psr_list, list) {
if (psr->encoder->crtc == crtc)
goto out;
@@ -53,7 +52,7 @@ static struct psr_drv *find_psr_by_crtc(struct drm_crtc *crtc)
psr = ERR_PTR(-ENODEV);
out:
- spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+ mutex_unlock(&drm_drv->psr_list_lock);
return psr;
}
@@ -61,9 +60,8 @@ static struct psr_drv *find_psr_by_encoder(struct drm_encoder *encoder)
{
struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
struct psr_drv *psr;
- unsigned long flags;
- spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+ mutex_lock(&drm_drv->psr_list_lock);
list_for_each_entry(psr, &drm_drv->psr_list, list) {
if (psr->encoder == encoder)
goto out;
@@ -71,7 +69,7 @@ static struct psr_drv *find_psr_by_encoder(struct drm_encoder *encoder)
psr = ERR_PTR(-ENODEV);
out:
- spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+ mutex_unlock(&drm_drv->psr_list_lock);
return psr;
}
@@ -112,23 +110,21 @@ static void psr_set_state_locked(struct psr_drv *psr, enum psr_state state)
static void psr_set_state(struct psr_drv *psr, enum psr_state state)
{
- unsigned long flags;
-
- spin_lock_irqsave(&psr->lock, flags);
+ mutex_lock(&psr->lock);
psr_set_state_locked(psr, state);
- spin_unlock_irqrestore(&psr->lock, flags);
+ mutex_unlock(&psr->lock);
}
-static void psr_flush_handler(struct timer_list *t)
+static void psr_flush_handler(struct work_struct *work)
{
- struct psr_drv *psr = from_timer(psr, t, flush_timer);
- unsigned long flags;
+ struct psr_drv *psr = container_of(to_delayed_work(work),
+ struct psr_drv, flush_work);
/* If the state has changed since we initiated the flush, do nothing */
- spin_lock_irqsave(&psr->lock, flags);
+ mutex_lock(&psr->lock);
if (psr->state == PSR_FLUSH)
psr_set_state_locked(psr, PSR_ENABLE);
- spin_unlock_irqrestore(&psr->lock, flags);
+ mutex_unlock(&psr->lock);
}
/**
@@ -141,14 +137,13 @@ static void psr_flush_handler(struct timer_list *t)
int rockchip_drm_psr_activate(struct drm_encoder *encoder)
{
struct psr_drv *psr = find_psr_by_encoder(encoder);
- unsigned long flags;
if (IS_ERR(psr))
return PTR_ERR(psr);
- spin_lock_irqsave(&psr->lock, flags);
+ mutex_lock(&psr->lock);
psr->active = true;
- spin_unlock_irqrestore(&psr->lock, flags);
+ mutex_unlock(&psr->lock);
return 0;
}
@@ -164,15 +159,14 @@ EXPORT_SYMBOL(rockchip_drm_psr_activate);
int rockchip_drm_psr_deactivate(struct drm_encoder *encoder)
{
struct psr_drv *psr = find_psr_by_encoder(encoder);
- unsigned long flags;
if (IS_ERR(psr))
return PTR_ERR(psr);
- spin_lock_irqsave(&psr->lock, flags);
+ mutex_lock(&psr->lock);
psr->active = false;
- spin_unlock_irqrestore(&psr->lock, flags);
- del_timer_sync(&psr->flush_timer);
+ mutex_unlock(&psr->lock);
+ cancel_delayed_work_sync(&psr->flush_work);
return 0;
}
@@ -180,9 +174,8 @@ EXPORT_SYMBOL(rockchip_drm_psr_deactivate);
static void rockchip_drm_do_flush(struct psr_drv *psr)
{
- mod_timer(&psr->flush_timer,
- round_jiffies_up(jiffies + PSR_FLUSH_TIMEOUT));
psr_set_state(psr, PSR_FLUSH);
+ mod_delayed_work(system_wq, &psr->flush_work, PSR_FLUSH_TIMEOUT_MS);
}
/**
@@ -219,12 +212,11 @@ void rockchip_drm_psr_flush_all(struct drm_device *dev)
{
struct rockchip_drm_private *drm_drv = dev->dev_private;
struct psr_drv *psr;
- unsigned long flags;
- spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+ mutex_lock(&drm_drv->psr_list_lock);
list_for_each_entry(psr, &drm_drv->psr_list, list)
rockchip_drm_do_flush(psr);
- spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+ mutex_unlock(&drm_drv->psr_list_lock);
}
EXPORT_SYMBOL(rockchip_drm_psr_flush_all);
@@ -241,7 +233,6 @@ int rockchip_drm_psr_register(struct drm_encoder *encoder,
{
struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
struct psr_drv *psr;
- unsigned long flags;
if (!encoder || !psr_set)
return -EINVAL;
@@ -250,17 +241,17 @@ int rockchip_drm_psr_register(struct drm_encoder *encoder,
if (!psr)
return -ENOMEM;
- timer_setup(&psr->flush_timer, psr_flush_handler, 0);
- spin_lock_init(&psr->lock);
+ INIT_DELAYED_WORK(&psr->flush_work, psr_flush_handler);
+ mutex_init(&psr->lock);
psr->active = true;
psr->state = PSR_DISABLE;
psr->encoder = encoder;
psr->set = psr_set;
- spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+ mutex_lock(&drm_drv->psr_list_lock);
list_add_tail(&psr->list, &drm_drv->psr_list);
- spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+ mutex_unlock(&drm_drv->psr_list_lock);
return 0;
}
@@ -278,16 +269,15 @@ void rockchip_drm_psr_unregister(struct drm_encoder *encoder)
{
struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
struct psr_drv *psr, *n;
- unsigned long flags;
- spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+ mutex_lock(&drm_drv->psr_list_lock);
list_for_each_entry_safe(psr, n, &drm_drv->psr_list, list) {
if (psr->encoder == encoder) {
- del_timer(&psr->flush_timer);
+ cancel_delayed_work_sync(&psr->flush_work);
list_del(&psr->list);
kfree(psr);
}
}
- spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+ mutex_unlock(&drm_drv->psr_list_lock);
}
EXPORT_SYMBOL(rockchip_drm_psr_unregister);
--
2.14.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 07/43] drm/bridge: analogix_dp: detect Sink PSR state after configuring the PSR
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (2 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 06/43] drm/rockchip: Don't use atomic constructs for psr Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 08/43] drm/rockchip: Remove analogix psr worker Thierry Escande
` (24 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Yakir Yang <ykk@rock-chips.com>
Make sure the request PSR state takes effect in analogix_dp_send_psr_spd()
function, or print the sink PSR error state if we failed to apply the
requested PSR setting.
Cc: 征增 王 <wzz@rock-chips.com>
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
[seanpaul changed timeout loop to a readx poll]
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 6 ++--
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 6 ++--
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 35 +++++++++++++++++++---
3 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 1477ea9ba85d..b52de046f5f1 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -122,8 +122,7 @@ int analogix_dp_enable_psr(struct analogix_dp_device *dp)
psr_vsc.DB0 = 0;
psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
- analogix_dp_send_psr_spd(dp, &psr_vsc);
- return 0;
+ return analogix_dp_send_psr_spd(dp, &psr_vsc);
}
EXPORT_SYMBOL_GPL(analogix_dp_enable_psr);
@@ -149,8 +148,7 @@ int analogix_dp_disable_psr(struct analogix_dp_device *dp)
if (ret != 1)
dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret);
- analogix_dp_send_psr_spd(dp, &psr_vsc);
- return 0;
+ return analogix_dp_send_psr_spd(dp, &psr_vsc);
}
EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 5c6a28806129..b039b28d8fcc 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,8 @@
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
+#define DP_TIMEOUT_PSR_LOOP_MS 300
+
/* DP_MAX_LANE_COUNT */
#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
@@ -247,8 +249,8 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp);
-void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
- struct edp_vsc_psr *vsc);
+int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
+ struct edp_vsc_psr *vsc);
ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
struct drm_dp_aux_msg *msg);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 303083ad28e3..005a3f7005d2 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -10,10 +10,11 @@
* option) any later version.
*/
-#include <linux/device.h>
-#include <linux/io.h>
#include <linux/delay.h>
+#include <linux/device.h>
#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
#include <drm/bridge/analogix_dp.h>
@@ -992,10 +993,25 @@ void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp)
writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON);
}
-void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
- struct edp_vsc_psr *vsc)
+static ssize_t analogix_dp_get_psr_status(struct analogix_dp_device *dp)
+{
+ ssize_t val;
+ u8 status;
+
+ val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status);
+ if (val < 0) {
+ dev_err(dp->dev, "PSR_STATUS read failed ret=%zd", val);
+ return val;
+ }
+ return status;
+}
+
+int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
+ struct edp_vsc_psr *vsc)
{
unsigned int val;
+ int ret;
+ ssize_t psr_status;
/* don't send info frame */
val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
@@ -1036,6 +1052,17 @@ void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
val |= IF_EN;
writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
+
+ ret = readx_poll_timeout(analogix_dp_get_psr_status, dp, psr_status,
+ psr_status >= 0 &&
+ ((vsc->DB1 && psr_status == DP_PSR_SINK_ACTIVE_RFB) ||
+ (!vsc->DB1 && psr_status == DP_PSR_SINK_INACTIVE)), 1500,
+ DP_TIMEOUT_PSR_LOOP_MS * 1000);
+ if (ret) {
+ dev_warn(dp->dev, "Failed to apply PSR %d\n", ret);
+ return ret;
+ }
+ return 0;
}
ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
--
2.14.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 08/43] drm/rockchip: Remove analogix psr worker
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (3 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 07/43] drm/bridge: analogix_dp: detect Sink PSR state after configuring the PSR Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 09/43] drm/bridge: analogix_dp: Don't change psr while bridge is disabled Thierry Escande
` (23 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Sean Paul <seanpaul@chromium.org>
Now that the spinlocks and timers are gone, we can remove the psr
worker located in rockchip's analogix driver and do the enable/disable
directly. This should simplify the code and remove races on disable.
Cc: 征增 王 <wzz@rock-chips.com>
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 31 ++-----------------------
1 file changed, 2 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 7d76ff47028d..36334839a3f8 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -71,10 +71,6 @@ struct rockchip_dp_device {
struct regmap *grf;
struct reset_control *rst;
- struct work_struct psr_work;
- struct mutex psr_lock;
- unsigned int psr_state;
-
const struct rockchip_dp_chip_data *data;
struct analogix_dp_device *adp;
@@ -84,28 +80,13 @@ struct rockchip_dp_device {
static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
{
struct rockchip_dp_device *dp = to_dp(encoder);
+ int ret;
if (!analogix_dp_psr_supported(dp->adp))
return;
DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
- mutex_lock(&dp->psr_lock);
- if (enabled)
- dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
- else
- dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
-
- schedule_work(&dp->psr_work);
- mutex_unlock(&dp->psr_lock);
-}
-
-static void analogix_dp_psr_work(struct work_struct *work)
-{
- struct rockchip_dp_device *dp =
- container_of(work, typeof(*dp), psr_work);
- int ret;
-
ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
if (ret) {
@@ -113,12 +94,10 @@ static void analogix_dp_psr_work(struct work_struct *work)
return;
}
- mutex_lock(&dp->psr_lock);
- if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE)
+ if (enabled)
analogix_dp_enable_psr(dp->adp);
else
analogix_dp_disable_psr(dp->adp);
- mutex_unlock(&dp->psr_lock);
}
static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
@@ -135,8 +114,6 @@ static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
struct rockchip_dp_device *dp = to_dp(plat_data);
int ret;
- cancel_work_sync(&dp->psr_work);
-
ret = clk_prepare_enable(dp->pclk);
if (ret < 0) {
DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
@@ -355,10 +332,6 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
dp->plat_data.power_off = rockchip_dp_powerdown;
dp->plat_data.get_modes = rockchip_dp_get_modes;
- mutex_init(&dp->psr_lock);
- dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
- INIT_WORK(&dp->psr_work, analogix_dp_psr_work);
-
ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
if (ret < 0)
goto err_cleanup_encoder;
--
2.14.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 09/43] drm/bridge: analogix_dp: Don't change psr while bridge is disabled
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (4 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 08/43] drm/rockchip: Remove analogix psr worker Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 11/43] drm/bridge: analogix_dp: add fast link train for eDP Thierry Escande
` (22 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
There is a race between AUX CH bring-up and enabling bridge which will
cause link training to fail. To avoid hitting it, don't change psr state
while enabling the bridge.
Cc: Tomeu Vizoso <tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Cc: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
[seanpaul fixed up the commit message a bit and renamed *_supported to *_enabled]
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 15 ++++++++-------
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 +-
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 2 +-
include/drm/bridge/analogix_dp.h | 2 +-
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index b52de046f5f1..84141571e960 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -98,18 +98,18 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
return 0;
}
-int analogix_dp_psr_supported(struct analogix_dp_device *dp)
+int analogix_dp_psr_enabled(struct analogix_dp_device *dp)
{
- return dp->psr_support;
+ return dp->psr_enable;
}
-EXPORT_SYMBOL_GPL(analogix_dp_psr_supported);
+EXPORT_SYMBOL_GPL(analogix_dp_psr_enabled);
int analogix_dp_enable_psr(struct analogix_dp_device *dp)
{
struct edp_vsc_psr psr_vsc;
- if (!dp->psr_support)
+ if (!dp->psr_enable)
return 0;
/* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
@@ -131,7 +131,7 @@ int analogix_dp_disable_psr(struct analogix_dp_device *dp)
struct edp_vsc_psr psr_vsc;
int ret;
- if (!dp->psr_support)
+ if (!dp->psr_enable)
return 0;
/* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
@@ -875,8 +875,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
/* Enable video */
analogix_dp_start_video(dp);
- dp->psr_support = analogix_dp_detect_sink_psr(dp);
- if (dp->psr_support)
+ dp->psr_enable = analogix_dp_detect_sink_psr(dp);
+ if (dp->psr_enable)
analogix_dp_enable_sink_psr(dp);
}
@@ -1118,6 +1118,7 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
if (ret)
DRM_ERROR("failed to setup the panel ret = %d\n", ret);
+ dp->psr_enable = false;
dp->dpms_mode = DRM_MODE_DPMS_OFF;
}
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index b039b28d8fcc..e135a42cb19e 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -170,7 +170,7 @@ struct analogix_dp_device {
int dpms_mode;
int hpd_gpio;
bool force_hpd;
- bool psr_support;
+ bool psr_enable;
struct mutex panel_lock;
bool panel_is_modeset;
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 36334839a3f8..3e8bf79bea58 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -82,7 +82,7 @@ static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
struct rockchip_dp_device *dp = to_dp(encoder);
int ret;
- if (!analogix_dp_psr_supported(dp->adp))
+ if (!analogix_dp_psr_enabled(dp->adp))
return;
DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 5518fc75dd6e..c2788483c882 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -40,7 +40,7 @@ struct analogix_dp_plat_data {
struct drm_connector *);
};
-int analogix_dp_psr_supported(struct analogix_dp_device *dp);
+int analogix_dp_psr_enabled(struct analogix_dp_device *dp);
int analogix_dp_enable_psr(struct analogix_dp_device *dp);
int analogix_dp_disable_psr(struct analogix_dp_device *dp);
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 11/43] drm/bridge: analogix_dp: add fast link train for eDP
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (5 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 09/43] drm/bridge: analogix_dp: Don't change psr while bridge is disabled Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 13/43] drm/bridge: analogix_dp: Move enable video into config_video() Thierry Escande
` (21 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
We would meet a short black screen when exit PSR with the full link
training, In this case, we should use fast link train instead of full
link training.
Signed-off-by: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 142 ++++++++++++++++-----
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 3 +
2 files changed, 114 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 84141571e960..e0775adf80b3 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -10,17 +10,18 @@
* option) any later version.
*/
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
#include <linux/clk.h>
-#include <linux/io.h>
+#include <linux/component.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
-#include <linux/gpio.h>
-#include <linux/component.h>
#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
@@ -35,6 +36,8 @@
#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
+static const bool verify_fast_training;
+
struct bridge_init {
struct i2c_client *client;
struct device_node *node;
@@ -528,7 +531,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
{
int lane, lane_count, retval;
u32 reg;
- u8 link_align, link_status[2], adjust_request[2];
+ u8 link_align, link_status[2], adjust_request[2], spread;
usleep_range(400, 401);
@@ -571,6 +574,20 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
dev_dbg(dp->dev, "final lane count = %.2x\n",
dp->link_train.lane_count);
+ retval = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD,
+ &spread);
+ if (retval != 1) {
+ dev_err(dp->dev, "failed to read downspread %d\n",
+ retval);
+ dp->fast_train_support = false;
+ } else {
+ dp->fast_train_support =
+ (spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING) ?
+ true : false;
+ }
+ dev_dbg(dp->dev, "fast link training %s\n",
+ dp->fast_train_support ? "supported" : "unsupported");
+
/* set enhanced mode if available */
analogix_dp_set_enhanced_mode(dp);
dp->link_train.lt_state = FINISHED;
@@ -627,10 +644,12 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
*lane_count = DPCD_MAX_LANE_COUNT(data);
}
-static void analogix_dp_init_training(struct analogix_dp_device *dp,
- enum link_lane_count_type max_lane,
- int max_rate)
+static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
+ u32 max_lanes, u32 max_rate)
{
+ int retval = 0;
+ bool training_finished = false;
+
/*
* MACRO_RST must be applied after the PLL_LOCK to avoid
* the DP inter pair skew issue for at least 10 us
@@ -656,18 +675,13 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
}
/* Setup TX lane count & rate */
- if (dp->link_train.lane_count > max_lane)
- dp->link_train.lane_count = max_lane;
+ if (dp->link_train.lane_count > max_lanes)
+ dp->link_train.lane_count = max_lanes;
if (dp->link_train.link_rate > max_rate)
dp->link_train.link_rate = max_rate;
/* All DP analog module power up */
analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
-}
-
-static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
-{
- int retval = 0, training_finished = 0;
dp->link_train.lt_state = START;
@@ -702,22 +716,88 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
return retval;
}
-static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
- u32 count, u32 bwtype)
+static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
{
- int i;
- int retval;
+ int i, ret;
+ u8 link_align, link_status[2];
+ enum pll_status status;
- for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
- analogix_dp_init_training(dp, count, bwtype);
- retval = analogix_dp_sw_link_training(dp);
- if (retval == 0)
- break;
+ analogix_dp_reset_macro(dp);
- usleep_range(100, 110);
+ analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+ analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
+
+ for (i = 0; i < dp->link_train.lane_count; i++) {
+ analogix_dp_set_lane_link_training(dp,
+ dp->link_train.training_lane[i], i);
}
- return retval;
+ ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
+ status != PLL_UNLOCKED, 120,
+ 120 * DP_TIMEOUT_LOOP_COUNT);
+ if (ret) {
+ DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
+ return ret;
+ }
+
+ /* source Set training pattern 1 */
+ analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
+ /* From DP spec, pattern must be on-screen for a minimum 500us */
+ usleep_range(500, 600);
+
+ analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
+ /* From DP spec, pattern must be on-screen for a minimum 500us */
+ usleep_range(500, 600);
+
+ /* TODO: enhanced_mode?*/
+ analogix_dp_set_training_pattern(dp, DP_NONE);
+
+ /*
+ * Useful for debugging issues with fast link training, disable for more
+ * speed
+ */
+ if (verify_fast_training) {
+ ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
+ &link_align);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
+ 2);
+ if (ret < 0) {
+ DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
+ ret);
+ return ret;
+ }
+
+ if (analogix_dp_clock_recovery_ok(link_status,
+ dp->link_train.lane_count)) {
+ DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
+ analogix_dp_reduce_link_rate(dp);
+ return -EIO;
+ }
+
+ if (analogix_dp_channel_eq_ok(link_status, link_align,
+ dp->link_train.lane_count)) {
+ DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
+ analogix_dp_reduce_link_rate(dp);
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+static int analogix_dp_train_link(struct analogix_dp_device *dp)
+{
+ if (dp->fast_train_support)
+ return analogix_dp_fast_link_train(dp);
+
+ return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
+ dp->video_info.max_link_rate);
}
static int analogix_dp_config_video(struct analogix_dp_device *dp)
@@ -850,10 +930,10 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
DRM_ERROR("failed to disable the panel\n");
}
- ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
- dp->video_info.max_link_rate);
+ ret = readx_poll_timeout(analogix_dp_train_link, dp, ret, !ret, 100,
+ DP_TIMEOUT_TRAINING_US * 5);
if (ret) {
- dev_err(dp->dev, "unable to do link train\n");
+ dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
return;
}
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index e135a42cb19e..920607d7eb3e 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,8 @@
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
+/* Training takes 22ms if AUX channel comm fails. Use this as retry interval */
+#define DP_TIMEOUT_TRAINING_US 22000
#define DP_TIMEOUT_PSR_LOOP_MS 300
/* DP_MAX_LANE_COUNT */
@@ -171,6 +173,7 @@ struct analogix_dp_device {
int hpd_gpio;
bool force_hpd;
bool psr_enable;
+ bool fast_train_support;
struct mutex panel_lock;
bool panel_is_modeset;
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 13/43] drm/bridge: analogix_dp: Move enable video into config_video()
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (6 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 11/43] drm/bridge: analogix_dp: add fast link train for eDP Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 14/43] drm/bridge: analogix_dp: Check AUX_EN status when doing AUX transfer Thierry Escande
` (20 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Lin Huang <hl@rock-chips.com>
We need to enable video before analogix_dp_is_video_stream_on(), so
we can get the right video stream status.
Cc: 征增 王 <wzz@rock-chips.com>
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 49a05eac41c1..8ef9e31c6713 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -820,11 +820,10 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
break;
if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
- dev_err(dp->dev, "Timeout of video streamclk ok\n");
+ dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
return -ETIMEDOUT;
}
-
- usleep_range(1, 2);
+ usleep_range(1000, 1001);
}
/* Set to use the register calculated M/N video */
@@ -839,6 +838,9 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
/* Configure video slave mode */
analogix_dp_enable_video_master(dp, 0);
+ /* Enable video */
+ analogix_dp_start_video(dp);
+
timeout_loop = 0;
for (;;) {
@@ -952,9 +954,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
DRM_ERROR("failed to enable the panel\n");
}
- /* Enable video */
- analogix_dp_start_video(dp);
-
dp->psr_enable = analogix_dp_detect_sink_psr(dp);
if (dp->psr_enable)
analogix_dp_enable_sink_psr(dp);
--
2.14.1
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 14/43] drm/bridge: analogix_dp: Check AUX_EN status when doing AUX transfer
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (7 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 13/43] drm/bridge: analogix_dp: Move enable video into config_video() Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 15/43] drm/bridge: analogix_dp: Don't use fast link training when panel just powered up Thierry Escande
` (19 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Lin Huang <hl@rock-chips.com>
We should check AUX_EN bit to confirm the AUX CH operation is completed.
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 25 +++++++++++++----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 9df2f3ef000c..e78c861b9e06 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1073,9 +1073,9 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
{
u32 reg;
u8 *buffer = msg->buffer;
- int timeout_loop = 0;
unsigned int i;
int num_transferred = 0;
+ int ret;
/* Buffer size of AUX CH is 16 bytes */
if (WARN_ON(msg->size > 16))
@@ -1139,17 +1139,20 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
- /* Is AUX CH command reply received? */
+ ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2,
+ reg, !(reg & AUX_EN), 25, 500 * 1000);
+ if (ret) {
+ dev_err(dp->dev, "AUX CH enable timeout!\n");
+ return -ETIMEDOUT;
+ }
+
/* TODO: Wait for an interrupt instead of looping? */
- reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
- while (!(reg & RPLY_RECEIV)) {
- timeout_loop++;
- if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
- dev_err(dp->dev, "AUX CH command reply failed!\n");
- return -ETIMEDOUT;
- }
- reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
- usleep_range(10, 11);
+ /* Is AUX CH command reply received? */
+ ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA,
+ reg, reg & RPLY_RECEIV, 10, 20 * 1000);
+ if (ret) {
+ dev_err(dp->dev, "AUX CH cmd reply timeout!\n");
+ return -ETIMEDOUT;
}
/* Clear interrupt source for AUX CH command reply */
--
2.14.1
_______________________________________________
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 15/43] drm/bridge: analogix_dp: Don't use fast link training when panel just powered up
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (8 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 14/43] drm/bridge: analogix_dp: Check AUX_EN status when doing AUX transfer Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 16/43] drm/bridge: analogix_dp: Retry bridge enable when it failed Thierry Escande
` (18 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz@rock-chips.com>
Panel would reset its setting when it powers down. It would forget the last
succeeded link training setting. So we can't use the last successful link
training setting to do fast link training. Let's reset fast_train_enable in
analogix_dp_bridge_disable();
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 9 +++++----
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 8ef9e31c6713..179c2106b8a2 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -579,14 +579,14 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
if (retval != 1) {
dev_err(dp->dev, "failed to read downspread %d\n",
retval);
- dp->fast_train_support = false;
+ dp->fast_train_enable = false;
} else {
- dp->fast_train_support =
+ dp->fast_train_enable =
(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING) ?
true : false;
}
dev_dbg(dp->dev, "fast link training %s\n",
- dp->fast_train_support ? "supported" : "unsupported");
+ dp->fast_train_enable ? "supported" : "unsupported");
/* set enhanced mode if available */
analogix_dp_set_enhanced_mode(dp);
@@ -793,7 +793,7 @@ static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
static int analogix_dp_train_link(struct analogix_dp_device *dp)
{
- if (dp->fast_train_support)
+ if (dp->fast_train_enable)
return analogix_dp_fast_link_train(dp);
return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
@@ -1198,6 +1198,7 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
DRM_ERROR("failed to setup the panel ret = %d\n", ret);
dp->psr_enable = false;
+ dp->fast_train_enable = false;
dp->dpms_mode = DRM_MODE_DPMS_OFF;
}
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 6a96ef7e6934..403ff853464b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -173,7 +173,7 @@ struct analogix_dp_device {
int hpd_gpio;
bool force_hpd;
bool psr_enable;
- bool fast_train_support;
+ bool fast_train_enable;
struct mutex panel_lock;
bool panel_is_modeset;
--
2.14.1
_______________________________________________
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 16/43] drm/bridge: analogix_dp: Retry bridge enable when it failed
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (9 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 15/43] drm/bridge: analogix_dp: Don't use fast link training when panel just powered up Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 17/43] drm/bridge: analogix_dp: Wait for HPD signal before configuring link Thierry Escande
` (17 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz@rock-chips.com>
When we enable bridge failed, we have to retry it, otherwise we would get
the abnormal display.
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 65 +++++++++++++++++-----
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 3 +-
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 5 +-
3 files changed, 56 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 179c2106b8a2..ba2506e17f6d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -43,8 +43,10 @@ struct bridge_init {
struct device_node *node;
};
-static void analogix_dp_init_dp(struct analogix_dp_device *dp)
+static int analogix_dp_init_dp(struct analogix_dp_device *dp)
{
+ int ret;
+
analogix_dp_reset(dp);
analogix_dp_swreset(dp);
@@ -56,10 +58,13 @@ static void analogix_dp_init_dp(struct analogix_dp_device *dp)
analogix_dp_enable_sw_function(dp);
analogix_dp_config_interrupt(dp);
- analogix_dp_init_analog_func(dp);
+ ret = analogix_dp_init_analog_func(dp);
+ if (ret)
+ return ret;
analogix_dp_init_hpd(dp);
analogix_dp_init_aux(dp);
+ return 0;
}
static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
@@ -922,7 +927,7 @@ static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
return IRQ_HANDLED;
}
-static void analogix_dp_commit(struct analogix_dp_device *dp)
+static int analogix_dp_commit(struct analogix_dp_device *dp)
{
int ret;
@@ -932,11 +937,10 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
DRM_ERROR("failed to disable the panel\n");
}
- ret = readx_poll_timeout(analogix_dp_train_link, dp, ret, !ret, 100,
- DP_TIMEOUT_TRAINING_US * 5);
+ ret = analogix_dp_train_link(dp);
if (ret) {
dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
- return;
+ return ret;
}
analogix_dp_enable_scramble(dp, 1);
@@ -957,6 +961,7 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
dp->psr_enable = analogix_dp_detect_sink_psr(dp);
if (dp->psr_enable)
analogix_dp_enable_sink_psr(dp);
+ return 0;
}
/*
@@ -1150,12 +1155,9 @@ static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge)
DRM_ERROR("failed to setup the panel ret = %d\n", ret);
}
-static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
+static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
{
- struct analogix_dp_device *dp = bridge->driver_private;
-
- if (dp->dpms_mode == DRM_MODE_DPMS_ON)
- return;
+ int ret;
pm_runtime_get_sync(dp->dev);
@@ -1163,11 +1165,46 @@ static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
dp->plat_data->power_on(dp->plat_data);
phy_power_on(dp->phy);
- analogix_dp_init_dp(dp);
+
+ ret = analogix_dp_init_dp(dp);
+ if (ret)
+ goto out_dp_init;
+
+ ret = analogix_dp_commit(dp);
+ if (ret)
+ goto out_dp_init;
+
enable_irq(dp->irq);
- analogix_dp_commit(dp);
+ return 0;
- dp->dpms_mode = DRM_MODE_DPMS_ON;
+out_dp_init:
+ phy_power_off(dp->phy);
+ if (dp->plat_data->power_off)
+ dp->plat_data->power_off(dp->plat_data);
+ pm_runtime_put_sync(dp->dev);
+
+ return ret;
+}
+
+static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
+{
+ struct analogix_dp_device *dp = bridge->driver_private;
+ int timeout_loop = 0;
+
+ if (dp->dpms_mode == DRM_MODE_DPMS_ON)
+ return;
+
+ while (timeout_loop < MAX_PLL_LOCK_LOOP) {
+ if (analogix_dp_set_bridge(dp) == 0) {
+ dp->dpms_mode = DRM_MODE_DPMS_ON;
+ return;
+ }
+ dev_err(dp->dev, "failed to set bridge, retry: %d\n",
+ timeout_loop);
+ timeout_loop++;
+ usleep_range(10, 11);
+ }
+ dev_err(dp->dev, "too many times retry set bridge, give it up\n");
}
static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 403ff853464b..769255dc6e99 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -19,6 +19,7 @@
#define DP_TIMEOUT_LOOP_COUNT 100
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
+#define MAX_PLL_LOCK_LOOP 5
/* Training takes 22ms if AUX channel comm fails. Use this as retry interval */
#define DP_TIMEOUT_TRAINING_US 22000
@@ -197,7 +198,7 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
enum analog_power_block block,
bool enable);
-void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
+int analogix_dp_init_analog_func(struct analogix_dp_device *dp);
void analogix_dp_init_hpd(struct analogix_dp_device *dp);
void analogix_dp_force_hpd(struct analogix_dp_device *dp);
enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index e78c861b9e06..b47c5af43560 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -333,7 +333,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
}
}
-void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
+int analogix_dp_init_analog_func(struct analogix_dp_device *dp)
{
u32 reg;
int timeout_loop = 0;
@@ -355,7 +355,7 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
timeout_loop++;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "failed to get pll lock status\n");
- return;
+ return -ETIMEDOUT;
}
usleep_range(10, 20);
}
@@ -366,6 +366,7 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
| AUX_FUNC_EN_N);
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
+ return 0;
}
void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
--
2.14.1
_______________________________________________
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 17/43] drm/bridge: analogix_dp: Wait for HPD signal before configuring link
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (10 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 16/43] drm/bridge: analogix_dp: Retry bridge enable when it failed Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 18/43] drm/bridge: analogix_dp: Set PD_INC_BG first when powering up edp phy Thierry Escande
` (16 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz@rock-chips.com>
According to DP spec v1.3 chap 3.5.1.2 Link Training, Link Policy Maker
must first detect that the HPD signal is asserted high by the Downstream
Device before establishing a link with it.
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index ba2506e17f6d..c940a5bb80ac 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1170,6 +1170,17 @@ static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
if (ret)
goto out_dp_init;
+ /*
+ * According to DP spec v1.3 chap 3.5.1.2 Link Training,
+ * We should first make sure the HPD signal is asserted high by device
+ * when we want to establish a link with it.
+ */
+ ret = analogix_dp_detect_hpd(dp);
+ if (ret) {
+ DRM_ERROR("failed to get hpd single ret = %d\n", ret);
+ goto out_dp_init;
+ }
+
ret = analogix_dp_commit(dp);
if (ret)
goto out_dp_init;
--
2.14.1
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 18/43] drm/bridge: analogix_dp: Set PD_INC_BG first when powering up edp phy
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (11 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 17/43] drm/bridge: analogix_dp: Wait for HPD signal before configuring link Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 19/43] drm/bridge: analogix_dp: Ensure edp is disabled when shutting down the panel Thierry Escande
` (15 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz@rock-chips.com>
Following the correct power up sequence:
dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 10 ++++++++--
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 3 +++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index b47c5af43560..bb72f8b0e603 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -321,10 +321,16 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
break;
case POWER_ALL:
if (enable) {
- reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
- CH1_PD | CH0_PD;
+ reg = DP_ALL_PD;
writel(reg, dp->reg_base + phy_pd_addr);
} else {
+ reg = DP_ALL_PD;
+ writel(reg, dp->reg_base + phy_pd_addr);
+ usleep_range(10, 15);
+ reg &= ~DP_INC_BG;
+ writel(reg, dp->reg_base + phy_pd_addr);
+ usleep_range(10, 15);
+
writel(0x00, dp->reg_base + phy_pd_addr);
}
break;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 40200c652533..9602668669f4 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -342,12 +342,15 @@
#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
/* ANALOGIX_DP_PHY_PD */
+#define DP_INC_BG (0x1 << 7)
+#define DP_EXP_BG (0x1 << 6)
#define DP_PHY_PD (0x1 << 5)
#define AUX_PD (0x1 << 4)
#define CH3_PD (0x1 << 3)
#define CH2_PD (0x1 << 2)
#define CH1_PD (0x1 << 1)
#define CH0_PD (0x1 << 0)
+#define DP_ALL_PD (0xff)
/* ANALOGIX_DP_PHY_TEST */
#define MACRO_RST (0x1 << 5)
--
2.14.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 19/43] drm/bridge: analogix_dp: Ensure edp is disabled when shutting down the panel
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (12 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 18/43] drm/bridge: analogix_dp: Set PD_INC_BG first when powering up edp phy Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 20/43] drm/bridge: analogix_dp: Extend hpd check time to 100ms Thierry Escande
` (14 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Lin Huang <hl@rock-chips.com>
When panel is shut down, we should make sure edp can be disabled to avoid
undefined behavior.
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index c940a5bb80ac..fa4ef28e286f 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1161,6 +1161,12 @@ static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
pm_runtime_get_sync(dp->dev);
+ ret = clk_prepare_enable(dp->clock);
+ if (ret < 0) {
+ DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
+ goto out_dp_clk_pre;
+ }
+
if (dp->plat_data->power_on)
dp->plat_data->power_on(dp->plat_data);
@@ -1192,6 +1198,8 @@ static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
phy_power_off(dp->phy);
if (dp->plat_data->power_off)
dp->plat_data->power_off(dp->plat_data);
+ clk_disable_unprepare(dp->clock);
+out_dp_clk_pre:
pm_runtime_put_sync(dp->dev);
return ret;
@@ -1235,10 +1243,13 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
disable_irq(dp->irq);
phy_power_off(dp->phy);
+ analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
if (dp->plat_data->power_off)
dp->plat_data->power_off(dp->plat_data);
+ clk_disable_unprepare(dp->clock);
+
pm_runtime_put_sync(dp->dev);
ret = analogix_dp_prepare_panel(dp, false, true);
--
2.14.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 20/43] drm/bridge: analogix_dp: Extend hpd check time to 100ms
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (13 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 19/43] drm/bridge: analogix_dp: Ensure edp is disabled when shutting down the panel Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 21/43] drm/bridge: analogix_dp: Fix incorrect usage of enhanced mode Thierry Escande
` (13 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Lin Huang <hl@rock-chips.com>
There was a 1ms delay to detect the hpd signal, which is too short to
detect a short pulse. This patch extends this delay to 100ms.
Cc: Stéphane Marchesin <marcheu@chromium.org>
Cc: 征增 王 <wzz@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index fa4ef28e286f..9df92dc54dbe 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -76,7 +76,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
return 0;
timeout_loop++;
- usleep_range(10, 11);
+ usleep_range(1000, 1100);
}
/*
--
2.14.1
_______________________________________________
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 21/43] drm/bridge: analogix_dp: Fix incorrect usage of enhanced mode
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (14 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 20/43] drm/bridge: analogix_dp: Extend hpd check time to 100ms Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 22/43] drm/bridge: analogix_dp: Check dpcd write/read status Thierry Escande
` (12 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Enhanced mode is required by the eDP 1.2 specification, and not doing it
early could result in a period of time where we have a link transmitting
idle packets without it. Since there is no reason to disable it, we just
enable it at the beginning of link training and then keep it on all the
time.
Cc: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Reviewed-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 9df92dc54dbe..846574d0dcb0 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -281,6 +281,8 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
if (retval < 0)
return retval;
+ /* set enhanced mode if available */
+ analogix_dp_set_enhanced_mode(dp);
/* Set TX pre-emphasis to minimum */
for (lane = 0; lane < lane_count; lane++)
@@ -593,8 +595,6 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
dev_dbg(dp->dev, "fast link training %s\n",
dp->fast_train_enable ? "supported" : "unsupported");
- /* set enhanced mode if available */
- analogix_dp_set_enhanced_mode(dp);
dp->link_train.lt_state = FINISHED;
return 0;
@@ -944,8 +944,6 @@ static int analogix_dp_commit(struct analogix_dp_device *dp)
}
analogix_dp_enable_scramble(dp, 1);
- analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
- analogix_dp_enable_enhanced_mode(dp, 1);
analogix_dp_init_video(dp);
ret = analogix_dp_config_video(dp);
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 22/43] drm/bridge: analogix_dp: Check dpcd write/read status
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (15 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 21/43] drm/bridge: analogix_dp: Fix incorrect usage of enhanced mode Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 23/43] drm/bridge: analogix_dp: Fix AUX_PD bit for Rockchip Thierry Escande
` (11 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
We need to check the dpcd write/read return value to see whether the
write/read was successful
Cc: Kristian H. Kristensen <hoegsberg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Reviewed-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 182 +++++++++++++++------
1 file changed, 135 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 846574d0dcb0..082b4e024052 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -160,80 +160,137 @@ int analogix_dp_disable_psr(struct analogix_dp_device *dp)
}
EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
-static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
+static int analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
{
unsigned char psr_version;
+ int ret;
+
+ ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
+ if (ret != 1) {
+ dev_err(dp->dev, "failed to get PSR version, disable it\n");
+ return ret;
+ }
- drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
- return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
+ dp->psr_enable = (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
+
+ return 0;
}
-static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
+static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
{
unsigned char psr_en;
+ int ret;
/* Disable psr function */
- drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
+ ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
+ if (ret != 1) {
+ dev_err(dp->dev, "failed to get psr config\n");
+ goto end;
+ }
+
psr_en &= ~DP_PSR_ENABLE;
- drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
+ if (ret != 1) {
+ dev_err(dp->dev, "failed to disable panel psr\n");
+ goto end;
+ }
/* Main-Link transmitter remains active during PSR active states */
psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
- drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
+ if (ret != 1) {
+ dev_err(dp->dev, "failed to set panel psr\n");
+ goto end;
+ }
/* Enable psr function */
psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
DP_PSR_CRC_VERIFICATION;
- drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
+ if (ret != 1) {
+ dev_err(dp->dev, "failed to set panel psr\n");
+ goto end;
+ }
analogix_dp_enable_psr_crc(dp);
+
+ return 0;
+end:
+ dev_err(dp->dev, "enable psr fail, force to disable psr\n");
+ dp->psr_enable = false;
+
+ return ret;
}
-static void
+static int
analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
bool enable)
{
u8 data;
+ int ret;
- drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
+ ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
+ if (ret != 1)
+ return ret;
if (enable)
- drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
- DP_LANE_COUNT_ENHANCED_FRAME_EN |
- DPCD_LANE_COUNT_SET(data));
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
+ DP_LANE_COUNT_ENHANCED_FRAME_EN |
+ DPCD_LANE_COUNT_SET(data));
else
- drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
- DPCD_LANE_COUNT_SET(data));
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
+ DPCD_LANE_COUNT_SET(data));
+
+ return ret < 0 ? ret : 0;
}
-static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
+static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
+ u8 *enhanced_mode_support)
{
u8 data;
- int retval;
+ int ret;
- drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
- retval = DPCD_ENHANCED_FRAME_CAP(data);
+ ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
+ if (ret != 1) {
+ *enhanced_mode_support = 0;
+ return ret;
+ }
- return retval;
+ *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
+
+ return 0;
}
-static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
+static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
{
u8 data;
+ int ret;
+
+ ret = analogix_dp_is_enhanced_mode_available(dp, &data);
+ if (ret < 0)
+ return ret;
+
+ ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
+ if (ret < 0)
+ return ret;
- data = analogix_dp_is_enhanced_mode_available(dp);
- analogix_dp_enable_rx_to_enhanced_mode(dp, data);
analogix_dp_enable_enhanced_mode(dp, data);
+
+ return 0;
}
-static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
+static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
{
+ int ret;
+
analogix_dp_set_training_pattern(dp, DP_NONE);
- drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
- DP_TRAINING_PATTERN_DISABLE);
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_DISABLE);
+
+ return ret < 0 ? ret : 0;
}
static void
@@ -282,7 +339,11 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
if (retval < 0)
return retval;
/* set enhanced mode if available */
- analogix_dp_set_enhanced_mode(dp);
+ retval = analogix_dp_set_enhanced_mode(dp);
+ if (retval < 0) {
+ dev_err(dp->dev, "failed to set enhance mode\n");
+ return retval;
+ }
/* Set TX pre-emphasis to minimum */
for (lane = 0; lane < lane_count; lane++)
@@ -567,10 +628,11 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
/* traing pattern Set to Normal */
- analogix_dp_training_pattern_dis(dp);
+ retval = analogix_dp_training_pattern_dis(dp);
+ if (retval < 0)
+ return retval;
dev_info(dp->dev, "Link Training success!\n");
-
analogix_dp_get_link_bandwidth(dp, ®);
dp->link_train.link_rate = reg;
dev_dbg(dp->dev, "final bandwidth = %.2x\n",
@@ -807,7 +869,6 @@ static int analogix_dp_train_link(struct analogix_dp_device *dp)
static int analogix_dp_config_video(struct analogix_dp_device *dp)
{
- int retval = 0;
int timeout_loop = 0;
int done_count = 0;
@@ -865,30 +926,42 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
usleep_range(1000, 1001);
}
- if (retval != 0)
- dev_err(dp->dev, "Video stream is not detected!\n");
-
- return retval;
+ return 0;
}
-static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
- bool enable)
+static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+ bool enable)
{
u8 data;
+ int ret;
if (enable) {
analogix_dp_enable_scrambling(dp);
- drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
- drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
+ ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
+ &data);
+ if (ret != 1)
+ return ret;
+
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
+ if (ret < 0)
+ return ret;
} else {
analogix_dp_disable_scrambling(dp);
- drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
- drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
+ ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
+ &data);
+ if (ret != 1)
+ return ret;
+
+ ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
+ if (ret < 0)
+ return ret;
}
+
+ return 0;
}
static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
@@ -943,23 +1016,36 @@ static int analogix_dp_commit(struct analogix_dp_device *dp)
return ret;
}
- analogix_dp_enable_scramble(dp, 1);
+ ret = analogix_dp_enable_scramble(dp, 1);
+ if (ret < 0) {
+ dev_err(dp->dev, "can not enable scramble\n");
+ return ret;
+ }
analogix_dp_init_video(dp);
ret = analogix_dp_config_video(dp);
- if (ret)
+ if (ret) {
dev_err(dp->dev, "unable to config video\n");
+ return ret;
+ }
/* Safe to enable the panel now */
if (dp->plat_data->panel) {
- if (drm_panel_enable(dp->plat_data->panel))
+ ret = drm_panel_enable(dp->plat_data->panel);
+ if (ret) {
DRM_ERROR("failed to enable the panel\n");
+ return ret;
+ }
}
- dp->psr_enable = analogix_dp_detect_sink_psr(dp);
+ ret = analogix_dp_detect_sink_psr(dp);
+ if (ret)
+ return ret;
+
if (dp->psr_enable)
- analogix_dp_enable_sink_psr(dp);
- return 0;
+ ret = analogix_dp_enable_sink_psr(dp);
+
+ return ret;
}
/*
@@ -1186,8 +1272,10 @@ static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
}
ret = analogix_dp_commit(dp);
- if (ret)
+ if (ret) {
+ DRM_ERROR("dp commit error, ret = %d\n", ret);
goto out_dp_init;
+ }
enable_irq(dp->irq);
return 0;
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 23/43] drm/bridge: analogix_dp: Fix AUX_PD bit for Rockchip
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (16 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 22/43] drm/bridge: analogix_dp: Check dpcd write/read status Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 24/43] drm/bridge: analogix_dp: Reset aux channel if an error occurred Thierry Escande
` (10 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
There are some different bits between Rockchip and Exynos in register
"AUX_PD". This patch fixes the incorrect operations about it.
Cc: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Reviewed-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 117 ++++++++++++----------
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 2 +
2 files changed, 65 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index bb72f8b0e603..dee1ba109b5f 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -248,76 +248,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
{
u32 reg;
u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+ u32 mask;
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
phy_pd_addr = ANALOGIX_DP_PD;
switch (block) {
case AUX_BLOCK:
- if (enable) {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg |= AUX_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- } else {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg &= ~AUX_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- }
+ if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
+ mask = RK_AUX_PD;
+ else
+ mask = AUX_PD;
+
+ reg = readl(dp->reg_base + phy_pd_addr);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH0_BLOCK:
- if (enable) {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg |= CH0_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- } else {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg &= ~CH0_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- }
+ mask = CH0_PD;
+ reg = readl(dp->reg_base + phy_pd_addr);
+
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH1_BLOCK:
- if (enable) {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg |= CH1_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- } else {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg &= ~CH1_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- }
+ mask = CH1_PD;
+ reg = readl(dp->reg_base + phy_pd_addr);
+
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH2_BLOCK:
- if (enable) {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg |= CH2_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- } else {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg &= ~CH2_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- }
+ mask = CH2_PD;
+ reg = readl(dp->reg_base + phy_pd_addr);
+
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ writel(reg, dp->reg_base + phy_pd_addr);
break;
case CH3_BLOCK:
- if (enable) {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg |= CH3_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- } else {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg &= ~CH3_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- }
+ mask = CH3_PD;
+ reg = readl(dp->reg_base + phy_pd_addr);
+
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ writel(reg, dp->reg_base + phy_pd_addr);
break;
case ANALOG_TOTAL:
- if (enable) {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg |= DP_PHY_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- } else {
- reg = readl(dp->reg_base + phy_pd_addr);
- reg &= ~DP_PHY_PD;
- writel(reg, dp->reg_base + phy_pd_addr);
- }
+ /*
+ * There is no bit named DP_PHY_PD, so We used DP_INC_BG
+ * to power off everything instead of DP_PHY_PD in
+ * Rockchip
+ */
+ if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
+ mask = DP_INC_BG;
+ else
+ mask = DP_PHY_PD;
+
+ reg = readl(dp->reg_base + phy_pd_addr);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ writel(reg, dp->reg_base + phy_pd_addr);
+ if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
+ usleep_range(10, 15);
break;
case POWER_ALL:
if (enable) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 9602668669f4..b633a4a5082a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -345,7 +345,9 @@
#define DP_INC_BG (0x1 << 7)
#define DP_EXP_BG (0x1 << 6)
#define DP_PHY_PD (0x1 << 5)
+#define RK_AUX_PD (0x1 << 5)
#define AUX_PD (0x1 << 4)
+#define RK_PLL_PD (0x1 << 4)
#define CH3_PD (0x1 << 3)
#define CH2_PD (0x1 << 2)
#define CH1_PD (0x1 << 1)
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 24/43] drm/bridge: analogix_dp: Reset aux channel if an error occurred
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (17 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 23/43] drm/bridge: analogix_dp: Fix AUX_PD bit for Rockchip Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 26/43] drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll Thierry Escande
` (9 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Lin Huang <hl@rock-chips.com>
AUX errors are caused by many different reasons. We may not know what
happened in aux channel on failure, so let's reset aux channel if some
errors occurred.
Cc: 征增 王 <wzz@rock-chips.com>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index dee1ba109b5f..7b7fd227e1f9 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -466,6 +466,10 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
reg = RPLY_RECEIV | AUX_ERR;
writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
+ analogix_dp_set_analog_power_down(dp, AUX_BLOCK, true);
+ usleep_range(10, 11);
+ analogix_dp_set_analog_power_down(dp, AUX_BLOCK, false);
+
analogix_dp_reset_aux(dp);
/* Disable AUX transaction H/W retry */
@@ -1159,7 +1163,7 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
reg, !(reg & AUX_EN), 25, 500 * 1000);
if (ret) {
dev_err(dp->dev, "AUX CH enable timeout!\n");
- return -ETIMEDOUT;
+ goto aux_error;
}
/* TODO: Wait for an interrupt instead of looping? */
@@ -1168,7 +1172,7 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
reg, reg & RPLY_RECEIV, 10, 20 * 1000);
if (ret) {
dev_err(dp->dev, "AUX CH cmd reply timeout!\n");
- return -ETIMEDOUT;
+ goto aux_error;
}
/* Clear interrupt source for AUX CH command reply */
@@ -1178,7 +1182,7 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
if (reg & AUX_ERR) {
writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
- return -EREMOTEIO;
+ goto aux_error;
}
/* Check AUX CH error access status */
@@ -1186,7 +1190,7 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
if ((reg & AUX_STATUS_MASK)) {
dev_err(dp->dev, "AUX CH error happened: %d\n\n",
reg & AUX_STATUS_MASK);
- return -EREMOTEIO;
+ goto aux_error;
}
if (msg->request & DP_AUX_I2C_READ) {
@@ -1212,4 +1216,10 @@ ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
msg->reply = DP_AUX_NATIVE_REPLY_ACK;
return num_transferred > 0 ? num_transferred : -EBUSY;
+
+aux_error:
+ /* if aux err happen, reset aux */
+ analogix_dp_init_aux(dp);
+
+ return -EREMOTEIO;
}
--
2.14.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 26/43] drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (18 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 24/43] drm/bridge: analogix_dp: Reset aux channel if an error occurred Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 27/43] drm/bridge: analogix_dp: Fix timeout of video streamclk config Thierry Escande
` (8 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Cc: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Reviewed-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 7b7fd227e1f9..02ab1aaa9993 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -230,16 +230,20 @@ enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
{
u32 reg;
+ u32 mask = DP_PLL_PD;
+ u32 pd_addr = ANALOGIX_DP_PLL_CTL;
- if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
- reg |= DP_PLL_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
- } else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
- reg &= ~DP_PLL_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+ if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
+ pd_addr = ANALOGIX_DP_PD;
+ mask = RK_PLL_PD;
}
+
+ reg = readl(dp->reg_base + pd_addr);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ writel(reg, dp->reg_base + pd_addr);
}
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 27/43] drm/bridge: analogix_dp: Fix timeout of video streamclk config
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (19 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 26/43] drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 28/43] drm/bridge: analogix_dp: Fix incorrect operations with register ANALOGIX_DP_FUNC_EN_1 Thierry Escande
` (7 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
The STRM_VALID bit in register ANALOGIX_DP_SYS_CTL_3 may be unstable,
so we may hit the error log "Timeout of video streamclk ok" since
checked this unstable bit.
In fact, we can go continue and the streamclk is ok if we wait enough time,
it does no effect on display.
Let's change this error to warn.
Cc: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Reviewed-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index e925c62eaadb..a64f0c3e795c 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -921,8 +921,9 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
done_count = 0;
}
if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
- dev_err(dp->dev, "Timeout of video streamclk ok\n");
- return -ETIMEDOUT;
+ dev_warn(dp->dev,
+ "Ignoring timeout of video streamclk ok\n");
+ break;
}
usleep_range(1000, 1001);
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 28/43] drm/bridge: analogix_dp: Fix incorrect operations with register ANALOGIX_DP_FUNC_EN_1
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (20 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 27/43] drm/bridge: analogix_dp: Fix timeout of video streamclk config Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:28 ` [PATCH v3 29/43] drm/bridge: analogix_dp: Move fast link training detect to set_bridge Thierry Escande
` (6 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Register ANALOGIX_DP_FUNC_EN_1(offset 0x18), Rockchip is different to
Exynos:
on Exynos edp phy,
BIT 7 MASTER_VID_FUNC_EN_N
BIT 6 reserved
BIT 5 SLAVE_VID_FUNC_EN_N
on Rockchip edp phy,
BIT 7 reserved
BIT 6 RK_VID_CAP_FUNC_EN_N
BIT 5 RK_VID_FIFO_FUNC_EN_N
So, we should do some private operations to Rockchip.
Cc: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Reviewed-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 19 ++++++++++++++-----
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 2 ++
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 02ab1aaa9993..4eae206ec31b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -126,9 +126,14 @@ void analogix_dp_reset(struct analogix_dp_device *dp)
analogix_dp_stop_video(dp);
analogix_dp_enable_video_mute(dp, 0);
- reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
- AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
- HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+ if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
+ reg = RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N |
+ SW_FUNC_EN_N;
+ else
+ reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+ AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+ HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
@@ -971,8 +976,12 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
u32 reg;
reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
- reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
- reg |= MASTER_VID_FUNC_EN_N;
+ if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
+ reg &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N);
+ } else {
+ reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
+ reg |= MASTER_VID_FUNC_EN_N;
+ }
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index b633a4a5082a..0cf27c731727 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -127,7 +127,9 @@
/* ANALOGIX_DP_FUNC_EN_1 */
#define MASTER_VID_FUNC_EN_N (0x1 << 7)
+#define RK_VID_CAP_FUNC_EN_N (0x1 << 6)
#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
+#define RK_VID_FIFO_FUNC_EN_N (0x1 << 5)
#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
#define AUD_FUNC_EN_N (0x1 << 3)
#define HDCP_FUNC_EN_N (0x1 << 2)
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 29/43] drm/bridge: analogix_dp: Move fast link training detect to set_bridge
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (21 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 28/43] drm/bridge: analogix_dp: Fix incorrect operations with register ANALOGIX_DP_FUNC_EN_1 Thierry Escande
@ 2018-01-30 20:28 ` Thierry Escande
2018-01-30 20:29 ` [PATCH v3 30/43] drm/bridge: analogix_dp: Reorder plat_data->power_off to happen sooner Thierry Escande
` (5 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:28 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
It's too early to detect fast link training, if other step after it
failed, we will set fast_link flag to 1, and retry set_bridge again. In
this case we will power down and power up panel power supply, and we
will do fast link training since we have set fast_link flag to 1. In
fact, we should do full link training now, not the fast link training.
So we should move the fast link detection at the end of set_bridge.
Cc: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: zain wang <wzz-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Reviewed-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 42 +++++++++++++---------
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index a64f0c3e795c..f82e2a3d13bf 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -601,7 +601,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
{
int lane, lane_count, retval;
u32 reg;
- u8 link_align, link_status[2], adjust_request[2], spread;
+ u8 link_align, link_status[2], adjust_request[2];
usleep_range(400, 401);
@@ -645,20 +645,6 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
dev_dbg(dp->dev, "final lane count = %.2x\n",
dp->link_train.lane_count);
- retval = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD,
- &spread);
- if (retval != 1) {
- dev_err(dp->dev, "failed to read downspread %d\n",
- retval);
- dp->fast_train_enable = false;
- } else {
- dp->fast_train_enable =
- (spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING) ?
- true : false;
- }
- dev_dbg(dp->dev, "fast link training %s\n",
- dp->fast_train_enable ? "supported" : "unsupported");
-
dp->link_train.lt_state = FINISHED;
return 0;
@@ -1003,6 +989,22 @@ static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
return IRQ_HANDLED;
}
+static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
+{
+ int ret;
+ u8 spread;
+
+ ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
+ if (ret != 1) {
+ dev_err(dp->dev, "failed to read downspread %d\n", ret);
+ return ret;
+ }
+ dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
+ dev_dbg(dp->dev, "fast link training %s\n",
+ dp->fast_train_enable ? "supported" : "unsupported");
+ return 0;
+}
+
static int analogix_dp_commit(struct analogix_dp_device *dp)
{
int ret;
@@ -1045,8 +1047,16 @@ static int analogix_dp_commit(struct analogix_dp_device *dp)
if (ret)
return ret;
- if (dp->psr_enable)
+ if (dp->psr_enable) {
ret = analogix_dp_enable_sink_psr(dp);
+ if (ret)
+ return ret;
+ }
+
+ /* Check whether panel supports fast training */
+ ret = analogix_dp_fast_link_train_detection(dp);
+ if (ret)
+ dp->psr_enable = false;
return ret;
}
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 30/43] drm/bridge: analogix_dp: Reorder plat_data->power_off to happen sooner
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (22 preceding siblings ...)
2018-01-30 20:28 ` [PATCH v3 29/43] drm/bridge: analogix_dp: Move fast link training detect to set_bridge Thierry Escande
@ 2018-01-30 20:29 ` Thierry Escande
2018-01-30 20:29 ` [PATCH v3 32/43] drm/bridge: analogix_dp: Properly disable aux chan retries on rockchip Thierry Escande
` (4 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:29 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
The current user of the analogix power_off is "analogix_dp-rockchip".
That driver does this:
- deactivate PSR
- turn off a clock
Both of these things (especially deactive PSR) should be done before
we turn the PHY power off and turn off analog power. Let's move the
callback up.
Note that without this patch (and with
https://patchwork.kernel.org/patch/9553349/ [seanpaul: this patch was
not applied, but it seems like the race can still occur]), I experienced
an error in reboot testing where one thread was at:
rockchip_drm_psr_deactivate
rockchip_dp_powerdown
analogix_dp_bridge_disable
drm_bridge_disable
...and the other thread was at:
analogix_dp_send_psr_spd
analogix_dp_enable_psr
analogix_dp_psr_set
psr_flush_handler
The flush handler thread was finding AUX channel errors and eventually
reported "Failed to apply PSR", where I had a kgdb breakpoint. Presumably
the device would have eventually given up and shut down anyway, but it
seems better to fix the order to be more correct.
Cc: Kristian H. Kristensen <hoegsberg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Reviewed-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index f82e2a3d13bf..23404de7ffc9 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1341,12 +1341,13 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
}
disable_irq(dp->irq);
- phy_power_off(dp->phy);
- analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
if (dp->plat_data->power_off)
dp->plat_data->power_off(dp->plat_data);
+ phy_power_off(dp->phy);
+ analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
+
clk_disable_unprepare(dp->clock);
pm_runtime_put_sync(dp->dev);
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 32/43] drm/bridge: analogix_dp: Properly disable aux chan retries on rockchip
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (23 preceding siblings ...)
2018-01-30 20:29 ` [PATCH v3 30/43] drm/bridge: analogix_dp: Reorder plat_data->power_off to happen sooner Thierry Escande
@ 2018-01-30 20:29 ` Thierry Escande
2018-01-30 20:29 ` [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31 Thierry Escande
` (3 subsequent siblings)
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:29 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Douglas Anderson <dianders@chromium.org>
The comments in analogix_dp_init_aux() claim that we're disabling aux
channel retries, but then right below it for Rockchip it sets them to
3. If we actually need 3 retries for Rockchip then we could adjust
the comment, but it seems more likely that we want the same retry
behavior across all platforms.
Cc: Stéphane Marchesin <marcheu@chromium.org>
Cc: 征增 王 <wzz@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 58e8a28e99aa..a5f2763d72e4 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -481,15 +481,16 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
analogix_dp_reset_aux(dp);
- /* Disable AUX transaction H/W retry */
+ /* AUX_BIT_PERIOD_EXPECTED_DELAY doesn't apply to Rockchip IP */
if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
- reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
- AUX_HW_RETRY_COUNT_SEL(3) |
- AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+ reg = 0;
else
- reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
- AUX_HW_RETRY_COUNT_SEL(0) |
- AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+ reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3);
+
+ /* Disable AUX transaction H/W retry */
+ reg |= AUX_HW_RETRY_COUNT_SEL(0) |
+ AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
--
2.14.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (24 preceding siblings ...)
2018-01-30 20:29 ` [PATCH v3 32/43] drm/bridge: analogix_dp: Properly disable aux chan retries on rockchip Thierry Escande
@ 2018-01-30 20:29 ` Thierry Escande
2018-01-31 12:54 ` Lucas Stach
2018-01-30 20:29 ` [PATCH v3 34/43] drm/rockchip: pre dither down when output bpc is 8bit Thierry Escande
` (2 subsequent siblings)
28 siblings, 1 reply; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:29 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Sean Paul <seanpaul@chromium.org>
Change the mode for Sharp lq123p1jx31 panel to something more
rockchip-friendly such that we can use the fixed PLLs to
generate the pixel clock
Cc: Chris Zhong <zyw@rock-chips.com>
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
---
drivers/gpu/drm/panel/panel-simple.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 5591984a392b..a4a6ea3ca0e6 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1742,17 +1742,18 @@ static const struct panel_desc sharp_lq101k1ly04 = {
};
static const struct drm_display_mode sharp_lq123p1jx31_mode = {
- .clock = 252750,
+ .clock = 266667,
.hdisplay = 2400,
.hsync_start = 2400 + 48,
.hsync_end = 2400 + 48 + 32,
- .htotal = 2400 + 48 + 32 + 80,
+ .htotal = 2400 + 48 + 32 + 139,
.vdisplay = 1600,
.vsync_start = 1600 + 3,
.vsync_end = 1600 + 3 + 10,
- .vtotal = 1600 + 3 + 10 + 33,
+ .vtotal = 1600 + 3 + 10 + 84,
.vrefresh = 60,
.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+ .type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER,
};
static const struct panel_desc sharp_lq123p1jx31 = {
--
2.14.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31
2018-01-30 20:29 ` [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31 Thierry Escande
@ 2018-01-31 12:54 ` Lucas Stach
2018-01-31 15:16 ` Sean Paul
0 siblings, 1 reply; 62+ messages in thread
From: Lucas Stach @ 2018-01-31 12:54 UTC (permalink / raw)
To: Thierry Escande, Archit Taneja, Inki Dae, Thierry Reding,
Sandy Huang, Sean Paul, David Airlie, Tomasz Figa,
Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, linux-kernel, dri-devel, Douglas Anderson,
linux-rockchip, Yakir Yang, Ørjan Eide, Haixia Shi,
Mark Yao
Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande:
> From: Sean Paul <seanpaul@chromium.org>
>
> Change the mode for Sharp lq123p1jx31 panel to something more
> rockchip-friendly such that we can use the fixed PLLs to
> generate the pixel clock
This should really switch to a display timing instead of exposing a
single mode. The display timing has min, typical, max tuples for all
the timings values, which would allow the attached driver to vary the
timings inside the allowed bounds if it makes sense.
Trying to hit a specific pixel clock to free up a PLL is exactly one of
the use cases envisioned for the display timings stuff.
Regards,
Lucas
> Cc: Chris Zhong <zyw@rock-chips.com>
> Cc: Stéphane Marchesin <marcheu@chromium.org>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
> ---
> drivers/gpu/drm/panel/panel-simple.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c
> b/drivers/gpu/drm/panel/panel-simple.c
> index 5591984a392b..a4a6ea3ca0e6 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -1742,17 +1742,18 @@ static const struct panel_desc
> sharp_lq101k1ly04 = {
> };
>
> static const struct drm_display_mode sharp_lq123p1jx31_mode = {
> - .clock = 252750,
> + .clock = 266667,
> .hdisplay = 2400,
> .hsync_start = 2400 + 48,
> .hsync_end = 2400 + 48 + 32,
> - .htotal = 2400 + 48 + 32 + 80,
> + .htotal = 2400 + 48 + 32 + 139,
> .vdisplay = 1600,
> .vsync_start = 1600 + 3,
> .vsync_end = 1600 + 3 + 10,
> - .vtotal = 1600 + 3 + 10 + 33,
> + .vtotal = 1600 + 3 + 10 + 84,
> .vrefresh = 60,
> .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
> + .type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER,
> };
>
> static const struct panel_desc sharp_lq123p1jx31 = {
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31
2018-01-31 12:54 ` Lucas Stach
@ 2018-01-31 15:16 ` Sean Paul
2018-01-31 16:52 ` Doug Anderson
0 siblings, 1 reply; 62+ messages in thread
From: Sean Paul @ 2018-01-31 15:16 UTC (permalink / raw)
To: Lucas Stach
Cc: Douglas Anderson, Thierry Escande, Lin Huang, David Airlie,
Linux Kernel Mailing List, dri-devel, Tomasz Figa,
open list:ARM/Rockchip SoC...,
Thierry Reding, Yakir Yang, Enric Balletbo i Serra,
Ørjan Eide, Haixia Shi, Zain Wang, Mark Yao
On Wed, Jan 31, 2018 at 7:54 AM, Lucas Stach <l.stach@pengutronix.de> wrote:
> Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande:
>> From: Sean Paul <seanpaul@chromium.org>
>>
>> Change the mode for Sharp lq123p1jx31 panel to something more
>> rockchip-friendly such that we can use the fixed PLLs to
>> generate the pixel clock
>
> This should really switch to a display timing instead of exposing a
> single mode. The display timing has min, typical, max tuples for all
> the timings values, which would allow the attached driver to vary the
> timings inside the allowed bounds if it makes sense.
>
> Trying to hit a specific pixel clock to free up a PLL is exactly one of
> the use cases envisioned for the display timings stuff.
>
Agreed, I think we had this discussion the first time around. We
should drop this patch.
Thanks for catching this!
Sean
> Regards,
> Lucas
>
>> Cc: Chris Zhong <zyw@rock-chips.com>
>> Cc: Stéphane Marchesin <marcheu@chromium.org>
>> Signed-off-by: Sean Paul <seanpaul@chromium.org>
>> Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
>> ---
>> drivers/gpu/drm/panel/panel-simple.c | 7 ++++---
>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/panel/panel-simple.c
>> b/drivers/gpu/drm/panel/panel-simple.c
>> index 5591984a392b..a4a6ea3ca0e6 100644
>> --- a/drivers/gpu/drm/panel/panel-simple.c
>> +++ b/drivers/gpu/drm/panel/panel-simple.c
>> @@ -1742,17 +1742,18 @@ static const struct panel_desc
>> sharp_lq101k1ly04 = {
>> };
>>
>> static const struct drm_display_mode sharp_lq123p1jx31_mode = {
>> - .clock = 252750,
>> + .clock = 266667,
>> .hdisplay = 2400,
>> .hsync_start = 2400 + 48,
>> .hsync_end = 2400 + 48 + 32,
>> - .htotal = 2400 + 48 + 32 + 80,
>> + .htotal = 2400 + 48 + 32 + 139,
>> .vdisplay = 1600,
>> .vsync_start = 1600 + 3,
>> .vsync_end = 1600 + 3 + 10,
>> - .vtotal = 1600 + 3 + 10 + 33,
>> + .vtotal = 1600 + 3 + 10 + 84,
>> .vrefresh = 60,
>> .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
>> + .type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER,
>> };
>>
>> static const struct panel_desc sharp_lq123p1jx31 = {
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31
2018-01-31 15:16 ` Sean Paul
@ 2018-01-31 16:52 ` Doug Anderson
2018-02-16 12:34 ` Enric Balletbo Serra
0 siblings, 1 reply; 62+ messages in thread
From: Doug Anderson @ 2018-01-31 16:52 UTC (permalink / raw)
To: Sean Paul
Cc: Haixia Shi, Thierry Escande, Lin Huang, David Airlie,
Linux Kernel Mailing List, dri-devel, Tomasz Figa,
open list:ARM/Rockchip SoC...,
Thierry Reding, Yakir Yang, Enric Balletbo i Serra,
Ørjan Eide, Mark Yao, Zain Wang
Hi,
On Wed, Jan 31, 2018 at 7:16 AM, Sean Paul <seanpaul@chromium.org> wrote:
> On Wed, Jan 31, 2018 at 7:54 AM, Lucas Stach <l.stach@pengutronix.de> wrote:
>> Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande:
>>> From: Sean Paul <seanpaul@chromium.org>
>>>
>>> Change the mode for Sharp lq123p1jx31 panel to something more
>>> rockchip-friendly such that we can use the fixed PLLs to
>>> generate the pixel clock
>>
>> This should really switch to a display timing instead of exposing a
>> single mode. The display timing has min, typical, max tuples for all
>> the timings values, which would allow the attached driver to vary the
>> timings inside the allowed bounds if it makes sense.
>>
>> Trying to hit a specific pixel clock to free up a PLL is exactly one of
>> the use cases envisioned for the display timings stuff.
>>
>
> Agreed, I think we had this discussion the first time around. We
> should drop this patch.
>
> Thanks for catching this!
Are you sure we should drop this? In order for things to work
properly (not generate noise on the digitizer or other EMI), this
needs to run at a very specific pixel clock with very specific
blanking times. I know that earlier we had slightly different
blanking times and Samsung came back and said that there was noise on
the digitizer. I could be wrong, but I don't think there's any way
currently to be able to specify exactly what timings should be used on
a particular board.
Don't get be wrong--I think a patch such as this one that claims a
single board's timings as the "right" ones for a generic panel is a
bit of a hack. ...but at the same time there are no other users of
this panel (that I know of) in mainline and the timings presented here
are certainly sane timings for this panel.
In any case, previous discussion at: https://patchwork.kernel.org/patch/9614603/
...oh, and looking at the previous discussion reminds me that the
timings presented in this here patch are actually not the right ones
(they have the right PLL, but the wrong blankings to avoid the noise
issues). See <//chromium-review.googlesource.com/381015>
-Doug
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31
2018-01-31 16:52 ` Doug Anderson
@ 2018-02-16 12:34 ` Enric Balletbo Serra
2018-02-16 20:54 ` Doug Anderson
0 siblings, 1 reply; 62+ messages in thread
From: Enric Balletbo Serra @ 2018-02-16 12:34 UTC (permalink / raw)
To: Doug Anderson
Cc: Thierry Escande, Lin Huang, David Airlie,
Linux Kernel Mailing List, dri-devel, Tomasz Figa,
open list:ARM/Rockchip SoC...,
Thierry Reding, Yakir Yang, Enric Balletbo i Serra,
Ørjan Eide, Mark Yao, Zain Wang, Haixia Shi
Hi,
2018-01-31 17:52 GMT+01:00 Doug Anderson <dianders@chromium.org>:
> Hi,
>
>
> On Wed, Jan 31, 2018 at 7:16 AM, Sean Paul <seanpaul@chromium.org> wrote:
>> On Wed, Jan 31, 2018 at 7:54 AM, Lucas Stach <l.stach@pengutronix.de> wrote:
>>> Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande:
>>>> From: Sean Paul <seanpaul@chromium.org>
>>>>
>>>> Change the mode for Sharp lq123p1jx31 panel to something more
>>>> rockchip-friendly such that we can use the fixed PLLs to
>>>> generate the pixel clock
>>>
>>> This should really switch to a display timing instead of exposing a
>>> single mode. The display timing has min, typical, max tuples for all
>>> the timings values, which would allow the attached driver to vary the
>>> timings inside the allowed bounds if it makes sense.
>>>
>>> Trying to hit a specific pixel clock to free up a PLL is exactly one of
>>> the use cases envisioned for the display timings stuff.
>>>
>>
>> Agreed, I think we had this discussion the first time around. We
>> should drop this patch.
>>
>> Thanks for catching this!
>
> Are you sure we should drop this? In order for things to work
> properly (not generate noise on the digitizer or other EMI), this
> needs to run at a very specific pixel clock with very specific
> blanking times. I know that earlier we had slightly different
> blanking times and Samsung came back and said that there was noise on
> the digitizer. I could be wrong, but I don't think there's any way
> currently to be able to specify exactly what timings should be used on
> a particular board.
>
> Don't get be wrong--I think a patch such as this one that claims a
> single board's timings as the "right" ones for a generic panel is a
> bit of a hack. ...but at the same time there are no other users of
> this panel (that I know of) in mainline and the timings presented here
> are certainly sane timings for this panel.
>
> In any case, previous discussion at: https://patchwork.kernel.org/patch/9614603/
>
>
> ...oh, and looking at the previous discussion reminds me that the
> timings presented in this here patch are actually not the right ones
> (they have the right PLL, but the wrong blankings to avoid the noise
> issues). See <//chromium-review.googlesource.com/381015>
>
As Thierry no longer has the hardware to test these patch series, I'll
take care of these and follow the upstreaming process. I think that
doesn't make sense send a v4 version of all 43 patches for this
change. Right now, only this patch received comments so I'll wait a
bit more for if we can get the other patches reviewed. If the others
are fine just and I don't need to send a new version just don't apply
this one and I will send a second version of that specific patch. Or
even better, is really trivial what needs to be changed, so maybe the
maintainer can do it? ;)
Regards,
Enric
>
>
> -Doug
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31
2018-02-16 12:34 ` Enric Balletbo Serra
@ 2018-02-16 20:54 ` Doug Anderson
2018-02-19 9:42 ` Enric Balletbo Serra
0 siblings, 1 reply; 62+ messages in thread
From: Doug Anderson @ 2018-02-16 20:54 UTC (permalink / raw)
To: Enric Balletbo Serra
Cc: Thierry Escande, Lin Huang, David Airlie,
Linux Kernel Mailing List, dri-devel, Tomasz Figa,
open list:ARM/Rockchip SoC...,
Thierry Reding, Yakir Yang, Enric Balletbo i Serra,
Ørjan Eide, Mark Yao, Zain Wang, Haixia Shi
Hi,
On Fri, Feb 16, 2018 at 4:34 AM, Enric Balletbo Serra
<eballetbo@gmail.com> wrote:
> Hi,
>
> 2018-01-31 17:52 GMT+01:00 Doug Anderson <dianders@chromium.org>:
>> Hi,
>>
>>
>> On Wed, Jan 31, 2018 at 7:16 AM, Sean Paul <seanpaul@chromium.org> wrote:
>>> On Wed, Jan 31, 2018 at 7:54 AM, Lucas Stach <l.stach@pengutronix.de> wrote:
>>>> Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande:
>>>>> From: Sean Paul <seanpaul@chromium.org>
>>>>>
>>>>> Change the mode for Sharp lq123p1jx31 panel to something more
>>>>> rockchip-friendly such that we can use the fixed PLLs to
>>>>> generate the pixel clock
>>>>
>>>> This should really switch to a display timing instead of exposing a
>>>> single mode. The display timing has min, typical, max tuples for all
>>>> the timings values, which would allow the attached driver to vary the
>>>> timings inside the allowed bounds if it makes sense.
>>>>
>>>> Trying to hit a specific pixel clock to free up a PLL is exactly one of
>>>> the use cases envisioned for the display timings stuff.
>>>>
>>>
>>> Agreed, I think we had this discussion the first time around. We
>>> should drop this patch.
>>>
>>> Thanks for catching this!
>>
>> Are you sure we should drop this? In order for things to work
>> properly (not generate noise on the digitizer or other EMI), this
>> needs to run at a very specific pixel clock with very specific
>> blanking times. I know that earlier we had slightly different
>> blanking times and Samsung came back and said that there was noise on
>> the digitizer. I could be wrong, but I don't think there's any way
>> currently to be able to specify exactly what timings should be used on
>> a particular board.
>>
>> Don't get be wrong--I think a patch such as this one that claims a
>> single board's timings as the "right" ones for a generic panel is a
>> bit of a hack. ...but at the same time there are no other users of
>> this panel (that I know of) in mainline and the timings presented here
>> are certainly sane timings for this panel.
>>
>> In any case, previous discussion at: https://patchwork.kernel.org/patch/9614603/
>>
>>
>> ...oh, and looking at the previous discussion reminds me that the
>> timings presented in this here patch are actually not the right ones
>> (they have the right PLL, but the wrong blankings to avoid the noise
>> issues). See <//chromium-review.googlesource.com/381015>
>>
>
> As Thierry no longer has the hardware to test these patch series, I'll
> take care of these and follow the upstreaming process. I think that
> doesn't make sense send a v4 version of all 43 patches for this
> change. Right now, only this patch received comments so I'll wait a
> bit more for if we can get the other patches reviewed. If the others
> are fine just and I don't need to send a new version just don't apply
> this one and I will send a second version of that specific patch. Or
> even better, is really trivial what needs to be changed, so maybe the
> maintainer can do it? ;)
Just as a heads up, Sean Paul has a series of patches to replace this
patch. The following are IDs from patchwork.kernel.org:
10207583 New [v3,1/6] dt-bindings: Clarify timing subnode use
as panel-timing
10207585 New [v3,2/6] dt-bindings: Add headings to
simple-panel bindings
10207591 New [v3,3/6] dt-bindings: Add panel-timing subnode
to simple-panel
10207593 New [v3,4/6] drm/panel: simple: Add ability to
override typical timing
10207595 New [v3,5/6] drm/panel: simple: Use display_timing
for lq123p1jx31
10207603 New [v3,6/6] arm64: dts: rockchip: Specify override
mode for kevin panel
-Doug
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31
2018-02-16 20:54 ` Doug Anderson
@ 2018-02-19 9:42 ` Enric Balletbo Serra
0 siblings, 0 replies; 62+ messages in thread
From: Enric Balletbo Serra @ 2018-02-19 9:42 UTC (permalink / raw)
To: Doug Anderson
Cc: Zain Wang, Lin Huang, David Airlie, Linux Kernel Mailing List,
dri-devel, Tomasz Figa, open list:ARM/Rockchip SoC...,
Thierry Reding, Enric Balletbo i Serra, Ørjan Eide,
Haixia Shi
Hi,
2018-02-16 21:54 GMT+01:00 Doug Anderson <dianders@chromium.org>:
> Hi,
>
> On Fri, Feb 16, 2018 at 4:34 AM, Enric Balletbo Serra
> <eballetbo@gmail.com> wrote:
>> Hi,
>>
>> 2018-01-31 17:52 GMT+01:00 Doug Anderson <dianders@chromium.org>:
>>> Hi,
>>>
>>>
>>> On Wed, Jan 31, 2018 at 7:16 AM, Sean Paul <seanpaul@chromium.org> wrote:
>>>> On Wed, Jan 31, 2018 at 7:54 AM, Lucas Stach <l.stach@pengutronix.de> wrote:
>>>>> Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande:
>>>>>> From: Sean Paul <seanpaul@chromium.org>
>>>>>>
>>>>>> Change the mode for Sharp lq123p1jx31 panel to something more
>>>>>> rockchip-friendly such that we can use the fixed PLLs to
>>>>>> generate the pixel clock
>>>>>
>>>>> This should really switch to a display timing instead of exposing a
>>>>> single mode. The display timing has min, typical, max tuples for all
>>>>> the timings values, which would allow the attached driver to vary the
>>>>> timings inside the allowed bounds if it makes sense.
>>>>>
>>>>> Trying to hit a specific pixel clock to free up a PLL is exactly one of
>>>>> the use cases envisioned for the display timings stuff.
>>>>>
>>>>
>>>> Agreed, I think we had this discussion the first time around. We
>>>> should drop this patch.
>>>>
>>>> Thanks for catching this!
>>>
>>> Are you sure we should drop this? In order for things to work
>>> properly (not generate noise on the digitizer or other EMI), this
>>> needs to run at a very specific pixel clock with very specific
>>> blanking times. I know that earlier we had slightly different
>>> blanking times and Samsung came back and said that there was noise on
>>> the digitizer. I could be wrong, but I don't think there's any way
>>> currently to be able to specify exactly what timings should be used on
>>> a particular board.
>>>
>>> Don't get be wrong--I think a patch such as this one that claims a
>>> single board's timings as the "right" ones for a generic panel is a
>>> bit of a hack. ...but at the same time there are no other users of
>>> this panel (that I know of) in mainline and the timings presented here
>>> are certainly sane timings for this panel.
>>>
>>> In any case, previous discussion at: https://patchwork.kernel.org/patch/9614603/
>>>
>>>
>>> ...oh, and looking at the previous discussion reminds me that the
>>> timings presented in this here patch are actually not the right ones
>>> (they have the right PLL, but the wrong blankings to avoid the noise
>>> issues). See <//chromium-review.googlesource.com/381015>
>>>
>>
>> As Thierry no longer has the hardware to test these patch series, I'll
>> take care of these and follow the upstreaming process. I think that
>> doesn't make sense send a v4 version of all 43 patches for this
>> change. Right now, only this patch received comments so I'll wait a
>> bit more for if we can get the other patches reviewed. If the others
>> are fine just and I don't need to send a new version just don't apply
>> this one and I will send a second version of that specific patch. Or
>> even better, is really trivial what needs to be changed, so maybe the
>> maintainer can do it? ;)
>
> Just as a heads up, Sean Paul has a series of patches to replace this
> patch. The following are IDs from patchwork.kernel.org:
>
> 10207583 New [v3,1/6] dt-bindings: Clarify timing subnode use
> as panel-timing
> 10207585 New [v3,2/6] dt-bindings: Add headings to
> simple-panel bindings
> 10207591 New [v3,3/6] dt-bindings: Add panel-timing subnode
> to simple-panel
> 10207593 New [v3,4/6] drm/panel: simple: Add ability to
> override typical timing
> 10207595 New [v3,5/6] drm/panel: simple: Use display_timing
> for lq123p1jx31
> 10207603 New [v3,6/6] arm64: dts: rockchip: Specify override
> mode for kevin panel
>
> -Doug
Nice, I was not aware of these, I'll test. That means that this patch
can be removed from these series as the Sean solution is a lot better.
Just a note that this patch can be removed without any collateral
impact on the other patches, so just ignore it.
Regards,
Enric
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 34/43] drm/rockchip: pre dither down when output bpc is 8bit
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (25 preceding siblings ...)
2018-01-30 20:29 ` [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31 Thierry Escande
@ 2018-01-30 20:29 ` Thierry Escande
2018-01-30 20:29 ` [PATCH v3 36/43] drm/rockchip: analogix_dp: Do not call Analogix code before bind Thierry Escande
2018-01-30 20:29 ` [PATCH v3 37/43] drm/rockchip: Disable PSR on input events Thierry Escande
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:29 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Some encoder have a crc verification check, crc check fail if
input and output data is not equal.
That means encoder input and output need use same color depth,
vop can output 10bit data to encoder, but some panel only support
8bit depth, that would make crc check die.
So pre dither down vop data to 8bit if panel's bpc is 8.
Signed-off-by: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
[seanpaul resolved conflict in rockchip_drm_vop.c]
Signed-off-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 2 ++
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 +
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++++++
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
5 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 8c884f9ce713..b3f46ed24cdc 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -218,6 +218,7 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
struct drm_connector_state *conn_state)
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct drm_display_info *di = &conn_state->connector->display_info;
/*
* The hardware IC designed that VOP must output the RGB10 video
@@ -229,6 +230,7 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
s->output_type = DRM_MODE_CONNECTOR_eDP;
+ s->output_bpc = di->bpc;
return 0;
}
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index 9c064a40458b..3a6ebfc26036 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -36,6 +36,7 @@ struct rockchip_crtc_state {
struct drm_crtc_state base;
int output_type;
int output_mode;
+ int output_bpc;
};
#define to_rockchip_crtc_state(s) \
container_of(s, struct rockchip_crtc_state, base)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index bf4b1a2f3fa4..4abb9d72d814 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -937,6 +937,12 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
!(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
s->output_mode = ROCKCHIP_OUT_MODE_P888;
+
+ if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8)
+ VOP_REG_SET(vop, common, pre_dither_down, 1);
+ else
+ VOP_REG_SET(vop, common, pre_dither_down, 0);
+
VOP_REG_SET(vop, common, out_mode, s->output_mode);
VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 56bbd2e2a8ef..084acdd0019a 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -67,6 +67,7 @@ struct vop_common {
struct vop_reg cfg_done;
struct vop_reg dsp_blank;
struct vop_reg data_blank;
+ struct vop_reg pre_dither_down;
struct vop_reg dither_down;
struct vop_reg dither_up;
struct vop_reg gate_en;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 2e4eea3459fe..08023d3ecb76 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -264,6 +264,7 @@ static const struct vop_common rk3288_common = {
.standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
+ .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 36/43] drm/rockchip: analogix_dp: Do not call Analogix code before bind
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (26 preceding siblings ...)
2018-01-30 20:29 ` [PATCH v3 34/43] drm/rockchip: pre dither down when output bpc is 8bit Thierry Escande
@ 2018-01-30 20:29 ` Thierry Escande
2018-01-30 20:29 ` [PATCH v3 37/43] drm/rockchip: Disable PSR on input events Thierry Escande
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:29 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Driver callbacks, such as system suspend or resume can be called any
time, specifically they can be called before the component bind
callback. Let's use dp->adp pointer as a safeguard and skip calling
Analogix entry points if it is an ERR_PTR().
Signed-off-by: Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 23317a2269e1..6d45d62466b3 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -368,6 +368,8 @@ static void rockchip_dp_unbind(struct device *dev, struct device *master,
analogix_dp_unbind(dp->adp);
rockchip_drm_psr_unregister(&dp->encoder);
dp->encoder.funcs->destroy(&dp->encoder);
+
+ dp->adp = ERR_PTR(-ENODEV);
}
static const struct component_ops rockchip_dp_component_ops = {
@@ -391,6 +393,7 @@ static int rockchip_dp_probe(struct platform_device *pdev)
return -ENOMEM;
dp->dev = dev;
+ dp->adp = ERR_PTR(-ENODEV);
dp->plat_data.panel = panel;
ret = rockchip_dp_of_probe(dp);
@@ -414,6 +417,9 @@ static int rockchip_dp_suspend(struct device *dev)
{
struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+ if (IS_ERR(dp->adp))
+ return 0;
+
return analogix_dp_suspend(dp->adp);
}
@@ -421,6 +427,9 @@ static int rockchip_dp_resume(struct device *dev)
{
struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+ if (IS_ERR(dp->adp))
+ return 0;
+
return analogix_dp_resume(dp->adp);
}
#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 37/43] drm/rockchip: Disable PSR on input events
[not found] ` <20180130202913.28724-1-thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
` (27 preceding siblings ...)
2018-01-30 20:29 ` [PATCH v3 36/43] drm/rockchip: analogix_dp: Do not call Analogix code before bind Thierry Escande
@ 2018-01-30 20:29 ` Thierry Escande
28 siblings, 0 replies; 62+ messages in thread
From: Thierry Escande @ 2018-01-30 20:29 UTC (permalink / raw)
To: Archit Taneja, Inki Dae, Thierry Reding, Sandy Huang, Sean Paul,
David Airlie, Tomasz Figa, Enric Balletbo i Serra
Cc: Zain Wang, Lin Huang, Douglas Anderson,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Yakir Yang,
Ørjan Eide, Mark Yao, Haixia Shi
From: "Kristian H. Kristensen" <hoegsberg-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
To improve PSR exit latency, we speculatively start exiting when we
receive input events. Occasionally, this may lead to false positives,
but most of the time we get a head start on coming out of PSR. Depending
on how userspace takes to produce a new frame in response to the event,
this can completely hide the exit latency. In case of Chrome OS, we
typically get the input notifier 50ms or more before the dirty_fb
triggered exit.
Signed-off-by: Kristian H. Kristensen <hoegsberg-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Thierry Escande <thierry.escande-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
drivers/gpu/drm/rockchip/rockchip_drm_psr.c | 134 ++++++++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c b/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
index 9376f4396b6b..a107845ba97c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
@@ -12,6 +12,8 @@
* GNU General Public License for more details.
*/
+#include <linux/input.h>
+
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
@@ -35,6 +37,9 @@ struct psr_drv {
enum psr_state state;
struct delayed_work flush_work;
+ struct work_struct disable_work;
+
+ struct input_handler input_handler;
int (*set)(struct drm_encoder *encoder, bool enable);
};
@@ -133,6 +138,18 @@ static void psr_flush_handler(struct work_struct *work)
mutex_unlock(&psr->lock);
}
+static void psr_disable_handler(struct work_struct *work)
+{
+ struct psr_drv *psr = container_of(work, struct psr_drv, disable_work);
+
+ /* If the state has changed since we initiated the flush, do nothing */
+ mutex_lock(&psr->lock);
+ if (psr->state == PSR_ENABLE)
+ psr_set_state_locked(psr, PSR_FLUSH);
+ mutex_unlock(&psr->lock);
+ mod_delayed_work(system_wq, &psr->flush_work, PSR_FLUSH_TIMEOUT_MS);
+}
+
/**
* rockchip_drm_psr_activate - activate PSR on the given pipe
* @encoder: encoder to obtain the PSR encoder
@@ -173,6 +190,7 @@ int rockchip_drm_psr_deactivate(struct drm_encoder *encoder)
psr->active = false;
mutex_unlock(&psr->lock);
cancel_delayed_work_sync(&psr->flush_work);
+ cancel_work_sync(&psr->disable_work);
return 0;
}
@@ -226,6 +244,95 @@ void rockchip_drm_psr_flush_all(struct drm_device *dev)
}
EXPORT_SYMBOL(rockchip_drm_psr_flush_all);
+static void psr_input_event(struct input_handle *handle,
+ unsigned int type, unsigned int code,
+ int value)
+{
+ struct psr_drv *psr = handle->handler->private;
+
+ schedule_work(&psr->disable_work);
+}
+
+static int psr_input_connect(struct input_handler *handler,
+ struct input_dev *dev,
+ const struct input_device_id *id)
+{
+ struct input_handle *handle;
+ int error;
+
+ handle = kzalloc(sizeof(struct input_handle), GFP_KERNEL);
+ if (!handle)
+ return -ENOMEM;
+
+ handle->dev = dev;
+ handle->handler = handler;
+ handle->name = "rockchip-psr";
+
+ error = input_register_handle(handle);
+ if (error)
+ goto err2;
+
+ error = input_open_device(handle);
+ if (error)
+ goto err1;
+
+ return 0;
+
+err1:
+ input_unregister_handle(handle);
+err2:
+ kfree(handle);
+ return error;
+}
+
+static void psr_input_disconnect(struct input_handle *handle)
+{
+ input_close_device(handle);
+ input_unregister_handle(handle);
+ kfree(handle);
+}
+
+/* Same device ids as cpu-boost */
+static const struct input_device_id psr_ids[] = {
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
+ INPUT_DEVICE_ID_MATCH_ABSBIT,
+ .evbit = { BIT_MASK(EV_ABS) },
+ .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
+ BIT_MASK(ABS_MT_POSITION_X) |
+ BIT_MASK(ABS_MT_POSITION_Y) },
+ }, /* multi-touch touchscreen */
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
+ .evbit = { BIT_MASK(EV_ABS) },
+ .absbit = { [BIT_WORD(ABS_X)] = BIT_MASK(ABS_X) }
+
+ }, /* stylus or joystick device */
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
+ .evbit = { BIT_MASK(EV_KEY) },
+ .keybit = { [BIT_WORD(BTN_LEFT)] = BIT_MASK(BTN_LEFT) },
+ }, /* pointer (e.g. trackpad, mouse) */
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
+ .evbit = { BIT_MASK(EV_KEY) },
+ .keybit = { [BIT_WORD(KEY_ESC)] = BIT_MASK(KEY_ESC) },
+ }, /* keyboard */
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
+ INPUT_DEVICE_ID_MATCH_KEYBIT,
+ .evbit = { BIT_MASK(EV_KEY) },
+ .keybit = {[BIT_WORD(BTN_JOYSTICK)] = BIT_MASK(BTN_JOYSTICK) },
+ }, /* joysticks not caught by ABS_X above */
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
+ INPUT_DEVICE_ID_MATCH_KEYBIT,
+ .evbit = { BIT_MASK(EV_KEY) },
+ .keybit = { [BIT_WORD(BTN_GAMEPAD)] = BIT_MASK(BTN_GAMEPAD) },
+ }, /* gamepad */
+ { },
+};
+
/**
* rockchip_drm_psr_register - register encoder to psr driver
* @encoder: encoder that obtain the PSR function
@@ -239,6 +346,7 @@ int rockchip_drm_psr_register(struct drm_encoder *encoder,
{
struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
struct psr_drv *psr;
+ int error;
if (!encoder || !psr_set)
return -EINVAL;
@@ -248,6 +356,7 @@ int rockchip_drm_psr_register(struct drm_encoder *encoder,
return -ENOMEM;
INIT_DELAYED_WORK(&psr->flush_work, psr_flush_handler);
+ INIT_WORK(&psr->disable_work, psr_disable_handler);
mutex_init(&psr->lock);
psr->active = true;
@@ -255,11 +364,33 @@ int rockchip_drm_psr_register(struct drm_encoder *encoder,
psr->encoder = encoder;
psr->set = psr_set;
+ psr->input_handler.event = psr_input_event;
+ psr->input_handler.connect = psr_input_connect;
+ psr->input_handler.disconnect = psr_input_disconnect;
+ psr->input_handler.name =
+ kasprintf(GFP_KERNEL, "rockchip-psr-%s", encoder->name);
+ if (!psr->input_handler.name) {
+ error = -ENOMEM;
+ goto err2;
+ }
+ psr->input_handler.id_table = psr_ids;
+ psr->input_handler.private = psr;
+
+ error = input_register_handler(&psr->input_handler);
+ if (error)
+ goto err1;
+
mutex_lock(&drm_drv->psr_list_lock);
list_add_tail(&psr->list, &drm_drv->psr_list);
mutex_unlock(&drm_drv->psr_list_lock);
return 0;
+
+ err1:
+ kfree(psr->input_handler.name);
+ err2:
+ kfree(psr);
+ return error;
}
EXPORT_SYMBOL(rockchip_drm_psr_register);
@@ -279,8 +410,11 @@ void rockchip_drm_psr_unregister(struct drm_encoder *encoder)
mutex_lock(&drm_drv->psr_list_lock);
list_for_each_entry_safe(psr, n, &drm_drv->psr_list, list) {
if (psr->encoder == encoder) {
+ input_unregister_handler(&psr->input_handler);
cancel_delayed_work_sync(&psr->flush_work);
+ cancel_work_sync(&psr->disable_work);
list_del(&psr->list);
+ kfree(psr->input_handler.name);
kfree(psr);
}
}
--
2.14.1
^ permalink raw reply related [flat|nested] 62+ messages in thread