From: Alex Deucher <alexdeucher@gmail.com>
To: Jiang Jian <jiangjian@cdjrlc.com>
Cc: Dave Airlie <airlied@linux.ie>, xinhui pan <Xinhui.Pan@amd.com>,
amd-gfx list <amd-gfx@lists.freedesktop.org>,
Maling list - DRI developers <dri-devel@lists.freedesktop.org>,
"Deucher, Alexander" <alexander.deucher@amd.com>,
Christian Koenig <christian.koenig@amd.com>
Subject: Re: [PATCH] gpu/drm/radeon: Fix typo in comments
Date: Wed, 22 Jun 2022 15:29:21 -0400 [thread overview]
Message-ID: <CADnq5_Onc2wC_y3RUQ1Y1aKZmHWRxbOFgp26MsuKAFRJ+w8cYw@mail.gmail.com> (raw)
In-Reply-To: <20220622142237.11492-1-jiangjian@cdjrlc.com>
Applied. Thanks!
On Wed, Jun 22, 2022 at 10:24 AM Jiang Jian <jiangjian@cdjrlc.com> wrote:
>
> Remove the repeated word 'and' from comments
>
> Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com>
> ---
> drivers/gpu/drm/radeon/r300_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
> index 60d5413bafa1..9d341cff63ee 100644
> --- a/drivers/gpu/drm/radeon/r300_reg.h
> +++ b/drivers/gpu/drm/radeon/r300_reg.h
> @@ -1103,7 +1103,7 @@
> * The destination register index is in FPI1 (color) and FPI3 (alpha)
> * together with enable bits.
> * There are separate enable bits for writing into temporary registers
> - * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
> + * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_*
> * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
> * same index must be used for both).
> *
> --
> 2.17.1
>
next prev parent reply other threads:[~2022-06-22 19:29 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-22 14:22 [PATCH] gpu/drm/radeon: Fix typo in comments Jiang Jian
2022-06-22 19:29 ` Alex Deucher [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-04-26 8:49 Zhenneng Li
2022-04-26 14:45 ` Alex Deucher
2021-07-29 8:20 Cai Huoqing
2021-07-30 2:17 ` Alex Deucher
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