* [PATCH] drm/hisilicon: Add new clock/resolution configurations
@ 2019-12-31 6:42 Tian Tao
2020-02-27 4:43 ` Xinliang Liu
0 siblings, 1 reply; 2+ messages in thread
From: Tian Tao @ 2019-12-31 6:42 UTC (permalink / raw)
To: puck.chen, airlied, daniel, tzimmermann, kraxel,
alexander.deucher, tglx, dri-devel, xinliang.liu, linux-kernel
Cc: linuxarm
Add the three new pll config for corresponding resolution 1440x900 and
1600x900, 640x480 for hibmc
Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
Signed-off-by: Gong junjie <gongjunjie2@huawei.com>
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 3 +++
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
index f1ce6cb..6bf4334 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
@@ -40,6 +40,7 @@ struct hibmc_dislay_pll_config {
};
static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {
+ {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ},
{800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},
{1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},
{1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},
@@ -47,6 +48,8 @@ static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {
{1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},
{1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
{1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
+ {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ},
+ {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
{1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},
{1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},
{1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
index 9b7e859..17b30c3 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
@@ -179,6 +179,7 @@
#define CRT_PLL1_HS_74MHZ 0x23941dc2
#define CRT_PLL1_HS_80MHZ 0x23941001
#define CRT_PLL1_HS_80MHZ_1152 0x23540fc2
+#define CRT_PLL1_HS_106MHZ 0x237C1641
#define CRT_PLL1_HS_108MHZ 0x23b41b01
#define CRT_PLL1_HS_162MHZ 0x23480681
#define CRT_PLL1_HS_148MHZ 0x23541dc2
@@ -191,6 +192,7 @@
#define CRT_PLL2_HS_78MHZ 0x50E147AE
#define CRT_PLL2_HS_74MHZ 0x602B6AE7
#define CRT_PLL2_HS_80MHZ 0x70000000
+#define CRT_PLL2_HS_106MHZ 0x0075c28f
#define CRT_PLL2_HS_108MHZ 0x80000000
#define CRT_PLL2_HS_162MHZ 0xA0000000
#define CRT_PLL2_HS_148MHZ 0xB0CCCCCD
--
2.7.4
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/hisilicon: Add new clock/resolution configurations
2019-12-31 6:42 [PATCH] drm/hisilicon: Add new clock/resolution configurations Tian Tao
@ 2020-02-27 4:43 ` Xinliang Liu
0 siblings, 0 replies; 2+ messages in thread
From: Xinliang Liu @ 2020-02-27 4:43 UTC (permalink / raw)
To: Tian Tao
Cc: airlied, puck.chen, linux-kernel, dri-devel, linuxarm, kraxel,
tzimmermann, alexander.deucher, tglx
[-- Attachment #1.1: Type: text/plain, Size: 2898 bytes --]
Thanks for the patch.
Applied to drm-misc-next.
On Tue, 31 Dec 2019 at 14:43, Tian Tao <tiantao6@hisilicon.com> wrote:
> Add the three new pll config for corresponding resolution 1440x900 and
> 1600x900, 640x480 for hibmc
>
> Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
> Signed-off-by: Gong junjie <gongjunjie2@huawei.com>
> ---
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 3 +++
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
> b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
> index f1ce6cb..6bf4334 100644
> --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
> +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
> @@ -40,6 +40,7 @@ struct hibmc_dislay_pll_config {
> };
>
> static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {
> + {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ},
> {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},
> {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},
> {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},
> @@ -47,6 +48,8 @@ static const struct hibmc_dislay_pll_config
> hibmc_pll_table[] = {
> {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},
> {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
> {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
> + {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ},
> + {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},
> {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},
> {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},
> {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},
> diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
> b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
> index 9b7e859..17b30c3 100644
> --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
> +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h
> @@ -179,6 +179,7 @@
> #define CRT_PLL1_HS_74MHZ 0x23941dc2
> #define CRT_PLL1_HS_80MHZ 0x23941001
> #define CRT_PLL1_HS_80MHZ_1152 0x23540fc2
> +#define CRT_PLL1_HS_106MHZ 0x237C1641
> #define CRT_PLL1_HS_108MHZ 0x23b41b01
> #define CRT_PLL1_HS_162MHZ 0x23480681
> #define CRT_PLL1_HS_148MHZ 0x23541dc2
> @@ -191,6 +192,7 @@
> #define CRT_PLL2_HS_78MHZ 0x50E147AE
> #define CRT_PLL2_HS_74MHZ 0x602B6AE7
> #define CRT_PLL2_HS_80MHZ 0x70000000
> +#define CRT_PLL2_HS_106MHZ 0x0075c28f
> #define CRT_PLL2_HS_108MHZ 0x80000000
> #define CRT_PLL2_HS_162MHZ 0xA0000000
> #define CRT_PLL2_HS_148MHZ 0xB0CCCCCD
> --
> 2.7.4
>
>
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