From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
To: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
Cc: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>,
Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>,
Vasily Khoruzhick
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Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>,
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Subject: Re: [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI
Date: Thu, 25 Oct 2018 21:21:31 +0530 [thread overview]
Message-ID: <CAMty3ZBJcH1fz5FyhT1rk9qiJ-aWoQYiH7P1ZyQPLKmVWOCkdA@mail.gmail.com> (raw)
In-Reply-To: <20181024181334.lul7ta7ijluwfb7v@flea>
On Wed, Oct 24, 2018 at 11:43 PM Maxime Ripard
<maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org> wrote:
>
> On Tue, Oct 23, 2018 at 09:20:32PM +0530, Jagan Teki wrote:
> > A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> > using minimum 500MHz can't release the clock and which
> > is not working.
> >
> > So use working minimum rate as 300MHz which is tested on
> > Bananapi DSI panel.
>
> I'm not quite sure what you mean by that. What do you mean by "500MHz
> can't release the clock"? Why would 300MHz work better then? Should be
> avoid reaching 500MHz if it's a frequency in the valid range?
PLL_MIPI can't be work with existing nkm where rate set to 270MHz
(from PLL_VIDEO)
/*** round rate call in ccu_nkm.c */
[ 2.408356] round: rate = 118800000
[ 2.408359] round: parent_rate = 158740688
[ 2.408417] round: rate = 148500000
[ 2.408420] round: parent_rate = 158740688
[ 2.408439] round: rate = 178200000
[ 2.408441] round: parent_rate = 158740688
[ 2.408460] round: rate = 205615384
[ 2.408462] round: parent_rate = 158740688
[ 2.408481] round: rate = 237600000
[ 2.408483] round: parent_rate = 158740688
[ 2.408502] round: rate = 270000000
[ 2.408504] round: parent_rate = 158740688
[ 2.408523] round: rate = 118800000
[ 2.408525] round: parent_rate = 158740560
[ 2.408544] round: rate = 148500000
[ 2.408546] round: parent_rate = 158740560
[ 2.408565] round: rate = 178200000
[ 2.408567] round: parent_rate = 158740560
[ 2.408586] round: rate = 205615384
[ 2.408588] round: parent_rate = 158740560
[ 2.408607] round: rate = 237600000
[ 2.408609] round: parent_rate = 158740560
[ 2.408627] round: rate = 270000000
[ 2.408630] round: parent_rate = 158740560
[ 2.408648] round: rate = 270000000
[ 2.408651] round: parent_rate = 158740640
[ 2.408670] round: rate = 270000000
[ 2.408672] round: parent_rate = 158740704
/** set rate call in ccu_nkm **/
[ 2.408685] set: rate = 270000000
[ 2.408688] set: parent_rate = 297000000
By using min and max rate as per A64 manual page 94 range of PLL can
be 500MHz~1.4GHz getting 1,2,1 nkm dividers which can't be work.
[ 2.423589] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[ 2.423643] ideal = 220000000, rounded = 0
[ 2.423647] ideal = 275000000, rounded = 0
[ 2.423651] ideal = 330000000, rounded = 0
[ 2.423692] ideal = 385000000, rounded = 384000000
[ 2.423732] ideal = 440000000, rounded = 440000000
[ 2.423736] sun4i_dclk_round_rate: div = 8 rate = 55000000
[ 2.423740] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[ 2.423744] ideal = 220000000, rounded = 0
[ 2.423748] ideal = 275000000, rounded = 0
[ 2.423751] ideal = 330000000, rounded = 0
[ 2.423791] ideal = 385000000, rounded = 384000000
[ 2.423831] ideal = 440000000, rounded = 440000000
[ 2.423834] sun4i_dclk_round_rate: div = 8 rate = 55000000
[ 2.423957] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
[ 2.423961] sun4i_dclk_recalc_rate: val = 1, rate = 440000000
[ 2.424378] ccu_nkm_set_rate: rate = 440000000, parent_rate = 220000000
[ 2.424381] ccu_nkm_set_rate: _nkm.n = 1
[ 2.424383] ccu_nkm_set_rate: _nkm.k = 2
[ 2.424385] ccu_nkm_set_rate: _nkm.m = 1
[ 2.424725] sun4i_dclk_set_rate div 8
[ 2.424732] sun4i_dclk_recalc_rate: val = 8, rate = 55000000
[ 2.561271] usb 3-1: new high-speed USB device number 2 using ehci-platform
[ 2.718486] hub 3-1:1.0: USB hub found
[ 2.718606] hub 3-1:1.0: 4 ports detected
[ 3.437263] ------------[ cut here ]------------
[ 3.437270] [CRTC:36:crtc-0] vblank wait timed out
So, lowering the min rate by 300MHz seems working with bounded nkm
dividers 5, 2, 9. Tested on two different panels.
[ 2.415773] [drm] No driver support for vblank timestamp query.
[ 2.424116] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[ 2.424172] ideal = 220000000, rounded = 0
[ 2.424176] ideal = 275000000, rounded = 0
[ 2.424194] ccu_nkm_round_rate: rate = 330000000
[ 2.424197] ideal = 330000000, rounded = 330000000
[ 2.424201] sun4i_dclk_round_rate: div = 6 rate = 55000000
[ 2.424205] sun4i_dclk_round_rate: min_div = 4 max_div = 127, rate = 55000000
[ 2.424209] ideal = 220000000, rounded = 0
[ 2.424213] ideal = 275000000, rounded = 0
[ 2.424230] ccu_nkm_round_rate: rate = 330000000
[ 2.424233] ideal = 330000000, rounded = 330000000
[ 2.424236] sun4i_dclk_round_rate: div = 6 rate = 55000000
[ 2.424253] ccu_nkm_round_rate: rate = 330000000
[ 2.424270] ccu_nkm_round_rate: rate = 330000000
[ 2.424278] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
[ 2.424281] sun4i_dclk_recalc_rate: val = 1, rate = 330000000
[ 2.424306] ccu_nkm_set_rate: rate = 330000000, parent_rate = 297000000
[ 2.424309] ccu_nkm_set_rate: _nkm.n = 5
[ 2.424311] ccu_nkm_set_rate: _nkm.k = 2
[ 2.424313] ccu_nkm_set_rate: _nkm.m = 9
[ 2.424661] sun4i_dclk_set_rate div 6
[ 2.424668] sun4i_dclk_recalc_rate: val = 6, rate = 55000000
Note: BPI-M64-bsp is setting the rate directly to 180MHz with 297MHz
parent with resulting dividers as 1, 2, 5. ans we can't produce this
180MHz rate with dclk_round_rate and ccu_nkm.
next prev parent reply other threads:[~2018-10-25 15:51 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-23 15:50 [PATCH v2 00/15] drm/sun4i: Allwinner A64 MIPI-DSI support Jagan Teki
2018-10-23 15:50 ` [PATCH v2 01/15] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY Jagan Teki
2018-10-24 8:48 ` Stephen Boyd
2018-10-23 15:50 ` [PATCH v2 02/15] clk: sunxi-ng: Add check for minimal rate to NKM PLLs Jagan Teki
2018-10-24 8:48 ` Stephen Boyd
[not found] ` <20181023155035.9101-3-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2018-10-24 18:04 ` Maxime Ripard
2018-10-25 10:55 ` Jagan Teki
[not found] ` <CAMty3ZC2wn-DjR+93yc-n-bAmVCHaEqR_=4XPddoo+7LjebTEg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-29 8:58 ` Maxime Ripard
2018-10-29 12:40 ` Jagan Teki
[not found] ` <e7566001-8933-adbb-4c30-7a3f66ebae4e-oRp2ZoJdM/RWk0Htik3J/w@public.gmane.org>
2018-11-05 10:11 ` Maxime Ripard
[not found] ` <20181023155035.9101-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2018-10-23 15:50 ` [PATCH v2 03/15] clk: sunxi-ng: Add check for maximum " Jagan Teki
2018-10-23 17:10 ` Vasily Khoruzhick
2018-10-24 8:48 ` Stephen Boyd
2018-10-23 15:50 ` [PATCH v2 05/15] dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI Jagan Teki
2018-10-23 15:50 ` [PATCH v2 06/15] drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param transfer Jagan Teki
2018-10-23 15:50 ` [PATCH v2 07/15] drm/sun4i: sun6i_mipi_dsi: Fix VBP size calculation Jagan Teki
2018-10-23 15:50 ` [PATCH v2 08/15] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits Jagan Teki
2018-10-23 15:50 ` [PATCH v2 10/15] dt-bindings: panel: Add Bananapi S070WV20-CT16 ICN6211 MIPI-DSI to RGB bridge Jagan Teki
[not found] ` <20181023155035.9101-11-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2018-10-24 18:07 ` Maxime Ripard
2018-10-24 20:36 ` Chen-Yu Tsai
2018-10-23 15:50 ` [PATCH v2 11/15] drm/panel: " Jagan Teki
2018-10-23 15:50 ` [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI Jagan Teki
2018-10-24 8:49 ` Stephen Boyd
[not found] ` <20181023155035.9101-13-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2018-10-24 18:13 ` Maxime Ripard
2018-10-25 15:51 ` Jagan Teki [this message]
[not found] ` <CAMty3ZBJcH1fz5FyhT1rk9qiJ-aWoQYiH7P1ZyQPLKmVWOCkdA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-29 9:08 ` Maxime Ripard
2018-10-29 15:08 ` Jagan Teki
2018-11-05 12:42 ` Maxime Ripard
2018-10-23 15:50 ` [PATCH v2 15/15] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel Jagan Teki
[not found] ` <20181023155035.9101-16-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2018-10-24 18:11 ` Maxime Ripard
2018-10-24 20:36 ` Chen-Yu Tsai
2018-10-23 15:50 ` [PATCH v2 04/15] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support Jagan Teki
[not found] ` <20181023155035.9101-5-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2018-10-24 18:06 ` Maxime Ripard
2018-10-25 11:02 ` Jagan Teki
2018-10-29 9:00 ` Maxime Ripard
2018-10-23 15:50 ` [PATCH v2 09/15] drm/sun4i: sun6i_mipi_dsi: Refactor vertical video start delay Jagan Teki
2018-10-23 15:50 ` [PATCH v2 13/15] dt-bindings: sun6i-dsi: Add compatible for A64 DPHY Jagan Teki
2018-10-24 18:09 ` Maxime Ripard
2018-10-25 12:52 ` Jagan Teki
[not found] ` <CAMty3ZC3jXKBVrrCSd0Un+ZNvNKPj4C0WpcpNOYJBK1=vehBQg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-29 9:01 ` Maxime Ripard
2018-10-23 15:50 ` [PATCH v2 14/15] arm64: dts: allwinner: a64: Add DSI pipeline Jagan Teki
[not found] ` <20181023155035.9101-15-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2018-10-24 18:10 ` Maxime Ripard
2018-10-25 13:21 ` Jagan Teki
[not found] ` <CAMty3ZC1jCfuP8tFKvgcdJ5R_Ou0ejAT_VYv=fV1Kh4UanLWcg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-29 9:01 ` Maxime Ripard
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