* [PATCH 0/1] Fixing the DSI dot clock on Allwinner @ 2023-03-19 16:07 Frank Oltmanns 2023-03-19 16:07 ` [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI Frank Oltmanns 0 siblings, 1 reply; 5+ messages in thread From: Frank Oltmanns @ 2023-03-19 16:07 UTC (permalink / raw) To: jagan, michael, Maxime Ripard, Chen-Yu Tsai, David Airlie, Daniel Vetter, Jernej Skrabec, Samuel Holland, open list:DRM DRIVERS FOR ALLWINNER A10, moderated list:ARM/Allwinner sunXi SoC support, open list:ARM/Allwinner sunXi SoC support, open list Cc: Frank Oltmanns According to the Allwinner A64's BSP code, the PLL rate needs to be set to the following frequency when using DSI: PLL rate = DCLK * bpp / lanes Source: [1] The relevant lines for DSI (ommisions and comments mine): dclk_rate = lcdp->panel_info.lcd_dclk_freq * 1000000; lcd_rate = dclk_rate * clk_info.dsi_div; // dsi_div = bpp/lane pll_rate = lcd_rate * clk_info.lcd_div; // lcd_div = 1 --> pll_rate = lcd_rate dsi_rate = pll_rate / clk_info.dsi_div // --> dsi_rate = dclk_rate clk_set_rate(lcdp->clk_parent, pll_rate); This was already discussed by Maxime, Jagan and Michael in the past in the thread following this message: [2]. Unfortunately, there never was a conclusion in the form of code. The attached patch is a slight variation of a patch that is part of megi's kernel branch that many PinePhone distributions (e.g. postmarketOS) use [3]. It calculates the TCON clock rate by using the formula above and dividing it by SUN6I_DSI_TCON_DIV, in order to force the parent clock to be set to the correct rate. If I read the thread following this message [2] correctly, this was also what Maxime had in mind. Please also note that, unfortunately, I only have a single board and panel (namely the PinePhone) to test this on. Thanks, Frank [1] https://github.com/BPI-SINOVOIP/BPI-M64-bsp/blob/master/linux-sunxi/drivers/video/sunxi/disp2/disp/de/disp_lcd.c#L781 [2] https://lore.kernel.org/lkml/CAMty3ZAsH2iZ+JEqTE3D58aXfGuhMSg9YoO56ZhhOeE4c4yQHQ@mail.gmail.com/ [3] https://github.com/megous/linux/commit/eb5f28fb58727f4a6546f211486aad0d19cdea3f Frank Oltmanns (1): drm/sun4i: tcon: Fix setting PLL rate when using DSI drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 ++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 15 deletions(-) -- 2.39.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI 2023-03-19 16:07 [PATCH 0/1] Fixing the DSI dot clock on Allwinner Frank Oltmanns @ 2023-03-19 16:07 ` Frank Oltmanns 2023-03-21 14:57 ` Maxime Ripard 0 siblings, 1 reply; 5+ messages in thread From: Frank Oltmanns @ 2023-03-19 16:07 UTC (permalink / raw) To: jagan, michael, Maxime Ripard, Chen-Yu Tsai, David Airlie, Daniel Vetter, Jernej Skrabec, Samuel Holland, open list:DRM DRIVERS FOR ALLWINNER A10, moderated list:ARM/Allwinner sunXi SoC support, open list:ARM/Allwinner sunXi SoC support, open list Cc: Frank Oltmanns Set the required PLL rate by adjusting the dotclock rate when calling clk_set_rate() when using DSI. According to the Allwinners A64's BSP code, a TCON divider of 4 has to be used and the PLL rate needs to be set to the following frequency when using DSI: PLL rate = DCLK * bpp / lanes After this change the common mode set function would only contain setting the resolution. Therefore, dissolve the function and transfer the functionality to the individual mode set functions. Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 ++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 62b3538bd81f..02d52be42f06 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -323,18 +323,6 @@ static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode, return delay; } -static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, - const struct drm_display_mode *mode) -{ - /* Configure the dot clock */ - clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); - - /* Set the resolution */ - regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, - SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | - SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); -} - static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, const struct drm_connector *connector) { @@ -399,10 +387,24 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, u32 block_space, start_delay; u32 tcon_div; + /* + * Configure the dot clock: + * For DSI the PLL rate has to respect the bits per pixel and + * number of lanes. + * + * According to the BSP code: + * TCON divider = 4 + * PLL rate = DCLK * bpp / lanes + */ tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 + * bpp / (lanes * SUN6I_DSI_TCON_DIV)); - sun4i_tcon0_mode_set_common(tcon, mode); + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -470,7 +472,14 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, tcon->dclk_min_div = 7; tcon->dclk_max_div = 7; - sun4i_tcon0_mode_set_common(tcon, mode); + + /* Configure the dot clock */ + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -549,7 +558,14 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, tcon->dclk_min_div = tcon->quirks->dclk_min_div; tcon->dclk_max_div = 127; - sun4i_tcon0_mode_set_common(tcon, mode); + + /* Configure the dot clock */ + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, connector); -- 2.39.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI 2023-03-19 16:07 ` [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI Frank Oltmanns @ 2023-03-21 14:57 ` Maxime Ripard 2023-03-21 19:55 ` Frank Oltmanns 0 siblings, 1 reply; 5+ messages in thread From: Maxime Ripard @ 2023-03-21 14:57 UTC (permalink / raw) To: Frank Oltmanns Cc: Samuel Holland, open list:DRM DRIVERS FOR ALLWINNER A10, open list, Jernej Skrabec, Chen-Yu Tsai, jagan, michael, open list:ARM/Allwinner sunXi SoC support, moderated list:ARM/Allwinner sunXi SoC support [-- Attachment #1: Type: text/plain, Size: 784 bytes --] Hi, On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote: > Set the required PLL rate by adjusting the dotclock rate when calling > clk_set_rate() when using DSI. > > According to the Allwinners A64's BSP code, a TCON divider of 4 has to > be used and the PLL rate needs to be set to the following frequency when > using DSI: > PLL rate = DCLK * bpp / lanes > > After this change the common mode set function would only contain > setting the resolution. Therefore, dissolve the function and transfer > the functionality to the individual mode set functions. > > Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> This is similar to: https://lore.kernel.org/all/20230320161636.24411-1-romanberanek@icloud.com/ What's the story there? Maxime [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI 2023-03-21 14:57 ` Maxime Ripard @ 2023-03-21 19:55 ` Frank Oltmanns 2023-03-22 3:25 ` Roman Beranek 0 siblings, 1 reply; 5+ messages in thread From: Frank Oltmanns @ 2023-03-21 19:55 UTC (permalink / raw) To: Maxime Ripard Cc: Samuel Holland, open list:DRM DRIVERS FOR ALLWINNER A10, open list, Jernej Skrabec, Roman Beranek, Chen-Yu Tsai, jagan, michael, open list:ARM/Allwinner sunXi SoC support, moderated list:ARM/Allwinner sunXi SoC support [-- Attachment #1: Type: text/plain, Size: 1207 bytes --] Hi Maxime, On 2023-03-21 at 15:57:39 +0100, Maxime Ripard <maxime@cerno.tech> wrote: > Hi, > > On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote: >> Set the required PLL rate by adjusting the dotclock rate when calling >> clk_set_rate() when using DSI. >> >> According to the Allwinners A64’s BSP code, a TCON divider of 4 has to >> be used and the PLL rate needs to be set to the following frequency when >> using DSI: >> PLL rate = DCLK * bpp / lanes >> >> After this change the common mode set function would only contain >> setting the resolution. Therefore, dissolve the function and transfer >> the functionality to the individual mode set functions. >> >> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> > > This is similar to: > <https://lore.kernel.org/all/20230320161636.24411-1-romanberanek@icloud.com/> > > What’s the story there? Sorry, as Roman wrote in the other thread, I submitted the patch after not hearing back from him for a week. My apologies, I wasn’t patient enough. So now there are two submissions to consider. FWIW, I think this patch is a bit more straightforward than the other one. Best regards, Frank > Maxime > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI 2023-03-21 19:55 ` Frank Oltmanns @ 2023-03-22 3:25 ` Roman Beranek 0 siblings, 0 replies; 5+ messages in thread From: Roman Beranek @ 2023-03-22 3:25 UTC (permalink / raw) To: Frank Oltmanns, Maxime Ripard Cc: Samuel Holland, open list:DRM DRIVERS FOR ALLWINNER A10, open list, Jernej Skrabec, Chen-Yu Tsai, jagan, michael, open list:ARM/Allwinner sunXi SoC support, moderated list:ARM/Allwinner sunXi SoC support On Tue Mar 21, 2023 at 8:55 PM CET, Frank Oltmanns wrote: > My apologies, I wasn’t patient enough. Frank, there's no need to apologize, in my judgement. You weren't impatient, we simply happened to run into a coordination problem for which, I think, neither of us was particularly to blamew. Take it easy :) Roman ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-03-22 3:25 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-03-19 16:07 [PATCH 0/1] Fixing the DSI dot clock on Allwinner Frank Oltmanns 2023-03-19 16:07 ` [PATCH 1/1] drm/sun4i: tcon: Fix setting PLL rate when using DSI Frank Oltmanns 2023-03-21 14:57 ` Maxime Ripard 2023-03-21 19:55 ` Frank Oltmanns 2023-03-22 3:25 ` Roman Beranek
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