* [PATCH 0/3] HDMI2.1 PCON Misc Fixes
@ 2021-02-04 6:48 Ankit Nautiyal
2021-02-04 6:48 ` [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Ankit Nautiyal
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, dri-devel
Patch1: fixes gitlab issue:
https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Patch2: Tweaks the drm_helpers for PCON configuration
Patch3: Removes unwanted code not applicable for older platforms.
Ankit Nautiyal (3):
i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
i915/display: Remove FRL related code from disable DP sequence for
older platforms
drivers/gpu/drm/drm_dp_helper.c | 18 +++++-----
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++-----
include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++--
3 files changed, 59 insertions(+), 21 deletions(-)
--
2.29.2
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 2021-02-04 6:48 [PATCH 0/3] HDMI2.1 PCON Misc Fixes Ankit Nautiyal @ 2021-02-04 6:48 ` Ankit Nautiyal 2021-02-05 19:58 ` Ville Syrjälä 2021-02-08 11:15 ` Jani Nikula 2021-02-04 6:48 ` [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal 2021-02-04 6:48 ` [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms Ankit Nautiyal 2 siblings, 2 replies; 15+ messages in thread From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw) To: intel-gfx; +Cc: uma.shankar, dri-devel DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. Do not read the registers if DPCD rev < 1.4. Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8c12d5375607..2b83f0f433a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) struct drm_i915_private *i915 = dp_to_i915(intel_dp); /* Clear the cached register set to avoid using stale values */ - memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) + return; + if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, intel_dp->pcon_dsc_dpcd, sizeof(intel_dp->pcon_dsc_dpcd)) < 0) -- 2.29.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 2021-02-04 6:48 ` [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Ankit Nautiyal @ 2021-02-05 19:58 ` Ville Syrjälä 2021-02-05 20:07 ` [Intel-gfx] " Navare, Manasi 2021-02-08 11:15 ` Jani Nikula 1 sibling, 1 reply; 15+ messages in thread From: Ville Syrjälä @ 2021-02-05 19:58 UTC (permalink / raw) To: Ankit Nautiyal; +Cc: intel-gfx, uma.shankar, dri-devel On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote: > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. > Do not read the registers if DPCD rev < 1.4. > > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 8c12d5375607..2b83f0f433a2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > /* Clear the cached register set to avoid using stale values */ > - > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); > > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) > + return; > + Can't check the spec, but makes sense that this stuff is only valid for recent DCPD revisions. Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, > intel_dp->pcon_dsc_dpcd, > sizeof(intel_dp->pcon_dsc_dpcd)) < 0) > -- > 2.29.2 -- Ville Syrjälä Intel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 2021-02-05 19:58 ` Ville Syrjälä @ 2021-02-05 20:07 ` Navare, Manasi 2021-02-05 20:06 ` Ville Syrjälä 0 siblings, 1 reply; 15+ messages in thread From: Navare, Manasi @ 2021-02-05 20:07 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Ankit Nautiyal, intel-gfx, dri-devel On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote: > On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote: > > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. > > Do not read the registers if DPCD rev < 1.4. > > > > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 8c12d5375607..2b83f0f433a2 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > > /* Clear the cached register set to avoid using stale values */ > > - > > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); > > > > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) > > + return; > > + > > Can't check the spec, but makes sense that this stuff is only valid > for recent DCPD revisions. > > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Yes checked the DP 1.4 spec and this is correct Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > > > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, > > intel_dp->pcon_dsc_dpcd, > > sizeof(intel_dp->pcon_dsc_dpcd)) < 0) > > -- > > 2.29.2 > > -- > Ville Syrjälä > Intel > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 2021-02-05 20:07 ` [Intel-gfx] " Navare, Manasi @ 2021-02-05 20:06 ` Ville Syrjälä 2021-02-05 20:22 ` Navare, Manasi 0 siblings, 1 reply; 15+ messages in thread From: Ville Syrjälä @ 2021-02-05 20:06 UTC (permalink / raw) To: Navare, Manasi; +Cc: Ankit Nautiyal, intel-gfx, dri-devel On Fri, Feb 05, 2021 at 12:07:41PM -0800, Navare, Manasi wrote: > On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote: > > On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote: > > > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. > > > Do not read the registers if DPCD rev < 1.4. > > > > > > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 8c12d5375607..2b83f0f433a2 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > > > > /* Clear the cached register set to avoid using stale values */ > > > - > > > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); > > > > > > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) > > > + return; > > > + > > > > Can't check the spec, but makes sense that this stuff is only valid > > for recent DCPD revisions. > > > > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Yes checked the DP 1.4 spec and this is correct I didn't think this is in the DP spec, but rather some special extra spec which I do not have. > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > > Manasi > > > > > > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, > > > intel_dp->pcon_dsc_dpcd, > > > sizeof(intel_dp->pcon_dsc_dpcd)) < 0) > > > -- > > > 2.29.2 > > > > -- > > Ville Syrjälä > > Intel > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 2021-02-05 20:06 ` Ville Syrjälä @ 2021-02-05 20:22 ` Navare, Manasi 0 siblings, 0 replies; 15+ messages in thread From: Navare, Manasi @ 2021-02-05 20:22 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Ankit Nautiyal, intel-gfx, dri-devel On Fri, Feb 05, 2021 at 10:06:48PM +0200, Ville Syrjälä wrote: > On Fri, Feb 05, 2021 at 12:07:41PM -0800, Navare, Manasi wrote: > > On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote: > > > On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote: > > > > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. > > > > Do not read the registers if DPCD rev < 1.4. > > > > > > > > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 > > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- > > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > > index 8c12d5375607..2b83f0f433a2 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) > > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > > > > > > /* Clear the cached register set to avoid using stale values */ > > > > - > > > > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); > > > > > > > > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) > > > > + return; > > > > + > > > > > > Can't check the spec, but makes sense that this stuff is only valid > > > for recent DCPD revisions. > > > > > > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Yes checked the DP 1.4 spec and this is correct > > I didn't think this is in the DP spec, but rather some special extra > spec which I do not have. Yes I meant just double checked that the DSC support itself from DP 1.4 and hence makes sense that the PCON DSC regs also from >= 1.4 Manasi > > > > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > > > > Manasi > > > > > > > > > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, > > > > intel_dp->pcon_dsc_dpcd, > > > > sizeof(intel_dp->pcon_dsc_dpcd)) < 0) > > > > -- > > > > 2.29.2 > > > > > > -- > > > Ville Syrjälä > > > Intel > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 2021-02-04 6:48 ` [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Ankit Nautiyal 2021-02-05 19:58 ` Ville Syrjälä @ 2021-02-08 11:15 ` Jani Nikula 2021-02-08 11:44 ` Nautiyal, Ankit K 1 sibling, 1 reply; 15+ messages in thread From: Jani Nikula @ 2021-02-08 11:15 UTC (permalink / raw) To: Ankit Nautiyal, intel-gfx; +Cc: uma.shankar, dri-devel On Thu, 04 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. > Do not read the registers if DPCD rev < 1.4. > > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 Please use Fixes: to reference commits that this patch fixes. Please use Closes: to reference issues that this patch fixes. No need to resend for this, can be fixed while applying, but please tell me the commit that introduced the problem. BR, Jani. > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 8c12d5375607..2b83f0f433a2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > /* Clear the cached register set to avoid using stale values */ > - > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); > > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) > + return; > + > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, > intel_dp->pcon_dsc_dpcd, > sizeof(intel_dp->pcon_dsc_dpcd)) < 0) -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 2021-02-08 11:15 ` Jani Nikula @ 2021-02-08 11:44 ` Nautiyal, Ankit K 2021-03-09 4:28 ` Nautiyal, Ankit K 0 siblings, 1 reply; 15+ messages in thread From: Nautiyal, Ankit K @ 2021-02-08 11:44 UTC (permalink / raw) To: Jani Nikula, intel-gfx; +Cc: uma.shankar, dri-devel On 2/8/2021 4:45 PM, Jani Nikula wrote: > On Thu, 04 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: >> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. >> Do not read the registers if DPCD rev < 1.4. >> >> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 > Please use Fixes: to reference commits that this patch fixes. > > Please use Closes: to reference issues that this patch fixes. > > No need to resend for this, can be fixed while applying, but please tell > me the commit that introduced the problem. > > BR, > Jani. > Alright will take care. Please find below the commit that introduced this: b9d96dacdc3d983eae234b52401edb56dbceb764 Patch : drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder https://patchwork.freedesktop.org/patch/408779/ Thanks & Regards, Ankit >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c >> index 8c12d5375607..2b83f0f433a2 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) >> struct drm_i915_private *i915 = dp_to_i915(intel_dp); >> >> /* Clear the cached register set to avoid using stale values */ >> - >> memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); >> >> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) >> + return; >> + >> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, >> intel_dp->pcon_dsc_dpcd, >> sizeof(intel_dp->pcon_dsc_dpcd)) < 0) _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 2021-02-08 11:44 ` Nautiyal, Ankit K @ 2021-03-09 4:28 ` Nautiyal, Ankit K 0 siblings, 0 replies; 15+ messages in thread From: Nautiyal, Ankit K @ 2021-03-09 4:28 UTC (permalink / raw) To: Jani Nikula, intel-gfx; +Cc: uma.shankar, dri-devel As I realized, this patch is mixing DPCD rev and DP version, need an appropriate check instead. As for the gitlab issue https://gitlab.freedesktop.org/drm/intel/-/issues/2868 this seems to be not due to a DPCD register not defined for an older sink. The DPCD read in that case should have been 0, instead of timeout. I will drop this patch for now, from the series and revisit it later. Thanks & Regards, Ankit On 2/8/2021 5:14 PM, Nautiyal, Ankit K wrote: > > On 2/8/2021 4:45 PM, Jani Nikula wrote: >> On Thu, 04 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: >>> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. >>> Do not read the registers if DPCD rev < 1.4. >>> >>> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 >> Please use Fixes: to reference commits that this patch fixes. >> >> Please use Closes: to reference issues that this patch fixes. >> >> No need to resend for this, can be fixed while applying, but please tell >> me the commit that introduced the problem. >> >> BR, >> Jani. >> > Alright will take care. Please find below the commit that introduced > this: > > b9d96dacdc3d983eae234b52401edb56dbceb764 > > Patch : drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder > https://patchwork.freedesktop.org/patch/408779/ > > > Thanks & Regards, > > Ankit > >>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >>> --- >>> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- >>> 1 file changed, 3 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c >>> b/drivers/gpu/drm/i915/display/intel_dp.c >>> index 8c12d5375607..2b83f0f433a2 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_dp.c >>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c >>> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct >>> intel_dp *intel_dp) >>> struct drm_i915_private *i915 = dp_to_i915(intel_dp); >>> /* Clear the cached register set to avoid using stale values */ >>> - >>> memset(intel_dp->pcon_dsc_dpcd, 0, >>> sizeof(intel_dp->pcon_dsc_dpcd)); >>> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) >>> + return; >>> + >>> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, >>> intel_dp->pcon_dsc_dpcd, >>> sizeof(intel_dp->pcon_dsc_dpcd)) < 0) _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON 2021-02-04 6:48 [PATCH 0/3] HDMI2.1 PCON Misc Fixes Ankit Nautiyal 2021-02-04 6:48 ` [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Ankit Nautiyal @ 2021-02-04 6:48 ` Ankit Nautiyal 2021-02-05 20:00 ` Ville Syrjälä 2021-02-11 6:43 ` [PATCH v2 " Ankit Nautiyal 2021-02-04 6:48 ` [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms Ankit Nautiyal 2 siblings, 2 replies; 15+ messages in thread From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw) To: intel-gfx; +Cc: uma.shankar, dri-devel Currently the FRL training mode (Concurrent, Sequential) and training type (Normal, Extended) are not defined properly and are passed as bool values in drm_helpers for pcon configuration for FRL training. This patch: -Defines FRL training type and link bring up sequence mode as enum. -Fixes the drm_helpers for FRL Training configuration to use these enums. -Modifies the calls to the above drm_helpers in i915/intel_dp as per the above change. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 18 +++++----- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++--- include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++-- 3 files changed, 56 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index eedbb48815b7..2ca4ab5af470 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 * @aux: DisplayPort AUX channel * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink - * @concurrent_mode: true if concurrent mode or operation is required, - * false otherwise. + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode) + enum dp_pcon_frl_train_mode frl_mode) { int ret; u8 buf; @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, if (ret < 0) return ret; - if (concurrent_mode) + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT) buf |= DP_PCON_ENABLE_CONCURRENT_LINK; else buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 * @aux: DisplayPort AUX channel * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink - * @extended_train_mode : true for Extended Mode, false for Normal Mode. - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting - * from min, and stops when link training is successful. In Extended mode, all - * frl bw selected in the mask are trained by the PCON. + * @frl_type : FRL training type, can be Extended, or Normal. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode) + enum dp_pcon_frl_train_type frl_type) { int ret; u8 buf = max_frl_mask; - if (extended_train_mode) + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED) buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; + else + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); if (ret < 0) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2b83f0f433a2..1962d6dd8641 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) { -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) -#define PCON_CONCURRENT_MODE (1 > 0) -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE #define TIMEOUT_FRL_READY_MS 500 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) return -ETIMEDOUT; max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, + DP_PCON_FRL_MODE_SEQUENTIAL); if (ret < 0) return ret; - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, + DP_PCON_FRL_TRAIN_NORMAL); if (ret < 0) return ret; ret = drm_dp_pcon_frl_enable(&intel_dp->aux); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index edffd1dcca3e..c3f56e87a5ec 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1646,6 +1646,48 @@ enum dp_content_type { DP_CONTENT_TYPE_GAME = 0x04, }; +/** + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type + * + * This enum is used to select FRL training type for FRL training between + * an HDMI2.1 PCON and an HDMI2.1 sink. + * + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification + * Sec 6.1 Table-3. + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK + * starting from min, and stops when link training is successful. + * In Extended FRL training, all frl bw selected in the mask are trained by the + * PCON. + * + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended + */ +enum dp_pcon_frl_train_type { + DP_PCON_FRL_TRAIN_NORMAL = 0, + DP_PCON_FRL_TRAIN_EXTENDED = 1, +}; + +/** + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode + * + * This enum is used to select mode for FRL Link bringup between an HDMI2.1 + * PCON and an HDMI2.1 sink. + * + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification + * Sec 6.1 Table-3. + * In Concurrent Mode, the FRL link bring up can be done along with DP Link + * training. In Sequential mode, the FRL link bring up is done prior to the + * DP Link training. + * + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode + */ + +enum dp_pcon_frl_train_mode { + DP_PCON_FRL_MODE_SEQUENTIAL = 0, + DP_PCON_FRL_MODE_CONCURRENT = 1, +}; + /** * struct drm_dp_vsc_sdp - drm DP VSC SDP * @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode); + enum dp_pcon_frl_train_mode frl_mode); int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode); + enum dp_pcon_frl_train_type frl_type); int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); -- 2.29.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON 2021-02-04 6:48 ` [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal @ 2021-02-05 20:00 ` Ville Syrjälä 2021-02-11 6:56 ` Nautiyal, Ankit K 2021-02-11 6:43 ` [PATCH v2 " Ankit Nautiyal 1 sibling, 1 reply; 15+ messages in thread From: Ville Syrjälä @ 2021-02-05 20:00 UTC (permalink / raw) To: Ankit Nautiyal; +Cc: intel-gfx, uma.shankar, dri-devel On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote: > Currently the FRL training mode (Concurrent, Sequential) and > training type (Normal, Extended) are not defined properly and > are passed as bool values in drm_helpers for pcon > configuration for FRL training. > > This patch: > -Defines FRL training type and link bring up sequence mode as enum. > -Fixes the drm_helpers for FRL Training configuration to use these enums. > -Modifies the calls to the above drm_helpers in i915/intel_dp as per the > above change. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/drm_dp_helper.c | 18 +++++----- > drivers/gpu/drm/i915/display/intel_dp.c | 10 +++--- > include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++-- > 3 files changed, 56 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index eedbb48815b7..2ca4ab5af470 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); > * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 > * @aux: DisplayPort AUX channel > * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink > - * @concurrent_mode: true if concurrent mode or operation is required, > - * false otherwise. > + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. > * > * Returns 0 if success, else returns negative error code. > */ > > int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, > - bool concurrent_mode) > + enum dp_pcon_frl_train_mode frl_mode) > { > int ret; > u8 buf; > @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, > if (ret < 0) > return ret; > > - if (concurrent_mode) > + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT) > buf |= DP_PCON_ENABLE_CONCURRENT_LINK; > else > buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; > @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); > * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 > * @aux: DisplayPort AUX channel > * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink > - * @extended_train_mode : true for Extended Mode, false for Normal Mode. > - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting > - * from min, and stops when link training is successful. In Extended mode, all > - * frl bw selected in the mask are trained by the PCON. > + * @frl_type : FRL training type, can be Extended, or Normal. > * > * Returns 0 if success, else returns negative error code. > */ > int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, > - bool extended_train_mode) > + enum dp_pcon_frl_train_type frl_type) > { > int ret; > u8 buf = max_frl_mask; > > - if (extended_train_mode) > + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED) > buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; > + else > + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; These names are annoyingly close to each other. Prettu much guaranteed to mix them up at some point. We should try to come up something a bit more distinctive for the enum, or just forget the enum and use the register values directly. > > ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); > if (ret < 0) > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 2b83f0f433a2..1962d6dd8641 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) > > static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) > { > -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) > -#define PCON_CONCURRENT_MODE (1 > 0) > -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE > -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE > #define TIMEOUT_FRL_READY_MS 500 > #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 > > @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) > return -ETIMEDOUT; > > max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); > - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); > + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, > + DP_PCON_FRL_MODE_SEQUENTIAL); > if (ret < 0) > return ret; > - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); > + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, > + DP_PCON_FRL_TRAIN_NORMAL); > if (ret < 0) > return ret; > ret = drm_dp_pcon_frl_enable(&intel_dp->aux); > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index edffd1dcca3e..c3f56e87a5ec 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1646,6 +1646,48 @@ enum dp_content_type { > DP_CONTENT_TYPE_GAME = 0x04, > }; > > +/** > + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type > + * > + * This enum is used to select FRL training type for FRL training between > + * an HDMI2.1 PCON and an HDMI2.1 sink. > + * > + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification > + * Sec 6.1 Table-3. > + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK > + * starting from min, and stops when link training is successful. > + * In Extended FRL training, all frl bw selected in the mask are trained by the > + * PCON. > + * > + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal > + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended > + */ > +enum dp_pcon_frl_train_type { > + DP_PCON_FRL_TRAIN_NORMAL = 0, > + DP_PCON_FRL_TRAIN_EXTENDED = 1, > +}; > + > +/** > + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode > + * > + * This enum is used to select mode for FRL Link bringup between an HDMI2.1 > + * PCON and an HDMI2.1 sink. > + * > + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification > + * Sec 6.1 Table-3. > + * In Concurrent Mode, the FRL link bring up can be done along with DP Link > + * training. In Sequential mode, the FRL link bring up is done prior to the > + * DP Link training. > + * > + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode > + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode > + */ > + > +enum dp_pcon_frl_train_mode { > + DP_PCON_FRL_MODE_SEQUENTIAL = 0, > + DP_PCON_FRL_MODE_CONCURRENT = 1, > +}; > + > /** > * struct drm_dp_vsc_sdp - drm DP VSC SDP > * > @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], > int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); > bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); > int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, > - bool concurrent_mode); > + enum dp_pcon_frl_train_mode frl_mode); > int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, > - bool extended_train_mode); > + enum dp_pcon_frl_train_type frl_type); > int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); > int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); > > -- > 2.29.2 -- Ville Syrjälä Intel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON 2021-02-05 20:00 ` Ville Syrjälä @ 2021-02-11 6:56 ` Nautiyal, Ankit K 0 siblings, 0 replies; 15+ messages in thread From: Nautiyal, Ankit K @ 2021-02-11 6:56 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, uma.shankar, dri-devel On 2/6/2021 1:30 AM, Ville Syrjälä wrote: > On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote: >> Currently the FRL training mode (Concurrent, Sequential) and >> training type (Normal, Extended) are not defined properly and >> are passed as bool values in drm_helpers for pcon >> configuration for FRL training. >> >> This patch: >> -Defines FRL training type and link bring up sequence mode as enum. >> -Fixes the drm_helpers for FRL Training configuration to use these enums. >> -Modifies the calls to the above drm_helpers in i915/intel_dp as per the >> above change. >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >> --- >> drivers/gpu/drm/drm_dp_helper.c | 18 +++++----- >> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++--- >> include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++-- >> 3 files changed, 56 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c >> index eedbb48815b7..2ca4ab5af470 100644 >> --- a/drivers/gpu/drm/drm_dp_helper.c >> +++ b/drivers/gpu/drm/drm_dp_helper.c >> @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); >> * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 >> * @aux: DisplayPort AUX channel >> * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink >> - * @concurrent_mode: true if concurrent mode or operation is required, >> - * false otherwise. >> + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. >> * >> * Returns 0 if success, else returns negative error code. >> */ >> >> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, >> - bool concurrent_mode) >> + enum dp_pcon_frl_train_mode frl_mode) >> { >> int ret; >> u8 buf; >> @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, >> if (ret < 0) >> return ret; >> >> - if (concurrent_mode) >> + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT) >> buf |= DP_PCON_ENABLE_CONCURRENT_LINK; >> else >> buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; >> @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); >> * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 >> * @aux: DisplayPort AUX channel >> * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink >> - * @extended_train_mode : true for Extended Mode, false for Normal Mode. >> - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting >> - * from min, and stops when link training is successful. In Extended mode, all >> - * frl bw selected in the mask are trained by the PCON. >> + * @frl_type : FRL training type, can be Extended, or Normal. >> * >> * Returns 0 if success, else returns negative error code. >> */ >> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, >> - bool extended_train_mode) >> + enum dp_pcon_frl_train_type frl_type) >> { >> int ret; >> u8 buf = max_frl_mask; >> >> - if (extended_train_mode) >> + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED) >> buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; >> + else >> + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; > These names are annoyingly close to each other. Prettu much > guaranteed to mix them up at some point. We should try to come > up something a bit more distinctive for the enum, or just forget > the enum and use the register values directly. Agreed. Sent next version of the patch, dropping the enum and used only appropriate register values. Thanks & Regards, Ankit >> >> ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); >> if (ret < 0) >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c >> index 2b83f0f433a2..1962d6dd8641 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) >> >> static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) >> { >> -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) >> -#define PCON_CONCURRENT_MODE (1 > 0) >> -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE >> -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE >> #define TIMEOUT_FRL_READY_MS 500 >> #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 >> >> @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) >> return -ETIMEDOUT; >> >> max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); >> - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); >> + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, >> + DP_PCON_FRL_MODE_SEQUENTIAL); >> if (ret < 0) >> return ret; >> - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); >> + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, >> + DP_PCON_FRL_TRAIN_NORMAL); >> if (ret < 0) >> return ret; >> ret = drm_dp_pcon_frl_enable(&intel_dp->aux); >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >> index edffd1dcca3e..c3f56e87a5ec 100644 >> --- a/include/drm/drm_dp_helper.h >> +++ b/include/drm/drm_dp_helper.h >> @@ -1646,6 +1646,48 @@ enum dp_content_type { >> DP_CONTENT_TYPE_GAME = 0x04, >> }; >> >> +/** >> + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type >> + * >> + * This enum is used to select FRL training type for FRL training between >> + * an HDMI2.1 PCON and an HDMI2.1 sink. >> + * >> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification >> + * Sec 6.1 Table-3. >> + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK >> + * starting from min, and stops when link training is successful. >> + * In Extended FRL training, all frl bw selected in the mask are trained by the >> + * PCON. >> + * >> + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal >> + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended >> + */ >> +enum dp_pcon_frl_train_type { >> + DP_PCON_FRL_TRAIN_NORMAL = 0, >> + DP_PCON_FRL_TRAIN_EXTENDED = 1, >> +}; >> + >> +/** >> + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode >> + * >> + * This enum is used to select mode for FRL Link bringup between an HDMI2.1 >> + * PCON and an HDMI2.1 sink. >> + * >> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification >> + * Sec 6.1 Table-3. >> + * In Concurrent Mode, the FRL link bring up can be done along with DP Link >> + * training. In Sequential mode, the FRL link bring up is done prior to the >> + * DP Link training. >> + * >> + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode >> + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode >> + */ >> + >> +enum dp_pcon_frl_train_mode { >> + DP_PCON_FRL_MODE_SEQUENTIAL = 0, >> + DP_PCON_FRL_MODE_CONCURRENT = 1, >> +}; >> + >> /** >> * struct drm_dp_vsc_sdp - drm DP VSC SDP >> * >> @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], >> int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); >> bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); >> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, >> - bool concurrent_mode); >> + enum dp_pcon_frl_train_mode frl_mode); >> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, >> - bool extended_train_mode); >> + enum dp_pcon_frl_train_type frl_type); >> int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); >> int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); >> >> -- >> 2.29.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON 2021-02-04 6:48 ` [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal 2021-02-05 20:00 ` Ville Syrjälä @ 2021-02-11 6:43 ` Ankit Nautiyal 1 sibling, 0 replies; 15+ messages in thread From: Ankit Nautiyal @ 2021-02-11 6:43 UTC (permalink / raw) To: intel-gfx; +Cc: airlied, uma.shankar, dri-devel Currently the FRL training mode (Concurrent, Sequential) and training type (Normal, Extended) are not defined properly and are passed as bool values in drm_helpers for pcon configuration for FRL training. This patch: -Add register masks for Sequential and Normal FRL training options. -Fixes the drm_helpers for FRL Training configuration to use the appropriate masks. -Modifies the calls to the above drm_helpers in i915/intel_dp as per the above change. v2: Re-used the register masks for these options, instead of enum. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 24 ++++++++++++++---------- drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++------ include/drm/drm_dp_helper.h | 6 ++++-- 3 files changed, 22 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index eedbb48815b7..cb2f53e56685 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -2635,14 +2635,16 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 * @aux: DisplayPort AUX channel * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink - * @concurrent_mode: true if concurrent mode or operation is required, - * false otherwise. + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. + * In Concurrent Mode, the FRL link bring up can be done along with + * DP Link training. In Sequential mode, the FRL link bring up is done prior to + * the DP Link training. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode) + u8 frl_mode) { int ret; u8 buf; @@ -2651,7 +2653,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, if (ret < 0) return ret; - if (concurrent_mode) + if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK) buf |= DP_PCON_ENABLE_CONCURRENT_LINK; else buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; @@ -2694,21 +2696,23 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 * @aux: DisplayPort AUX channel * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink - * @extended_train_mode : true for Extended Mode, false for Normal Mode. - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting - * from min, and stops when link training is successful. In Extended mode, all - * frl bw selected in the mask are trained by the PCON. + * @frl_type : FRL training type, can be Extended, or Normal. + * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask + * starting from min, and stops when link training is successful. In Extended + * FRL training, all frl bw selected in the mask are trained by the PCON. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode) + u8 frl_type) { int ret; u8 buf = max_frl_mask; - if (extended_train_mode) + if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED) buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; + else + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); if (ret < 0) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 61beeb3161e2..510c6b442c1b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2559,10 +2559,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) { -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) -#define PCON_CONCURRENT_MODE (1 > 0) -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE #define TIMEOUT_FRL_READY_MS 500 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 @@ -2596,10 +2592,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) return -ETIMEDOUT; max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, + DP_PCON_ENABLE_SEQUENTIAL_LINK); if (ret < 0) return ret; - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, + DP_PCON_FRL_LINK_TRAIN_NORMAL); if (ret < 0) return ret; ret = drm_dp_pcon_frl_enable(&intel_dp->aux); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index edffd1dcca3e..f1c7e09728d4 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1171,6 +1171,7 @@ struct drm_device; # define DP_PCON_ENABLE_MAX_BW_48GBPS 6 # define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) # define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) +# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) # define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) # define DP_PCON_ENABLE_HPD_READY (1 << 6) # define DP_PCON_ENABLE_HDMI_LINK (1 << 7) @@ -1185,6 +1186,7 @@ struct drm_device; # define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) # define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) # define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) +# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) /* PCON HDMI LINK STATUS */ #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B @@ -2149,9 +2151,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode); + u8 frl_mode); int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode); + u8 frl_type); int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); -- 2.29.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms 2021-02-04 6:48 [PATCH 0/3] HDMI2.1 PCON Misc Fixes Ankit Nautiyal 2021-02-04 6:48 ` [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Ankit Nautiyal 2021-02-04 6:48 ` [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal @ 2021-02-04 6:48 ` Ankit Nautiyal 2021-02-05 20:01 ` Ville Syrjälä 2 siblings, 1 reply; 15+ messages in thread From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw) To: intel-gfx; +Cc: uma.shankar, dri-devel Remove code for resetting frl related members from intel_disable_dp, as this is not applicable for older platforms. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1962d6dd8641..9d94bdf5f517 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2387,8 +2387,6 @@ static void intel_disable_dp(struct intel_atomic_state *state, intel_edp_backlight_off(old_conn_state); intel_dp_set_power(intel_dp, DP_SET_POWER_D3); intel_pps_off(intel_dp); - intel_dp->frl.is_trained = false; - intel_dp->frl.trained_rate_gbps = 0; } static void g4x_disable_dp(struct intel_atomic_state *state, -- 2.29.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms 2021-02-04 6:48 ` [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms Ankit Nautiyal @ 2021-02-05 20:01 ` Ville Syrjälä 0 siblings, 0 replies; 15+ messages in thread From: Ville Syrjälä @ 2021-02-05 20:01 UTC (permalink / raw) To: Ankit Nautiyal; +Cc: intel-gfx, uma.shankar, dri-devel On Thu, Feb 04, 2021 at 12:18:42PM +0530, Ankit Nautiyal wrote: > Remove code for resetting frl related members from intel_disable_dp, as > this is not applicable for older platforms. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 1962d6dd8641..9d94bdf5f517 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2387,8 +2387,6 @@ static void intel_disable_dp(struct intel_atomic_state *state, > intel_edp_backlight_off(old_conn_state); > intel_dp_set_power(intel_dp, DP_SET_POWER_D3); > intel_pps_off(intel_dp); > - intel_dp->frl.is_trained = false; > - intel_dp->frl.trained_rate_gbps = 0; If we don't need it in the ddi path we don't need it here. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > } > > static void g4x_disable_dp(struct intel_atomic_state *state, > -- > 2.29.2 -- Ville Syrjälä Intel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2021-03-09 4:28 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-02-04 6:48 [PATCH 0/3] HDMI2.1 PCON Misc Fixes Ankit Nautiyal 2021-02-04 6:48 ` [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Ankit Nautiyal 2021-02-05 19:58 ` Ville Syrjälä 2021-02-05 20:07 ` [Intel-gfx] " Navare, Manasi 2021-02-05 20:06 ` Ville Syrjälä 2021-02-05 20:22 ` Navare, Manasi 2021-02-08 11:15 ` Jani Nikula 2021-02-08 11:44 ` Nautiyal, Ankit K 2021-03-09 4:28 ` Nautiyal, Ankit K 2021-02-04 6:48 ` [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal 2021-02-05 20:00 ` Ville Syrjälä 2021-02-11 6:56 ` Nautiyal, Ankit K 2021-02-11 6:43 ` [PATCH v2 " Ankit Nautiyal 2021-02-04 6:48 ` [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms Ankit Nautiyal 2021-02-05 20:01 ` Ville Syrjälä
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