* [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database
@ 2023-12-02 21:40 Dmitry Baryshkov
2023-12-02 21:40 ` [PATCH 01/12] drm/msm: fix BPC1 -> BPC4 Dmitry Baryshkov
` (11 more replies)
0 siblings, 12 replies; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
During the review of [1] Abhinav pointed out that mdp_rgb_formats and
mdp_rgb_yuv_formats arrays from patch 1 are directly based on the struct
mdp_format formats array. This was true, because MDP4 / MDP5 drivers
used their own (small) list of supported formats. The DPU driver,
supporting more formats, had larger database of the formats and their
properties. While we don't have plans to expand MDP5 formats support, it
make sense to merge these two databases into a common dataset.
[1] https://patchwork.freedesktop.org/series/120377/
Dmitry Baryshkov (12):
drm/msm: fix BPC1 -> BPC4
drm/msm/disp: add mdp_fetch_mode enum
drm/msm/dpu: use format-related definitions from mdp_common.xml.h
drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware
drm/msm/dpu: in dpu_format replace bitmap with unsigned long field
drm/msm/dpu: pull format flag definitions to msm_drv.h
drm/msm: merge dpu_format and mdp_format in struct msm_format
drm/msm: convert msm_format::unpack_tight to the flag
drm/msm: convert msm_format::unpack_align_msb to the flag
drm/msm: convert msm_format::alpha_enable to the flag
drm/msm: merge dpu format database to MDP formats
drm/msm: drop msm_kms_funcs::get_format() callback
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 22 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 658 +-----------------
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 23 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 123 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 45 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 17 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 22 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 75 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 6 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 -
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 89 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 16 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 98 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +-
drivers/gpu/drm/msm/disp/mdp_common.xml.h | 8 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 611 +++++++++++++---
drivers/gpu/drm/msm/disp/mdp_kms.h | 17 -
drivers/gpu/drm/msm/msm_drv.h | 64 ++
drivers/gpu/drm/msm/msm_fb.c | 2 +-
drivers/gpu/drm/msm/msm_kms.h | 4 -
30 files changed, 884 insertions(+), 1065 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 01/12] drm/msm: fix BPC1 -> BPC4
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-10 19:15 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 02/12] drm/msm/disp: add mdp_fetch_mode enum Dmitry Baryshkov
` (10 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Fix enum mdp_bpc::BPC1 value to be BPC4 instead (as shown in the DPU
driver). This commit should be replaced with the registers sync with
Mesa instead.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/mdp_common.xml.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp_common.xml.h b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
index 4dd8d7db2862..5220688727e4 100644
--- a/drivers/gpu/drm/msm/disp/mdp_common.xml.h
+++ b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
@@ -94,7 +94,7 @@ enum mdp_component_type {
};
enum mdp_bpc {
- BPC1 = 0,
+ BPC4 = 0,
BPC5 = 1,
BPC6 = 2,
BPC8 = 3,
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 02/12] drm/msm/disp: add mdp_fetch_mode enum
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
2023-12-02 21:40 ` [PATCH 01/12] drm/msm: fix BPC1 -> BPC4 Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-10 19:19 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h Dmitry Baryshkov
` (9 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Pull in new enum from the mesa registers. This commit should be replaced
with the registers sync with Mesa instead.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/mdp_common.xml.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp_common.xml.h b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
index 5220688727e4..2fa333bab3d2 100644
--- a/drivers/gpu/drm/msm/disp/mdp_common.xml.h
+++ b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
@@ -107,5 +107,11 @@ enum mdp_bpc_alpha {
BPC8A = 3,
};
+enum mdp_fetch_mode {
+ MDP_FETCH_LINEAR = 0,
+ MDP_FETCH_TILE = 1,
+ MDP_FETCH_UBWC = 2,
+};
+
#endif /* MDP_COMMON_XML */
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
2023-12-02 21:40 ` [PATCH 01/12] drm/msm: fix BPC1 -> BPC4 Dmitry Baryshkov
2023-12-02 21:40 ` [PATCH 02/12] drm/msm/disp: add mdp_fetch_mode enum Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-10 20:00 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 04/12] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware Dmitry Baryshkov
` (8 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Instead of having DPU-specific defines, switch to the definitions from
the mdp_common.xml.h file. This is the preparation for merged of DPU and
MDP format tables.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 290 +++++++++---------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 64 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
6 files changed, 164 insertions(+), 214 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 0b6a761d68b7..4fead04d83a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -640,7 +640,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
wb_cfg->dest.height = job->fb->height;
wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
- if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
+ if ((wb_cfg->dest.format->fetch_planes == MDP_PLANE_PLANAR) &&
(wb_cfg->dest.format->element[0] == C1_B_Cb))
swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index e366ab134249..05e82f5dd0e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -35,11 +35,11 @@
bp, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED, \
+ .fetch_planes = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
+ .chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
@@ -54,11 +54,11 @@ bp, flg, fm, np) \
alpha, bp, flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED, \
+ .fetch_planes = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
+ .chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
@@ -74,7 +74,7 @@ alpha, bp, flg, fm, np, th) \
alpha, chroma, count, bp, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED, \
+ .fetch_planes = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3)}, \
.bits = { g, b, r, a }, \
@@ -92,7 +92,7 @@ alpha, chroma, count, bp, flg, fm, np) \
#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
+ .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
@@ -111,7 +111,7 @@ alpha, chroma, count, bp, flg, fm, np) \
flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
+ .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
@@ -129,7 +129,7 @@ flg, fm, np, th) \
#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
+ .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
@@ -148,7 +148,7 @@ flg, fm, np, th) \
flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
+ .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false, \
.element = { (e0), (e1), 0, 0 }, \
.bits = { g, b, r, a }, \
@@ -168,7 +168,7 @@ flg, fm, np, th) \
flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PLANAR, \
+ .fetch_planes = MDP_PLANE_PLANAR, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), 0 }, \
.bits = { g, b, r, a }, \
@@ -195,286 +195,286 @@ struct dpu_media_color_map {
static const struct dpu_format dpu_format_map[] = {
INTERLEAVED_RGB_FMT(ARGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 4, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGB888,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
false, 3, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGR888,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 3, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGB565,
- 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
+ 0, BPC5, BPC6, BPC5,
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGR565,
- 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
+ 0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
+ BPC1A, BPC5, BPC5, BPC5,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
+ BPC4A, BPC4, BPC4, BPC4,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 2, 0,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRA1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
+ MDP_FETCH_LINEAR, 1),
PSEUDO_YUV_FMT(NV12,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_420, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV21,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_420, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV16,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV61,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
- DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT_LOOSE(P010,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(VYUY,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(UYVY,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YUYV,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YVYU,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
+ false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
PLANAR_YUV_FMT(YUV420,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb, C0_G_Y,
- false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 3),
+ false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
PLANAR_YUV_FMT(YVU420,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr, C0_G_Y,
- false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 3),
+ false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
};
/*
@@ -485,88 +485,88 @@ static const struct dpu_format dpu_format_map[] = {
*/
static const struct dpu_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(BGR565,
- 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
+ 0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
false, 2, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* ARGB8888 and ABGR8888 purposely have the same color
* ordering. The hardware only supports ABGR8888 UBWC
* natively.
*/
INTERLEAVED_RGB_FMT_TILED(ARGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
false, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* XRGB2101010 and ARGB2101010 purposely have the same color
* ordering. The hardware only supports ARGB2101010 UBWC
* natively.
*/
INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
PSEUDO_YUV_FMT_TILED(NV12,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV |
+ CHROMA_420, DPU_FORMAT_FLAG_YUV |
DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
+ MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
PSEUDO_YUV_FMT_TILED(P010,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
+ 0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_DX |
+ CHROMA_420, DPU_FORMAT_FLAG_DX |
DPU_FORMAT_FLAG_YUV |
DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
+ MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
};
/* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support
* Note: Not using the drm_format_*_subsampling since we have formats
*/
static void _dpu_get_v_h_subsample_rate(
- enum dpu_chroma_samp_type chroma_sample,
+ enum mdp_chroma_samp_type chroma_sample,
uint32_t *v_sample,
uint32_t *h_sample)
{
@@ -574,15 +574,15 @@ static void _dpu_get_v_h_subsample_rate(
return;
switch (chroma_sample) {
- case DPU_CHROMA_H2V1:
+ case CHROMA_H2V1:
*v_sample = 1;
*h_sample = 2;
break;
- case DPU_CHROMA_H1V2:
+ case CHROMA_H1V2:
*v_sample = 2;
*h_sample = 1;
break;
- case DPU_CHROMA_420:
+ case CHROMA_420:
*v_sample = 2;
*h_sample = 2;
break;
@@ -724,7 +724,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->num_planes = fmt->num_planes;
/* Due to memset above, only need to set planes of interest */
- if (fmt->fetch_planes == DPU_PLANE_INTERLEAVED) {
+ if (fmt->fetch_planes == MDP_PLANE_INTERLEAVED) {
layout->num_planes = 1;
layout->plane_size[0] = width * height * layout->format->bpp;
layout->plane_pitch[0] = width * layout->format->bpp;
@@ -751,7 +751,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->plane_size[1] = layout->plane_pitch[1] *
(height / v_subsample);
- if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
+ if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
layout->num_planes = 2;
layout->plane_size[1] *= 2;
layout->plane_pitch[1] *= 2;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index e8b8908d3e12..06c6001b0626 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -204,9 +204,9 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
(0x21 << 8));
else
/* Interface treats all the pixel data in RGB888 format */
- panel_format = (COLOR_8BIT |
- (COLOR_8BIT << 2) |
- (COLOR_8BIT << 4) |
+ panel_format = (BPC8 |
+ (BPC8 << 2) |
+ (BPC8 << 4) |
(0x21 << 8));
DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index d85157acfbf8..ebb3f9f493c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -9,6 +9,7 @@
#include <linux/err.h>
#include "msm_drv.h"
+#include "disp/mdp_common.xml.h"
#define DPU_DBG_NAME "dpu"
@@ -49,12 +50,12 @@ enum dpu_format_flags {
(test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
#define DPU_FORMAT_IS_DX(X) \
(test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
-#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR)
+#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
#define DPU_FORMAT_IS_TILE(X) \
- (((X)->fetch_mode == DPU_FETCH_UBWC) && \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
!test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
#define DPU_FORMAT_IS_UBWC(X) \
- (((X)->fetch_mode == DPU_FETCH_UBWC) && \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
@@ -291,57 +292,6 @@ enum {
C3_ALPHA = 3
};
-/**
- * enum dpu_plane_type - defines how the color component pixel packing
- * @DPU_PLANE_INTERLEAVED : Color components in single plane
- * @DPU_PLANE_PLANAR : Color component in separate planes
- * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
- */
-enum dpu_plane_type {
- DPU_PLANE_INTERLEAVED,
- DPU_PLANE_PLANAR,
- DPU_PLANE_PSEUDO_PLANAR,
-};
-
-/**
- * enum dpu_chroma_samp_type - chroma sub-samplng type
- * @DPU_CHROMA_RGB : No chroma subsampling
- * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled
- * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled
- * @DPU_CHROMA_420 : 420 subsampling
- */
-enum dpu_chroma_samp_type {
- DPU_CHROMA_RGB,
- DPU_CHROMA_H2V1,
- DPU_CHROMA_H1V2,
- DPU_CHROMA_420
-};
-
-/**
- * dpu_fetch_type - Defines How DPU HW fetches data
- * @DPU_FETCH_LINEAR : fetch is line by line
- * @DPU_FETCH_TILE : fetches data in Z order from a tile
- * @DPU_FETCH_UBWC : fetch and decompress data
- */
-enum dpu_fetch_type {
- DPU_FETCH_LINEAR,
- DPU_FETCH_TILE,
- DPU_FETCH_UBWC
-};
-
-/**
- * Value of enum chosen to fit the number of bits
- * expected by the HW programming.
- */
-enum {
- COLOR_ALPHA_1BIT = 0,
- COLOR_ALPHA_4BIT = 1,
- COLOR_4BIT = 0,
- COLOR_5BIT = 1, /* No 5-bit Alpha */
- COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
- COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
-};
-
/**
* enum dpu_3d_blend_mode
* Desribes how the 3d data is blended
@@ -381,17 +331,17 @@ enum dpu_3d_blend_mode {
*/
struct dpu_format {
struct msm_format base;
- enum dpu_plane_type fetch_planes;
+ enum mdp_fetch_type fetch_planes;
u8 element[DPU_MAX_PLANES];
u8 bits[DPU_MAX_PLANES];
- enum dpu_chroma_samp_type chroma_sample;
+ enum mdp_chroma_samp_type chroma_sample;
u8 unpack_align_msb;
u8 unpack_tight;
u8 unpack_count;
u8 bpp;
u8 alpha_enable;
u8 num_planes;
- enum dpu_fetch_type fetch_mode;
+ enum mdp_fetch_mode fetch_mode;
DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
u16 tile_width;
u16 tile_height;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 8e3c65989c49..d6530b11fc82 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -240,10 +240,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
chroma_samp = fmt->chroma_sample;
if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
- if (chroma_samp == DPU_CHROMA_H2V1)
- chroma_samp = DPU_CHROMA_H1V2;
- else if (chroma_samp == DPU_CHROMA_H1V2)
- chroma_samp = DPU_CHROMA_H2V1;
+ if (chroma_samp == CHROMA_H2V1)
+ chroma_samp = CHROMA_H1V2;
+ else if (chroma_samp == CHROMA_H1V2)
+ chroma_samp = CHROMA_H2V1;
}
src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
@@ -253,7 +253,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
if (flags & DPU_SSPP_ROT_90)
src_format |= BIT(11); /* ROT90 */
- if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED)
+ if (fmt->alpha_enable && fmt->fetch_planes == MDP_PLANE_INTERLEAVED)
src_format |= BIT(8); /* SRCC3_EN */
if (flags & DPU_SSPP_SOLID_FILL)
@@ -266,7 +266,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
(fmt->unpack_align_msb << 18) |
((fmt->bpp - 1) << 9);
- if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
+ if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
if (DPU_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 1e0da38c6f2a..17d0b4bcdc89 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -215,8 +215,8 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
/* FIXME: in multirect case account for the src_width of all the planes */
- if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
- if (fmt->chroma_sample == DPU_CHROMA_420) {
+ if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
+ if (fmt->chroma_sample == CHROMA_420) {
/* NV12 */
total_fl = (fixed_buff_size / 2) /
((src_width + 32) * fmt->bpp);
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 04/12] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
` (2 preceding siblings ...)
2023-12-02 21:40 ` [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-19 21:06 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 05/12] drm/msm/dpu: in dpu_format replace bitmap with unsigned long field Dmitry Baryshkov
` (7 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
MDP4 and MDP5 drivers enumerate supported formats each time the plane is
created. In preparation to merger of MDP DPU format databases, define
precise formats list, so that changes to the database do not cause the
driver to add unsupported format to the list.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 57 ++++++++++++++++++++--
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 36 +++++++++++---
drivers/gpu/drm/msm/disp/mdp_format.c | 28 -----------
drivers/gpu/drm/msm/disp/mdp_kms.h | 1 -
4 files changed, 80 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index b689b618da78..cebe20c82a54 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -371,6 +371,47 @@ static const uint64_t supported_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+const uint32_t mdp4_rgb_formats[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+};
+
+const uint32_t mdp4_rgb_yuv_formats[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
enum mdp4_pipe pipe_id, bool private_plane)
@@ -379,6 +420,8 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
struct mdp4_plane *mdp4_plane;
int ret;
enum drm_plane_type type;
+ const uint32_t *formats;
+ unsigned int nformats;
mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
if (!mdp4_plane) {
@@ -392,13 +435,17 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
mdp4_plane->name = pipe_names[pipe_id];
mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
- mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
- ARRAY_SIZE(mdp4_plane->formats),
- !pipe_supports_yuv(mdp4_plane->caps));
-
type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
+
+ if (pipe_supports_yuv(mdp4_plane->caps)) {
+ formats = mdp4_rgb_yuv_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
+ } else {
+ formats = mdp4_rgb_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_formats);
+ }
ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
- mdp4_plane->formats, mdp4_plane->nformats,
+ formats, nformats,
supported_format_modifiers, type, NULL);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index 0d5ff03cb091..aa8342d93393 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -17,9 +17,6 @@
struct mdp5_plane {
struct drm_plane base;
-
- uint32_t nformats;
- uint32_t formats[32];
};
#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
@@ -1007,6 +1004,32 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
return mask;
}
+const uint32_t mdp5_plane_formats[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp5_plane_init(struct drm_device *dev,
enum drm_plane_type type)
@@ -1023,12 +1046,9 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
plane = &mdp5_plane->base;
- mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
- ARRAY_SIZE(mdp5_plane->formats), false);
-
ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
- mdp5_plane->formats, mdp5_plane->nformats,
- NULL, type, NULL);
+ mdp5_plane_formats, ARRAY_SIZE(mdp5_plane_formats),
+ NULL, type, NULL);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 025595336f26..69ab5bcff1a9 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -80,10 +80,6 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
#define BPC0A 0
-/*
- * Note: Keep RGB formats 1st, followed by YUV formats to avoid breaking
- * mdp_get_rgb_formats()'s implementation.
- */
static const struct mdp_format formats[] = {
/* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
@@ -138,30 +134,6 @@ static const struct mdp_format formats[] = {
MDP_PLANE_PLANAR, CHROMA_420, true),
};
-/*
- * Note:
- * @rgb_only must be set to true, when requesting
- * supported formats for RGB pipes.
- */
-uint32_t mdp_get_formats(uint32_t *pixel_formats, uint32_t max_formats,
- bool rgb_only)
-{
- uint32_t i;
- for (i = 0; i < ARRAY_SIZE(formats); i++) {
- const struct mdp_format *f = &formats[i];
-
- if (i == max_formats)
- break;
-
- if (rgb_only && MDP_FORMAT_IS_YUV(f))
- break;
-
- pixel_formats[i] = f->base.pixel_format;
- }
-
- return i;
-}
-
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
uint64_t modifier)
{
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h b/drivers/gpu/drm/msm/disp/mdp_kms.h
index b0286d5d5130..d0718c16de3e 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -91,7 +91,6 @@ struct mdp_format {
#define to_mdp_format(x) container_of(x, struct mdp_format, base)
#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
-uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
/* MDP capabilities */
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 05/12] drm/msm/dpu: in dpu_format replace bitmap with unsigned long field
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
` (3 preceding siblings ...)
2023-12-02 21:40 ` [PATCH 04/12] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-10 20:40 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 06/12] drm/msm/dpu: pull format flag definitions to msm_drv.h Dmitry Baryshkov
` (6 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Using bitmap for the flags results in a clumsy syntax on test_bit,
replace it with unsigned long type and simple binary ops.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 18 +++++++++---------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 16 +++++++---------
2 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 05e82f5dd0e6..3112d85808c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -45,7 +45,7 @@ bp, flg, fm, np) \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -64,7 +64,7 @@ alpha, bp, flg, fm, np, th) \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -84,7 +84,7 @@ alpha, chroma, count, bp, flg, fm, np) \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -102,7 +102,7 @@ alpha, chroma, count, bp, flg, fm, np) \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -121,7 +121,7 @@ flg, fm, np, th) \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -139,7 +139,7 @@ flg, fm, np, th) \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -158,7 +158,7 @@ flg, fm, np, th) \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -178,7 +178,7 @@ flg, fm, np) \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -1047,7 +1047,7 @@ const struct dpu_format *dpu_get_dpu_format_ext(
DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",
(char *)&format, modifier);
else
- DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",
+ DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %ld\n",
(char *)&format, modifier,
DPU_FORMAT_IS_UBWC(fmt),
DPU_FORMAT_IS_YUV(fmt));
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index ebb3f9f493c3..caa0ff2d192f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -40,23 +40,21 @@ enum dpu_format_flags {
DPU_FORMAT_FLAG_YUV_BIT,
DPU_FORMAT_FLAG_DX_BIT,
DPU_FORMAT_FLAG_COMPRESSED_BIT,
- DPU_FORMAT_FLAG_BIT_MAX,
};
#define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT)
#define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT)
#define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
-#define DPU_FORMAT_IS_YUV(X) \
- (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
-#define DPU_FORMAT_IS_DX(X) \
- (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
+
+#define DPU_FORMAT_IS_YUV(X) ((X)->flags & DPU_FORMAT_FLAG_YUV)
+#define DPU_FORMAT_IS_DX(X) ((X)->flags & DPU_FORMAT_FLAG_DX)
#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
#define DPU_FORMAT_IS_TILE(X) \
(((X)->fetch_mode == MDP_FETCH_UBWC) && \
- !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
+ !((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
#define DPU_FORMAT_IS_UBWC(X) \
(((X)->fetch_mode == MDP_FETCH_UBWC) && \
- test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
+ ((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
@@ -325,7 +323,7 @@ enum dpu_3d_blend_mode {
* @alpha_enable: whether the format has an alpha channel
* @num_planes: number of planes (including meta data planes)
* @fetch_mode: linear, tiled, or ubwc hw fetch behavior
- * @flag: usage bit flags
+ * @flags: usage bit flags
* @tile_width: format tile width
* @tile_height: format tile height
*/
@@ -342,7 +340,7 @@ struct dpu_format {
u8 alpha_enable;
u8 num_planes;
enum mdp_fetch_mode fetch_mode;
- DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
+ unsigned long flags;
u16 tile_width;
u16 tile_height;
};
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 06/12] drm/msm/dpu: pull format flag definitions to msm_drv.h
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
` (4 preceding siblings ...)
2023-12-02 21:40 ` [PATCH 05/12] drm/msm/dpu: in dpu_format replace bitmap with unsigned long field Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-11 18:41 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 07/12] drm/msm: merge dpu_format and mdp_format in struct msm_format Dmitry Baryshkov
` (5 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
In preparation to merger of formats databases, pull format flag
definitions to msm_drv.h header, so that they are visibile to both dpu
and mdp drivers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 98 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 28 ++----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 8 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 6 +-
drivers/gpu/drm/msm/disp/mdp_kms.h | 3 +-
drivers/gpu/drm/msm/msm_drv.h | 24 +++++
8 files changed, 91 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 3112d85808c7..25d3451e8260 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -44,8 +44,8 @@ bp, flg, fm, np) \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -63,8 +63,8 @@ alpha, bp, flg, fm, np, th) \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -83,8 +83,8 @@ alpha, chroma, count, bp, flg, fm, np) \
.unpack_tight = 1, \
.unpack_count = count, \
.bpp = bp, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -101,8 +101,8 @@ alpha, chroma, count, bp, flg, fm, np) \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -120,8 +120,8 @@ flg, fm, np, th) \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -138,8 +138,8 @@ flg, fm, np, th) \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -157,8 +157,8 @@ flg, fm, np, th) \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -177,8 +177,8 @@ flg, fm, np) \
.unpack_tight = 1, \
.unpack_count = 1, \
.bpp = bp, \
- .fetch_mode = fm, \
- .flags = flg, \
+ .base.fetch_mode = fm, \
+ .base.flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -365,115 +365,115 @@ static const struct dpu_format dpu_format_map[] = {
INTERLEAVED_RGB_FMT(BGRA1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
+ true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBA1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
+ true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ABGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
+ true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(ARGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
+ true, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XRGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
+ false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(BGRX1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
+ false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(XBGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
+ false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
INTERLEAVED_RGB_FMT(RGBX1010102,
BPC8A, BPC8, BPC8, BPC8,
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
+ false, 4, MSM_FORMAT_FLAG_DX,
MDP_FETCH_LINEAR, 1),
PSEUDO_YUV_FMT(NV12,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, DPU_FORMAT_FLAG_YUV,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV21,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
- CHROMA_420, DPU_FORMAT_FLAG_YUV,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV16,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT(NV61,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb,
- CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT_LOOSE(P010,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
+ CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(VYUY,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
- false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(UYVY,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
- false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YUYV,
0, BPC8, BPC8, BPC8,
C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
- false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(YVYU,
0, BPC8, BPC8, BPC8,
C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
- false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 2),
PLANAR_YUV_FMT(YUV420,
0, BPC8, BPC8, BPC8,
C2_R_Cr, C1_B_Cb, C0_G_Y,
- false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 3),
PLANAR_YUV_FMT(YVU420,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr, C0_G_Y,
- false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
MDP_FETCH_LINEAR, 3),
};
@@ -487,13 +487,13 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(BGR565,
0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 2, DPU_FORMAT_FLAG_COMPRESSED,
+ false, 2, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* ARGB8888 and ABGR8888 purposely have the same color
@@ -503,37 +503,37 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(ARGB8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_COMPRESSED,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB8888,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_COMPRESSED,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
/* XRGB2101010 and ARGB2101010 purposely have the same color
@@ -543,22 +543,22 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
BPC8A, BPC8, BPC8, BPC8,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
PSEUDO_YUV_FMT_TILED(NV12,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, DPU_FORMAT_FLAG_YUV |
- DPU_FORMAT_FLAG_COMPRESSED,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
PSEUDO_YUV_FMT_TILED(P010,
0, BPC8, BPC8, BPC8,
C1_B_Cb, C2_R_Cr,
- CHROMA_420, DPU_FORMAT_FLAG_DX |
- DPU_FORMAT_FLAG_YUV |
- DPU_FORMAT_FLAG_COMPRESSED,
+ CHROMA_420, MSM_FORMAT_FLAG_DX |
+ MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index caa0ff2d192f..2139e3dedef3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -36,25 +36,11 @@
#define DPU_MAX_DE_CURVES 3
#endif
-enum dpu_format_flags {
- DPU_FORMAT_FLAG_YUV_BIT,
- DPU_FORMAT_FLAG_DX_BIT,
- DPU_FORMAT_FLAG_COMPRESSED_BIT,
-};
-
-#define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT)
-#define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT)
-#define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
-
-#define DPU_FORMAT_IS_YUV(X) ((X)->flags & DPU_FORMAT_FLAG_YUV)
-#define DPU_FORMAT_IS_DX(X) ((X)->flags & DPU_FORMAT_FLAG_DX)
-#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
-#define DPU_FORMAT_IS_TILE(X) \
- (((X)->fetch_mode == MDP_FETCH_UBWC) && \
- !((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
-#define DPU_FORMAT_IS_UBWC(X) \
- (((X)->fetch_mode == MDP_FETCH_UBWC) && \
- ((X)->flags & DPU_FORMAT_FLAG_COMPRESSED))
+#define DPU_FORMAT_IS_YUV(X) MSM_FORMAT_IS_YUV(&(X)->base)
+#define DPU_FORMAT_IS_DX(X) MSM_FORMAT_IS_DX(&(X)->base)
+#define DPU_FORMAT_IS_LINEAR(X) MSM_FORMAT_IS_LINEAR(&(X)->base)
+#define DPU_FORMAT_IS_TILE(X) MSM_FORMAT_IS_TILE(&(X)->base)
+#define DPU_FORMAT_IS_UBWC(X) MSM_FORMAT_IS_UBWC(&(X)->base)
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
@@ -322,8 +308,6 @@ enum dpu_3d_blend_mode {
* @bpp: bytes per pixel
* @alpha_enable: whether the format has an alpha channel
* @num_planes: number of planes (including meta data planes)
- * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
- * @flags: usage bit flags
* @tile_width: format tile width
* @tile_height: format tile height
*/
@@ -339,8 +323,6 @@ struct dpu_format {
u8 bpp;
u8 alpha_enable;
u8 num_planes;
- enum mdp_fetch_mode fetch_mode;
- unsigned long flags;
u16 tile_width;
u16 tile_height;
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index d6530b11fc82..1363dcc72a6d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -266,10 +266,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
(fmt->unpack_align_msb << 18) |
((fmt->bpp - 1) << 9);
- if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
+ if (!DPU_FORMAT_IS_LINEAR(fmt)) {
if (DPU_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
- src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
+ src_format |= (fmt->base.fetch_mode & 3) << 30; /*FRAME_FORMAT */
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
DPU_FETCH_CONFIG_RESET_VALUE |
ctx->ubwc->highest_bank_bit << 18);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 17d0b4bcdc89..aa505b1a9f3b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -295,14 +295,14 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
(fmt) ? fmt->base.pixel_format : 0,
- (fmt) ? fmt->fetch_mode : 0,
+ (fmt) ? fmt->base.fetch_mode : 0,
cfg.danger_lut,
cfg.safe_lut);
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
pdpu->pipe - SSPP_VIG0,
fmt ? (char *)&fmt->base.pixel_format : NULL,
- fmt ? fmt->fetch_mode : -1,
+ fmt ? fmt->base.fetch_mode : -1,
cfg.danger_lut,
cfg.safe_lut);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index aa8342d93393..e40f6d1d5433 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -634,10 +634,10 @@ static uint32_t get_scale_config(const struct mdp_format *format,
uint32_t src, uint32_t dst, bool horz)
{
const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
- bool scaling = format->is_yuv ? true : (src != dst);
+ bool yuv = MDP_FORMAT_IS_YUV(format);
+ bool scaling = yuv ? true : (src != dst);
uint32_t sub;
uint32_t ya_filter, uv_filter;
- bool yuv = format->is_yuv;
if (!scaling)
return 0;
@@ -666,7 +666,7 @@ static void calc_pixel_ext(const struct mdp_format *format,
int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
bool horz)
{
- bool scaling = format->is_yuv ? true : (src != dst);
+ bool scaling = MDP_FORMAT_IS_YUV(format) ? true : (src != dst);
int i;
/*
@@ -696,7 +696,7 @@ static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
uint32_t roi_w = src_w;
uint32_t roi_h = src_h;
- if (format->is_yuv && i == COMP_1_2) {
+ if (MDP_FORMAT_IS_YUV(format) && i == COMP_1_2) {
roi_w /= info->hsub;
roi_h /= info->vsub;
}
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 69ab5bcff1a9..30919641c813 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -63,7 +63,10 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
};
#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
- .base = { .pixel_format = DRM_FORMAT_ ## name }, \
+ .base = { \
+ .pixel_format = DRM_FORMAT_ ## name, \
+ .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
+ }, \
.bpc_a = BPC ## a ## A, \
.bpc_r = BPC ## r, \
.bpc_g = BPC ## g, \
@@ -75,7 +78,6 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
.unpack_count = cnt, \
.fetch_type = fp, \
.chroma_sample = cs, \
- .is_yuv = yuv, \
}
#define BPC0A 0
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h b/drivers/gpu/drm/msm/disp/mdp_kms.h
index d0718c16de3e..ffa71777dada 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -86,10 +86,9 @@ struct mdp_format {
uint8_t cpp, unpack_count;
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
- bool is_yuv;
};
#define to_mdp_format(x) container_of(x, struct mdp_format, base)
-#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
+#define MDP_FORMAT_IS_YUV(mdp_format) (MSM_FORMAT_IS_YUV(&(mdp_format)->base))
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 628ef3e663ea..b37546ffb0c3 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -33,6 +33,8 @@
#include <drm/msm_drm.h>
#include <drm/drm_gem.h>
+#include "disp/mdp_common.xml.h"
+
#ifdef CONFIG_FAULT_INJECTION
extern struct fault_attr fail_gem_alloc;
extern struct fault_attr fail_gem_iova;
@@ -249,10 +251,32 @@ struct msm_drm_private {
bool disable_err_irq;
};
+enum msm_format_flags {
+ MSM_FORMAT_FLAG_YUV_BIT,
+ MSM_FORMAT_FLAG_DX_BIT,
+ MSM_FORMAT_FLAG_COMPRESSED_BIT,
+};
+
+#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
+#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
+#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
+
struct msm_format {
uint32_t pixel_format;
+ unsigned long flags;
+ enum mdp_fetch_mode fetch_mode;
};
+#define MSM_FORMAT_IS_YUV(X) ((X)->flags & MSM_FORMAT_FLAG_YUV)
+#define MSM_FORMAT_IS_DX(X) ((X)->flags & MSM_FORMAT_FLAG_DX)
+#define MSM_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
+#define MSM_FORMAT_IS_TILE(X) \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
+ !((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
+#define MSM_FORMAT_IS_UBWC(X) \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
+ ((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
+
struct msm_pending_timer;
int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 07/12] drm/msm: merge dpu_format and mdp_format in struct msm_format
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
` (5 preceding siblings ...)
2023-12-02 21:40 ` [PATCH 06/12] drm/msm/dpu: pull format flag definitions to msm_drv.h Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-11 19:15 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 08/12] drm/msm: convert msm_format::unpack_tight to the flag Dmitry Baryshkov
` (4 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Structures dpu_format and mdp_format are largely the same structures.
In order to remove duplication between format databases, merge these two
stucture definitions into the global struct msm_format.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 184 ++++++++++--------
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 41 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 14 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 16 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 74 +++----
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 26 +--
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 7 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 54 ++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 28 ++-
drivers/gpu/drm/msm/disp/mdp_kms.h | 13 --
drivers/gpu/drm/msm/msm_drv.h | 28 +++
24 files changed, 279 insertions(+), 288 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 3c475f8042b0..9041b0d71b25 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -331,7 +331,7 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
}
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
- struct dpu_plane_state *pstate, struct dpu_format *format)
+ struct dpu_plane_state *pstate, const struct msm_format *format)
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
uint32_t blend_op;
@@ -374,7 +374,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
fg_alpha, bg_alpha, blend_op);
DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
- &format->base.pixel_format, format->alpha_enable, blend_op);
+ &format->pixel_format, format->alpha_enable, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -406,7 +406,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
struct dpu_crtc_mixer *mixer,
u32 num_mixers,
enum dpu_stage stage,
- struct dpu_format *format,
+ const struct msm_format *format,
uint64_t modifier,
struct dpu_sw_pipe *pipe,
unsigned int stage_idx,
@@ -423,7 +423,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
state, to_dpu_plane_state(state), stage_idx,
- format->base.pixel_format,
+ format->pixel_format,
modifier);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
@@ -451,7 +451,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
struct drm_plane_state *state;
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_plane_state *pstate = NULL;
- struct dpu_format *format;
+ const struct msm_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
uint32_t lm_idx;
@@ -470,7 +470,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
+ format = msm_framebuffer_format(pstate->base.fb);
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index a01fda711883..35aaead897e1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -232,7 +232,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
{
struct drm_display_mode mode;
struct dpu_hw_intf_timing_params timing_params = { 0 };
- const struct dpu_format *fmt = NULL;
+ const struct msm_format *fmt = NULL;
u32 fmt_fourcc = DRM_FORMAT_RGB888;
unsigned long lock_flags;
struct dpu_hw_intf_cfg intf_cfg = { 0 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 4fead04d83a0..a400c44a1a71 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -640,7 +640,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
wb_cfg->dest.height = job->fb->height;
wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
- if ((wb_cfg->dest.format->fetch_planes == MDP_PLANE_PLANAR) &&
+ if ((wb_cfg->dest.format->fetch_type == MDP_PLANE_PLANAR) &&
(wb_cfg->dest.format->element[0] == C1_B_Cb))
swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 25d3451e8260..ea9d5fb01000 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -34,18 +34,21 @@
#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
bp, flg, fm, np) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_INTERLEAVED, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -53,18 +56,21 @@ bp, flg, fm, np) \
#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
alpha, bp, flg, fm, np, th) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_INTERLEAVED, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -73,36 +79,42 @@ alpha, bp, flg, fm, np, th) \
#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
alpha, chroma, count, bp, flg, fm, np) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_INTERLEAVED, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3)}, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = count, \
.bpp = bp, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -110,36 +122,42 @@ alpha, chroma, count, bp, flg, fm, np) \
#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
flg, fm, np, th) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -147,18 +165,21 @@ flg, fm, np, th) \
#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
flg, fm, np, th) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
.unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -167,18 +188,21 @@ flg, fm, np, th) \
#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
flg, fm, np) \
{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = MDP_PLANE_PLANAR, \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PLANAR, \
.alpha_enable = alpha, \
.element = { (e0), (e1), (e2), 0 }, \
- .bits = { g, b, r, a }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
.unpack_tight = 1, \
.unpack_count = 1, \
.bpp = bp, \
- .base.fetch_mode = fm, \
- .base.flags = flg, \
+ .fetch_mode = fm, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -193,7 +217,7 @@ struct dpu_media_color_map {
uint32_t color;
};
-static const struct dpu_format dpu_format_map[] = {
+static const struct msm_format dpu_format_map[] = {
INTERLEAVED_RGB_FMT(ARGB8888,
BPC8A, BPC8, BPC8, BPC8,
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
@@ -483,7 +507,7 @@ static const struct dpu_format dpu_format_map[] = {
* If a compression ratio needs to be used for this or any other format,
* the data will be passed by user-space.
*/
-static const struct dpu_format dpu_format_map_ubwc[] = {
+static const struct msm_format dpu_format_map_ubwc[] = {
INTERLEAVED_RGB_FMT_TILED(BGR565,
0, BPC5, BPC6, BPC5,
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
@@ -593,7 +617,7 @@ static void _dpu_get_v_h_subsample_rate(
}
}
-static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
+static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt)
{
static const struct dpu_media_color_map dpu_media_ubwc_map[] = {
{DRM_FORMAT_ABGR8888, COLOR_FMT_RGBA8888_UBWC},
@@ -609,9 +633,9 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
int color_fmt = -1;
int i;
- if (fmt->base.pixel_format == DRM_FORMAT_NV12 ||
- fmt->base.pixel_format == DRM_FORMAT_P010) {
- if (DPU_FORMAT_IS_DX(fmt)) {
+ if (fmt->pixel_format == DRM_FORMAT_NV12 ||
+ fmt->pixel_format == DRM_FORMAT_P010) {
+ if (MSM_FORMAT_IS_DX(fmt)) {
if (fmt->unpack_tight)
color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
else
@@ -622,7 +646,7 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
}
for (i = 0; i < ARRAY_SIZE(dpu_media_ubwc_map); ++i)
- if (fmt->base.pixel_format == dpu_media_ubwc_map[i].format) {
+ if (fmt->pixel_format == dpu_media_ubwc_map[i].format) {
color_fmt = dpu_media_ubwc_map[i].color;
break;
}
@@ -630,14 +654,14 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
}
static int _dpu_format_get_plane_sizes_ubwc(
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const uint32_t width,
const uint32_t height,
struct dpu_hw_fmt_layout *layout)
{
int i;
int color;
- bool meta = DPU_FORMAT_IS_UBWC(fmt);
+ bool meta = MSM_FORMAT_IS_UBWC(fmt);
memset(layout, 0, sizeof(struct dpu_hw_fmt_layout));
layout->format = fmt;
@@ -648,11 +672,11 @@ static int _dpu_format_get_plane_sizes_ubwc(
color = _dpu_format_get_media_color_ubwc(fmt);
if (color < 0) {
DRM_ERROR("UBWC format not supported for fmt: %4.4s\n",
- (char *)&fmt->base.pixel_format);
+ (char *)&fmt->pixel_format);
return -EINVAL;
}
- if (DPU_FORMAT_IS_YUV(layout->format)) {
+ if (MSM_FORMAT_IS_YUV(layout->format)) {
uint32_t y_sclines, uv_sclines;
uint32_t y_meta_scanlines = 0;
uint32_t uv_meta_scanlines = 0;
@@ -709,7 +733,7 @@ static int _dpu_format_get_plane_sizes_ubwc(
}
static int _dpu_format_get_plane_sizes_linear(
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const uint32_t width,
const uint32_t height,
struct dpu_hw_fmt_layout *layout,
@@ -724,7 +748,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->num_planes = fmt->num_planes;
/* Due to memset above, only need to set planes of interest */
- if (fmt->fetch_planes == MDP_PLANE_INTERLEAVED) {
+ if (fmt->fetch_type == MDP_PLANE_INTERLEAVED) {
layout->num_planes = 1;
layout->plane_size[0] = width * height * layout->format->bpp;
layout->plane_pitch[0] = width * layout->format->bpp;
@@ -742,8 +766,8 @@ static int _dpu_format_get_plane_sizes_linear(
return -EINVAL;
}
- if ((fmt->base.pixel_format == DRM_FORMAT_NV12) &&
- (DPU_FORMAT_IS_DX(fmt)))
+ if ((fmt->pixel_format == DRM_FORMAT_NV12) &&
+ (MSM_FORMAT_IS_DX(fmt)))
bpp = 2;
layout->plane_pitch[0] = width * bpp;
layout->plane_pitch[1] = layout->plane_pitch[0] / h_subsample;
@@ -751,7 +775,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->plane_size[1] = layout->plane_pitch[1] *
(height / v_subsample);
- if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
+ if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
layout->num_planes = 2;
layout->plane_size[1] *= 2;
layout->plane_pitch[1] *= 2;
@@ -781,7 +805,7 @@ static int _dpu_format_get_plane_sizes_linear(
}
static int dpu_format_get_plane_sizes(
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const uint32_t w,
const uint32_t h,
struct dpu_hw_fmt_layout *layout,
@@ -797,7 +821,7 @@ static int dpu_format_get_plane_sizes(
return -ERANGE;
}
- if (DPU_FORMAT_IS_UBWC(fmt) || DPU_FORMAT_IS_TILE(fmt))
+ if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt))
return _dpu_format_get_plane_sizes_ubwc(fmt, w, h, layout);
return _dpu_format_get_plane_sizes_linear(fmt, w, h, layout, pitches);
@@ -823,10 +847,10 @@ static int _dpu_format_populate_addrs_ubwc(
return -EFAULT;
}
- meta = DPU_FORMAT_IS_UBWC(layout->format);
+ meta = MSM_FORMAT_IS_UBWC(layout->format);
/* Per-format logic for verifying active planes */
- if (DPU_FORMAT_IS_YUV(layout->format)) {
+ if (MSM_FORMAT_IS_YUV(layout->format)) {
/************************************************/
/* UBWC ** */
/* buffer ** DPU PLANE */
@@ -942,7 +966,7 @@ int dpu_format_populate_layout(
return -ERANGE;
}
- layout->format = to_dpu_format(msm_framebuffer_format(fb));
+ layout->format = msm_framebuffer_format(fb);
/* Populate the plane sizes etc via get_format */
ret = dpu_format_get_plane_sizes(layout->format, fb->width, fb->height,
@@ -951,8 +975,8 @@ int dpu_format_populate_layout(
return ret;
/* Populate the addresses given the fb */
- if (DPU_FORMAT_IS_UBWC(layout->format) ||
- DPU_FORMAT_IS_TILE(layout->format))
+ if (MSM_FORMAT_IS_UBWC(layout->format) ||
+ MSM_FORMAT_IS_TILE(layout->format))
ret = _dpu_format_populate_addrs_ubwc(aspace, fb, layout);
else
ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
@@ -962,23 +986,21 @@ int dpu_format_populate_layout(
int dpu_format_check_modified_format(
const struct msm_kms *kms,
- const struct msm_format *msm_fmt,
+ const struct msm_format *fmt,
const struct drm_mode_fb_cmd2 *cmd,
struct drm_gem_object **bos)
{
const struct drm_format_info *info;
- const struct dpu_format *fmt;
struct dpu_hw_fmt_layout layout;
uint32_t bos_total_size = 0;
int ret, i;
- if (!msm_fmt || !cmd || !bos) {
+ if (!fmt || !cmd || !bos) {
DRM_ERROR("invalid arguments\n");
return -EINVAL;
}
- fmt = to_dpu_format(msm_fmt);
- info = drm_format_info(fmt->base.pixel_format);
+ info = drm_format_info(fmt->pixel_format);
if (!info)
return -EINVAL;
@@ -1005,13 +1027,13 @@ int dpu_format_check_modified_format(
return 0;
}
-const struct dpu_format *dpu_get_dpu_format_ext(
+const struct msm_format *dpu_get_dpu_format_ext(
const uint32_t format,
const uint64_t modifier)
{
uint32_t i = 0;
- const struct dpu_format *fmt = NULL;
- const struct dpu_format *map = NULL;
+ const struct msm_format *fmt = NULL;
+ const struct msm_format *map = NULL;
ssize_t map_size = 0;
/*
@@ -1037,7 +1059,7 @@ const struct dpu_format *dpu_get_dpu_format_ext(
}
for (i = 0; i < map_size; i++) {
- if (format == map[i].base.pixel_format) {
+ if (format == map[i].pixel_format) {
fmt = &map[i];
break;
}
@@ -1049,8 +1071,8 @@ const struct dpu_format *dpu_get_dpu_format_ext(
else
DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %ld\n",
(char *)&format, modifier,
- DPU_FORMAT_IS_UBWC(fmt),
- DPU_FORMAT_IS_YUV(fmt));
+ MSM_FORMAT_IS_UBWC(fmt),
+ MSM_FORMAT_IS_YUV(fmt));
return fmt;
}
@@ -1060,9 +1082,5 @@ const struct msm_format *dpu_get_msm_format(
const uint32_t format,
const uint64_t modifiers)
{
- const struct dpu_format *fmt = dpu_get_dpu_format_ext(format,
- modifiers);
- if (fmt)
- return &fmt->base;
- return NULL;
+ return dpu_get_dpu_format_ext(format, modifiers);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
index 84b8b3289f18..f45c16810adb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
@@ -14,7 +14,7 @@
* @format: DRM FourCC Code
* @modifiers: format modifier array from client, one per plane
*/
-const struct dpu_format *dpu_get_dpu_format_ext(
+const struct msm_format *dpu_get_dpu_format_ext(
const uint32_t format,
const uint64_t modifier);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 06c6001b0626..d0faef4b19f2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -96,7 +96,7 @@
static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
const struct dpu_hw_intf_timing_params *p,
- const struct dpu_format *fmt)
+ const struct msm_format *fmt)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
u32 hsync_period, vsync_period;
@@ -197,10 +197,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
(p->vsync_polarity << 1) | /* VSYNC Polarity */
(p->hsync_polarity << 0); /* HSYNC Polarity */
- if (!DPU_FORMAT_IS_YUV(fmt))
- panel_format = (fmt->bits[C0_G_Y] |
- (fmt->bits[C1_B_Cb] << 2) |
- (fmt->bits[C2_R_Cr] << 4) |
+ if (!MSM_FORMAT_IS_YUV(fmt))
+ panel_format = (fmt->bpc_g_y |
+ (fmt->bpc_b_cb << 2) |
+ (fmt->bpc_r_cr << 4) |
(0x21 << 8));
else
/* Interface treats all the pixel data in RGB888 format */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index c539025c418b..d60648ab1ffc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -80,7 +80,7 @@ struct dpu_hw_intf_cmd_mode_cfg {
struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
- const struct dpu_format *fmt);
+ const struct msm_format *fmt);
void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_prog_fetch *fetch);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 2139e3dedef3..8e31387c2896 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -36,12 +36,6 @@
#define DPU_MAX_DE_CURVES 3
#endif
-#define DPU_FORMAT_IS_YUV(X) MSM_FORMAT_IS_YUV(&(X)->base)
-#define DPU_FORMAT_IS_DX(X) MSM_FORMAT_IS_DX(&(X)->base)
-#define DPU_FORMAT_IS_LINEAR(X) MSM_FORMAT_IS_LINEAR(&(X)->base)
-#define DPU_FORMAT_IS_TILE(X) MSM_FORMAT_IS_TILE(&(X)->base)
-#define DPU_FORMAT_IS_UBWC(X) MSM_FORMAT_IS_UBWC(&(X)->base)
-
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
#define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
@@ -295,39 +289,6 @@ enum dpu_3d_blend_mode {
BLEND_3D_MAX
};
-/** struct dpu_format - defines the format configuration which
- * allows DPU HW to correctly fetch and decode the format
- * @base: base msm_format structure containing fourcc code
- * @fetch_planes: how the color components are packed in pixel format
- * @element: element color ordering
- * @bits: element bit widths
- * @chroma_sample: chroma sub-samplng type
- * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
- * @unpack_tight: 0 for loose, 1 for tight
- * @unpack_count: 0 = 1 component, 1 = 2 component
- * @bpp: bytes per pixel
- * @alpha_enable: whether the format has an alpha channel
- * @num_planes: number of planes (including meta data planes)
- * @tile_width: format tile width
- * @tile_height: format tile height
- */
-struct dpu_format {
- struct msm_format base;
- enum mdp_fetch_type fetch_planes;
- u8 element[DPU_MAX_PLANES];
- u8 bits[DPU_MAX_PLANES];
- enum mdp_chroma_samp_type chroma_sample;
- u8 unpack_align_msb;
- u8 unpack_tight;
- u8 unpack_count;
- u8 bpp;
- u8 alpha_enable;
- u8 num_planes;
- u16 tile_width;
- u16 tile_height;
-};
-#define to_dpu_format(x) container_of(x, struct dpu_format, base)
-
/**
* struct dpu_hw_fmt_layout - format information of the source pixel data
* @format: pixel format parameters
@@ -340,7 +301,7 @@ struct dpu_format {
* @plane_pitch: pitch of each plane
*/
struct dpu_hw_fmt_layout {
- const struct dpu_format *format;
+ const struct msm_format *format;
uint32_t num_planes;
uint32_t width;
uint32_t height;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 1363dcc72a6d..46b7b00e6701 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -205,7 +205,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
* Setup source pixel format, flip,
*/
static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, u32 flags)
+ const struct msm_format *fmt, u32 flags)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
@@ -246,14 +246,14 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
chroma_samp = CHROMA_H2V1;
}
- src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
- (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
- (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
+ src_format = (chroma_samp << 23) | (fmt->fetch_type << 19) |
+ (fmt->bpc_a << 6) | (fmt->bpc_r_cr << 4) |
+ (fmt->bpc_b_cb << 2) | (fmt->bpc_g_y << 0);
if (flags & DPU_SSPP_ROT_90)
src_format |= BIT(11); /* ROT90 */
- if (fmt->alpha_enable && fmt->fetch_planes == MDP_PLANE_INTERLEAVED)
+ if (fmt->alpha_enable && fmt->fetch_type == MDP_PLANE_INTERLEAVED)
src_format |= BIT(8); /* SRCC3_EN */
if (flags & DPU_SSPP_SOLID_FILL)
@@ -266,10 +266,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
(fmt->unpack_align_msb << 18) |
((fmt->bpp - 1) << 9);
- if (!DPU_FORMAT_IS_LINEAR(fmt)) {
- if (DPU_FORMAT_IS_UBWC(fmt))
+ if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
+ if (MSM_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
- src_format |= (fmt->base.fetch_mode & 3) << 30; /*FRAME_FORMAT */
+ src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
DPU_FETCH_CONFIG_RESET_VALUE |
ctx->ubwc->highest_bank_bit << 18);
@@ -294,7 +294,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
break;
case UBWC_4_0:
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
- DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
+ MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
break;
}
}
@@ -302,20 +302,20 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
opmode |= MDSS_MDP_OP_PE_OVERRIDE;
/* if this is YUV pixel format, enable CSC */
- if (DPU_FORMAT_IS_YUV(fmt))
+ if (MSM_FORMAT_IS_YUV(fmt))
src_format |= BIT(15);
- if (DPU_FORMAT_IS_DX(fmt))
+ if (MSM_FORMAT_IS_DX(fmt))
src_format |= BIT(14);
/* update scaler opmode, if appropriate */
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
- DPU_FORMAT_IS_YUV(fmt));
+ MSM_FORMAT_IS_YUV(fmt));
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
_sspp_setup_csc10_opmode(ctx,
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
- DPU_FORMAT_IS_YUV(fmt));
+ MSM_FORMAT_IS_YUV(fmt));
DPU_REG_WRITE(c, format_off, src_format);
DPU_REG_WRITE(c, unpack_pat_off, unpack);
@@ -384,7 +384,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
- const struct dpu_format *format)
+ const struct msm_format *format)
{
if (!ctx || !scaler3_cfg)
return;
@@ -564,7 +564,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
}
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index f93969fddb22..dd23fbfcd904 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -198,7 +198,7 @@ struct dpu_hw_sspp_ops {
* @flags: Extra flags for format config
*/
void (*setup_format)(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, u32 flags);
+ const struct msm_format *fmt, u32 flags);
/**
* setup_rects - setup pipe ROI rectangles
@@ -294,7 +294,7 @@ struct dpu_hw_sspp_ops {
*/
void (*setup_scaler)(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
- const struct dpu_format *format);
+ const struct msm_format *format);
/**
* get_scaler_ver - get scaler h/w version
@@ -309,7 +309,7 @@ struct dpu_hw_sspp_ops {
* @enable: whether the CDP should be enabled for this pipe
*/
void (*setup_cdp)(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable);
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 18b16b2d2bf5..602fc5345573 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -282,7 +282,7 @@ static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c,
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
u32 scaler_offset, u32 scaler_version,
- const struct dpu_format *format)
+ const struct msm_format *format)
{
u32 op_mode = 0;
u32 phase_init, preload, src_y_rgb, src_uv, dst;
@@ -293,7 +293,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
op_mode |= BIT(0);
op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
- if (format && DPU_FORMAT_IS_YUV(format)) {
+ if (format && MSM_FORMAT_IS_YUV(format)) {
op_mode |= BIT(12);
op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
}
@@ -367,7 +367,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
end:
- if (format && !DPU_FORMAT_IS_DX(format))
+ if (format && !MSM_FORMAT_IS_DX(format))
op_mode |= BIT(14);
if (format && format->alpha_enable) {
@@ -532,16 +532,16 @@ int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
#define CDP_PRELOAD_AHEAD_64 BIT(3)
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
- const struct dpu_format *fmt, bool enable)
+ const struct msm_format *fmt, bool enable)
{
u32 cdp_cntl = CDP_PRELOAD_AHEAD_64;
if (enable)
cdp_cntl |= CDP_ENABLE;
- if (DPU_FORMAT_IS_UBWC(fmt))
+ if (MSM_FORMAT_IS_UBWC(fmt))
cdp_cntl |= CDP_UBWC_META_ENABLE;
- if (DPU_FORMAT_IS_UBWC(fmt) ||
- DPU_FORMAT_IS_TILE(fmt))
+ if (MSM_FORMAT_IS_UBWC(fmt) ||
+ MSM_FORMAT_IS_TILE(fmt))
cdp_cntl |= CDP_TILE_AMORTIZE_ENABLE;
DPU_REG_WRITE(c, offset, cdp_cntl);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 4bea139081bc..a84519f132cf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -338,7 +338,7 @@ void *dpu_hw_util_get_dir(void);
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
u32 scaler_offset, u32 scaler_version,
- const struct dpu_format *format);
+ const struct msm_format *format);
u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
u32 scaler_offset);
@@ -348,7 +348,7 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
const struct dpu_csc_cfg *data, bool csc10);
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
- const struct dpu_format *fmt, bool enable);
+ const struct msm_format *fmt, bool enable);
u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
u32 total_fl);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 9668fb97c047..36dc57465958 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -65,7 +65,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
struct dpu_hw_wb_cfg *data)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
- const struct dpu_format *fmt = data->dest.format;
+ const struct msm_format *fmt = data->dest.format;
u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
u32 write_config = 0;
u32 opmode = 0;
@@ -74,13 +74,13 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
chroma_samp = fmt->chroma_sample;
dst_format = (chroma_samp << 23) |
- (fmt->fetch_planes << 19) |
- (fmt->bits[C3_ALPHA] << 6) |
- (fmt->bits[C2_R_Cr] << 4) |
- (fmt->bits[C1_B_Cb] << 2) |
- (fmt->bits[C0_G_Y] << 0);
+ (fmt->fetch_type << 19) |
+ (fmt->bpc_a << 6) |
+ (fmt->bpc_r_cr << 4) |
+ (fmt->bpc_b_cb << 2) |
+ (fmt->bpc_g_y << 0);
- if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
+ if (fmt->bpc_a || fmt->alpha_enable) {
dst_format |= BIT(8); /* DSTC3_EN */
if (!fmt->alpha_enable ||
!(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA)))
@@ -144,7 +144,7 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
}
static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable)
{
if (!ctx)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
index 88792f450a92..e8ab131d50be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
@@ -46,7 +46,7 @@ struct dpu_hw_wb_ops {
struct dpu_hw_qos_cfg *cfg);
void (*setup_cdp)(struct dpu_hw_wb *ctx,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable);
bool (*setup_clk_force_ctrl)(struct dpu_hw_wb *ctx,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index aa505b1a9f3b..5c0062d97d45 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -114,7 +114,7 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
* Prefill BW Equation: line src bytes * line_time
*/
static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const struct drm_display_mode *mode,
struct dpu_sw_pipe_cfg *pipe_cfg)
{
@@ -196,7 +196,7 @@ static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode,
static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
enum dpu_qos_lut_usage lut_usage,
- const struct dpu_format *fmt, u32 src_width)
+ const struct msm_format *fmt, u32 src_width)
{
struct dpu_plane *pdpu;
u32 fixed_buff_size;
@@ -215,7 +215,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
/* FIXME: in multirect case account for the src_width of all the planes */
- if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
+ if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
if (fmt->chroma_sample == CHROMA_420) {
/* NV12 */
total_fl = (fixed_buff_size / 2) /
@@ -237,7 +237,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
pipe->sspp->idx - SSPP_VIG0,
- (char *)&fmt->base.pixel_format,
+ (char *)&fmt->pixel_format,
src_width, total_fl);
return total_fl;
@@ -252,7 +252,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
*/
static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
+ const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_hw_qos_cfg cfg;
@@ -261,7 +261,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
if (!pdpu->is_rt_pipe) {
lut_usage = DPU_QOS_LUT_USAGE_NRT;
} else {
- if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
+ if (fmt && MSM_FORMAT_IS_LINEAR(fmt))
lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
else
lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
@@ -285,24 +285,24 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
pdpu->is_rt_pipe);
trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
- (fmt) ? fmt->base.pixel_format : 0,
+ (fmt) ? fmt->pixel_format : 0,
pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage);
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
pdpu->pipe - SSPP_VIG0,
- fmt ? (char *)&fmt->base.pixel_format : NULL,
+ fmt ? (char *)&fmt->pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, cfg.creq_lut);
trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
- (fmt) ? fmt->base.pixel_format : 0,
- (fmt) ? fmt->base.fetch_mode : 0,
+ (fmt) ? fmt->pixel_format : 0,
+ (fmt) ? fmt->fetch_mode : 0,
cfg.danger_lut,
cfg.safe_lut);
DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
pdpu->pipe - SSPP_VIG0,
- fmt ? (char *)&fmt->base.pixel_format : NULL,
- fmt ? fmt->base.fetch_mode : -1,
+ fmt ? (char *)&fmt->pixel_format : NULL,
+ fmt ? fmt->fetch_mode : -1,
cfg.danger_lut,
cfg.safe_lut);
@@ -426,7 +426,7 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
unsigned int rotation)
{
@@ -479,7 +479,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
}
}
- if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
+ if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
&& (src_w == dst_w))
return;
@@ -542,11 +542,11 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {
};
static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt)
+ const struct msm_format *fmt)
{
const struct dpu_csc_cfg *csc_ptr;
- if (!DPU_FORMAT_IS_YUV(fmt))
+ if (!MSM_FORMAT_IS_YUV(fmt))
return NULL;
if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)
@@ -558,12 +558,12 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
}
static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, bool color_fill,
+ const struct msm_format *fmt, bool color_fill,
struct dpu_sw_pipe_cfg *pipe_cfg,
unsigned int rotation)
{
struct dpu_hw_sspp *pipe_hw = pipe->sspp;
- const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
+ const struct drm_format_info *info = drm_format_info(fmt->pixel_format);
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
u32 src_width = drm_rect_width(&pipe_cfg->src_rect);
@@ -609,7 +609,7 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
struct dpu_sw_pipe *pipe,
struct drm_rect *dst_rect,
u32 fill_color,
- const struct dpu_format *fmt)
+ const struct msm_format *fmt)
{
struct dpu_sw_pipe_cfg pipe_cfg;
@@ -647,7 +647,7 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
uint32_t color, uint32_t alpha)
{
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
const struct drm_plane *plane = &pdpu->base;
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
@@ -736,7 +736,7 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane,
static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
const struct dpu_sspp_sub_blks *sblk,
- struct drm_rect src, const struct dpu_format *fmt)
+ struct drm_rect src, const struct msm_format *fmt)
{
size_t num_formats;
const u32 *supported_formats;
@@ -755,8 +755,8 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
supported_formats = sblk->rotation_cfg->rot_format_list;
num_formats = sblk->rotation_cfg->rot_num_formats;
- if (!DPU_FORMAT_IS_UBWC(fmt) ||
- !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats))
+ if (!MSM_FORMAT_IS_UBWC(fmt) ||
+ !dpu_find_format(fmt->pixel_format, supported_formats, num_formats))
return -EINVAL;
return 0;
@@ -765,15 +765,15 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *pipe_cfg,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const struct drm_display_mode *mode)
{
uint32_t min_src_size;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
- min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
+ min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
- if (DPU_FORMAT_IS_YUV(fmt) &&
+ if (MSM_FORMAT_IS_YUV(fmt) &&
(!(pipe->sspp->cap->features & DPU_SSPP_SCALER) ||
!(pipe->sspp->cap->features & DPU_SSPP_CSC_ANY))) {
DPU_DEBUG_PLANE(pdpu,
@@ -790,7 +790,7 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
}
/* valid yuv image */
- if (DPU_FORMAT_IS_YUV(fmt) &&
+ if (MSM_FORMAT_IS_YUV(fmt) &&
(pipe_cfg->src_rect.x1 & 0x1 ||
pipe_cfg->src_rect.y1 & 0x1 ||
drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
@@ -830,7 +830,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
struct dpu_sw_pipe *pipe = &pstate->pipe;
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
const struct drm_crtc_state *crtc_state = NULL;
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct drm_rect fb_rect = { 0 };
@@ -890,7 +890,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -E2BIG;
}
- fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
+ fmt = msm_framebuffer_format(new_plane_state->fb);
max_linewidth = pdpu->catalog->caps->max_linewidth;
@@ -902,7 +902,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
* full width is more than max_linewidth, thus each rect is
* wider than allowed.
*/
- if (DPU_FORMAT_IS_UBWC(fmt) &&
+ if (MSM_FORMAT_IS_UBWC(fmt) &&
drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n",
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
@@ -919,7 +919,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) ||
(!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) &&
!test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) ||
- DPU_FORMAT_IS_YUV(fmt)) {
+ MSM_FORMAT_IS_YUV(fmt)) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
return -E2BIG;
@@ -977,8 +977,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
{
- const struct dpu_format *format =
- to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(pdpu->base.state->fb);
const struct dpu_csc_cfg *csc_ptr;
if (!pipe->sspp || !pipe->sspp->ops.setup_csc)
@@ -1049,7 +1049,7 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error)
static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *pipe_cfg,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
int frame_rate,
struct dpu_hw_fmt_layout *layout)
{
@@ -1127,8 +1127,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
bool is_rt_pipe;
- const struct dpu_format *fmt =
- to_dpu_format(msm_framebuffer_format(fb));
+ const struct msm_format *fmt =
+ msm_framebuffer_format(fb);
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
@@ -1152,7 +1152,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
crtc->base.id, DRM_RECT_ARG(&state->dst),
- (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
+ (char *)&fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
drm_mode_vrefresh(&crtc->mode),
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 5e5c31b44a8a..f7bec46c386d 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -182,8 +182,8 @@ static void blend_setup(struct drm_crtc *crtc)
enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
int idx = idxs[pipe_id];
if (idx > 0) {
- const struct mdp_format *format =
- to_mdp_format(msm_framebuffer_format(plane->state->fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(plane->state->fb);
alpha[idx-1] = format->alpha_enable;
}
}
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index cebe20c82a54..0bae90d3f21e 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -218,7 +218,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
struct mdp4_kms *mdp4_kms = get_kms(plane);
enum mdp4_pipe pipe = mdp4_plane->pipe;
- const struct mdp_format *format;
+ const struct msm_format *format;
uint32_t op_mode = 0;
uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
@@ -241,7 +241,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
fb->base.id, src_x, src_y, src_w, src_h,
crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
- format = to_mdp_format(msm_framebuffer_format(fb));
+ format = msm_framebuffer_format(fb);
if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
DRM_DEV_ERROR(dev->dev, "Width down scaling exceeds limits!\n");
@@ -267,7 +267,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
- if (MDP_FORMAT_IS_YUV(format)) {
+ if (MSM_FORMAT_IS_YUV(format)) {
if (crtc_w > src_w)
sel_unit = SCALE_PIXEL_RPT;
else if (crtc_w <= (src_w / 4))
@@ -283,7 +283,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEY_EN;
- if (MDP_FORMAT_IS_YUV(format)) {
+ if (MSM_FORMAT_IS_YUV(format)) {
if (crtc_h > src_h)
sel_unit = SCALE_PIXEL_RPT;
@@ -316,11 +316,11 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
- MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
- MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
- MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
+ MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
+ MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
+ MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
- MDP4_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
+ MDP4_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
@@ -328,12 +328,12 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
- MDP4_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
- MDP4_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
- MDP4_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
- MDP4_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
+ MDP4_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
+ MDP4_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
+ MDP4_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
+ MDP4_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
- if (MDP_FORMAT_IS_YUV(format)) {
+ if (MSM_FORMAT_IS_YUV(format)) {
struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);
op_mode |= MDP4_PIPE_OP_MODE_SRC_YCBCR;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 4a3db2ea1689..0f653e62b4a0 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -216,7 +216,7 @@ static void blend_setup(struct drm_crtc *crtc)
struct mdp5_kms *mdp5_kms = get_kms(crtc);
struct drm_plane *plane;
struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
- const struct mdp_format *format;
+ const struct msm_format *format;
struct mdp5_hw_mixer *mixer = pipeline->mixer;
uint32_t lm = mixer->lm;
struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
@@ -274,7 +274,7 @@ static void blend_setup(struct drm_crtc *crtc)
ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
DBG("Border Color is enabled");
} else if (plane_cnt) {
- format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
+ format = msm_framebuffer_format(pstates[STAGE_BASE]->base.fb);
if (format->alpha_enable)
bg_alpha_enabled = true;
@@ -285,8 +285,7 @@ static void blend_setup(struct drm_crtc *crtc)
if (!pstates[i])
continue;
- format = to_mdp_format(
- msm_framebuffer_format(pstates[i]->base.fb));
+ format = msm_framebuffer_format(pstates[i]->base.fb);
plane = pstates[i]->base.plane;
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index e40f6d1d5433..3b7c3eac8eda 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -228,12 +228,12 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
if (plane_enabled(state)) {
unsigned int rotation;
- const struct mdp_format *format;
+ const struct msm_format *format;
struct mdp5_kms *mdp5_kms = get_kms(plane);
uint32_t blkcfg = 0;
- format = to_mdp_format(msm_framebuffer_format(state->fb));
- if (MDP_FORMAT_IS_YUV(format))
+ format = msm_framebuffer_format(state->fb);
+ if (MSM_FORMAT_IS_YUV(format))
caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
if (((state->src_w >> 16) != state->crtc_w) ||
@@ -268,8 +268,8 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
new_hwpipe = true;
if (mdp5_kms->smp) {
- const struct mdp_format *format =
- to_mdp_format(msm_framebuffer_format(state->fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(state->fb);
blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
state->src_w >> 16, false);
@@ -630,11 +630,11 @@ static int calc_scaley_steps(struct drm_plane *plane,
return 0;
}
-static uint32_t get_scale_config(const struct mdp_format *format,
+static uint32_t get_scale_config(const struct msm_format *format,
uint32_t src, uint32_t dst, bool horz)
{
- const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
- bool yuv = MDP_FORMAT_IS_YUV(format);
+ const struct drm_format_info *info = drm_format_info(format->pixel_format);
+ bool yuv = MSM_FORMAT_IS_YUV(format);
bool scaling = yuv ? true : (src != dst);
uint32_t sub;
uint32_t ya_filter, uv_filter;
@@ -661,12 +661,12 @@ static uint32_t get_scale_config(const struct mdp_format *format,
COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
}
-static void calc_pixel_ext(const struct mdp_format *format,
+static void calc_pixel_ext(const struct msm_format *format,
uint32_t src, uint32_t dst, uint32_t phase_step[2],
int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
bool horz)
{
- bool scaling = MDP_FORMAT_IS_YUV(format) ? true : (src != dst);
+ bool scaling = MSM_FORMAT_IS_YUV(format) ? true : (src != dst);
int i;
/*
@@ -684,11 +684,11 @@ static void calc_pixel_ext(const struct mdp_format *format,
}
static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
- const struct mdp_format *format,
+ const struct msm_format *format,
uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
{
- const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
+ const struct drm_format_info *info = drm_format_info(format->pixel_format);
uint32_t lr, tb, req;
int i;
@@ -696,7 +696,7 @@ static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
uint32_t roi_w = src_w;
uint32_t roi_h = src_h;
- if (MDP_FORMAT_IS_YUV(format) && i == COMP_1_2) {
+ if (MSM_FORMAT_IS_YUV(format) && i == COMP_1_2) {
roi_w /= info->hsub;
roi_h /= info->vsub;
}
@@ -770,8 +770,8 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
{
enum mdp5_pipe pipe = hwpipe->pipe;
bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
- const struct mdp_format *format =
- to_mdp_format(msm_framebuffer_format(fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(fb);
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
@@ -795,21 +795,21 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
- MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
- MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
- MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
+ MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
+ MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
+ MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
- MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
+ MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
- MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
- MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
- MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
- MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
+ MDP5_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
+ MDP5_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
+ MDP5_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
+ MDP5_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
(hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
@@ -842,7 +842,7 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
}
if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
- if (MDP_FORMAT_IS_YUV(format))
+ if (MSM_FORMAT_IS_YUV(format))
csc_enable(mdp5_kms, pipe,
mdp_get_default_csc_cfg(CSC_YUV2RGB));
else
@@ -861,7 +861,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
struct mdp5_kms *mdp5_kms = get_kms(plane);
enum mdp5_pipe pipe = hwpipe->pipe;
struct mdp5_hw_pipe *right_hwpipe;
- const struct mdp_format *format;
+ const struct msm_format *format;
uint32_t nplanes, config = 0;
struct phase_step step = { { 0 } };
struct pixel_ext pe = { { 0 } };
@@ -882,8 +882,8 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
if (WARN_ON(nplanes > pipe2nclients(pipe)))
return -EINVAL;
- format = to_mdp_format(msm_framebuffer_format(fb));
- pix_format = format->base.pixel_format;
+ format = msm_framebuffer_format(fb);
+ pix_format = format->pixel_format;
src_x = src->x1;
src_y = src->y1;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
index 8b59562e29e2..4a00333a7565 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
@@ -114,10 +114,10 @@ static void set_fifo_thresholds(struct mdp5_smp *smp,
* presumably happens during the dma from scanout buffer).
*/
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
- const struct mdp_format *format,
+ const struct msm_format *format,
u32 width, bool hdecim)
{
- const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
+ const struct drm_format_info *info = drm_format_info(format->pixel_format);
struct mdp5_kms *mdp5_kms = get_kms(smp);
int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg);
int i, hsub, nplanes, nlines;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
index d8b6a11413d9..ecad04e7ee92 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
@@ -72,7 +72,7 @@ struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms,
void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p);
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
- const struct mdp_format *format,
+ const struct msm_format *format,
u32 width, bool hdecim);
int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state,
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 30919641c813..5fc55f41e74f 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -63,26 +63,24 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
};
#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
- .base = { \
- .pixel_format = DRM_FORMAT_ ## name, \
- .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
- }, \
+ .pixel_format = DRM_FORMAT_ ## name, \
.bpc_a = BPC ## a ## A, \
- .bpc_r = BPC ## r, \
- .bpc_g = BPC ## g, \
- .bpc_b = BPC ## b, \
- .unpack = { e0, e1, e2, e3 }, \
+ .bpc_r_cr = BPC ## r, \
+ .bpc_g_y = BPC ## g, \
+ .bpc_b_cb = BPC ## b, \
+ .element = { e0, e1, e2, e3 }, \
+ .fetch_type = fp, \
+ .chroma_sample = cs, \
.alpha_enable = alpha, \
.unpack_tight = tight, \
- .cpp = c, \
.unpack_count = cnt, \
- .fetch_type = fp, \
- .chroma_sample = cs, \
+ .bpp = c, \
+ .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
}
#define BPC0A 0
-static const struct mdp_format formats[] = {
+static const struct msm_format formats[] = {
/* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
@@ -141,9 +139,9 @@ const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
{
int i;
for (i = 0; i < ARRAY_SIZE(formats); i++) {
- const struct mdp_format *f = &formats[i];
- if (f->base.pixel_format == format)
- return &f->base;
+ const struct msm_format *f = &formats[i];
+ if (f->pixel_format == format)
+ return f;
}
return NULL;
}
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h b/drivers/gpu/drm/msm/disp/mdp_kms.h
index ffa71777dada..bb3bfb9d3bf4 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -77,19 +77,6 @@ void mdp_irq_update(struct mdp_kms *mdp_kms);
* pixel format helpers:
*/
-struct mdp_format {
- struct msm_format base;
- enum mdp_bpc bpc_r, bpc_g, bpc_b;
- enum mdp_bpc_alpha bpc_a;
- uint8_t unpack[4];
- bool alpha_enable, unpack_tight;
- uint8_t cpp, unpack_count;
- enum mdp_fetch_type fetch_type;
- enum mdp_chroma_samp_type chroma_sample;
-};
-#define to_mdp_format(x) container_of(x, struct mdp_format, base)
-#define MDP_FORMAT_IS_YUV(mdp_format) (MSM_FORMAT_IS_YUV(&(mdp_format)->base))
-
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
/* MDP capabilities */
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index b37546ffb0c3..c8c465c36487 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -261,10 +261,38 @@ enum msm_format_flags {
#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
+/**
+ * struct msm_format: defines the format configuration
+ * @pixel_format: format fourcc
+ * @element: element color ordering
+ * @fetch_type: how the color components are packed in pixel format
+ * @chroma_sample: chroma sub-samplng type
+ * @alpha_enable: whether the format has an alpha channel
+ * @unpack_tight: whether to use tight or loose unpack
+ * @unpack_align_msb: unpack aligned to LSB or MSB
+ * @unpack_count: number of the components to unpack
+ * @bpp: bytes per pixel
+ * @flags: usage bit flags
+ * @num_planes: number of planes (including meta data planes)
+ * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
+ * @tile_height: format tile height
+ */
struct msm_format {
uint32_t pixel_format;
+ enum mdp_bpc bpc_g_y, bpc_b_cb, bpc_r_cr;
+ enum mdp_bpc_alpha bpc_a;
+ u8 element[4];
+ enum mdp_fetch_type fetch_type;
+ enum mdp_chroma_samp_type chroma_sample;
+ bool alpha_enable;
+ u8 unpack_tight;
+ u8 unpack_align_msb;
+ u8 unpack_count;
+ u8 bpp;
unsigned long flags;
+ u8 num_planes;
enum mdp_fetch_mode fetch_mode;
+ u16 tile_height;
};
#define MSM_FORMAT_IS_YUV(X) ((X)->flags & MSM_FORMAT_FLAG_YUV)
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 08/12] drm/msm: convert msm_format::unpack_tight to the flag
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
` (6 preceding siblings ...)
2023-12-02 21:40 ` [PATCH 07/12] drm/msm: merge dpu_format and mdp_format in struct msm_format Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-11 21:02 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 09/12] drm/msm: convert msm_format::unpack_align_msb " Dmitry Baryshkov
` (3 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Instead of having a u8 or bool field unpack_tight, convert it to the
flag, this save space in the tables and allows us to handle all booleans
in the same way.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 22 +++------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 3 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 52 ++++++++++-----------
drivers/gpu/drm/msm/msm_drv.h | 4 +-
7 files changed, 41 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index ea9d5fb01000..419400311837 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -44,11 +44,10 @@ bp, flg, fm, np) \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -66,11 +65,10 @@ alpha, bp, flg, fm, np, th) \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -89,11 +87,10 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -110,11 +107,10 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -132,11 +128,10 @@ flg, fm, np, th) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -153,7 +148,6 @@ flg, fm, np, th) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
- .unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -175,7 +169,6 @@ flg, fm, np, th) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 1, \
- .unpack_tight = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -198,11 +191,10 @@ flg, fm, np) \
.bpc_a = a, \
.chroma_sample = chroma, \
.unpack_align_msb = 0, \
- .unpack_tight = 1, \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -636,7 +628,7 @@ static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt)
if (fmt->pixel_format == DRM_FORMAT_NV12 ||
fmt->pixel_format == DRM_FORMAT_P010) {
if (MSM_FORMAT_IS_DX(fmt)) {
- if (fmt->unpack_tight)
+ if (fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT)
color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
else
color_fmt = COLOR_FMT_P010_UBWC;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 46b7b00e6701..f6c772df048b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -262,7 +262,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
(fmt->element[1] << 8) | (fmt->element[0] << 0);
src_format |= ((fmt->unpack_count - 1) << 12) |
- (fmt->unpack_tight << 17) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
(fmt->unpack_align_msb << 18) |
((fmt->bpp - 1) << 9);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 36dc57465958..12418256326d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -93,7 +93,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
(fmt->element[0] << 0);
dst_format |= (fmt->unpack_align_msb << 18) |
- (fmt->unpack_tight << 17) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
((fmt->unpack_count - 1) << 12) |
((fmt->bpp - 1) << 9);
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index 0bae90d3f21e..ef7e525c3bd2 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -325,7 +325,8 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
- COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
+ COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
+ MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
MDP4_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index 3b7c3eac8eda..cc0dc451dc2e 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -801,7 +801,8 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
- COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
+ COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
+ MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 5fc55f41e74f..b9f0b13d25d5 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -62,7 +62,7 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
},
};
-#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
+#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, c, cnt, fp, cs, yuv) { \
.pixel_format = DRM_FORMAT_ ## name, \
.bpc_a = BPC ## a ## A, \
.bpc_r_cr = BPC ## r, \
@@ -72,65 +72,65 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
.fetch_type = fp, \
.chroma_sample = cs, \
.alpha_enable = alpha, \
- .unpack_tight = tight, \
.unpack_count = cnt, \
.bpp = c, \
- .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (yuv ? MSM_FORMAT_FLAG_YUV : 0), \
}
#define BPC0A 0
static const struct msm_format formats[] = {
- /* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
- FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
+ /* name a r g b e0 e1 e2 e3 alpha cpp cnt ... */
+ FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
+ FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
+ FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
+ FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
+ FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
+ FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
+ FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
+ FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, 4, 4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
+ FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, 3, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 3, 3,
+ FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, 3, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB565, 0, 5, 6, 5, 1, 0, 2, 0, false, true, 2, 3,
+ FMT(RGB565, 0, 5, 6, 5, 1, 0, 2, 0, false, 2, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR565, 0, 5, 6, 5, 2, 0, 1, 0, false, true, 2, 3,
+ FMT(BGR565, 0, 5, 6, 5, 2, 0, 1, 0, false, 2, 3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
/* --- RGB formats above / YUV formats below this line --- */
/* 2 plane YUV */
- FMT(NV12, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 2, 2,
+ FMT(NV12, 0, 8, 8, 8, 1, 2, 0, 0, false, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV21, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 2, 2,
+ FMT(NV21, 0, 8, 8, 8, 2, 1, 0, 0, false, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV16, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 2, 2,
+ FMT(NV16, 0, 8, 8, 8, 1, 2, 0, 0, false, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
- FMT(NV61, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 2, 2,
+ FMT(NV61, 0, 8, 8, 8, 2, 1, 0, 0, false, 2, 2,
MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
/* 1 plane YUV */
- FMT(VYUY, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 2, 4,
+ FMT(VYUY, 0, 8, 8, 8, 2, 0, 1, 0, false, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(UYVY, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 2, 4,
+ FMT(UYVY, 0, 8, 8, 8, 1, 0, 2, 0, false, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YUYV, 0, 8, 8, 8, 0, 1, 0, 2, false, true, 2, 4,
+ FMT(YUYV, 0, 8, 8, 8, 0, 1, 0, 2, false, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YVYU, 0, 8, 8, 8, 0, 2, 0, 1, false, true, 2, 4,
+ FMT(YVYU, 0, 8, 8, 8, 0, 2, 0, 1, false, 2, 4,
MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
/* 3 plane YUV */
- FMT(YUV420, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 1, 1,
+ FMT(YUV420, 0, 8, 8, 8, 2, 1, 0, 0, false, 1, 1,
MDP_PLANE_PLANAR, CHROMA_420, true),
- FMT(YVU420, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 1, 1,
+ FMT(YVU420, 0, 8, 8, 8, 1, 2, 0, 0, false, 1, 1,
MDP_PLANE_PLANAR, CHROMA_420, true),
};
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index c8c465c36487..61a4587382b5 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -255,11 +255,13 @@ enum msm_format_flags {
MSM_FORMAT_FLAG_YUV_BIT,
MSM_FORMAT_FLAG_DX_BIT,
MSM_FORMAT_FLAG_COMPRESSED_BIT,
+ MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT,
};
#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
+#define MSM_FORMAT_FLAG_UNPACK_TIGHT BIT(MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT)
/**
* struct msm_format: defines the format configuration
@@ -268,7 +270,6 @@ enum msm_format_flags {
* @fetch_type: how the color components are packed in pixel format
* @chroma_sample: chroma sub-samplng type
* @alpha_enable: whether the format has an alpha channel
- * @unpack_tight: whether to use tight or loose unpack
* @unpack_align_msb: unpack aligned to LSB or MSB
* @unpack_count: number of the components to unpack
* @bpp: bytes per pixel
@@ -285,7 +286,6 @@ struct msm_format {
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
bool alpha_enable;
- u8 unpack_tight;
u8 unpack_align_msb;
u8 unpack_count;
u8 bpp;
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 09/12] drm/msm: convert msm_format::unpack_align_msb to the flag
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
` (7 preceding siblings ...)
2023-12-02 21:40 ` [PATCH 08/12] drm/msm: convert msm_format::unpack_tight to the flag Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-11 21:13 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 10/12] drm/msm: convert msm_format::alpha_enable " Dmitry Baryshkov
` (2 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Instead of having a u8 or bool field unpack_align_msb, convert it to the
flag, this save space in the tables and allows us to handle all booleans
in the same way.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 12 ++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
drivers/gpu/drm/msm/msm_drv.h | 4 ++--
4 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 419400311837..baf0fd67bf42 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -43,7 +43,6 @@ bp, flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
- .unpack_align_msb = 0, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
@@ -64,7 +63,6 @@ alpha, bp, flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
- .unpack_align_msb = 0, \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
@@ -86,7 +84,6 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
@@ -106,7 +103,6 @@ alpha, chroma, count, bp, flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -127,7 +123,6 @@ flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
@@ -147,11 +142,10 @@ flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -168,11 +162,10 @@ flg, fm, np, th) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 1, \
.unpack_count = 2, \
.bpp = 2, \
.fetch_mode = fm, \
- .flags = flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -190,7 +183,6 @@ flg, fm, np) \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = chroma, \
- .unpack_align_msb = 0, \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index f6c772df048b..c1ff70d80bdb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -263,7 +263,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
(fmt->element[1] << 8) | (fmt->element[0] << 0);
src_format |= ((fmt->unpack_count - 1) << 12) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
- (fmt->unpack_align_msb << 18) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->bpp - 1) << 9);
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 12418256326d..1eadaabc8b25 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -92,7 +92,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
(fmt->element[1] << 8) |
(fmt->element[0] << 0);
- dst_format |= (fmt->unpack_align_msb << 18) |
+ dst_format |= ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
((fmt->unpack_count - 1) << 12) |
((fmt->bpp - 1) << 9);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 61a4587382b5..7ea24d776a50 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -256,12 +256,14 @@ enum msm_format_flags {
MSM_FORMAT_FLAG_DX_BIT,
MSM_FORMAT_FLAG_COMPRESSED_BIT,
MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT,
+ MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT,
};
#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
#define MSM_FORMAT_FLAG_UNPACK_TIGHT BIT(MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT)
+#define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
/**
* struct msm_format: defines the format configuration
@@ -270,7 +272,6 @@ enum msm_format_flags {
* @fetch_type: how the color components are packed in pixel format
* @chroma_sample: chroma sub-samplng type
* @alpha_enable: whether the format has an alpha channel
- * @unpack_align_msb: unpack aligned to LSB or MSB
* @unpack_count: number of the components to unpack
* @bpp: bytes per pixel
* @flags: usage bit flags
@@ -286,7 +287,6 @@ struct msm_format {
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
bool alpha_enable;
- u8 unpack_align_msb;
u8 unpack_count;
u8 bpp;
unsigned long flags;
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 10/12] drm/msm: convert msm_format::alpha_enable to the flag
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
` (8 preceding siblings ...)
2023-12-02 21:40 ` [PATCH 09/12] drm/msm: convert msm_format::unpack_align_msb " Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-11 21:20 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 11/12] drm/msm: merge dpu format database to MDP formats Dmitry Baryshkov
2023-12-02 21:40 ` [PATCH 12/12] drm/msm: drop msm_kms_funcs::get_format() callback Dmitry Baryshkov
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Instead of having a bool field alpha_enable, convert it to the
flag, this save space in the tables and allows us to handle all booleans
in the same way.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 ++++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 24 ++++++++++-----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 7 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 4 ++--
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 3 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 9 ++++----
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 ++-
drivers/gpu/drm/msm/disp/mdp_format.c | 2 +-
drivers/gpu/drm/msm/msm_drv.h | 4 ++--
11 files changed, 40 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 9041b0d71b25..201010038660 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -342,7 +342,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
/* default to opaque blending */
if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
- !format->alpha_enable) {
+ !(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE)) {
blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
DPU_BLEND_BG_ALPHA_BG_CONST;
} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
@@ -373,8 +373,8 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
lm->ops.setup_blend_config(lm, pstate->stage,
fg_alpha, bg_alpha, blend_op);
- DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
- &format->pixel_format, format->alpha_enable, blend_op);
+ DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%lu blend_op:0x%x\n",
+ &format->pixel_format, format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -472,7 +472,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
format = msm_framebuffer_format(pstate->base.fb);
- if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
+ if (pstate->stage == DPU_STAGE_BASE &&
+ format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE)
bg_alpha_enable = true;
set_bit(pstate->pipe.sspp->idx, fetch_active);
@@ -495,7 +496,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
- if (bg_alpha_enable && !format->alpha_enable)
+ if (bg_alpha_enable &&
+ !(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE))
mixer[lm_idx].mixer_op_mode = 0;
else
mixer[lm_idx].mixer_op_mode |=
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index baf0fd67bf42..de9e93cb42c4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -36,7 +36,6 @@ bp, flg, fm, np) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
@@ -46,7 +45,9 @@ bp, flg, fm, np) \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
+ flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -56,7 +57,6 @@ alpha, bp, flg, fm, np, th) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3) }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
@@ -66,7 +66,9 @@ alpha, bp, flg, fm, np, th) \
.unpack_count = uc, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
+ flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -77,7 +79,6 @@ alpha, chroma, count, bp, flg, fm, np) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
.element = { (e0), (e1), (e2), (e3)}, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
@@ -87,7 +88,9 @@ alpha, chroma, count, bp, flg, fm, np) \
.unpack_count = count, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
+ flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
@@ -96,7 +99,6 @@ alpha, chroma, count, bp, flg, fm, np) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
@@ -116,7 +118,6 @@ flg, fm, np, th) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
@@ -135,7 +136,6 @@ flg, fm, np, th) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
@@ -155,7 +155,6 @@ flg, fm, np, th) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = 0, \
.element = { (e0), (e1), 0, 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
@@ -176,7 +175,6 @@ flg, fm, np) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_PLANAR, \
- .alpha_enable = alpha, \
.element = { (e0), (e1), (e2), 0 }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
@@ -186,7 +184,9 @@ flg, fm, np) \
.unpack_count = 1, \
.bpp = bp, \
.fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
+ flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT \
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index c1ff70d80bdb..4903dd8d6f36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -253,7 +253,8 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
if (flags & DPU_SSPP_ROT_90)
src_format |= BIT(11); /* ROT90 */
- if (fmt->alpha_enable && fmt->fetch_type == MDP_PLANE_INTERLEAVED)
+ if (fmt->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE &&
+ fmt->fetch_type == MDP_PLANE_INTERLEAVED)
src_format |= BIT(8); /* SRCC3_EN */
if (flags & DPU_SSPP_SOLID_FILL)
@@ -275,14 +276,14 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
ctx->ubwc->highest_bank_bit << 18);
switch (ctx->ubwc->ubwc_enc_version) {
case UBWC_1_0:
- fast_clear = fmt->alpha_enable ? BIT(31) : 0;
+ fast_clear = fmt->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE ? BIT(31) : 0;
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
BIT(8) |
(ctx->ubwc->highest_bank_bit << 4));
break;
case UBWC_2_0:
- fast_clear = fmt->alpha_enable ? BIT(31) : 0;
+ fast_clear = fmt->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE ? BIT(31) : 0;
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
fast_clear | (ctx->ubwc->ubwc_swizzle) |
(ctx->ubwc->highest_bank_bit << 4));
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 602fc5345573..08c530f9b1cb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -370,7 +370,8 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
if (format && !MSM_FORMAT_IS_DX(format))
op_mode |= BIT(14);
- if (format && format->alpha_enable) {
+ if (format &&
+ format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE) {
op_mode |= BIT(10);
if (scaler_version == 0x1002)
op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 1eadaabc8b25..97967fc623fb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -80,9 +80,9 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
(fmt->bpc_b_cb << 2) |
(fmt->bpc_g_y << 0);
- if (fmt->bpc_a || fmt->alpha_enable) {
+ if (fmt->bpc_a || fmt->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE) {
dst_format |= BIT(8); /* DSTC3_EN */
- if (!fmt->alpha_enable ||
+ if (!(fmt->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE) ||
!(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA)))
dst_format |= BIT(14); /* DST_ALPHA_X */
}
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index f7bec46c386d..2663c8793ec0 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -184,7 +184,7 @@ static void blend_setup(struct drm_crtc *crtc)
if (idx > 0) {
const struct msm_format *format =
msm_framebuffer_format(plane->state->fb);
- alpha[idx-1] = format->alpha_enable;
+ alpha[idx-1] = format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE;
}
}
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index ef7e525c3bd2..67c22e02f402 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -319,7 +319,8 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
- COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
+ COND(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE,
+ MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
MDP4_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 0f653e62b4a0..0332e66ed3cf 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -276,7 +276,7 @@ static void blend_setup(struct drm_crtc *crtc)
} else if (plane_cnt) {
format = msm_framebuffer_format(pstates[STAGE_BASE]->base.fb);
- if (format->alpha_enable)
+ if (format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE)
bg_alpha_enabled = true;
}
@@ -292,14 +292,15 @@ static void blend_setup(struct drm_crtc *crtc)
fg_alpha = pstates[i]->base.alpha >> 8;
bg_alpha = 0xFF - fg_alpha;
- if (!format->alpha_enable && bg_alpha_enabled)
+ if (!(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE) &&
+ bg_alpha_enabled)
mixer_op_mode = 0;
else
mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i);
DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
- if (format->alpha_enable &&
+ if (format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE &&
pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
@@ -311,7 +312,7 @@ static void blend_setup(struct drm_crtc *crtc)
} else {
blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
}
- } else if (format->alpha_enable &&
+ } else if (format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE &&
pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index cc0dc451dc2e..01797f3e6d8f 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -798,7 +798,8 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
- COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
+ COND(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE,
+ MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index b9f0b13d25d5..fa2a76a35106 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -71,10 +71,10 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
.element = { e0, e1, e2, e3 }, \
.fetch_type = fp, \
.chroma_sample = cs, \
- .alpha_enable = alpha, \
.unpack_count = cnt, \
.bpp = c, \
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0), \
(yuv ? MSM_FORMAT_FLAG_YUV : 0), \
}
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 7ea24d776a50..dea6d47854fe 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -257,6 +257,7 @@ enum msm_format_flags {
MSM_FORMAT_FLAG_COMPRESSED_BIT,
MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT,
MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT,
+ MSM_FORMAT_FLAG_ALPHA_ENABLE_BIT
};
#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
@@ -264,6 +265,7 @@ enum msm_format_flags {
#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
#define MSM_FORMAT_FLAG_UNPACK_TIGHT BIT(MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT)
#define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
+#define MSM_FORMAT_FLAG_ALPHA_ENABLE BIT(MSM_FORMAT_FLAG_ALPHA_ENABLE_BIT)
/**
* struct msm_format: defines the format configuration
@@ -271,7 +273,6 @@ enum msm_format_flags {
* @element: element color ordering
* @fetch_type: how the color components are packed in pixel format
* @chroma_sample: chroma sub-samplng type
- * @alpha_enable: whether the format has an alpha channel
* @unpack_count: number of the components to unpack
* @bpp: bytes per pixel
* @flags: usage bit flags
@@ -286,7 +287,6 @@ struct msm_format {
u8 element[4];
enum mdp_fetch_type fetch_type;
enum mdp_chroma_samp_type chroma_sample;
- bool alpha_enable;
u8 unpack_count;
u8 bpp;
unsigned long flags;
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 11/12] drm/msm: merge dpu format database to MDP formats
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
` (9 preceding siblings ...)
2023-12-02 21:40 ` [PATCH 10/12] drm/msm: convert msm_format::alpha_enable " Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-12 19:47 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 12/12] drm/msm: drop msm_kms_funcs::get_format() callback Dmitry Baryshkov
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Finally remove duplication between DPU and generic MDP code by merging
DPU format lists to the MDP format database.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 602 ------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 23 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 10 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 595 +++++++++++++++--
drivers/gpu/drm/msm/disp/mdp_kms.h | 2 -
drivers/gpu/drm/msm/msm_drv.h | 12 +
10 files changed, 549 insertions(+), 706 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 35aaead897e1..bd3ab2ab6515 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -267,7 +267,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
- fmt = dpu_get_dpu_format(fmt_fourcc);
+ fmt = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
intf_cfg.intf = phys_enc->hw_intf->idx;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index a400c44a1a71..cef6066c0d3e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -622,8 +622,8 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
- wb_cfg->dest.format = dpu_get_dpu_format_ext(
- format->pixel_format, job->fb->modifier);
+ wb_cfg->dest.format = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base,
+ format->pixel_format, job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
DPU_ERROR("failed to get format %x\n", format->pixel_format);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index de9e93cb42c4..dff2ff173d80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -11,186 +11,11 @@
#include "dpu_kms.h"
#include "dpu_formats.h"
-#define DPU_UBWC_META_MACRO_W_H 16
-#define DPU_UBWC_META_BLOCK_SIZE 256
#define DPU_UBWC_PLANE_SIZE_ALIGNMENT 4096
-#define DPU_TILE_HEIGHT_DEFAULT 1
-#define DPU_TILE_HEIGHT_TILED 4
-#define DPU_TILE_HEIGHT_UBWC 4
-#define DPU_TILE_HEIGHT_NV12 8
-
#define DPU_MAX_IMG_WIDTH 0x3FFF
#define DPU_MAX_IMG_HEIGHT 0x3FFF
-/*
- * DPU supported format packing, bpp, and other format
- * information.
- * DPU currently only supports interleaved RGB formats
- * UBWC support for a pixel format is indicated by the flag,
- * there is additional meta data plane for such formats
- */
-
-#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
-bp, flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_INTERLEAVED, \
- .element = { (e0), (e1), (e2), (e3) }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = CHROMA_FULL, \
- .unpack_count = uc, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
- (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
- flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
-alpha, bp, flg, fm, np, th) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_INTERLEAVED, \
- .element = { (e0), (e1), (e2), (e3) }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = CHROMA_FULL, \
- .unpack_count = uc, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
- (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
- flg, \
- .num_planes = np, \
- .tile_height = th \
-}
-
-
-#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
-alpha, chroma, count, bp, flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_INTERLEAVED, \
- .element = { (e0), (e1), (e2), (e3)}, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = count, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
- (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
- flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .element = { (e0), (e1), 0, 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
-flg, fm, np, th) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .element = { (e0), (e1), 0, 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
- .num_planes = np, \
- .tile_height = th \
-}
-
-#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .element = { (e0), (e1), 0, 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
-flg, fm, np, th) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
- .element = { (e0), (e1), 0, 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
- .num_planes = np, \
- .tile_height = th \
-}
-
-
-#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
-flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_PLANAR, \
- .element = { (e0), (e1), (e2), 0 }, \
- .bpc_g_y = g, \
- .bpc_b_cb = b, \
- .bpc_r_cr = r, \
- .bpc_a = a, \
- .chroma_sample = chroma, \
- .unpack_count = 1, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
- (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
- flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
/*
* struct dpu_media_color_map - maps drm format to media format
* @format: DRM base pixel format
@@ -201,375 +26,6 @@ struct dpu_media_color_map {
uint32_t color;
};
-static const struct msm_format dpu_format_map[] = {
- INTERLEAVED_RGB_FMT(ARGB8888,
- BPC8A, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA8888,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA8888,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX8888,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB8888,
- BPC8A, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX8888,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 4, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGB888,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
- false, 3, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGR888,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 3, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGB565,
- 0, BPC5, BPC6, BPC5,
- C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGR565,
- 0, BPC5, BPC6, BPC5,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ARGB1555,
- BPC1A, BPC5, BPC5, BPC5,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR1555,
- BPC1A, BPC5, BPC5, BPC5,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA5551,
- BPC1A, BPC5, BPC5, BPC5,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA5551,
- BPC1A, BPC5, BPC5, BPC5,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB1555,
- BPC1A, BPC5, BPC5, BPC5,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR1555,
- BPC1A, BPC5, BPC5, BPC5,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX5551,
- BPC1A, BPC5, BPC5, BPC5,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX5551,
- BPC1A, BPC5, BPC5, BPC5,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ARGB4444,
- BPC4A, BPC4, BPC4, BPC4,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR4444,
- BPC4A, BPC4, BPC4, BPC4,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA4444,
- BPC4A, BPC4, BPC4, BPC4,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA4444,
- BPC4A, BPC4, BPC4, BPC4,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB4444,
- BPC4A, BPC4, BPC4, BPC4,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR4444,
- BPC4A, BPC4, BPC4, BPC4,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX4444,
- BPC4A, BPC4, BPC4, BPC4,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX4444,
- BPC4A, BPC4, BPC4, BPC4,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 2, 0,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA1010102,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA1010102,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ARGB2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX1010102,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX1010102,
- BPC8A, BPC8, BPC8, BPC8,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 4, MSM_FORMAT_FLAG_DX,
- MDP_FETCH_LINEAR, 1),
-
- PSEUDO_YUV_FMT(NV12,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_420, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT(NV21,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C1_B_Cb,
- CHROMA_420, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT(NV16,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT(NV61,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C1_B_Cb,
- CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT_LOOSE(P010,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(VYUY,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
- false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(UYVY,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
- false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(YUYV,
- 0, BPC8, BPC8, BPC8,
- C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
- false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(YVYU,
- 0, BPC8, BPC8, BPC8,
- C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
- false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 2),
-
- PLANAR_YUV_FMT(YUV420,
- 0, BPC8, BPC8, BPC8,
- C2_R_Cr, C1_B_Cb, C0_G_Y,
- false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 3),
-
- PLANAR_YUV_FMT(YVU420,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr, C0_G_Y,
- false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
- MDP_FETCH_LINEAR, 3),
-};
-
-/*
- * UBWC formats table:
- * This table holds the UBWC formats supported.
- * If a compression ratio needs to be used for this or any other format,
- * the data will be passed by user-space.
- */
-static const struct msm_format dpu_format_map_ubwc[] = {
- INTERLEAVED_RGB_FMT_TILED(BGR565,
- 0, BPC5, BPC6, BPC5,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 2, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(ABGR8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- /* ARGB8888 and ABGR8888 purposely have the same color
- * ordering. The hardware only supports ABGR8888 UBWC
- * natively.
- */
- INTERLEAVED_RGB_FMT_TILED(ARGB8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XBGR8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XRGB8888,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- /* XRGB2101010 and ARGB2101010 purposely have the same color
- * ordering. The hardware only supports ARGB2101010 UBWC
- * natively.
- */
- INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
- BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- PSEUDO_YUV_FMT_TILED(NV12,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_420, MSM_FORMAT_FLAG_YUV |
- MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
-
- PSEUDO_YUV_FMT_TILED(P010,
- 0, BPC8, BPC8, BPC8,
- C1_B_Cb, C2_R_Cr,
- CHROMA_420, MSM_FORMAT_FLAG_DX |
- MSM_FORMAT_FLAG_YUV |
- MSM_FORMAT_FLAG_COMPRESSED,
- MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
-};
-
/* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support
* Note: Not using the drm_format_*_subsampling since we have formats
*/
@@ -1010,61 +466,3 @@ int dpu_format_check_modified_format(
return 0;
}
-
-const struct msm_format *dpu_get_dpu_format_ext(
- const uint32_t format,
- const uint64_t modifier)
-{
- uint32_t i = 0;
- const struct msm_format *fmt = NULL;
- const struct msm_format *map = NULL;
- ssize_t map_size = 0;
-
- /*
- * Currently only support exactly zero or one modifier.
- * All planes use the same modifier.
- */
- DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier);
-
- switch (modifier) {
- case 0:
- map = dpu_format_map;
- map_size = ARRAY_SIZE(dpu_format_map);
- break;
- case DRM_FORMAT_MOD_QCOM_COMPRESSED:
- map = dpu_format_map_ubwc;
- map_size = ARRAY_SIZE(dpu_format_map_ubwc);
- DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",
- (char *)&format);
- break;
- default:
- DPU_ERROR("unsupported format modifier %llX\n", modifier);
- return NULL;
- }
-
- for (i = 0; i < map_size; i++) {
- if (format == map[i].pixel_format) {
- fmt = &map[i];
- break;
- }
- }
-
- if (fmt == NULL)
- DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",
- (char *)&format, modifier);
- else
- DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %ld\n",
- (char *)&format, modifier,
- MSM_FORMAT_IS_UBWC(fmt),
- MSM_FORMAT_IS_YUV(fmt));
-
- return fmt;
-}
-
-const struct msm_format *dpu_get_msm_format(
- struct msm_kms *kms,
- const uint32_t format,
- const uint64_t modifiers)
-{
- return dpu_get_dpu_format_ext(format, modifiers);
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
index f45c16810adb..9fec1d36b0b7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
@@ -9,17 +9,6 @@
#include "msm_gem.h"
#include "dpu_hw_mdss.h"
-/**
- * dpu_get_dpu_format_ext() - Returns dpu format structure pointer.
- * @format: DRM FourCC Code
- * @modifiers: format modifier array from client, one per plane
- */
-const struct msm_format *dpu_get_dpu_format_ext(
- const uint32_t format,
- const uint64_t modifier);
-
-#define dpu_get_dpu_format(f) dpu_get_dpu_format_ext(f, 0)
-
/**
* dpu_find_format - validate if the pixel format is supported
* @format: dpu format
@@ -42,18 +31,6 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats,
return false;
}
-/**
- * dpu_get_msm_format - get an dpu_format by its msm_format base
- * callback function registers with the msm_kms layer
- * @kms: kms driver
- * @format: DRM FourCC Code
- * @modifiers: data layout modifier
- */
-const struct msm_format *dpu_get_msm_format(
- struct msm_kms *kms,
- const uint32_t format,
- const uint64_t modifiers);
-
/**
* dpu_format_check_modified_format - validate format and buffers for
* dpu non-standard, i.e. modified format
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 8e31387c2896..3a029d994241 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -260,16 +260,6 @@ enum dpu_vbif {
VBIF_MAX,
};
-/**
- * DPU HW,Component order color map
- */
-enum {
- C0_G_Y = 0,
- C1_B_Cb = 1,
- C2_R_Cr = 2,
- C3_ALPHA = 3
-};
-
/**
* enum dpu_3d_blend_mode
* Desribes how the 3d data is blended
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index babec724c76a..faff3aaf1029 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -981,7 +981,7 @@ static const struct msm_kms_funcs kms_funcs = {
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
- .get_format = dpu_get_msm_format,
+ .get_format = mdp_get_format,
.destroy = dpu_kms_destroy,
.snapshot = dpu_kms_mdp_snapshot,
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 5c0062d97d45..1d7e0068e9c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -649,6 +649,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
{
const struct msm_format *fmt;
const struct drm_plane *plane = &pdpu->base;
+ struct msm_drm_private *priv = plane->dev->dev_private;
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
@@ -658,7 +659,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
* select fill format to match user property expectation,
* h/w only supports RGB variants
*/
- fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
+ fmt = priv->kms->funcs->get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
/* should not happen ever */
if (!fmt)
return;
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index fa2a76a35106..3aab2ca3f717 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -62,87 +62,554 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
},
};
-#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, c, cnt, fp, cs, yuv) { \
- .pixel_format = DRM_FORMAT_ ## name, \
- .bpc_a = BPC ## a ## A, \
- .bpc_r_cr = BPC ## r, \
- .bpc_g_y = BPC ## g, \
- .bpc_b_cb = BPC ## b, \
- .element = { e0, e1, e2, e3 }, \
- .fetch_type = fp, \
- .chroma_sample = cs, \
- .unpack_count = cnt, \
- .bpp = c, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
- (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0), \
- (yuv ? MSM_FORMAT_FLAG_YUV : 0), \
+#define MDP_TILE_HEIGHT_DEFAULT 1
+#define MDP_TILE_HEIGHT_UBWC 4
+#define MDP_TILE_HEIGHT_NV12 8
+
+#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
+bp, flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .element = { (e0), (e1), (e2), (e3) }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = CHROMA_FULL, \
+ .unpack_count = uc, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
+ flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
+alpha, bp, flg, fm, np, th) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .element = { (e0), (e1), (e2), (e3) }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = CHROMA_FULL, \
+ .unpack_count = uc, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
+ flg, \
+ .num_planes = np, \
+ .tile_height = th \
+}
+
+#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
+alpha, chroma, count, bp, flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .element = { (e0), (e1), (e2), (e3)}, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = count, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
+ flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
+flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PLANAR, \
+ .element = { (e0), (e1), (e2), 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 1, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
+ flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
+flg, fm, np, th) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = th \
}
-#define BPC0A 0
-
-static const struct msm_format formats[] = {
- /* name a r g b e0 e1 e2 e3 alpha cpp cnt ... */
- FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, 3, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, 3, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB565, 0, 5, 6, 5, 1, 0, 2, 0, false, 2, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR565, 0, 5, 6, 5, 2, 0, 1, 0, false, 2, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
+static const struct msm_format mdp_formats[] = {
+ INTERLEAVED_RGB_FMT(ARGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGB888,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
+ false, 3, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGR888,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+ false, 3, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGB565,
+ 0, BPC5, BPC6, BPC5,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGR565,
+ 0, BPC5, BPC6, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ARGB1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ARGB4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ARGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
/* --- RGB formats above / YUV formats below this line --- */
/* 2 plane YUV */
- FMT(NV12, 0, 8, 8, 8, 1, 2, 0, 0, false, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV21, 0, 8, 8, 8, 2, 1, 0, 0, false, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV16, 0, 8, 8, 8, 1, 2, 0, 0, false, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
- FMT(NV61, 0, 8, 8, 8, 2, 1, 0, 0, false, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
+ PSEUDO_YUV_FMT(NV12,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT(NV21,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C1_B_Cb,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT(NV16,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT(NV61,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C1_B_Cb,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT_LOOSE(P010,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
/* 1 plane YUV */
- FMT(VYUY, 0, 8, 8, 8, 2, 0, 1, 0, false, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(UYVY, 0, 8, 8, 8, 1, 0, 2, 0, false, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YUYV, 0, 8, 8, 8, 0, 1, 0, 2, false, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YVYU, 0, 8, 8, 8, 0, 2, 0, 1, false, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
+ INTERLEAVED_YUV_FMT(VYUY,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ INTERLEAVED_YUV_FMT(UYVY,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ INTERLEAVED_YUV_FMT(YUYV,
+ 0, BPC8, BPC8, BPC8,
+ C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ INTERLEAVED_YUV_FMT(YVYU,
+ 0, BPC8, BPC8, BPC8,
+ C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
/* 3 plane YUV */
- FMT(YUV420, 0, 8, 8, 8, 2, 1, 0, 0, false, 1, 1,
- MDP_PLANE_PLANAR, CHROMA_420, true),
- FMT(YVU420, 0, 8, 8, 8, 1, 2, 0, 0, false, 1, 1,
- MDP_PLANE_PLANAR, CHROMA_420, true),
+ PLANAR_YUV_FMT(YUV420,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C1_B_Cb, C0_G_Y,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
+
+ PLANAR_YUV_FMT(YVU420,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr, C0_G_Y,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
+};
+
+/*
+ * UBWC formats table:
+ * This table holds the UBWC formats supported.
+ * If a compression ratio needs to be used for this or any other format,
+ * the data will be passed by user-space.
+ */
+static const struct msm_format mdp_formats_ubwc[] = {
+ INTERLEAVED_RGB_FMT_TILED(BGR565,
+ 0, BPC5, BPC6, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+ false, 2, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(ABGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ /* ARGB8888 and ABGR8888 purposely have the same color
+ * ordering. The hardware only supports ABGR8888 UBWC
+ * natively.
+ */
+ INTERLEAVED_RGB_FMT_TILED(ARGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XBGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XRGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ /* XRGB2101010 and ARGB2101010 purposely have the same color
+ * ordering. The hardware only supports ARGB2101010 UBWC
+ * natively.
+ */
+ INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ PSEUDO_YUV_FMT_TILED(NV12,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_NV12),
+
+ PSEUDO_YUV_FMT_TILED(P010,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_DX |
+ MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_UBWC),
};
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
uint64_t modifier)
{
+ const struct msm_format *map = NULL;
+ ssize_t map_size;
int i;
- for (i = 0; i < ARRAY_SIZE(formats); i++) {
- const struct msm_format *f = &formats[i];
+
+ switch (modifier) {
+ case 0:
+ map = mdp_formats;
+ map_size = ARRAY_SIZE(mdp_formats);
+ break;
+ case DRM_FORMAT_MOD_QCOM_COMPRESSED:
+ map = mdp_formats_ubwc;
+ map_size = ARRAY_SIZE(mdp_formats_ubwc);
+ break;
+ default:
+ drm_err(kms->dev, "unsupported format modifier %llX\n", modifier);
+ return NULL;
+ }
+
+ for (i = 0; i < map_size; i++) {
+ const struct msm_format *f = &map[i];
+
if (f->pixel_format == format)
return f;
}
+
+ drm_err(kms->dev, "unsupported fmt: %p4cc modifier 0x%llX\n",
+ &format, modifier);
+
return NULL;
}
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h b/drivers/gpu/drm/msm/disp/mdp_kms.h
index bb3bfb9d3bf4..7941b226720f 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -77,8 +77,6 @@ void mdp_irq_update(struct mdp_kms *mdp_kms);
* pixel format helpers:
*/
-const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
-
/* MDP capabilities */
#define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */
#define MDP_CAP_DSC BIT(1) /* VESA Display Stream Compression */
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index dea6d47854fe..e7651a0e878c 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -267,6 +267,16 @@ enum msm_format_flags {
#define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
#define MSM_FORMAT_FLAG_ALPHA_ENABLE BIT(MSM_FORMAT_FLAG_ALPHA_ENABLE_BIT)
+/**
+ * DPU HW,Component order color map
+ */
+enum {
+ C0_G_Y = 0,
+ C1_B_Cb = 1,
+ C2_R_Cr = 2,
+ C3_ALPHA = 3
+};
+
/**
* struct msm_format: defines the format configuration
* @pixel_format: format fourcc
@@ -305,6 +315,8 @@ struct msm_format {
(((X)->fetch_mode == MDP_FETCH_UBWC) && \
((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
+const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
+
struct msm_pending_timer;
int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 12/12] drm/msm: drop msm_kms_funcs::get_format() callback
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
` (10 preceding siblings ...)
2023-12-02 21:40 ` [PATCH 11/12] drm/msm: merge dpu format database to MDP formats Dmitry Baryshkov
@ 2023-12-02 21:40 ` Dmitry Baryshkov
2024-04-12 21:40 ` Abhinav Kumar
11 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2023-12-02 21:40 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Marijn Suijten
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Now as all subdrivers were converted to use common database of formats,
drop the get_format() callback and use mdp_get_format() directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 1 -
drivers/gpu/drm/msm/msm_fb.c | 2 +-
drivers/gpu/drm/msm/msm_kms.h | 4 ----
8 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index bd3ab2ab6515..bf7eb70ed2da 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -267,7 +267,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
- fmt = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
+ fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
intf_cfg.intf = phys_enc->hw_intf->idx;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index cef6066c0d3e..c1ec514e73d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -622,7 +622,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
- wb_cfg->dest.format = phys_enc->dpu_kms->base.funcs->get_format(&phys_enc->dpu_kms->base,
+ wb_cfg->dest.format = mdp_get_format(&phys_enc->dpu_kms->base,
format->pixel_format, job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index faff3aaf1029..4977269fbe57 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -981,7 +981,6 @@ static const struct msm_kms_funcs kms_funcs = {
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
- .get_format = mdp_get_format,
.destroy = dpu_kms_destroy,
.snapshot = dpu_kms_mdp_snapshot,
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 1d7e0068e9c3..a8ede71d84de 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -659,7 +659,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
* select fill format to match user property expectation,
* h/w only supports RGB variants
*/
- fmt = priv->kms->funcs->get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
+ fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
/* should not happen ever */
if (!fmt)
return;
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 4ba1cb74ad76..6e4e74f9d63d 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -151,7 +151,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.flush_commit = mdp4_flush_commit,
.wait_flush = mdp4_wait_flush,
.complete_commit = mdp4_complete_commit,
- .get_format = mdp_get_format,
.round_pixclk = mdp4_round_pixclk,
.destroy = mdp4_destroy,
},
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 48f447f4e183..18670ea40a3a 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -267,7 +267,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.prepare_commit = mdp5_prepare_commit,
.wait_flush = mdp5_wait_flush,
.complete_commit = mdp5_complete_commit,
- .get_format = mdp_get_format,
.set_split_display = mdp5_set_split_display,
.destroy = mdp5_kms_destroy,
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c
index e3f61c39df69..8326150e5e0c 100644
--- a/drivers/gpu/drm/msm/msm_fb.c
+++ b/drivers/gpu/drm/msm/msm_fb.c
@@ -181,7 +181,7 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
(char *)&mode_cmd->pixel_format);
n = info->num_planes;
- format = kms->funcs->get_format(kms, mode_cmd->pixel_format,
+ format = mdp_get_format(kms, mode_cmd->pixel_format,
mode_cmd->modifier[0]);
if (!format) {
DRM_DEV_ERROR(dev->dev, "unsupported pixel format: %4.4s\n",
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 44aa435d68ce..2b2f3d359709 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -92,10 +92,6 @@ struct msm_kms_funcs {
* Format handling:
*/
- /* get msm_format w/ optional format modifiers from drm_mode_fb_cmd2 */
- const struct msm_format *(*get_format)(struct msm_kms *kms,
- const uint32_t format,
- const uint64_t modifiers);
/* do format checking on format modified through fb_cmd2 modifiers */
int (*check_modified_format)(const struct msm_kms *kms,
const struct msm_format *msm_fmt,
--
2.39.2
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 01/12] drm/msm: fix BPC1 -> BPC4
2023-12-02 21:40 ` [PATCH 01/12] drm/msm: fix BPC1 -> BPC4 Dmitry Baryshkov
@ 2024-04-10 19:15 ` Abhinav Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-10 19:15 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Fix enum mdp_bpc::BPC1 value to be BPC4 instead (as shown in the DPU
> driver). This commit should be replaced with the registers sync with
> Mesa instead.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/mdp_common.xml.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 02/12] drm/msm/disp: add mdp_fetch_mode enum
2023-12-02 21:40 ` [PATCH 02/12] drm/msm/disp: add mdp_fetch_mode enum Dmitry Baryshkov
@ 2024-04-10 19:19 ` Abhinav Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-10 19:19 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Pull in new enum from the mesa registers. This commit should be replaced
> with the registers sync with Mesa instead.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/mdp_common.xml.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2023-12-02 21:40 ` [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h Dmitry Baryshkov
@ 2024-04-10 20:00 ` Abhinav Kumar
2024-04-10 20:16 ` Dmitry Baryshkov
0 siblings, 1 reply; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-10 20:00 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Instead of having DPU-specific defines, switch to the definitions from
> the mdp_common.xml.h file. This is the preparation for merged of DPU and
> MDP format tables.
>
Adding MDP_***__ usages in DPU driver is quite confusing.
Can we align to a common naming scheme such as DISP_***?
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 290 +++++++++---------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 64 +---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 12 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
> 6 files changed, 164 insertions(+), 214 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> index 0b6a761d68b7..4fead04d83a0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> @@ -640,7 +640,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
> wb_cfg->dest.height = job->fb->height;
> wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
>
> - if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
> + if ((wb_cfg->dest.format->fetch_planes == MDP_PLANE_PLANAR) &&
> (wb_cfg->dest.format->element[0] == C1_B_Cb))
> swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> index e366ab134249..05e82f5dd0e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> @@ -35,11 +35,11 @@
> bp, flg, fm, np) \
> { \
> .base.pixel_format = DRM_FORMAT_ ## fmt, \
> - .fetch_planes = DPU_PLANE_INTERLEAVED, \
> + .fetch_planes = MDP_PLANE_INTERLEAVED, \
> .alpha_enable = alpha, \
> .element = { (e0), (e1), (e2), (e3) }, \
> .bits = { g, b, r, a }, \
> - .chroma_sample = DPU_CHROMA_RGB, \
> + .chroma_sample = CHROMA_FULL, \
> .unpack_align_msb = 0, \
> .unpack_tight = 1, \
> .unpack_count = uc, \
> @@ -54,11 +54,11 @@ bp, flg, fm, np) \
> alpha, bp, flg, fm, np, th) \
> { \
> .base.pixel_format = DRM_FORMAT_ ## fmt, \
> - .fetch_planes = DPU_PLANE_INTERLEAVED, \
> + .fetch_planes = MDP_PLANE_INTERLEAVED, \
> .alpha_enable = alpha, \
> .element = { (e0), (e1), (e2), (e3) }, \
> .bits = { g, b, r, a }, \
> - .chroma_sample = DPU_CHROMA_RGB, \
> + .chroma_sample = CHROMA_FULL, \
> .unpack_align_msb = 0, \
> .unpack_tight = 1, \
> .unpack_count = uc, \
> @@ -74,7 +74,7 @@ alpha, bp, flg, fm, np, th) \
> alpha, chroma, count, bp, flg, fm, np) \
> { \
> .base.pixel_format = DRM_FORMAT_ ## fmt, \
> - .fetch_planes = DPU_PLANE_INTERLEAVED, \
> + .fetch_planes = MDP_PLANE_INTERLEAVED, \
> .alpha_enable = alpha, \
> .element = { (e0), (e1), (e2), (e3)}, \
> .bits = { g, b, r, a }, \
> @@ -92,7 +92,7 @@ alpha, chroma, count, bp, flg, fm, np) \
> #define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
> { \
> .base.pixel_format = DRM_FORMAT_ ## fmt, \
> - .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
> + .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
> .alpha_enable = false, \
> .element = { (e0), (e1), 0, 0 }, \
> .bits = { g, b, r, a }, \
> @@ -111,7 +111,7 @@ alpha, chroma, count, bp, flg, fm, np) \
> flg, fm, np, th) \
> { \
> .base.pixel_format = DRM_FORMAT_ ## fmt, \
> - .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
> + .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
> .alpha_enable = false, \
> .element = { (e0), (e1), 0, 0 }, \
> .bits = { g, b, r, a }, \
> @@ -129,7 +129,7 @@ flg, fm, np, th) \
> #define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
> { \
> .base.pixel_format = DRM_FORMAT_ ## fmt, \
> - .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
> + .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
> .alpha_enable = false, \
> .element = { (e0), (e1), 0, 0 }, \
> .bits = { g, b, r, a }, \
> @@ -148,7 +148,7 @@ flg, fm, np, th) \
> flg, fm, np, th) \
> { \
> .base.pixel_format = DRM_FORMAT_ ## fmt, \
> - .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
> + .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
> .alpha_enable = false, \
> .element = { (e0), (e1), 0, 0 }, \
> .bits = { g, b, r, a }, \
> @@ -168,7 +168,7 @@ flg, fm, np, th) \
> flg, fm, np) \
> { \
> .base.pixel_format = DRM_FORMAT_ ## fmt, \
> - .fetch_planes = DPU_PLANE_PLANAR, \
> + .fetch_planes = MDP_PLANE_PLANAR, \
> .alpha_enable = alpha, \
> .element = { (e0), (e1), (e2), 0 }, \
> .bits = { g, b, r, a }, \
> @@ -195,286 +195,286 @@ struct dpu_media_color_map {
>
> static const struct dpu_format dpu_format_map[] = {
> INTERLEAVED_RGB_FMT(ARGB8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
> true, 4, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(ABGR8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 4, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(XBGR8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> false, 4, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGBA8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
> true, 4, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGRA8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
> true, 4, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGRX8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
> false, 4, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(XRGB8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
> false, 4, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGBX8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
> false, 4, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGB888,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
> false, 3, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGR888,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
> false, 3, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGB565,
> - 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
> + 0, BPC5, BPC6, BPC5,
> C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGR565,
> - 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
> + 0, BPC5, BPC6, BPC5,
> C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(ARGB1555,
> - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
> + BPC1A, BPC5, BPC5, BPC5,
> C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
> true, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(ABGR1555,
> - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
> + BPC1A, BPC5, BPC5, BPC5,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGBA5551,
> - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
> + BPC1A, BPC5, BPC5, BPC5,
> C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
> true, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGRA5551,
> - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
> + BPC1A, BPC5, BPC5, BPC5,
> C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
> true, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(XRGB1555,
> - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
> + BPC1A, BPC5, BPC5, BPC5,
> C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(XBGR1555,
> - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
> + BPC1A, BPC5, BPC5, BPC5,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGBX5551,
> - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
> + BPC1A, BPC5, BPC5, BPC5,
> C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGRX5551,
> - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
> + BPC1A, BPC5, BPC5, BPC5,
> C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(ARGB4444,
> - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
> + BPC4A, BPC4, BPC4, BPC4,
> C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
> true, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(ABGR4444,
> - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
> + BPC4A, BPC4, BPC4, BPC4,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGBA4444,
> - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
> + BPC4A, BPC4, BPC4, BPC4,
> C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
> true, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGRA4444,
> - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
> + BPC4A, BPC4, BPC4, BPC4,
> C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
> true, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(XRGB4444,
> - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
> + BPC4A, BPC4, BPC4, BPC4,
> C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(XBGR4444,
> - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
> + BPC4A, BPC4, BPC4, BPC4,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGBX4444,
> - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
> + BPC4A, BPC4, BPC4, BPC4,
> C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGRX4444,
> - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
> + BPC4A, BPC4, BPC4, BPC4,
> C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
> false, 2, 0,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGRA1010102,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
> true, 4, DPU_FORMAT_FLAG_DX,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGBA1010102,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
> true, 4, DPU_FORMAT_FLAG_DX,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(ABGR2101010,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 4, DPU_FORMAT_FLAG_DX,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(ARGB2101010,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
> true, 4, DPU_FORMAT_FLAG_DX,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(XRGB2101010,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
> false, 4, DPU_FORMAT_FLAG_DX,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGRX1010102,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
> false, 4, DPU_FORMAT_FLAG_DX,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(XBGR2101010,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> false, 4, DPU_FORMAT_FLAG_DX,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(RGBX1010102,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
> false, 4, DPU_FORMAT_FLAG_DX,
> - DPU_FETCH_LINEAR, 1),
> + MDP_FETCH_LINEAR, 1),
>
> PSEUDO_YUV_FMT(NV12,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C1_B_Cb, C2_R_Cr,
> - DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 2),
> + CHROMA_420, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 2),
>
> PSEUDO_YUV_FMT(NV21,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C2_R_Cr, C1_B_Cb,
> - DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 2),
> + CHROMA_420, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 2),
>
> PSEUDO_YUV_FMT(NV16,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C1_B_Cb, C2_R_Cr,
> - DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 2),
> + CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 2),
>
> PSEUDO_YUV_FMT(NV61,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C2_R_Cr, C1_B_Cb,
> - DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 2),
> + CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 2),
>
> PSEUDO_YUV_FMT_LOOSE(P010,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C1_B_Cb, C2_R_Cr,
> - DPU_CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 2),
> + CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 2),
>
> INTERLEAVED_YUV_FMT(VYUY,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
> - false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 2),
> + false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 2),
>
> INTERLEAVED_YUV_FMT(UYVY,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
> - false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 2),
> + false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 2),
>
> INTERLEAVED_YUV_FMT(YUYV,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
> - false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 2),
> + false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 2),
>
> INTERLEAVED_YUV_FMT(YVYU,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
> - false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 2),
> + false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 2),
>
> PLANAR_YUV_FMT(YUV420,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C2_R_Cr, C1_B_Cb, C0_G_Y,
> - false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 3),
> + false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 3),
>
> PLANAR_YUV_FMT(YVU420,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C1_B_Cb, C2_R_Cr, C0_G_Y,
> - false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
> - DPU_FETCH_LINEAR, 3),
> + false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
> + MDP_FETCH_LINEAR, 3),
> };
>
> /*
> @@ -485,88 +485,88 @@ static const struct dpu_format dpu_format_map[] = {
> */
> static const struct dpu_format dpu_format_map_ubwc[] = {
> INTERLEAVED_RGB_FMT_TILED(BGR565,
> - 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
> + 0, BPC5, BPC6, BPC5,
> C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
> false, 2, DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
>
> INTERLEAVED_RGB_FMT_TILED(ABGR8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 4, DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
>
> /* ARGB8888 and ABGR8888 purposely have the same color
> * ordering. The hardware only supports ABGR8888 UBWC
> * natively.
> */
> INTERLEAVED_RGB_FMT_TILED(ARGB8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 4, DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
>
> INTERLEAVED_RGB_FMT_TILED(XBGR8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> false, 4, DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
>
> INTERLEAVED_RGB_FMT_TILED(XRGB8888,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> false, 4, DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
>
> INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
>
> INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
>
> INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
>
> /* XRGB2101010 and ARGB2101010 purposely have the same color
> * ordering. The hardware only supports ARGB2101010 UBWC
> * natively.
> */
> INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
> - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + BPC8A, BPC8, BPC8, BPC8,
> C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
> true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
>
> PSEUDO_YUV_FMT_TILED(NV12,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C1_B_Cb, C2_R_Cr,
> - DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV |
> + CHROMA_420, DPU_FORMAT_FLAG_YUV |
> DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
> + MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
>
> PSEUDO_YUV_FMT_TILED(P010,
> - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> + 0, BPC8, BPC8, BPC8,
> C1_B_Cb, C2_R_Cr,
> - DPU_CHROMA_420, DPU_FORMAT_FLAG_DX |
> + CHROMA_420, DPU_FORMAT_FLAG_DX |
> DPU_FORMAT_FLAG_YUV |
> DPU_FORMAT_FLAG_COMPRESSED,
> - DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
> + MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
> };
>
> /* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support
> * Note: Not using the drm_format_*_subsampling since we have formats
> */
> static void _dpu_get_v_h_subsample_rate(
> - enum dpu_chroma_samp_type chroma_sample,
> + enum mdp_chroma_samp_type chroma_sample,
> uint32_t *v_sample,
> uint32_t *h_sample)
> {
> @@ -574,15 +574,15 @@ static void _dpu_get_v_h_subsample_rate(
> return;
>
> switch (chroma_sample) {
> - case DPU_CHROMA_H2V1:
> + case CHROMA_H2V1:
> *v_sample = 1;
> *h_sample = 2;
> break;
> - case DPU_CHROMA_H1V2:
> + case CHROMA_H1V2:
> *v_sample = 2;
> *h_sample = 1;
> break;
> - case DPU_CHROMA_420:
> + case CHROMA_420:
> *v_sample = 2;
> *h_sample = 2;
> break;
> @@ -724,7 +724,7 @@ static int _dpu_format_get_plane_sizes_linear(
> layout->num_planes = fmt->num_planes;
>
> /* Due to memset above, only need to set planes of interest */
> - if (fmt->fetch_planes == DPU_PLANE_INTERLEAVED) {
> + if (fmt->fetch_planes == MDP_PLANE_INTERLEAVED) {
> layout->num_planes = 1;
> layout->plane_size[0] = width * height * layout->format->bpp;
> layout->plane_pitch[0] = width * layout->format->bpp;
> @@ -751,7 +751,7 @@ static int _dpu_format_get_plane_sizes_linear(
> layout->plane_size[1] = layout->plane_pitch[1] *
> (height / v_subsample);
>
> - if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
> + if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
> layout->num_planes = 2;
> layout->plane_size[1] *= 2;
> layout->plane_pitch[1] *= 2;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index e8b8908d3e12..06c6001b0626 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -204,9 +204,9 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
> (0x21 << 8));
> else
> /* Interface treats all the pixel data in RGB888 format */
> - panel_format = (COLOR_8BIT |
> - (COLOR_8BIT << 2) |
> - (COLOR_8BIT << 4) |
> + panel_format = (BPC8 |
> + (BPC8 << 2) |
> + (BPC8 << 4) |
> (0x21 << 8));
>
> DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index d85157acfbf8..ebb3f9f493c3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -9,6 +9,7 @@
> #include <linux/err.h>
>
> #include "msm_drv.h"
> +#include "disp/mdp_common.xml.h"
>
> #define DPU_DBG_NAME "dpu"
>
> @@ -49,12 +50,12 @@ enum dpu_format_flags {
> (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
> #define DPU_FORMAT_IS_DX(X) \
> (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
> -#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR)
> +#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
> #define DPU_FORMAT_IS_TILE(X) \
> - (((X)->fetch_mode == DPU_FETCH_UBWC) && \
> + (((X)->fetch_mode == MDP_FETCH_UBWC) && \
> !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
> #define DPU_FORMAT_IS_UBWC(X) \
> - (((X)->fetch_mode == DPU_FETCH_UBWC) && \
> + (((X)->fetch_mode == MDP_FETCH_UBWC) && \
> test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
>
> #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
> @@ -291,57 +292,6 @@ enum {
> C3_ALPHA = 3
> };
>
> -/**
> - * enum dpu_plane_type - defines how the color component pixel packing
> - * @DPU_PLANE_INTERLEAVED : Color components in single plane
> - * @DPU_PLANE_PLANAR : Color component in separate planes
> - * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
> - */
> -enum dpu_plane_type {
> - DPU_PLANE_INTERLEAVED,
> - DPU_PLANE_PLANAR,
> - DPU_PLANE_PSEUDO_PLANAR,
> -};
> -
> -/**
> - * enum dpu_chroma_samp_type - chroma sub-samplng type
> - * @DPU_CHROMA_RGB : No chroma subsampling
> - * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled
> - * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled
> - * @DPU_CHROMA_420 : 420 subsampling
> - */
> -enum dpu_chroma_samp_type {
> - DPU_CHROMA_RGB,
> - DPU_CHROMA_H2V1,
> - DPU_CHROMA_H1V2,
> - DPU_CHROMA_420
> -};
> -
> -/**
> - * dpu_fetch_type - Defines How DPU HW fetches data
> - * @DPU_FETCH_LINEAR : fetch is line by line
> - * @DPU_FETCH_TILE : fetches data in Z order from a tile
> - * @DPU_FETCH_UBWC : fetch and decompress data
> - */
> -enum dpu_fetch_type {
> - DPU_FETCH_LINEAR,
> - DPU_FETCH_TILE,
> - DPU_FETCH_UBWC
> -};
> -
> -/**
> - * Value of enum chosen to fit the number of bits
> - * expected by the HW programming.
> - */
> -enum {
> - COLOR_ALPHA_1BIT = 0,
> - COLOR_ALPHA_4BIT = 1,
> - COLOR_4BIT = 0,
> - COLOR_5BIT = 1, /* No 5-bit Alpha */
> - COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
> - COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
> -};
> -
> /**
> * enum dpu_3d_blend_mode
> * Desribes how the 3d data is blended
> @@ -381,17 +331,17 @@ enum dpu_3d_blend_mode {
> */
> struct dpu_format {
> struct msm_format base;
> - enum dpu_plane_type fetch_planes;
> + enum mdp_fetch_type fetch_planes;
> u8 element[DPU_MAX_PLANES];
> u8 bits[DPU_MAX_PLANES];
> - enum dpu_chroma_samp_type chroma_sample;
> + enum mdp_chroma_samp_type chroma_sample;
> u8 unpack_align_msb;
> u8 unpack_tight;
> u8 unpack_count;
> u8 bpp;
> u8 alpha_enable;
> u8 num_planes;
> - enum dpu_fetch_type fetch_mode;
> + enum mdp_fetch_mode fetch_mode;
> DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
> u16 tile_width;
> u16 tile_height;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 8e3c65989c49..d6530b11fc82 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -240,10 +240,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
>
> chroma_samp = fmt->chroma_sample;
> if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
> - if (chroma_samp == DPU_CHROMA_H2V1)
> - chroma_samp = DPU_CHROMA_H1V2;
> - else if (chroma_samp == DPU_CHROMA_H1V2)
> - chroma_samp = DPU_CHROMA_H2V1;
> + if (chroma_samp == CHROMA_H2V1)
> + chroma_samp = CHROMA_H1V2;
> + else if (chroma_samp == CHROMA_H1V2)
> + chroma_samp = CHROMA_H2V1;
> }
>
> src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
> @@ -253,7 +253,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
> if (flags & DPU_SSPP_ROT_90)
> src_format |= BIT(11); /* ROT90 */
>
> - if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED)
> + if (fmt->alpha_enable && fmt->fetch_planes == MDP_PLANE_INTERLEAVED)
> src_format |= BIT(8); /* SRCC3_EN */
>
> if (flags & DPU_SSPP_SOLID_FILL)
> @@ -266,7 +266,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
> (fmt->unpack_align_msb << 18) |
> ((fmt->bpp - 1) << 9);
>
> - if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
> + if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
> if (DPU_FORMAT_IS_UBWC(fmt))
> opmode |= MDSS_MDP_OP_BWC_EN;
> src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 1e0da38c6f2a..17d0b4bcdc89 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -215,8 +215,8 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
>
> /* FIXME: in multirect case account for the src_width of all the planes */
>
> - if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
> - if (fmt->chroma_sample == DPU_CHROMA_420) {
> + if (fmt->fetch_planes == MDP_PLANE_PSEUDO_PLANAR) {
> + if (fmt->chroma_sample == CHROMA_420) {
> /* NV12 */
> total_fl = (fixed_buff_size / 2) /
> ((src_width + 32) * fmt->bpp);
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2024-04-10 20:00 ` Abhinav Kumar
@ 2024-04-10 20:16 ` Dmitry Baryshkov
2024-04-10 20:18 ` Abhinav Kumar
0 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2024-04-10 20:16 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > Instead of having DPU-specific defines, switch to the definitions from
> > the mdp_common.xml.h file. This is the preparation for merged of DPU and
> > MDP format tables.
> >
>
> Adding MDP_***__ usages in DPU driver is quite confusing.
>
> Can we align to a common naming scheme such as DISP_***?
No, it's not something display-generic. It is specific to MDP
platforms. In the end DPU is a continuation of the MDP lineup, isn't
it?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2024-04-10 20:16 ` Dmitry Baryshkov
@ 2024-04-10 20:18 ` Abhinav Kumar
2024-04-10 21:12 ` Dmitry Baryshkov
0 siblings, 1 reply; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-10 20:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
> On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
>>> Instead of having DPU-specific defines, switch to the definitions from
>>> the mdp_common.xml.h file. This is the preparation for merged of DPU and
>>> MDP format tables.
>>>
>>
>> Adding MDP_***__ usages in DPU driver is quite confusing.
>>
>> Can we align to a common naming scheme such as DISP_***?
>
> No, it's not something display-generic. It is specific to MDP
> platforms. In the end DPU is a continuation of the MDP lineup, isn't
> it?
>
No some aspects of the hw are completely different as you already know
between MDP4/MDP5 and DPU. Bringing back MDP usages into DPU does not
seem right.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 05/12] drm/msm/dpu: in dpu_format replace bitmap with unsigned long field
2023-12-02 21:40 ` [PATCH 05/12] drm/msm/dpu: in dpu_format replace bitmap with unsigned long field Dmitry Baryshkov
@ 2024-04-10 20:40 ` Abhinav Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-10 20:40 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Using bitmap for the flags results in a clumsy syntax on test_bit,
> replace it with unsigned long type and simple binary ops.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 18 +++++++++---------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 16 +++++++---------
> 2 files changed, 16 insertions(+), 18 deletions(-)
>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2024-04-10 20:18 ` Abhinav Kumar
@ 2024-04-10 21:12 ` Dmitry Baryshkov
2024-04-10 23:54 ` Abhinav Kumar
0 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2024-04-10 21:12 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
>
>
> On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
> > On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> > >
> > >
> > >
> > > On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > > > Instead of having DPU-specific defines, switch to the definitions from
> > > > the mdp_common.xml.h file. This is the preparation for merged of DPU and
> > > > MDP format tables.
> > > >
> > >
> > > Adding MDP_***__ usages in DPU driver is quite confusing.
> > >
> > > Can we align to a common naming scheme such as DISP_***?
> >
> > No, it's not something display-generic. It is specific to MDP
> > platforms. In the end DPU is a continuation of the MDP lineup, isn't
> > it?
> >
>
> No some aspects of the hw are completely different as you already know
> between MDP4/MDP5 and DPU. Bringing back MDP usages into DPU does not seem
> right.
MDP4 is different, it's true. But there is a lot of common between MDP5
and DPU. Frakly speaking, I don't see an issue with using the constant
that was defined for MDP5 for DPU layer. Especially since we are also
going to use mdp_ functions for format handling.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2024-04-10 21:12 ` Dmitry Baryshkov
@ 2024-04-10 23:54 ` Abhinav Kumar
2024-04-11 1:20 ` Dmitry Baryshkov
2024-04-11 2:38 ` Dmitry Baryshkov
0 siblings, 2 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-10 23:54 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On 4/10/2024 2:12 PM, Dmitry Baryshkov wrote:
> On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
>>
>>
>> On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
>>> On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>>>
>>>>
>>>>
>>>> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
>>>>> Instead of having DPU-specific defines, switch to the definitions from
>>>>> the mdp_common.xml.h file. This is the preparation for merged of DPU and
>>>>> MDP format tables.
>>>>>
>>>>
>>>> Adding MDP_***__ usages in DPU driver is quite confusing.
>>>>
>>>> Can we align to a common naming scheme such as DISP_***?
>>>
>>> No, it's not something display-generic. It is specific to MDP
>>> platforms. In the end DPU is a continuation of the MDP lineup, isn't
>>> it?
>>>
>>
>> No some aspects of the hw are completely different as you already know
>> between MDP4/MDP5 and DPU. Bringing back MDP usages into DPU does not seem
>> right.
>
> MDP4 is different, it's true. But there is a lot of common between MDP5
> and DPU. Frakly speaking, I don't see an issue with using the constant
> that was defined for MDP5 for DPU layer. Especially since we are also
> going to use mdp_ functions for format handling.
>
All the HW naming etc in the doc has migrated to DPU and in fact it only
makes sense to start using DPU for MDP5 as we plan to move mdp5 targets
to DPU anyway. Not the other way around.
MDP4 remains different.
How about MSM_DISP then? I dont get why this is MDP platform specific.
Because the term MDP no longer holds true for DPU.
I am even looking for future chipsets. We cannot live with MDP5 names.
Have to think of generic names for formats.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2024-04-10 23:54 ` Abhinav Kumar
@ 2024-04-11 1:20 ` Dmitry Baryshkov
2024-04-11 1:21 ` Dmitry Baryshkov
2024-04-11 2:38 ` Dmitry Baryshkov
1 sibling, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2024-04-11 1:20 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On Thu, 11 Apr 2024 at 02:54, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 4/10/2024 2:12 PM, Dmitry Baryshkov wrote:
> > On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
> >>
> >>
> >> On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
> >>> On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> >>>>
> >>>>
> >>>>
> >>>> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> >>>>> Instead of having DPU-specific defines, switch to the definitions from
> >>>>> the mdp_common.xml.h file. This is the preparation for merged of DPU and
> >>>>> MDP format tables.
> >>>>>
> >>>>
> >>>> Adding MDP_***__ usages in DPU driver is quite confusing.
> >>>>
> >>>> Can we align to a common naming scheme such as DISP_***?
> >>>
> >>> No, it's not something display-generic. It is specific to MDP
> >>> platforms. In the end DPU is a continuation of the MDP lineup, isn't
> >>> it?
> >>>
> >>
> >> No some aspects of the hw are completely different as you already know
> >> between MDP4/MDP5 and DPU. Bringing back MDP usages into DPU does not seem
> >> right.
> >
> > MDP4 is different, it's true. But there is a lot of common between MDP5
> > and DPU. Frakly speaking, I don't see an issue with using the constant
> > that was defined for MDP5 for DPU layer. Especially since we are also
> > going to use mdp_ functions for format handling.
> >
>
> All the HW naming etc in the doc has migrated to DPU and in fact it only
> makes sense to start using DPU for MDP5 as we plan to move mdp5 targets
> to DPU anyway. Not the other way around.
>
> MDP4 remains different.
>
> How about MSM_DISP then? I dont get why this is MDP platform specific.
I expect MSM_DISP to be applicable to all MSM displays, even if e.g.
at some point DPU2 switches colour component encoding.
> Because the term MDP no longer holds true for DPU.
The XML is still called mdp_common. And the functions are in the mdp_
namespace. I don't think we should be changing them just because the
name has changed.
Likewise if MDP3 is not compatible with these definitions (to be
honest, I didn't check) I still don't think we should change these
names.
> I am even looking for future chipsets. We cannot live with MDP5 names.
> Have to think of generic names for formats.
Ok, I'm open for suggestions from your side.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2024-04-11 1:20 ` Dmitry Baryshkov
@ 2024-04-11 1:21 ` Dmitry Baryshkov
0 siblings, 0 replies; 39+ messages in thread
From: Dmitry Baryshkov @ 2024-04-11 1:21 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On Thu, 11 Apr 2024 at 04:20, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Thu, 11 Apr 2024 at 02:54, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> >
> >
> >
> > On 4/10/2024 2:12 PM, Dmitry Baryshkov wrote:
> > > On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
> > >>
> > >>
> > >> On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
> > >>> On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> > >>>>
> > >>>>
> > >>>>
> > >>>> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > >>>>> Instead of having DPU-specific defines, switch to the definitions from
> > >>>>> the mdp_common.xml.h file. This is the preparation for merged of DPU and
> > >>>>> MDP format tables.
> > >>>>>
> > >>>>
> > >>>> Adding MDP_***__ usages in DPU driver is quite confusing.
> > >>>>
> > >>>> Can we align to a common naming scheme such as DISP_***?
> > >>>
> > >>> No, it's not something display-generic. It is specific to MDP
> > >>> platforms. In the end DPU is a continuation of the MDP lineup, isn't
> > >>> it?
> > >>>
> > >>
> > >> No some aspects of the hw are completely different as you already know
> > >> between MDP4/MDP5 and DPU. Bringing back MDP usages into DPU does not seem
> > >> right.
> > >
> > > MDP4 is different, it's true. But there is a lot of common between MDP5
> > > and DPU. Frakly speaking, I don't see an issue with using the constant
> > > that was defined for MDP5 for DPU layer. Especially since we are also
> > > going to use mdp_ functions for format handling.
> > >
> >
> > All the HW naming etc in the doc has migrated to DPU and in fact it only
> > makes sense to start using DPU for MDP5 as we plan to move mdp5 targets
> > to DPU anyway. Not the other way around.
> >
> > MDP4 remains different.
> >
> > How about MSM_DISP then? I dont get why this is MDP platform specific.
>
> I expect MSM_DISP to be applicable to all MSM displays, even if e.g.
> at some point DPU2 switches colour component encoding.
>
> > Because the term MDP no longer holds true for DPU.
>
> The XML is still called mdp_common. And the functions are in the mdp_
> namespace. I don't think we should be changing them just because the
> name has changed.
> Likewise if MDP3 is not compatible with these definitions (to be
> honest, I didn't check) I still don't think we should change these
> names.
>
> > I am even looking for future chipsets. We cannot live with MDP5 names.
> > Have to think of generic names for formats.
>
> Ok, I'm open for suggestions from your side.
My proposal: MDPU? Neither MDP nor DPU.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2024-04-10 23:54 ` Abhinav Kumar
2024-04-11 1:20 ` Dmitry Baryshkov
@ 2024-04-11 2:38 ` Dmitry Baryshkov
2024-04-19 20:59 ` Abhinav Kumar
1 sibling, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2024-04-11 2:38 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On Thu, 11 Apr 2024 at 02:54, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 4/10/2024 2:12 PM, Dmitry Baryshkov wrote:
> > On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
> >>
> >>
> >> On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
> >>> On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> >>>>
> >>>>
> >>>>
> >>>> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> >>>>> Instead of having DPU-specific defines, switch to the definitions from
> >>>>> the mdp_common.xml.h file. This is the preparation for merged of DPU and
> >>>>> MDP format tables.
> >>>>>
> >>>>
> >>>> Adding MDP_***__ usages in DPU driver is quite confusing.
> >>>>
> >>>> Can we align to a common naming scheme such as DISP_***?
> >>>
> >>> No, it's not something display-generic. It is specific to MDP
> >>> platforms. In the end DPU is a continuation of the MDP lineup, isn't
> >>> it?
> >>>
> >>
> >> No some aspects of the hw are completely different as you already know
> >> between MDP4/MDP5 and DPU. Bringing back MDP usages into DPU does not seem
> >> right.
> >
> > MDP4 is different, it's true. But there is a lot of common between MDP5
> > and DPU. Frakly speaking, I don't see an issue with using the constant
> > that was defined for MDP5 for DPU layer. Especially since we are also
> > going to use mdp_ functions for format handling.
> >
>
> All the HW naming etc in the doc has migrated to DPU and in fact it only
> makes sense to start using DPU for MDP5 as we plan to move mdp5 targets
> to DPU anyway. Not the other way around.
>
> MDP4 remains different.
>
> How about MSM_DISP then? I dont get why this is MDP platform specific.
> Because the term MDP no longer holds true for DPU.
>
> I am even looking for future chipsets. We cannot live with MDP5 names.
> Have to think of generic names for formats.
Another point: MDP_ is still frequently used in the DPU driver. See
dpu_hwio.h, dpu_hw_catalog.h or dpu_hw_interrupts.c
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 06/12] drm/msm/dpu: pull format flag definitions to msm_drv.h
2023-12-02 21:40 ` [PATCH 06/12] drm/msm/dpu: pull format flag definitions to msm_drv.h Dmitry Baryshkov
@ 2024-04-11 18:41 ` Abhinav Kumar
2024-04-11 18:42 ` Abhinav Kumar
0 siblings, 1 reply; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-11 18:41 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> In preparation to merger of formats databases, pull format flag
> definitions to msm_drv.h header, so that they are visibile to both dpu
> and mdp drivers.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 98 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 28 ++----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
> drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 8 +-
> drivers/gpu/drm/msm/disp/mdp_format.c | 6 +-
> drivers/gpu/drm/msm/disp/mdp_kms.h | 3 +-
> drivers/gpu/drm/msm/msm_drv.h | 24 +++++
> 8 files changed, 91 insertions(+), 84 deletions(-)
>
<snip>
> +#define DPU_FORMAT_IS_YUV(X) MSM_FORMAT_IS_YUV(&(X)->base)
> +#define DPU_FORMAT_IS_DX(X) MSM_FORMAT_IS_DX(&(X)->base)
> +#define DPU_FORMAT_IS_LINEAR(X) MSM_FORMAT_IS_LINEAR(&(X)->base)
> +#define DPU_FORMAT_IS_TILE(X) MSM_FORMAT_IS_TILE(&(X)->base)
> +#define DPU_FORMAT_IS_UBWC(X) MSM_FORMAT_IS_UBWC(&(X)->base)
>
Do we need another wrapper macro on top of MSM_FORMAT_*** macros? Why
cant we use them directly?
Same comment for MDP_FORMAT_IS_YUV macro as well.
Rest LGTM.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 06/12] drm/msm/dpu: pull format flag definitions to msm_drv.h
2024-04-11 18:41 ` Abhinav Kumar
@ 2024-04-11 18:42 ` Abhinav Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-11 18:42 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 4/11/2024 11:41 AM, Abhinav Kumar wrote:
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
>> In preparation to merger of formats databases, pull format flag
>> definitions to msm_drv.h header, so that they are visibile to both dpu
>> and mdp drivers.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 98 ++++++++++-----------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 28 ++----
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +-
>> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
>> drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 8 +-
>> drivers/gpu/drm/msm/disp/mdp_format.c | 6 +-
>> drivers/gpu/drm/msm/disp/mdp_kms.h | 3 +-
>> drivers/gpu/drm/msm/msm_drv.h | 24 +++++
>> 8 files changed, 91 insertions(+), 84 deletions(-)
>>
>
> <snip>
>
>> +#define DPU_FORMAT_IS_YUV(X) MSM_FORMAT_IS_YUV(&(X)->base)
>> +#define DPU_FORMAT_IS_DX(X) MSM_FORMAT_IS_DX(&(X)->base)
>> +#define DPU_FORMAT_IS_LINEAR(X) MSM_FORMAT_IS_LINEAR(&(X)->base)
>> +#define DPU_FORMAT_IS_TILE(X) MSM_FORMAT_IS_TILE(&(X)->base)
>> +#define DPU_FORMAT_IS_UBWC(X) MSM_FORMAT_IS_UBWC(&(X)->base)
>
> Do we need another wrapper macro on top of MSM_FORMAT_*** macros? Why
> cant we use them directly?
>
> Same comment for MDP_FORMAT_IS_YUV macro as well.
>
> Rest LGTM.
never mind, the next change does exactly this. Hence this one LGTM
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 07/12] drm/msm: merge dpu_format and mdp_format in struct msm_format
2023-12-02 21:40 ` [PATCH 07/12] drm/msm: merge dpu_format and mdp_format in struct msm_format Dmitry Baryshkov
@ 2024-04-11 19:15 ` Abhinav Kumar
2024-04-11 19:17 ` Dmitry Baryshkov
0 siblings, 1 reply; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-11 19:15 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Structures dpu_format and mdp_format are largely the same structures.
> In order to remove duplication between format databases, merge these two
> stucture definitions into the global struct msm_format.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +-
> .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
> .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 184 ++++++++++--------
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 41 +---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 14 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 16 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 74 +++----
> drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 +-
> drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 26 +--
> drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 7 +-
> drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 54 ++---
> drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +-
> drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +-
> drivers/gpu/drm/msm/disp/mdp_format.c | 28 ++-
> drivers/gpu/drm/msm/disp/mdp_kms.h | 13 --
> drivers/gpu/drm/msm/msm_drv.h | 28 +++
> 24 files changed, 279 insertions(+), 288 deletions(-)
>
<snip>
> int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state,
> diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
> index 30919641c813..5fc55f41e74f 100644
> --- a/drivers/gpu/drm/msm/disp/mdp_format.c
> +++ b/drivers/gpu/drm/msm/disp/mdp_format.c
> @@ -63,26 +63,24 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
> };
>
> #define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
> - .base = { \
> - .pixel_format = DRM_FORMAT_ ## name, \
> - .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
> - }, \
> + .pixel_format = DRM_FORMAT_ ## name, \
> .bpc_a = BPC ## a ## A, \
> - .bpc_r = BPC ## r, \
> - .bpc_g = BPC ## g, \
> - .bpc_b = BPC ## b, \
> - .unpack = { e0, e1, e2, e3 }, \
> + .bpc_r_cr = BPC ## r, \
> + .bpc_g_y = BPC ## g, \
> + .bpc_b_cb = BPC ## b, \
> + .element = { e0, e1, e2, e3 }, \
> + .fetch_type = fp, \
> + .chroma_sample = cs, \
> .alpha_enable = alpha, \
> .unpack_tight = tight, \
> - .cpp = c, \
> .unpack_count = cnt, \
> - .fetch_type = fp, \
> - .chroma_sample = cs, \
Minor nit:
These two lines are only moving the locations of assignment so
unnecessary change?
Rest LGTM,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
For validation, are you relying mostly on the CI here OR also other
internal farms? Even though mostly its just making code common, basic
display coming up on one target each of MDP4/MDP5/DPU will be great to
be safe.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 07/12] drm/msm: merge dpu_format and mdp_format in struct msm_format
2024-04-11 19:15 ` Abhinav Kumar
@ 2024-04-11 19:17 ` Dmitry Baryshkov
0 siblings, 0 replies; 39+ messages in thread
From: Dmitry Baryshkov @ 2024-04-11 19:17 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On Thu, 11 Apr 2024 at 22:15, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > Structures dpu_format and mdp_format are largely the same structures.
> > In order to remove duplication between format databases, merge these two
> > stucture definitions into the global struct msm_format.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +-
> > .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
> > .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 184 ++++++++++--------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 41 +---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 +--
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 14 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 16 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 74 +++----
> > drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 +-
> > drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 26 +--
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 7 +-
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 54 ++---
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +-
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +-
> > drivers/gpu/drm/msm/disp/mdp_format.c | 28 ++-
> > drivers/gpu/drm/msm/disp/mdp_kms.h | 13 --
> > drivers/gpu/drm/msm/msm_drv.h | 28 +++
> > 24 files changed, 279 insertions(+), 288 deletions(-)
> >
>
> <snip>
>
> > int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state,
> > diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
> > index 30919641c813..5fc55f41e74f 100644
> > --- a/drivers/gpu/drm/msm/disp/mdp_format.c
> > +++ b/drivers/gpu/drm/msm/disp/mdp_format.c
> > @@ -63,26 +63,24 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
> > };
> >
> > #define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
> > - .base = { \
> > - .pixel_format = DRM_FORMAT_ ## name, \
> > - .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \
> > - }, \
> > + .pixel_format = DRM_FORMAT_ ## name, \
> > .bpc_a = BPC ## a ## A, \
> > - .bpc_r = BPC ## r, \
> > - .bpc_g = BPC ## g, \
> > - .bpc_b = BPC ## b, \
> > - .unpack = { e0, e1, e2, e3 }, \
> > + .bpc_r_cr = BPC ## r, \
> > + .bpc_g_y = BPC ## g, \
> > + .bpc_b_cb = BPC ## b, \
> > + .element = { e0, e1, e2, e3 }, \
> > + .fetch_type = fp, \
> > + .chroma_sample = cs, \
> > .alpha_enable = alpha, \
> > .unpack_tight = tight, \
> > - .cpp = c, \
> > .unpack_count = cnt, \
> > - .fetch_type = fp, \
> > - .chroma_sample = cs, \
>
> Minor nit:
>
> These two lines are only moving the locations of assignment so
> unnecessary change?
Sure, let's drop that. I think it was just C&P of some kind.
>
> Rest LGTM,
>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> For validation, are you relying mostly on the CI here OR also other
> internal farms? Even though mostly its just making code common, basic
> display coming up on one target each of MDP4/MDP5/DPU will be great to
> be safe.
It was a visual inspection, but not for each and every platform.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 08/12] drm/msm: convert msm_format::unpack_tight to the flag
2023-12-02 21:40 ` [PATCH 08/12] drm/msm: convert msm_format::unpack_tight to the flag Dmitry Baryshkov
@ 2024-04-11 21:02 ` Abhinav Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-11 21:02 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Instead of having a u8 or bool field unpack_tight, convert it to the
> flag, this save space in the tables and allows us to handle all booleans
> in the same way.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 22 +++------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
> drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 3 +-
> drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 +-
> drivers/gpu/drm/msm/disp/mdp_format.c | 52 ++++++++++-----------
> drivers/gpu/drm/msm/msm_drv.h | 4 +-
> 7 files changed, 41 insertions(+), 47 deletions(-)
>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 09/12] drm/msm: convert msm_format::unpack_align_msb to the flag
2023-12-02 21:40 ` [PATCH 09/12] drm/msm: convert msm_format::unpack_align_msb " Dmitry Baryshkov
@ 2024-04-11 21:13 ` Abhinav Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-11 21:13 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Instead of having a u8 or bool field unpack_align_msb, convert it to the
> flag, this save space in the tables and allows us to handle all booleans
> in the same way.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 12 ++----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
> drivers/gpu/drm/msm/msm_drv.h | 4 ++--
> 4 files changed, 6 insertions(+), 14 deletions(-)
>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 10/12] drm/msm: convert msm_format::alpha_enable to the flag
2023-12-02 21:40 ` [PATCH 10/12] drm/msm: convert msm_format::alpha_enable " Dmitry Baryshkov
@ 2024-04-11 21:20 ` Abhinav Kumar
2024-04-11 21:42 ` Dmitry Baryshkov
0 siblings, 1 reply; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-11 21:20 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Instead of having a bool field alpha_enable, convert it to the
> flag, this save space in the tables and allows us to handle all booleans
> in the same way.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 ++++++-----
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 24 ++++++++++-----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 7 +++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 3 ++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 4 ++--
> drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 2 +-
> drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 3 ++-
> drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 9 ++++----
> drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 ++-
> drivers/gpu/drm/msm/disp/mdp_format.c | 2 +-
> drivers/gpu/drm/msm/msm_drv.h | 4 ++--
> 11 files changed, 40 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 9041b0d71b25..201010038660 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -342,7 +342,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
>
> /* default to opaque blending */
> if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> - !format->alpha_enable) {
> + !(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE)) {
> blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
> DPU_BLEND_BG_ALPHA_BG_CONST;
> } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
> @@ -373,8 +373,8 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> lm->ops.setup_blend_config(lm, pstate->stage,
> fg_alpha, bg_alpha, blend_op);
>
> - DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
> - &format->pixel_format, format->alpha_enable, blend_op);
> + DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%lu blend_op:0x%x\n",
> + &format->pixel_format, format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE, blend_op);
> }
>
> static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
> @@ -472,7 +472,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>
> format = msm_framebuffer_format(pstate->base.fb);
>
> - if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
> + if (pstate->stage == DPU_STAGE_BASE &&
> + format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE)
> bg_alpha_enable = true;
>
> set_bit(pstate->pipe.sspp->idx, fetch_active);
> @@ -495,7 +496,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
> _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
>
> - if (bg_alpha_enable && !format->alpha_enable)
> + if (bg_alpha_enable &&
> + !(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE))
> mixer[lm_idx].mixer_op_mode = 0;
> else
> mixer[lm_idx].mixer_op_mode |=
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> index baf0fd67bf42..de9e93cb42c4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> @@ -36,7 +36,6 @@ bp, flg, fm, np) \
> { \
> .pixel_format = DRM_FORMAT_ ## fmt, \
> .fetch_type = MDP_PLANE_INTERLEAVED, \
> - .alpha_enable = alpha, \
> .element = { (e0), (e1), (e2), (e3) }, \
> .bpc_g_y = g, \
> .bpc_b_cb = b, \
> @@ -46,7 +45,9 @@ bp, flg, fm, np) \
> .unpack_count = uc, \
> .bpp = bp, \
> .fetch_mode = fm, \
> - .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
> + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
> + (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
> + flg, \
In the previous two patches where the same thing was done for
unpack_tight and unpack_align_msb, it was different in the sense that
just on the basis of which macro we were choosing we knew the value of
those flags so you could just unconditionally OR those flags.
But for alpha, you are performing a conditional before ORing this so I
think for this leaving it as a bool is cleaner.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 10/12] drm/msm: convert msm_format::alpha_enable to the flag
2024-04-11 21:20 ` Abhinav Kumar
@ 2024-04-11 21:42 ` Dmitry Baryshkov
0 siblings, 0 replies; 39+ messages in thread
From: Dmitry Baryshkov @ 2024-04-11 21:42 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On Fri, 12 Apr 2024 at 00:20, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > Instead of having a bool field alpha_enable, convert it to the
> > flag, this save space in the tables and allows us to handle all booleans
> > in the same way.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 ++++++-----
> > drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 24 ++++++++++-----------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 7 +++---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 3 ++-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 4 ++--
> > drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 2 +-
> > drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 3 ++-
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 9 ++++----
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 ++-
> > drivers/gpu/drm/msm/disp/mdp_format.c | 2 +-
> > drivers/gpu/drm/msm/msm_drv.h | 4 ++--
> > 11 files changed, 40 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > index 9041b0d71b25..201010038660 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > @@ -342,7 +342,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> >
> > /* default to opaque blending */
> > if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> > - !format->alpha_enable) {
> > + !(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE)) {
> > blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
> > DPU_BLEND_BG_ALPHA_BG_CONST;
> > } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
> > @@ -373,8 +373,8 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> > lm->ops.setup_blend_config(lm, pstate->stage,
> > fg_alpha, bg_alpha, blend_op);
> >
> > - DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
> > - &format->pixel_format, format->alpha_enable, blend_op);
> > + DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%lu blend_op:0x%x\n",
> > + &format->pixel_format, format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE, blend_op);
> > }
> >
> > static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
> > @@ -472,7 +472,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> >
> > format = msm_framebuffer_format(pstate->base.fb);
> >
> > - if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
> > + if (pstate->stage == DPU_STAGE_BASE &&
> > + format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE)
> > bg_alpha_enable = true;
> >
> > set_bit(pstate->pipe.sspp->idx, fetch_active);
> > @@ -495,7 +496,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> > for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
> > _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
> >
> > - if (bg_alpha_enable && !format->alpha_enable)
> > + if (bg_alpha_enable &&
> > + !(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE))
> > mixer[lm_idx].mixer_op_mode = 0;
> > else
> > mixer[lm_idx].mixer_op_mode |=
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > index baf0fd67bf42..de9e93cb42c4 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> > @@ -36,7 +36,6 @@ bp, flg, fm, np) \
> > { \
> > .pixel_format = DRM_FORMAT_ ## fmt, \
> > .fetch_type = MDP_PLANE_INTERLEAVED, \
> > - .alpha_enable = alpha, \
> > .element = { (e0), (e1), (e2), (e3) }, \
> > .bpc_g_y = g, \
> > .bpc_b_cb = b, \
> > @@ -46,7 +45,9 @@ bp, flg, fm, np) \
> > .unpack_count = uc, \
> > .bpp = bp, \
> > .fetch_mode = fm, \
> > - .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
> > + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
> > + (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
> > + flg, \
>
> In the previous two patches where the same thing was done for
> unpack_tight and unpack_align_msb, it was different in the sense that
> just on the basis of which macro we were choosing we knew the value of
> those flags so you could just unconditionally OR those flags.
>
> But for alpha, you are performing a conditional before ORing this so I
> think for this leaving it as a bool is cleaner.
Ack
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 11/12] drm/msm: merge dpu format database to MDP formats
2023-12-02 21:40 ` [PATCH 11/12] drm/msm: merge dpu format database to MDP formats Dmitry Baryshkov
@ 2024-04-12 19:47 ` Abhinav Kumar
2024-04-13 6:02 ` Dmitry Baryshkov
0 siblings, 1 reply; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-12 19:47 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Finally remove duplication between DPU and generic MDP code by merging
> DPU format lists to the MDP format database.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
> .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 602 ------------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 23 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 10 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +-
> drivers/gpu/drm/msm/disp/mdp_format.c | 595 +++++++++++++++--
> drivers/gpu/drm/msm/disp/mdp_kms.h | 2 -
> drivers/gpu/drm/msm/msm_drv.h | 12 +
> 10 files changed, 549 insertions(+), 706 deletions(-)
>
I cross-checked a few macros visually (not each one) and it LGTM in
terms of just moving it from dpu_formats.c to mdp_format.c
Even in this change I had the same concern about whether to use MDP for
dpu formats.
But I think even if we make it MSM_*** then we will have to keep them in
some msm_** header and not mdp_format.c
So lets go ahead with the MDP naming which you have. If we see its not
working out later on, please be open to a mass renaming that time.
<snip>
> index dea6d47854fe..e7651a0e878c 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -267,6 +267,16 @@ enum msm_format_flags {
> #define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
> #define MSM_FORMAT_FLAG_ALPHA_ENABLE BIT(MSM_FORMAT_FLAG_ALPHA_ENABLE_BIT)
>
> +/**
> + * DPU HW,Component order color map
> + */
> +enum {
> + C0_G_Y = 0,
> + C1_B_Cb = 1,
> + C2_R_Cr = 2,
> + C3_ALPHA = 3
> +};
> +
> /**
> * struct msm_format: defines the format configuration
> * @pixel_format: format fourcc
> @@ -305,6 +315,8 @@ struct msm_format {
> (((X)->fetch_mode == MDP_FETCH_UBWC) && \
> ((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
>
> +const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
> +
> struct msm_pending_timer;
>
> int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
I am now thinking that do you think it makes sense to move all
MDP_FORMAT macros to a new mdp_formats.h including the RGB/YUV bitfield
macros (even though I already acked that change).
Instead of bloating msm_drv.h even more?
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 12/12] drm/msm: drop msm_kms_funcs::get_format() callback
2023-12-02 21:40 ` [PATCH 12/12] drm/msm: drop msm_kms_funcs::get_format() callback Dmitry Baryshkov
@ 2024-04-12 21:40 ` Abhinav Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-12 21:40 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> Now as all subdrivers were converted to use common database of formats,
> drop the get_format() callback and use mdp_get_format() directly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
> drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 -
> drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 1 -
> drivers/gpu/drm/msm/msm_fb.c | 2 +-
> drivers/gpu/drm/msm/msm_kms.h | 4 ----
> 8 files changed, 4 insertions(+), 11 deletions(-)
>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 11/12] drm/msm: merge dpu format database to MDP formats
2024-04-12 19:47 ` Abhinav Kumar
@ 2024-04-13 6:02 ` Dmitry Baryshkov
0 siblings, 0 replies; 39+ messages in thread
From: Dmitry Baryshkov @ 2024-04-13 6:02 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On Fri, 12 Apr 2024 at 22:47, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > Finally remove duplication between DPU and generic MDP code by merging
> > DPU format lists to the MDP format database.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
> > .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 602 ------------------
> > drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 23 -
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 10 -
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +-
> > drivers/gpu/drm/msm/disp/mdp_format.c | 595 +++++++++++++++--
> > drivers/gpu/drm/msm/disp/mdp_kms.h | 2 -
> > drivers/gpu/drm/msm/msm_drv.h | 12 +
> > 10 files changed, 549 insertions(+), 706 deletions(-)
> >
>
> I cross-checked a few macros visually (not each one) and it LGTM in
> terms of just moving it from dpu_formats.c to mdp_format.c
>
> Even in this change I had the same concern about whether to use MDP for
> dpu formats.
>
> But I think even if we make it MSM_*** then we will have to keep them in
> some msm_** header and not mdp_format.c
>
> So lets go ahead with the MDP naming which you have. If we see its not
> working out later on, please be open to a mass renaming that time.
Ack.
>
> <snip>
>
> > index dea6d47854fe..e7651a0e878c 100644
> > --- a/drivers/gpu/drm/msm/msm_drv.h
> > +++ b/drivers/gpu/drm/msm/msm_drv.h
> > @@ -267,6 +267,16 @@ enum msm_format_flags {
> > #define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
> > #define MSM_FORMAT_FLAG_ALPHA_ENABLE BIT(MSM_FORMAT_FLAG_ALPHA_ENABLE_BIT)
> >
> > +/**
> > + * DPU HW,Component order color map
> > + */
> > +enum {
> > + C0_G_Y = 0,
> > + C1_B_Cb = 1,
> > + C2_R_Cr = 2,
> > + C3_ALPHA = 3
> > +};
> > +
> > /**
> > * struct msm_format: defines the format configuration
> > * @pixel_format: format fourcc
> > @@ -305,6 +315,8 @@ struct msm_format {
> > (((X)->fetch_mode == MDP_FETCH_UBWC) && \
> > ((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
> >
> > +const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
> > +
> > struct msm_pending_timer;
> >
> > int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
>
> I am now thinking that do you think it makes sense to move all
> MDP_FORMAT macros to a new mdp_formats.h including the RGB/YUV bitfield
> macros (even though I already acked that change).
>
> Instead of bloating msm_drv.h even more?
Sounds like a good idea, yes. Thank you!
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
2024-04-11 2:38 ` Dmitry Baryshkov
@ 2024-04-19 20:59 ` Abhinav Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-19 20:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On 4/10/2024 7:38 PM, Dmitry Baryshkov wrote:
> On Thu, 11 Apr 2024 at 02:54, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 4/10/2024 2:12 PM, Dmitry Baryshkov wrote:
>>> On Wed, Apr 10, 2024 at 01:18:42PM -0700, Abhinav Kumar wrote:
>>>>
>>>>
>>>> On 4/10/2024 1:16 PM, Dmitry Baryshkov wrote:
>>>>> On Wed, 10 Apr 2024 at 23:00, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
>>>>>>> Instead of having DPU-specific defines, switch to the definitions from
>>>>>>> the mdp_common.xml.h file. This is the preparation for merged of DPU and
>>>>>>> MDP format tables.
>>>>>>>
>>>>>>
>>>>>> Adding MDP_***__ usages in DPU driver is quite confusing.
>>>>>>
>>>>>> Can we align to a common naming scheme such as DISP_***?
>>>>>
>>>>> No, it's not something display-generic. It is specific to MDP
>>>>> platforms. In the end DPU is a continuation of the MDP lineup, isn't
>>>>> it?
>>>>>
>>>>
>>>> No some aspects of the hw are completely different as you already know
>>>> between MDP4/MDP5 and DPU. Bringing back MDP usages into DPU does not seem
>>>> right.
>>>
>>> MDP4 is different, it's true. But there is a lot of common between MDP5
>>> and DPU. Frakly speaking, I don't see an issue with using the constant
>>> that was defined for MDP5 for DPU layer. Especially since we are also
>>> going to use mdp_ functions for format handling.
>>>
>>
>> All the HW naming etc in the doc has migrated to DPU and in fact it only
>> makes sense to start using DPU for MDP5 as we plan to move mdp5 targets
>> to DPU anyway. Not the other way around.
>>
>> MDP4 remains different.
>>
>> How about MSM_DISP then? I dont get why this is MDP platform specific.
>> Because the term MDP no longer holds true for DPU.
>>
>> I am even looking for future chipsets. We cannot live with MDP5 names.
>> Have to think of generic names for formats.
>
> Another point: MDP_ is still frequently used in the DPU driver. See
> dpu_hwio.h, dpu_hw_catalog.h or dpu_hw_interrupts.c
>
As I wrote in
https://patchwork.freedesktop.org/patch/570148/?series=127230&rev=1,
lets go ahead with the MDP naming which you have. If we see its not
working out later on, please be open to a mass renaming that time.
With that expectation set,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 04/12] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware
2023-12-02 21:40 ` [PATCH 04/12] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware Dmitry Baryshkov
@ 2024-04-19 21:06 ` Abhinav Kumar
2024-04-19 21:21 ` Dmitry Baryshkov
0 siblings, 1 reply; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-19 21:06 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul, Marijn Suijten
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> MDP4 and MDP5 drivers enumerate supported formats each time the plane is
> created. In preparation to merger of MDP DPU format databases, define
> precise formats list, so that changes to the database do not cause the
> driver to add unsupported format to the list.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 57 ++++++++++++++++++++--
> drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 36 +++++++++++---
> drivers/gpu/drm/msm/disp/mdp_format.c | 28 -----------
> drivers/gpu/drm/msm/disp/mdp_kms.h | 1 -
> 4 files changed, 80 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
> index b689b618da78..cebe20c82a54 100644
> --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
> +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
> @@ -371,6 +371,47 @@ static const uint64_t supported_format_modifiers[] = {
> DRM_FORMAT_MOD_INVALID
> };
>
> +const uint32_t mdp4_rgb_formats[] = {
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_RGBA8888,
> + DRM_FORMAT_BGRA8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_RGBX8888,
> + DRM_FORMAT_BGRX8888,
> + DRM_FORMAT_RGB888,
> + DRM_FORMAT_BGR888,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_BGR565,
> +};
> +
> +const uint32_t mdp4_rgb_yuv_formats[] = {
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_RGBA8888,
> + DRM_FORMAT_BGRA8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_RGBX8888,
> + DRM_FORMAT_BGRX8888,
> + DRM_FORMAT_RGB888,
> + DRM_FORMAT_BGR888,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_BGR565,
> +
> + DRM_FORMAT_NV12,
> + DRM_FORMAT_NV21,
> + DRM_FORMAT_NV16,
> + DRM_FORMAT_NV61,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_YUV420,
> + DRM_FORMAT_YVU420,
> +};
> +
> /* initialize plane */
> struct drm_plane *mdp4_plane_init(struct drm_device *dev,
> enum mdp4_pipe pipe_id, bool private_plane)
> @@ -379,6 +420,8 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
> struct mdp4_plane *mdp4_plane;
> int ret;
> enum drm_plane_type type;
> + const uint32_t *formats;
> + unsigned int nformats;
>
> mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
> if (!mdp4_plane) {
> @@ -392,13 +435,17 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
> mdp4_plane->name = pipe_names[pipe_id];
> mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
>
> - mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
> - ARRAY_SIZE(mdp4_plane->formats),
> - !pipe_supports_yuv(mdp4_plane->caps));
> -
> type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
> +
> + if (pipe_supports_yuv(mdp4_plane->caps)) {
> + formats = mdp4_rgb_yuv_formats;
> + nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
> + } else {
> + formats = mdp4_rgb_formats;
> + nformats = ARRAY_SIZE(mdp4_rgb_formats);
> + }
> ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
> - mdp4_plane->formats, mdp4_plane->nformats,
> + formats, nformats,
> supported_format_modifiers, type, NULL);
> if (ret)
> goto fail;
> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> index 0d5ff03cb091..aa8342d93393 100644
> --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> @@ -17,9 +17,6 @@
>
> struct mdp5_plane {
> struct drm_plane base;
> -
> - uint32_t nformats;
> - uint32_t formats[32];
> };
> #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
>
> @@ -1007,6 +1004,32 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
> return mask;
> }
>
> +const uint32_t mdp5_plane_formats[] = {
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_RGBA8888,
> + DRM_FORMAT_BGRA8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_RGBX8888,
> + DRM_FORMAT_BGRX8888,
> + DRM_FORMAT_RGB888,
> + DRM_FORMAT_BGR888,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_BGR565,
> +
> + DRM_FORMAT_NV12,
> + DRM_FORMAT_NV21,
> + DRM_FORMAT_NV16,
> + DRM_FORMAT_NV61,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_YUV420,
> + DRM_FORMAT_YVU420,
> +};
> +
> /* initialize plane */
> struct drm_plane *mdp5_plane_init(struct drm_device *dev,
> enum drm_plane_type type)
> @@ -1023,12 +1046,9 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
>
> plane = &mdp5_plane->base;
>
> - mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
> - ARRAY_SIZE(mdp5_plane->formats), false);
> -
> ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
> - mdp5_plane->formats, mdp5_plane->nformats,
> - NULL, type, NULL);
> + mdp5_plane_formats, ARRAY_SIZE(mdp5_plane_formats),
> + NULL, type, NULL);
> if (ret)
> goto fail;
>
Did you accidentally drop checking for YUV format cap before adding the
formats for the plane similar to
> + if (pipe_supports_yuv(mdp4_plane->caps)) {
> + formats = mdp4_rgb_yuv_formats;
> + nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
> + } else {
> + formats = mdp4_rgb_formats;
> + nformats = ARRAY_SIZE(mdp4_rgb_formats);
> + }
Also, from what I checked the format table is identical between mdp4 and
mdp5. Even if we cannot unify mdp4/5 and dpu tables, we can atleast have
mdp_4_5_rgb and mdp_4_5_rgb_yuv?
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 04/12] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware
2024-04-19 21:06 ` Abhinav Kumar
@ 2024-04-19 21:21 ` Dmitry Baryshkov
2024-04-19 21:57 ` Abhinav Kumar
0 siblings, 1 reply; 39+ messages in thread
From: Dmitry Baryshkov @ 2024-04-19 21:21 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On Sat, 20 Apr 2024 at 00:06, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
> > MDP4 and MDP5 drivers enumerate supported formats each time the plane is
> > created. In preparation to merger of MDP DPU format databases, define
> > precise formats list, so that changes to the database do not cause the
> > driver to add unsupported format to the list.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 57 ++++++++++++++++++++--
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 36 +++++++++++---
> > drivers/gpu/drm/msm/disp/mdp_format.c | 28 -----------
> > drivers/gpu/drm/msm/disp/mdp_kms.h | 1 -
> > 4 files changed, 80 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
> > index b689b618da78..cebe20c82a54 100644
> > --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
> > @@ -371,6 +371,47 @@ static const uint64_t supported_format_modifiers[] = {
> > DRM_FORMAT_MOD_INVALID
> > };
> >
> > +const uint32_t mdp4_rgb_formats[] = {
> > + DRM_FORMAT_ARGB8888,
> > + DRM_FORMAT_ABGR8888,
> > + DRM_FORMAT_RGBA8888,
> > + DRM_FORMAT_BGRA8888,
> > + DRM_FORMAT_XRGB8888,
> > + DRM_FORMAT_XBGR8888,
> > + DRM_FORMAT_RGBX8888,
> > + DRM_FORMAT_BGRX8888,
> > + DRM_FORMAT_RGB888,
> > + DRM_FORMAT_BGR888,
> > + DRM_FORMAT_RGB565,
> > + DRM_FORMAT_BGR565,
> > +};
> > +
> > +const uint32_t mdp4_rgb_yuv_formats[] = {
> > + DRM_FORMAT_ARGB8888,
> > + DRM_FORMAT_ABGR8888,
> > + DRM_FORMAT_RGBA8888,
> > + DRM_FORMAT_BGRA8888,
> > + DRM_FORMAT_XRGB8888,
> > + DRM_FORMAT_XBGR8888,
> > + DRM_FORMAT_RGBX8888,
> > + DRM_FORMAT_BGRX8888,
> > + DRM_FORMAT_RGB888,
> > + DRM_FORMAT_BGR888,
> > + DRM_FORMAT_RGB565,
> > + DRM_FORMAT_BGR565,
> > +
> > + DRM_FORMAT_NV12,
> > + DRM_FORMAT_NV21,
> > + DRM_FORMAT_NV16,
> > + DRM_FORMAT_NV61,
> > + DRM_FORMAT_VYUY,
> > + DRM_FORMAT_UYVY,
> > + DRM_FORMAT_YUYV,
> > + DRM_FORMAT_YVYU,
> > + DRM_FORMAT_YUV420,
> > + DRM_FORMAT_YVU420,
> > +};
> > +
> > /* initialize plane */
> > struct drm_plane *mdp4_plane_init(struct drm_device *dev,
> > enum mdp4_pipe pipe_id, bool private_plane)
> > @@ -379,6 +420,8 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
> > struct mdp4_plane *mdp4_plane;
> > int ret;
> > enum drm_plane_type type;
> > + const uint32_t *formats;
> > + unsigned int nformats;
> >
> > mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
> > if (!mdp4_plane) {
> > @@ -392,13 +435,17 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
> > mdp4_plane->name = pipe_names[pipe_id];
> > mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
> >
> > - mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
> > - ARRAY_SIZE(mdp4_plane->formats),
> > - !pipe_supports_yuv(mdp4_plane->caps));
> > -
> > type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
> > +
> > + if (pipe_supports_yuv(mdp4_plane->caps)) {
> > + formats = mdp4_rgb_yuv_formats;
> > + nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
> > + } else {
> > + formats = mdp4_rgb_formats;
> > + nformats = ARRAY_SIZE(mdp4_rgb_formats);
> > + }
> > ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
> > - mdp4_plane->formats, mdp4_plane->nformats,
> > + formats, nformats,
> > supported_format_modifiers, type, NULL);
> > if (ret)
> > goto fail;
> > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> > index 0d5ff03cb091..aa8342d93393 100644
> > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> > @@ -17,9 +17,6 @@
> >
> > struct mdp5_plane {
> > struct drm_plane base;
> > -
> > - uint32_t nformats;
> > - uint32_t formats[32];
> > };
> > #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
> >
> > @@ -1007,6 +1004,32 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
> > return mask;
> > }
> >
> > +const uint32_t mdp5_plane_formats[] = {
> > + DRM_FORMAT_ARGB8888,
> > + DRM_FORMAT_ABGR8888,
> > + DRM_FORMAT_RGBA8888,
> > + DRM_FORMAT_BGRA8888,
> > + DRM_FORMAT_XRGB8888,
> > + DRM_FORMAT_XBGR8888,
> > + DRM_FORMAT_RGBX8888,
> > + DRM_FORMAT_BGRX8888,
> > + DRM_FORMAT_RGB888,
> > + DRM_FORMAT_BGR888,
> > + DRM_FORMAT_RGB565,
> > + DRM_FORMAT_BGR565,
> > +
> > + DRM_FORMAT_NV12,
> > + DRM_FORMAT_NV21,
> > + DRM_FORMAT_NV16,
> > + DRM_FORMAT_NV61,
> > + DRM_FORMAT_VYUY,
> > + DRM_FORMAT_UYVY,
> > + DRM_FORMAT_YUYV,
> > + DRM_FORMAT_YVYU,
> > + DRM_FORMAT_YUV420,
> > + DRM_FORMAT_YVU420,
> > +};
> > +
> > /* initialize plane */
> > struct drm_plane *mdp5_plane_init(struct drm_device *dev,
> > enum drm_plane_type type)
> > @@ -1023,12 +1046,9 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
> >
> > plane = &mdp5_plane->base;
> >
> > - mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
> > - ARRAY_SIZE(mdp5_plane->formats), false);
> > -
> > ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
> > - mdp5_plane->formats, mdp5_plane->nformats,
> > - NULL, type, NULL);
> > + mdp5_plane_formats, ARRAY_SIZE(mdp5_plane_formats),
> > + NULL, type, NULL);
> > if (ret)
> > goto fail;
> >
>
> Did you accidentally drop checking for YUV format cap before adding the
> formats for the plane similar to
No. MDP5 driver asks RGB+YUV planes see the mdp_get_formats() arguments.
>
> > + if (pipe_supports_yuv(mdp4_plane->caps)) {
> > + formats = mdp4_rgb_yuv_formats;
> > + nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
> > + } else {
> > + formats = mdp4_rgb_formats;
> > + nformats = ARRAY_SIZE(mdp4_rgb_formats);
> > + }
>
>
> Also, from what I checked the format table is identical between mdp4 and
> mdp5. Even if we cannot unify mdp4/5 and dpu tables, we can atleast have
> mdp_4_5_rgb and mdp_4_5_rgb_yuv?
I'd rather not do that. If we are to change mdp4 or mdp5 planes at
some point, I don't want to think about the second driver. The amount
of duplication is minimal compared to the burden of thinking about the
second driver.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 04/12] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware
2024-04-19 21:21 ` Dmitry Baryshkov
@ 2024-04-19 21:57 ` Abhinav Kumar
0 siblings, 0 replies; 39+ messages in thread
From: Abhinav Kumar @ 2024-04-19 21:57 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Sean Paul, Marijn Suijten, Stephen Boyd, David Airlie,
Daniel Vetter, Bjorn Andersson, linux-arm-msm, dri-devel,
freedreno
On 4/19/2024 2:21 PM, Dmitry Baryshkov wrote:
> On Sat, 20 Apr 2024 at 00:06, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 12/2/2023 1:40 PM, Dmitry Baryshkov wrote:
>>> MDP4 and MDP5 drivers enumerate supported formats each time the plane is
>>> created. In preparation to merger of MDP DPU format databases, define
>>> precise formats list, so that changes to the database do not cause the
>>> driver to add unsupported format to the list.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 57 ++++++++++++++++++++--
>>> drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 36 +++++++++++---
>>> drivers/gpu/drm/msm/disp/mdp_format.c | 28 -----------
>>> drivers/gpu/drm/msm/disp/mdp_kms.h | 1 -
>>> 4 files changed, 80 insertions(+), 42 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
>>> index b689b618da78..cebe20c82a54 100644
>>> --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
>>> @@ -371,6 +371,47 @@ static const uint64_t supported_format_modifiers[] = {
>>> DRM_FORMAT_MOD_INVALID
>>> };
>>>
>>> +const uint32_t mdp4_rgb_formats[] = {
>>> + DRM_FORMAT_ARGB8888,
>>> + DRM_FORMAT_ABGR8888,
>>> + DRM_FORMAT_RGBA8888,
>>> + DRM_FORMAT_BGRA8888,
>>> + DRM_FORMAT_XRGB8888,
>>> + DRM_FORMAT_XBGR8888,
>>> + DRM_FORMAT_RGBX8888,
>>> + DRM_FORMAT_BGRX8888,
>>> + DRM_FORMAT_RGB888,
>>> + DRM_FORMAT_BGR888,
>>> + DRM_FORMAT_RGB565,
>>> + DRM_FORMAT_BGR565,
>>> +};
>>> +
>>> +const uint32_t mdp4_rgb_yuv_formats[] = {
>>> + DRM_FORMAT_ARGB8888,
>>> + DRM_FORMAT_ABGR8888,
>>> + DRM_FORMAT_RGBA8888,
>>> + DRM_FORMAT_BGRA8888,
>>> + DRM_FORMAT_XRGB8888,
>>> + DRM_FORMAT_XBGR8888,
>>> + DRM_FORMAT_RGBX8888,
>>> + DRM_FORMAT_BGRX8888,
>>> + DRM_FORMAT_RGB888,
>>> + DRM_FORMAT_BGR888,
>>> + DRM_FORMAT_RGB565,
>>> + DRM_FORMAT_BGR565,
>>> +
>>> + DRM_FORMAT_NV12,
>>> + DRM_FORMAT_NV21,
>>> + DRM_FORMAT_NV16,
>>> + DRM_FORMAT_NV61,
>>> + DRM_FORMAT_VYUY,
>>> + DRM_FORMAT_UYVY,
>>> + DRM_FORMAT_YUYV,
>>> + DRM_FORMAT_YVYU,
>>> + DRM_FORMAT_YUV420,
>>> + DRM_FORMAT_YVU420,
>>> +};
>>> +
>>> /* initialize plane */
>>> struct drm_plane *mdp4_plane_init(struct drm_device *dev,
>>> enum mdp4_pipe pipe_id, bool private_plane)
>>> @@ -379,6 +420,8 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
>>> struct mdp4_plane *mdp4_plane;
>>> int ret;
>>> enum drm_plane_type type;
>>> + const uint32_t *formats;
>>> + unsigned int nformats;
>>>
>>> mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
>>> if (!mdp4_plane) {
>>> @@ -392,13 +435,17 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
>>> mdp4_plane->name = pipe_names[pipe_id];
>>> mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
>>>
>>> - mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
>>> - ARRAY_SIZE(mdp4_plane->formats),
>>> - !pipe_supports_yuv(mdp4_plane->caps));
>>> -
>>> type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
>>> +
>>> + if (pipe_supports_yuv(mdp4_plane->caps)) {
>>> + formats = mdp4_rgb_yuv_formats;
>>> + nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
>>> + } else {
>>> + formats = mdp4_rgb_formats;
>>> + nformats = ARRAY_SIZE(mdp4_rgb_formats);
>>> + }
>>> ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
>>> - mdp4_plane->formats, mdp4_plane->nformats,
>>> + formats, nformats,
>>> supported_format_modifiers, type, NULL);
>>> if (ret)
>>> goto fail;
>>> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
>>> index 0d5ff03cb091..aa8342d93393 100644
>>> --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
>>> +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
>>> @@ -17,9 +17,6 @@
>>>
>>> struct mdp5_plane {
>>> struct drm_plane base;
>>> -
>>> - uint32_t nformats;
>>> - uint32_t formats[32];
>>> };
>>> #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
>>>
>>> @@ -1007,6 +1004,32 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
>>> return mask;
>>> }
>>>
>>> +const uint32_t mdp5_plane_formats[] = {
>>> + DRM_FORMAT_ARGB8888,
>>> + DRM_FORMAT_ABGR8888,
>>> + DRM_FORMAT_RGBA8888,
>>> + DRM_FORMAT_BGRA8888,
>>> + DRM_FORMAT_XRGB8888,
>>> + DRM_FORMAT_XBGR8888,
>>> + DRM_FORMAT_RGBX8888,
>>> + DRM_FORMAT_BGRX8888,
>>> + DRM_FORMAT_RGB888,
>>> + DRM_FORMAT_BGR888,
>>> + DRM_FORMAT_RGB565,
>>> + DRM_FORMAT_BGR565,
>>> +
>>> + DRM_FORMAT_NV12,
>>> + DRM_FORMAT_NV21,
>>> + DRM_FORMAT_NV16,
>>> + DRM_FORMAT_NV61,
>>> + DRM_FORMAT_VYUY,
>>> + DRM_FORMAT_UYVY,
>>> + DRM_FORMAT_YUYV,
>>> + DRM_FORMAT_YVYU,
>>> + DRM_FORMAT_YUV420,
>>> + DRM_FORMAT_YVU420,
>>> +};
>>> +
>>> /* initialize plane */
>>> struct drm_plane *mdp5_plane_init(struct drm_device *dev,
>>> enum drm_plane_type type)
>>> @@ -1023,12 +1046,9 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
>>>
>>> plane = &mdp5_plane->base;
>>>
>>> - mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
>>> - ARRAY_SIZE(mdp5_plane->formats), false);
>>> -
>>> ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
>>> - mdp5_plane->formats, mdp5_plane->nformats,
>>> - NULL, type, NULL);
>>> + mdp5_plane_formats, ARRAY_SIZE(mdp5_plane_formats),
>>> + NULL, type, NULL);
>>> if (ret)
>>> goto fail;
>>>
>>
>> Did you accidentally drop checking for YUV format cap before adding the
>> formats for the plane similar to
>
> No. MDP5 driver asks RGB+YUV planes see the mdp_get_formats() arguments.
>
Ack.
>>
>> > + if (pipe_supports_yuv(mdp4_plane->caps)) {
>> > + formats = mdp4_rgb_yuv_formats;
>> > + nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
>> > + } else {
>> > + formats = mdp4_rgb_formats;
>> > + nformats = ARRAY_SIZE(mdp4_rgb_formats);
>> > + }
>>
>>
>> Also, from what I checked the format table is identical between mdp4 and
>> mdp5. Even if we cannot unify mdp4/5 and dpu tables, we can atleast have
>> mdp_4_5_rgb and mdp_4_5_rgb_yuv?
>
> I'd rather not do that. If we are to change mdp4 or mdp5 planes at
> some point, I don't want to think about the second driver. The amount
> of duplication is minimal compared to the burden of thinking about the
> second driver.
>
Ok, I dont expect them to change tbh as it has not happened last few
years now.
Anyway, that part is fine. Hence
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2024-04-19 21:57 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-12-02 21:40 [PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database Dmitry Baryshkov
2023-12-02 21:40 ` [PATCH 01/12] drm/msm: fix BPC1 -> BPC4 Dmitry Baryshkov
2024-04-10 19:15 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 02/12] drm/msm/disp: add mdp_fetch_mode enum Dmitry Baryshkov
2024-04-10 19:19 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h Dmitry Baryshkov
2024-04-10 20:00 ` Abhinav Kumar
2024-04-10 20:16 ` Dmitry Baryshkov
2024-04-10 20:18 ` Abhinav Kumar
2024-04-10 21:12 ` Dmitry Baryshkov
2024-04-10 23:54 ` Abhinav Kumar
2024-04-11 1:20 ` Dmitry Baryshkov
2024-04-11 1:21 ` Dmitry Baryshkov
2024-04-11 2:38 ` Dmitry Baryshkov
2024-04-19 20:59 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 04/12] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware Dmitry Baryshkov
2024-04-19 21:06 ` Abhinav Kumar
2024-04-19 21:21 ` Dmitry Baryshkov
2024-04-19 21:57 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 05/12] drm/msm/dpu: in dpu_format replace bitmap with unsigned long field Dmitry Baryshkov
2024-04-10 20:40 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 06/12] drm/msm/dpu: pull format flag definitions to msm_drv.h Dmitry Baryshkov
2024-04-11 18:41 ` Abhinav Kumar
2024-04-11 18:42 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 07/12] drm/msm: merge dpu_format and mdp_format in struct msm_format Dmitry Baryshkov
2024-04-11 19:15 ` Abhinav Kumar
2024-04-11 19:17 ` Dmitry Baryshkov
2023-12-02 21:40 ` [PATCH 08/12] drm/msm: convert msm_format::unpack_tight to the flag Dmitry Baryshkov
2024-04-11 21:02 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 09/12] drm/msm: convert msm_format::unpack_align_msb " Dmitry Baryshkov
2024-04-11 21:13 ` Abhinav Kumar
2023-12-02 21:40 ` [PATCH 10/12] drm/msm: convert msm_format::alpha_enable " Dmitry Baryshkov
2024-04-11 21:20 ` Abhinav Kumar
2024-04-11 21:42 ` Dmitry Baryshkov
2023-12-02 21:40 ` [PATCH 11/12] drm/msm: merge dpu format database to MDP formats Dmitry Baryshkov
2024-04-12 19:47 ` Abhinav Kumar
2024-04-13 6:02 ` Dmitry Baryshkov
2023-12-02 21:40 ` [PATCH 12/12] drm/msm: drop msm_kms_funcs::get_format() callback Dmitry Baryshkov
2024-04-12 21:40 ` Abhinav Kumar
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