From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Chen-Yu Tsai <wens@csie.org>,
Maxime Ripard <maxime.ripard@bootlin.com>
Cc: devicetree@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Arnd Bergmann <arnd@arndb.de>,
dri-devel@lists.freedesktop.org,
Georgi Djakov <georgi.djakov@linaro.org>,
Paul Kocialkowski <paul.kocialkowski@bootlin.com>,
Yong Deng <yong.deng@magewell.com>,
Robin Murphy <robin.murphy@arm.com>,
Dave Martin <dave.martin@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 2/7] dt-bindings: bus: Add binding for the Allwinner MBUS controller
Date: Thu, 14 Mar 2019 21:26:01 +0100 [thread overview]
Message-ID: <c991c14130f624285d1aceeeb5c1b2edf5ac8b69.1552595146.git-series.maxime.ripard@bootlin.com> (raw)
In-Reply-To: <cover.221220f2f28e14ef07cce84e753ac662085d84ff.1552595146.git-series.maxime.ripard@bootlin.com>
The MBUS controller drives the MBUS that other devices in the SoC will
use to perform DMA. It also has a register interface that allows to
monitor and control the bandwidth and priorities for masters on that
bus.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt | 36 +++++++-
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt
diff --git a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt
new file mode 100644
index 000000000000..1464a4713553
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt
@@ -0,0 +1,36 @@
+Allwinner Memory Bus (MBUS) controller
+
+The MBUS controller drives the MBUS that other devices in the SoC will
+use to perform DMA. It also has a register interface that allows to
+monitor and control the bandwidth and priorities for masters on that
+bus.
+
+Required properties:
+ - compatible: Must be one of:
+ - allwinner,sun5i-a13-mbus
+ - reg: Offset and length of the register set for the controller
+ - clocks: phandle to the clock driving the controller
+ - dma-ranges: See section 2.3.9 of the DeviceTree Specification
+ - #interconnect-cells: Must be one, with the argument being the MBUS
+ port ID
+
+Each device having to perform their DMA through the MBUS must have the
+interconnects and interconnect-names properties set to the MBUS
+controller and with "dma-mem" as the interconnect name.
+
+Example:
+
+mbus: dram-controller@1c01000 {
+ compatible = "allwinner,sun5i-a13-mbus";
+ reg = <0x01c01000 0x1000>;
+ clocks = <&ccu CLK_MBUS>;
+ dma-ranges = <0x00000000 0x40000000 0x20000000>;
+ #interconnect-cells = <1>;
+};
+
+fe0: display-frontend@1e00000 {
+ compatible = "allwinner,sun5i-a13-display-frontend";
+ ...
+ interconnects = <&mbus 19>;
+ interconnect-names = "dma-mem";
+};
--
git-series 0.9.1
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next prev parent reply other threads:[~2019-03-14 20:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-14 20:25 [PATCH v4 0/7] sunxi: Add DT representation for the MBUS controller Maxime Ripard
2019-03-14 20:26 ` [PATCH v4 1/7] dt-bindings: interconnect: Add a dma interconnect name Maxime Ripard
2019-03-22 16:46 ` Georgi Djakov
2019-03-14 20:26 ` Maxime Ripard [this message]
2019-03-14 20:26 ` [PATCH v4 3/7] of: address: Add parent pointer to the __of_translate_address args Maxime Ripard
2019-03-27 12:40 ` Robin Murphy
2019-03-14 20:26 ` [PATCH v4 4/7] of: address: Add support for the parent DMA bus Maxime Ripard
2019-03-27 12:46 ` Robin Murphy
2019-03-14 20:26 ` [PATCH v4 5/7] drm/sun4i: Rely on dma interconnect for our RAM offset Maxime Ripard
2019-03-27 12:50 ` Robin Murphy
2019-03-14 20:26 ` [PATCH v4 6/7] clk: sunxi-ng: sun5i: Export the MBUS clock Maxime Ripard
2019-03-14 20:26 ` [PATCH v4 7/7] ARM: dts: sun5i: Add the MBUS controller Maxime Ripard
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