[PATCH 0/2] drm/rockchip: dw_hdmi: Add 4k@30 support

[PATCH 0/2] drm/rockchip: dw_hdmi: Add 4k@30 support

[Sascha Hauer]

This series adds support for 4k@30 to the rockchip HDMI controller. This
has been tested on a rk3568 rock3a board. It should be possible to add
4k@60 support the same way, but it doesn't work for me, so let's add
4k@30 as a first step.

Sascha

Sascha Hauer (2):
  drm/rockchip: dw_hdmi: relax mode_valid hook
  drm/rockchip: dw_hdmi: Add support for 4k@30 resolution

 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

-- 
2.30.2

[PATCH 1/2] drm/rockchip: dw_hdmi: relax mode_valid hook

[Sascha Hauer]

The driver checks if the pixel clock of the given mode matches an entry
in the mpll config table. The frequencies in the mpll table are meant as
a frequency range up to which the entry works, not as a frequency that
must match the pixel clock. Return MODE_OK when the pixelclock is
smaller than one of the mpll frequencies to allow for more display
resolutions.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index c14f888938688..b6b662dabedc6 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -251,7 +251,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
 	int i;
 
 	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
-		if (pclk == mpll_cfg[i].mpixelclock) {
+		if (pclk <= mpll_cfg[i].mpixelclock) {
 			valid = true;
 			break;
 		}
-- 
2.30.2

Re: [PATCH 1/2] drm/rockchip: dw_hdmi: relax mode_valid hook

[Robin Murphy]

On 2022-08-22 16:20, Sascha Hauer wrote:
> The driver checks if the pixel clock of the given mode matches an entry
> in the mpll config table. The frequencies in the mpll table are meant as
> a frequency range up to which the entry works, not as a frequency that
> must match the pixel clock. Return MODE_OK when the pixelclock is
> smaller than one of the mpll frequencies to allow for more display
> resolutions.

Has the issue been fixed that this table is also used to validate modes 
on RK3328, which doesn't even *have* the Synopsys phy? Last time I 
looked, that tended to lead to complete display breakage when the proper 
phy driver later decides it doesn't like a pixel clock that mode_valid 
already said was OK.

The more general concern is that these known-good clock rates are good, 
but others may not be even when nominally supported, which I suspect is 
the dirty secret of why it was implemented this way to begin with. I 
would really really love this patch so my RK3399 board can drive my 
1920x1200 monitor at native resolution, but on the other hand my RK3288 
box generates such a crap 154MHz clock for that mode that - unless 
that's been improved in the meantime too - patch #2 might be almost be 
considered a regression if it means such a setup would start defaulting 
to an unusably glitchy display instead of falling back to 1920x1080 
which does at least work perfectly (even if the slightly squished aspect 
ratio is ugly).

Thanks,
Robin.

> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>   drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> index c14f888938688..b6b662dabedc6 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> @@ -251,7 +251,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
>   	int i;
>   
>   	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
> -		if (pclk == mpll_cfg[i].mpixelclock) {
> +		if (pclk <= mpll_cfg[i].mpixelclock) {
>   			valid = true;
>   			break;
>   		}

Re: [PATCH 1/2] drm/rockchip: dw_hdmi: relax mode_valid hook

[Sascha Hauer]

On Wed, Aug 24, 2022 at 05:07:50PM +0100, Robin Murphy wrote:
> On 2022-08-22 16:20, Sascha Hauer wrote:
> > The driver checks if the pixel clock of the given mode matches an entry
> > in the mpll config table. The frequencies in the mpll table are meant as
> > a frequency range up to which the entry works, not as a frequency that
> > must match the pixel clock. Return MODE_OK when the pixelclock is
> > smaller than one of the mpll frequencies to allow for more display
> > resolutions.
> 
> Has the issue been fixed that this table is also used to validate modes on
> RK3328, which doesn't even *have* the Synopsys phy? Last time I looked, that
> tended to lead to complete display breakage when the proper phy driver later
> decides it doesn't like a pixel clock that mode_valid already said was OK.
> 
> The more general concern is that these known-good clock rates are good, but
> others may not be even when nominally supported, which I suspect is the
> dirty secret of why it was implemented this way to begin with. I would
> really really love this patch so my RK3399 board can drive my 1920x1200
> monitor at native resolution, but on the other hand my RK3288 box generates
> such a crap 154MHz clock for that mode that - unless that's been improved in
> the meantime too - patch #2 might be almost be considered a regression if it
> means such a setup would start defaulting to an unusably glitchy display
> instead of falling back to 1920x1080 which does at least work perfectly
> (even if the slightly squished aspect ratio is ugly).

I could limit the change to rk3568 only. Would that be an option?
Not sure if I should rk3399 as well then as this would work, at least in
your setup.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 1/2] drm/rockchip: dw_hdmi: relax mode_valid hook

[Robin Murphy]

On 25/08/2022 12:40 pm, Sascha Hauer wrote:
> On Wed, Aug 24, 2022 at 05:07:50PM +0100, Robin Murphy wrote:
>> On 2022-08-22 16:20, Sascha Hauer wrote:
>>> The driver checks if the pixel clock of the given mode matches an entry
>>> in the mpll config table. The frequencies in the mpll table are meant as
>>> a frequency range up to which the entry works, not as a frequency that
>>> must match the pixel clock. Return MODE_OK when the pixelclock is
>>> smaller than one of the mpll frequencies to allow for more display
>>> resolutions.
>>
>> Has the issue been fixed that this table is also used to validate modes on
>> RK3328, which doesn't even *have* the Synopsys phy? Last time I looked, that
>> tended to lead to complete display breakage when the proper phy driver later
>> decides it doesn't like a pixel clock that mode_valid already said was OK.
>>
>> The more general concern is that these known-good clock rates are good, but
>> others may not be even when nominally supported, which I suspect is the
>> dirty secret of why it was implemented this way to begin with. I would
>> really really love this patch so my RK3399 board can drive my 1920x1200
>> monitor at native resolution, but on the other hand my RK3288 box generates
>> such a crap 154MHz clock for that mode that - unless that's been improved in
>> the meantime too - patch #2 might be almost be considered a regression if it
>> means such a setup would start defaulting to an unusably glitchy display
>> instead of falling back to 1920x1080 which does at least work perfectly
>> (even if the slightly squished aspect ratio is ugly).
> 
> I could limit the change to rk3568 only. Would that be an option?
> Not sure if I should rk3399 as well then as this would work, at least in
> your setup.

I think for now it might be enough to force an exact match if 
hdmi->plat_data.phy_force_vendor is set, with a big fat comment that 
it's to preserve the previous behaviour until vendor phy support can be 
sorted out properly. Beyond that, given that RK3288 and RK3399 do 
nominally support 4K as well, I don't think we actually have to leave 
them out, I just wanted to flag up that untested non-standard clock 
rates are a known source of potential issues once we open the door to them.

Cheers,
Robin.

[PATCH 2/2] drm/rockchip: dw_hdmi: Add support for 4k@30 resolution

[Sascha Hauer]

This adds the PLL/phy settings to support higher resolutions like 4k@30.
The values were taken from the Rockchip downstream Kernel.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index b6b662dabedc6..5d1cc36406aca 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -160,6 +160,12 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
 			{ 0x214c, 0x0003},
 			{ 0x4064, 0x0003}
 		},
+	}, {
+		340000000, {
+			{ 0x0052, 0x0003 },
+			{ 0x214d, 0x0003 },
+			{ 0x4065, 0x0003 },
+		},
 	}, {
 		~0UL, {
 			{ 0x00a0, 0x000a },
@@ -185,6 +191,8 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 		146250000, { 0x0038, 0x0038, 0x0038 },
 	}, {
 		148500000, { 0x0000, 0x0038, 0x0038 },
+	}, {
+		600000000, { 0x0000, 0x0000, 0x0000 },
 	}, {
 		~0UL,      { 0x0000, 0x0000, 0x0000},
 	}
-- 
2.30.2

Re: [PATCH 0/2] drm/rockchip: dw_hdmi: Add 4k@30 support

[Michael Riesch]

Hi Sascha,

Can you Cc: linux-rockchip list to get more feedback?

On 8/22/22 17:20, Sascha Hauer wrote:
> This series adds support for 4k@30 to the rockchip HDMI controller. This
> has been tested on a rk3568 rock3a board. It should be possible to add
> 4k@60 support the same way, but it doesn't work for me, so let's add
> 4k@30 as a first step.
> 
> Sascha
> 
> Sascha Hauer (2):
>   drm/rockchip: dw_hdmi: relax mode_valid hook
>   drm/rockchip: dw_hdmi: Add support for 4k@30 resolution

Great stuff, thanks!

On a Radxa ROCK3 Model A with a HP 27f 4k monitor

Tested-by: Michael Riesch <michael.riesch@wolfvision.net>

Best regards,
Michael

> 
>  drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 

Re: [PATCH 0/2] drm/rockchip: dw_hdmi: Add 4k@30 support

[Sascha Hauer]

On Wed, Aug 24, 2022 at 07:43:03AM +0200, Michael Riesch wrote:
> Hi Sascha,
> 
> Can you Cc: linux-rockchip list to get more feedback?

Yes, will do that next time.

> 
> On 8/22/22 17:20, Sascha Hauer wrote:
> > This series adds support for 4k@30 to the rockchip HDMI controller. This
> > has been tested on a rk3568 rock3a board. It should be possible to add
> > 4k@60 support the same way, but it doesn't work for me, so let's add
> > 4k@30 as a first step.
> > 
> > Sascha
> > 
> > Sascha Hauer (2):
> >   drm/rockchip: dw_hdmi: relax mode_valid hook
> >   drm/rockchip: dw_hdmi: Add support for 4k@30 resolution
> 
> Great stuff, thanks!
> 
> On a Radxa ROCK3 Model A with a HP 27f 4k monitor
> 
> Tested-by: Michael Riesch <michael.riesch@wolfvision.net>

Thanks

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 0/2] drm/rockchip: dw_hdmi: Add 4k@30 support

[Sascha Hauer]

Hi Andy Et al.,

On Mon, Aug 22, 2022 at 05:20:15PM +0200, Sascha Hauer wrote:
> This series adds support for 4k@30 to the rockchip HDMI controller. This
> has been tested on a rk3568 rock3a board. It should be possible to add
> 4k@60 support the same way, but it doesn't work for me, so let's add
> 4k@30 as a first step.

I tried adding 4k@60 support the same way, just by adding the missing
fields for 600MHz in the PLL/phy settings. I get a picture on the
screen, but it's not very stable: The monitor often gets black, scans
through the different HDMI inputs and then syncs again. Also when I
re-plug the cable while weston is running I won't get any picture
anymore (the same works fine with lower resolutions). I also tried
the Rock3a 4.19 Kernel which is based on the Rockchip Kernel and I saw
similar problems there.

Do you have an idea what could go wrong there?

Sascha


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 0/2] drm/rockchip: dw_hdmi: Add 4k@30 support

[Andy Yan]

Hi Sascha:

On 8/24/22 15:07, Sascha Hauer wrote:
> Hi Andy Et al.,
>
> On Mon, Aug 22, 2022 at 05:20:15PM +0200, Sascha Hauer wrote:
>> This series adds support for 4k@30 to the rockchip HDMI controller. This
>> has been tested on a rk3568 rock3a board. It should be possible to add
>> 4k@60 support the same way, but it doesn't work for me, so let's add
>> 4k@30 as a first step.
> I tried adding 4k@60 support the same way, just by adding the missing
> fields for 600MHz in the PLL/phy settings. I get a picture on the
> screen, but it's not very stable: The monitor often gets black, scans
> through the different HDMI inputs and then syncs again. Also when I
> re-plug the cable while weston is running I won't get any picture
> anymore (the same works fine with lower resolutions). I also tried
> the Rock3a 4.19 Kernel which is based on the Rockchip Kernel and I saw
> similar problems there.
>
> Do you have an idea what could go wrong there?


4K HDMI output from hdmi need very carefully tuning  of HDMI PHY and PLL.

I can make sure that HDMI 4K output on rk3399/rk3288/rk356x are work 
fine with our

vendor kernel, but the upstream kernel is only can run at 1080p output, 
I have tested

on rk3399 and rk3568-evb1[0]


I am not  familiar with hdmi tuning, so I am sorry i can't give detail 
idea about this issue,

maybe a more carefully comparison with hdmi driver and pll 
configuration  between upstream kernel and rockchip 4.19 kernel?

I think you have rk356x evb board, do you have a detail test about 4K 
HDMI output with this board? If you have issue about 4k hdmi output

on this board with rockchip 4.19 kernel, we can help to figure it out.

Anyway, I loop Algea to the list, he is maintaining our hdmi 
development, but I am sorry to say that he is

also very busy😅

I don't have a rock3a, so I can't confirm the problem you described on 
4.19 kernel.




[0]https://patchwork.kernel.org/project/linux-rockchip/patch/20220225075150.2729401-16-s.hauer@pengutronix.de/



>
> Sascha
>
>