* [PATCH v4 00/19] drm/msm/dpu: another catalog rework
@ 2023-06-19 21:25 Dmitry Baryshkov
2023-06-19 21:25 ` [PATCH v4 01/19] drm/msm: enumerate DSI interfaces Dmitry Baryshkov
` (18 more replies)
0 siblings, 19 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
Having a macro with 10 arguments doesn't seem like a good idea. It makes
it inherently harder to compare the actual structure values. Also this
leads to adding macros covering varieties of the block.
As it was previously discussed, inline all foo_BLK macros in order to
ease performing changes to the catalog data.
Major part of the conversion was performed using vim script found at
[1]. Then some manual cleanups were applied, like dropping fields set to
0.
Dependencies: msm-next-lumag.
Changes since v3:
- Fixed DSC 1.1 block length to 0x140 (Marijn)
- Fixed mdp->caps assignment in dpu_hw_mdptop_init() (Marijn)
Changes since v2:
- Rebased on top of msm-next-lumag
- Fixed MSM_DP/DSI_CONTROLLER_n usage in sm6350 and sm6375 catalog data
(Abhinav, Marijn).
Changes since v1:
- Rebased on top of msm-next
- Dropped dependency on interrupt rework
[1] https://pastebin.ubuntu.com/p/K6vkjmxZdd/
Dmitry Baryshkov (19):
drm/msm: enumerate DSI interfaces
drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n
drm/msm/dpu: simplify peer LM handling
drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
drm/msm/dpu: drop enum dpu_mdp and MDP_TOP value
drm/msm/dpu: expand .clk_ctrls definitions
drm/msm/dpu: drop zero features from dpu_mdp_cfg data
drm/msm/dpu: drop zero features from dpu_ctl_cfg data
drm/msm/dpu: correct indentation for CTL definitions
drm/msm/dpu: inline SSPP_BLK macros
drm/msm/dpu: inline DSPP_BLK macros
drm/msm/dpu: inline LM_BLK macros
drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros
drm/msm/dpu: inline MERGE_3D_BLK macros
drm/msm/dpu: inline various PP_BLK_* macros
drm/msm/dpu: inline WB_BLK macros
drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros
drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK
drm/msm/dpu: drop empty features mask INTF_SDM845_MASK
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 327 ++++++++----
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 348 +++++++++----
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 411 ++++++++++-----
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 448 +++++++++++-----
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 430 +++++++++++-----
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 184 +++++--
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 88 +++-
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 188 ++++---
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 88 +++-
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 95 +++-
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 418 ++++++++++-----
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 244 ++++++---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 484 +++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 445 +++++++++++-----
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 467 ++++++++++++-----
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 130 -----
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 37 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 9 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 34 +-
drivers/gpu/drm/msm/msm_drv.h | 8 +-
23 files changed, 3321 insertions(+), 1576 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v4 01/19] drm/msm: enumerate DSI interfaces
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-19 21:25 ` [PATCH v4 02/19] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n Dmitry Baryshkov
` (17 subsequent siblings)
18 siblings, 0 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
Follow the DP example and define MSM_DSI_CONTROLLER_n enumeration.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/msm_drv.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index e13a8cbd61c9..ad4fad2bcdc8 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -65,6 +65,12 @@ enum msm_dp_controller {
MSM_DP_CONTROLLER_COUNT,
};
+enum msm_dsi_controller {
+ MSM_DSI_CONTROLLER_0,
+ MSM_DSI_CONTROLLER_1,
+ MSM_DSI_CONTROLLER_COUNT,
+};
+
#define MSM_GPU_MAX_RINGS 4
#define MAX_H_TILES_PER_DISPLAY 2
@@ -117,7 +123,7 @@ struct msm_drm_private {
struct hdmi *hdmi;
/* DSI is shared by mdp4 and mdp5 */
- struct msm_dsi *dsi[2];
+ struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT];
struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 02/19] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
2023-06-19 21:25 ` [PATCH v4 01/19] drm/msm: enumerate DSI interfaces Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-07-03 0:53 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 03/19] drm/msm/dpu: simplify peer LM handling Dmitry Baryshkov
` (16 subsequent siblings)
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
In several catalog entries we did not use existing MSM_DP_CONTROLLER_n
constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n
for DSI interfaces.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 ++++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 ++++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 8 ++++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++--
15 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 7d0d0e74c3b0..be0514bf27ec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -139,13 +139,13 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
};
static const struct dpu_intf_cfg msm8998_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK,
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK,
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
- INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK,
+ INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index b6098141bb9b..b33472625fcb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -143,16 +143,16 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
};
static const struct dpu_intf_cfg sdm845_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK,
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK,
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
- INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK,
+ INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK,
+ INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index b5f751354267..64ed10da1b73 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -162,18 +162,18 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
};
static const struct dpu_intf_cfg sm8150_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
+ INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 8ed2b263c5ea..6ae1f6f67ec8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -166,11 +166,11 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index daebd2170041..48c97e9f8a45 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -163,18 +163,18 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
};
static const struct dpu_intf_cfg sm8250_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
+ INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 67566b07195a..00366f7fe969 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -92,7 +92,7 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 031fc8dae3c6..8688f09dd560 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -66,7 +66,7 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
};
static const struct dpu_intf_cfg sm6115_intf[] = {
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 06eba23b0236..2bb2346d27a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -102,10 +102,10 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
};
static const struct dpu_intf_cfg sm6350_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 35, INTF_SC7180_MASK,
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 35, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 35, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index f2808098af39..d106ff28372d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -63,7 +63,7 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
};
static const struct dpu_intf_cfg qcm2290_intf[] = {
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 241fa6746674..842ea5bcbe16 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -71,7 +71,7 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
};
static const struct dpu_intf_cfg sm6375_intf[] = {
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 8da424eaee6a..8fa9d83a539d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -169,11 +169,11 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+ INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 900fee410e11..2862c64bbc3e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -116,7 +116,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index f6ce6b090f71..520b210e8c0c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -161,11 +161,11 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+ INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 8d13c369213c..b782603642f4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -177,11 +177,11 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+ INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index f17b9a7fee85..025a149bab97 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -181,11 +181,11 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+ INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 03/19] drm/msm/dpu: simplify peer LM handling
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
2023-06-19 21:25 ` [PATCH v4 01/19] drm/msm: enumerate DSI interfaces Dmitry Baryshkov
2023-06-19 21:25 ` [PATCH v4 02/19] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-07-03 1:34 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field Dmitry Baryshkov
` (15 subsequent siblings)
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
For each LM there is at max 1 peer LM which can be driven by the same
CTL, so there no need to have a mask instead of just an ID of the peer
LM.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 34 +++++++------------
3 files changed, 15 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 0de507d4d7b7..30fb5b1f3966 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -394,7 +394,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
.features = _fmask, \
.sblk = _sblk, \
.pingpong = _pp, \
- .lm_pair_mask = (1 << _lmpair), \
+ .lm_pair = _lmpair, \
.dspp = _dspp \
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index b860784ade72..b07caa4b867e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -554,14 +554,14 @@ struct dpu_sspp_cfg {
* @features bit mask identifying sub-blocks/features
* @sblk: LM Sub-blocks information
* @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported
- * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
+ * @lm_pair: ID of LM that can be controlled by same CTL
*/
struct dpu_lm_cfg {
DPU_HW_BLK_INFO;
const struct dpu_lm_sub_blks *sblk;
u32 pingpong;
u32 dspp;
- unsigned long lm_pair_mask;
+ unsigned long lm_pair;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 471842bbb950..e333f4eeafc1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -253,28 +253,19 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
}
/**
- * _dpu_rm_check_lm_peer - check if a mixer is a peer of the primary
+ * _dpu_rm_get_lm_peer - get the id of a mixer which is a peer of the primary
* @rm: dpu resource manager handle
* @primary_idx: index of primary mixer in rm->mixer_blks[]
- * @peer_idx: index of other mixer in rm->mixer_blks[]
- * Return: true if rm->mixer_blks[peer_idx] is a peer of
- * rm->mixer_blks[primary_idx]
*/
-static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx,
- int peer_idx)
+static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx)
{
const struct dpu_lm_cfg *prim_lm_cfg;
- const struct dpu_lm_cfg *peer_cfg;
prim_lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[primary_idx])->cap;
- peer_cfg = to_dpu_hw_mixer(rm->mixer_blks[peer_idx])->cap;
- if (!test_bit(peer_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
- DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id,
- peer_cfg->id);
- return false;
- }
- return true;
+ if (prim_lm_cfg->lm_pair >= LM_0 && prim_lm_cfg->lm_pair < LM_MAX)
+ return prim_lm_cfg->lm_pair - LM_0;
+ return -EINVAL;
}
/**
@@ -351,7 +342,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
int lm_idx[MAX_BLOCKS];
int pp_idx[MAX_BLOCKS];
int dspp_idx[MAX_BLOCKS] = {0};
- int i, j, lm_count = 0;
+ int i, lm_count = 0;
if (!reqs->topology.num_lm) {
DPU_ERROR("invalid number of lm: %d\n", reqs->topology.num_lm);
@@ -376,16 +367,15 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
++lm_count;
/* Valid primary mixer found, find matching peers */
- for (j = i + 1; j < ARRAY_SIZE(rm->mixer_blks) &&
- lm_count < reqs->topology.num_lm; j++) {
- if (!rm->mixer_blks[j])
+ if (lm_count < reqs->topology.num_lm) {
+ int j = _dpu_rm_get_lm_peer(rm, i);
+
+ /* ignore the peer if there is an error or if the peer was already processed */
+ if (j < 0 || j < i)
continue;
- if (!_dpu_rm_check_lm_peer(rm, i, j)) {
- DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j,
- LM_0 + i);
+ if (!rm->mixer_blks[j])
continue;
- }
if (!_dpu_rm_check_lm_and_get_connected_blks(rm,
global_state, enc_id, j,
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (2 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 03/19] drm/msm/dpu: simplify peer LM handling Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-26 12:28 ` Marijn Suijten
2023-07-03 2:01 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 05/19] drm/msm/dpu: drop enum dpu_mdp and MDP_TOP value Dmitry Baryshkov
` (14 subsequent siblings)
18 siblings, 2 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
There is always a single MDP TOP block. Drop the mdp_count field and
stop declaring dpu_mdp_cfg instances as arrays.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38 +++----------------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
19 files changed, 41 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index be0514bf27ec..e0d2ee48d733 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
.highest_bank_bit = 0x2,
};
-static const struct dpu_mdp_cfg msm8998_mdp[] = {
- {
+static const struct dpu_mdp_cfg msm8998_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x458,
.features = BIT(DPU_MDP_VSYNC_SEL),
@@ -41,7 +40,6 @@ static const struct dpu_mdp_cfg msm8998_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
- },
};
static const struct dpu_ctl_cfg msm8998_ctl[] = {
@@ -192,8 +190,7 @@ static const struct dpu_perf_cfg msm8998_perf_data = {
const struct dpu_mdss_cfg dpu_msm8998_cfg = {
.caps = &msm8998_dpu_caps,
.ubwc = &msm8998_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(msm8998_mdp),
- .mdp = msm8998_mdp,
+ .mdp = &msm8998_mdp,
.ctl_count = ARRAY_SIZE(msm8998_ctl),
.ctl = msm8998_ctl,
.sspp_count = ARRAY_SIZE(msm8998_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index b33472625fcb..72295d5a10dc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = {
.highest_bank_bit = 0x2,
};
-static const struct dpu_mdp_cfg sdm845_mdp[] = {
- {
+static const struct dpu_mdp_cfg sdm845_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x45c,
.features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL),
@@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- },
};
static const struct dpu_ctl_cfg sdm845_ctl[] = {
@@ -196,8 +194,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
const struct dpu_mdss_cfg dpu_sdm845_cfg = {
.caps = &sdm845_dpu_caps,
.ubwc = &sdm845_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sdm845_mdp),
- .mdp = sdm845_mdp,
+ .mdp = &sdm845_mdp,
.ctl_count = ARRAY_SIZE(sdm845_ctl),
.ctl = sdm845_ctl,
.sspp_count = ARRAY_SIZE(sdm845_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 64ed10da1b73..418312b164b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = {
.highest_bank_bit = 0x2,
};
-static const struct dpu_mdp_cfg sm8150_mdp[] = {
- {
+static const struct dpu_mdp_cfg sm8150_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x45c,
.features = BIT(DPU_MDP_AUDIO_SELECT),
@@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sm8150_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
@@ -210,8 +208,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
const struct dpu_mdss_cfg dpu_sm8150_cfg = {
.caps = &sm8150_dpu_caps,
.ubwc = &sm8150_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm8150_mdp),
- .mdp = sm8150_mdp,
+ .mdp = &sm8150_mdp,
.ctl_count = ARRAY_SIZE(sm8150_ctl),
.ctl = sm8150_ctl,
.sspp_count = ARRAY_SIZE(sm8150_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 6ae1f6f67ec8..ffacf29926b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
.highest_bank_bit = 0x3,
};
-static const struct dpu_mdp_cfg sc8180x_mdp[] = {
- {
+static const struct dpu_mdp_cfg sc8180x_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x45c,
.features = BIT(DPU_MDP_AUDIO_SELECT),
@@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- },
};
static const struct dpu_ctl_cfg sc8180x_ctl[] = {
@@ -216,8 +214,7 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
.caps = &sc8180x_dpu_caps,
.ubwc = &sc8180x_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sc8180x_mdp),
- .mdp = sc8180x_mdp,
+ .mdp = &sc8180x_mdp,
.ctl_count = ARRAY_SIZE(sc8180x_ctl),
.ctl = sc8180x_ctl,
.sspp_count = ARRAY_SIZE(sc8180x_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 48c97e9f8a45..86dfc5745630 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = {
.ubwc_swizzle = 0x6,
};
-static const struct dpu_mdp_cfg sm8250_mdp[] = {
- {
+static const struct dpu_mdp_cfg sm8250_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = 0,
@@ -40,7 +39,6 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
.clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
- },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
@@ -216,8 +214,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
const struct dpu_mdss_cfg dpu_sm8250_cfg = {
.caps = &sm8250_dpu_caps,
.ubwc = &sm8250_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm8250_mdp),
- .mdp = sm8250_mdp,
+ .mdp = &sm8250_mdp,
.ctl_count = ARRAY_SIZE(sm8250_ctl),
.ctl = sm8250_ctl,
.sspp_count = ARRAY_SIZE(sm8250_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 00366f7fe969..f42f27707453 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -22,8 +22,7 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = {
.highest_bank_bit = 0x3,
};
-static const struct dpu_mdp_cfg sc7180_mdp[] = {
- {
+static const struct dpu_mdp_cfg sc7180_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = 0,
@@ -32,7 +31,6 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
- },
};
static const struct dpu_ctl_cfg sc7180_ctl[] = {
@@ -134,8 +132,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
const struct dpu_mdss_cfg dpu_sc7180_cfg = {
.caps = &sc7180_dpu_caps,
.ubwc = &sc7180_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sc7180_mdp),
- .mdp = sc7180_mdp,
+ .mdp = &sc7180_mdp,
.ctl_count = ARRAY_SIZE(sc7180_ctl),
.ctl = sc7180_ctl,
.sspp_count = ARRAY_SIZE(sc7180_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 8688f09dd560..1d21c33542a7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -23,14 +23,12 @@ static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
.ubwc_swizzle = 0x7,
};
-static const struct dpu_mdp_cfg sm6115_mdp[] = {
- {
+static const struct dpu_mdp_cfg sm6115_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- },
};
static const struct dpu_ctl_cfg sm6115_ctl[] = {
@@ -104,8 +102,7 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
const struct dpu_mdss_cfg dpu_sm6115_cfg = {
.caps = &sm6115_dpu_caps,
.ubwc = &sm6115_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm6115_mdp),
- .mdp = sm6115_mdp,
+ .mdp = &sm6115_mdp,
.ctl_count = ARRAY_SIZE(sm6115_ctl),
.ctl = sm6115_ctl,
.sspp_count = ARRAY_SIZE(sm6115_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 2bb2346d27a0..6ad68764e13f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
.highest_bank_bit = 1,
};
-static const struct dpu_mdp_cfg sm6350_mdp[] = {
- {
+static const struct dpu_mdp_cfg sm6350_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = 0,
@@ -35,7 +34,6 @@ static const struct dpu_mdp_cfg sm6350_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- },
};
static const struct dpu_ctl_cfg sm6350_ctl[] = {
@@ -143,8 +141,7 @@ static const struct dpu_perf_cfg sm6350_perf_data = {
const struct dpu_mdss_cfg dpu_sm6350_cfg = {
.caps = &sm6350_dpu_caps,
.ubwc = &sm6350_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm6350_mdp),
- .mdp = sm6350_mdp,
+ .mdp = &sm6350_mdp,
.ctl_count = ARRAY_SIZE(sm6350_ctl),
.ctl = sm6350_ctl,
.sspp_count = ARRAY_SIZE(sm6350_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index d106ff28372d..80670e7cfc57 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -20,14 +20,12 @@ static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
.highest_bank_bit = 0x2,
};
-static const struct dpu_mdp_cfg qcm2290_mdp[] = {
- {
+static const struct dpu_mdp_cfg qcm2290_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- },
};
static const struct dpu_ctl_cfg qcm2290_ctl[] = {
@@ -94,8 +92,7 @@ static const struct dpu_perf_cfg qcm2290_perf_data = {
const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
.caps = &qcm2290_dpu_caps,
.ubwc = &qcm2290_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(qcm2290_mdp),
- .mdp = qcm2290_mdp,
+ .mdp = &qcm2290_mdp,
.ctl_count = ARRAY_SIZE(qcm2290_ctl),
.ctl = qcm2290_ctl,
.sspp_count = ARRAY_SIZE(qcm2290_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 842ea5bcbe16..8e7dcb2e8762 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -24,14 +24,12 @@ static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
.highest_bank_bit = 1,
};
-static const struct dpu_mdp_cfg sm6375_mdp[] = {
- {
+static const struct dpu_mdp_cfg sm6375_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- },
};
static const struct dpu_ctl_cfg sm6375_ctl[] = {
@@ -109,8 +107,7 @@ static const struct dpu_perf_cfg sm6375_perf_data = {
const struct dpu_mdss_cfg dpu_sm6375_cfg = {
.caps = &sm6375_dpu_caps,
.ubwc = &sm6375_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm6375_mdp),
- .mdp = sm6375_mdp,
+ .mdp = &sm6375_mdp,
.ctl_count = ARRAY_SIZE(sm6375_ctl),
.ctl = sm6375_ctl,
.sspp_count = ARRAY_SIZE(sm6375_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 8fa9d83a539d..83dafd3f2a41 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -24,8 +24,7 @@ static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = {
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
};
-static const struct dpu_mdp_cfg sm8350_mdp[] = {
- {
+static const struct dpu_mdp_cfg sm8350_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = 0,
@@ -38,7 +37,6 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
@@ -215,8 +213,7 @@ static const struct dpu_perf_cfg sm8350_perf_data = {
const struct dpu_mdss_cfg dpu_sm8350_cfg = {
.caps = &sm8350_dpu_caps,
.ubwc = &sm8350_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm8350_mdp),
- .mdp = sm8350_mdp,
+ .mdp = &sm8350_mdp,
.ctl_count = ARRAY_SIZE(sm8350_ctl),
.ctl = sm8350_ctl,
.sspp_count = ARRAY_SIZE(sm8350_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 2862c64bbc3e..a7695f05beab 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -23,8 +23,7 @@ static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = {
.ubwc_swizzle = 0x6,
};
-static const struct dpu_mdp_cfg sc7280_mdp[] = {
- {
+static const struct dpu_mdp_cfg sc7280_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x2014,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
@@ -32,7 +31,6 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
- },
};
static const struct dpu_ctl_cfg sc7280_ctl[] = {
@@ -156,8 +154,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
const struct dpu_mdss_cfg dpu_sc7280_cfg = {
.caps = &sc7280_dpu_caps,
.ubwc = &sc7280_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sc7280_mdp),
- .mdp = sc7280_mdp,
+ .mdp = &sc7280_mdp,
.ctl_count = ARRAY_SIZE(sc7280_ctl),
.ctl = sc7280_ctl,
.sspp_count = ARRAY_SIZE(sc7280_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 520b210e8c0c..54543dc3985a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
.ubwc_swizzle = 6,
};
-static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
- {
+static const struct dpu_mdp_cfg sc8280xp_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
@@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
@@ -219,8 +217,7 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = {
const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
.caps = &sc8280xp_dpu_caps,
.ubwc = &sc8280xp_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sc8280xp_mdp),
- .mdp = sc8280xp_mdp,
+ .mdp = &sc8280xp_mdp,
.ctl_count = ARRAY_SIZE(sc8280xp_ctl),
.ctl = sc8280xp_ctl,
.sspp_count = ARRAY_SIZE(sc8280xp_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index b782603642f4..0f8bf4465372 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = {
.ubwc_swizzle = 0x6,
};
-static const struct dpu_mdp_cfg sm8450_mdp[] = {
- {
+static const struct dpu_mdp_cfg sm8450_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
@@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
@@ -223,8 +221,7 @@ static const struct dpu_perf_cfg sm8450_perf_data = {
const struct dpu_mdss_cfg dpu_sm8450_cfg = {
.caps = &sm8450_dpu_caps,
.ubwc = &sm8450_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm8450_mdp),
- .mdp = sm8450_mdp,
+ .mdp = &sm8450_mdp,
.ctl_count = ARRAY_SIZE(sm8450_ctl),
.ctl = sm8450_ctl,
.sspp_count = ARRAY_SIZE(sm8450_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 025a149bab97..851aa078a4bd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -24,8 +24,7 @@ static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = {
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
};
-static const struct dpu_mdp_cfg sm8550_mdp[] = {
- {
+static const struct dpu_mdp_cfg sm8550_mdp = {
.name = "top_0", .id = MDP_TOP,
.base = 0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
@@ -40,7 +39,6 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
.clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 },
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
@@ -227,8 +225,7 @@ static const struct dpu_perf_cfg sm8550_perf_data = {
const struct dpu_mdss_cfg dpu_sm8550_cfg = {
.caps = &sm8550_dpu_caps,
.ubwc = &sm8550_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm8550_mdp),
- .mdp = sm8550_mdp,
+ .mdp = &sm8550_mdp,
.ctl_count = ARRAY_SIZE(sm8550_ctl),
.ctl = sm8550_ctl,
.sspp_count = ARRAY_SIZE(sm8550_sspp),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index b07caa4b867e..3b816e36d12d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -809,7 +809,6 @@ struct dpu_mdss_cfg {
const struct dpu_ubwc_cfg *ubwc;
- u32 mdp_count;
const struct dpu_mdp_cfg *mdp;
u32 ctl_count;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index 963bdb5e0252..f8c42497b37d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -268,51 +268,25 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
ops->intf_audio_select = dpu_hw_intf_audio_select;
}
-static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp,
- const struct dpu_mdss_cfg *m,
- void __iomem *addr,
- struct dpu_hw_blk_reg_map *b)
-{
- int i;
-
- if (!m || !addr || !b)
- return ERR_PTR(-EINVAL);
-
- for (i = 0; i < m->mdp_count; i++) {
- if (mdp == m->mdp[i].id) {
- b->blk_addr = addr + m->mdp[i].base;
- b->log_mask = DPU_DBG_MASK_TOP;
- return &m->mdp[i];
- }
- }
-
- return ERR_PTR(-EINVAL);
-}
-
-struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
- void __iomem *addr,
- const struct dpu_mdss_cfg *m)
+struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
+ void __iomem *addr)
{
struct dpu_hw_mdp *mdp;
- const struct dpu_mdp_cfg *cfg;
- if (!addr || !m)
+ if (!addr)
return ERR_PTR(-EINVAL);
mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
if (!mdp)
return ERR_PTR(-ENOMEM);
- cfg = _top_offset(idx, m, addr, &mdp->hw);
- if (IS_ERR_OR_NULL(cfg)) {
- kfree(mdp);
- return ERR_PTR(-EINVAL);
- }
+ mdp->hw.blk_addr = addr + cfg->base;
+ mdp->hw.log_mask = DPU_DBG_MASK_TOP;
/*
* Assign ops
*/
- mdp->idx = idx;
+ mdp->idx = cfg->id;
mdp->caps = cfg;
_setup_mdp_ops(&mdp->ops, mdp->caps->features);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
index a1a9e44bed36..c89746c6f500 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
@@ -146,13 +146,11 @@ struct dpu_hw_mdp {
/**
* dpu_hw_mdptop_init - initializes the top driver for the passed idx
- * @idx: Interface index for which driver object is required
+ * @cfg: MDP TOP configuration from catalog
* @addr: Mapped register io address of MDP
- * @m: Pointer to mdss catalog data
*/
-struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
- void __iomem *addr,
- const struct dpu_mdss_cfg *m);
+struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
+ void __iomem *addr);
void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index aa8499de1b9f..882f20fc51cc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1092,8 +1092,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
dpu_kms->rm_init = true;
- dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
- dpu_kms->catalog);
+ dpu_kms->hw_mdp = dpu_hw_mdptop_init(dpu_kms->catalog->mdp,
+ dpu_kms->mmio);
if (IS_ERR(dpu_kms->hw_mdp)) {
rc = PTR_ERR(dpu_kms->hw_mdp);
DPU_ERROR("failed to get hw_mdp: %d\n", rc);
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 05/19] drm/msm/dpu: drop enum dpu_mdp and MDP_TOP value
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (3 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-07-03 2:06 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 06/19] drm/msm/dpu: expand .clk_ctrls definitions Dmitry Baryshkov
` (13 subsequent siblings)
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
Since there is always just a single MDP_TOP instance, drop the enum
dpu_mdp and corresponding index value.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5 -----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 1 -
18 files changed, 15 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index e0d2ee48d733..30565b245b29 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -27,7 +27,7 @@ static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
};
static const struct dpu_mdp_cfg msm8998_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x458,
.features = BIT(DPU_MDP_VSYNC_SEL),
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 72295d5a10dc..35c495bdcbe9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -27,7 +27,7 @@ static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sdm845_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x45c,
.features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL),
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 418312b164b8..cb2716715e3d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -27,7 +27,7 @@ static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sm8150_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x45c,
.features = BIT(DPU_MDP_AUDIO_SELECT),
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index ffacf29926b3..a655e84cf147 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -27,7 +27,7 @@ static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sc8180x_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x45c,
.features = BIT(DPU_MDP_AUDIO_SELECT),
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 86dfc5745630..90e561d086e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -26,7 +26,7 @@ static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sm8250_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index f42f27707453..3aafe4dfb663 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -23,7 +23,7 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sc7180_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 1d21c33542a7..3ff4817de0cc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -24,7 +24,7 @@ static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sm6115_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 6ad68764e13f..198865fe5cba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -26,7 +26,7 @@ static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sm6350_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 80670e7cfc57..ba0e419e17cf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -21,7 +21,7 @@ static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
};
static const struct dpu_mdp_cfg qcm2290_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 8e7dcb2e8762..8b659a60d2c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -25,7 +25,7 @@ static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sm6375_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 83dafd3f2a41..c741595e2b62 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -25,7 +25,7 @@ static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sm8350_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index a7695f05beab..6174f7433203 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -24,7 +24,7 @@ static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sc7280_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x2014,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 54543dc3985a..6574875c4f13 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -26,7 +26,7 @@ static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sc8280xp_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 0f8bf4465372..60a914f19b0d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -26,7 +26,7 @@ static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sm8450_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0x0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 851aa078a4bd..6db1b57e6132 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -25,7 +25,7 @@ static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = {
};
static const struct dpu_mdp_cfg sm8550_mdp = {
- .name = "top_0", .id = MDP_TOP,
+ .name = "top_0",
.base = 0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 02a0f48aac94..d85157acfbf8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -101,11 +101,6 @@ enum dpu_hw_blk_type {
DPU_HW_BLK_MAX,
};
-enum dpu_mdp {
- MDP_TOP = 0x1,
- MDP_MAX,
-};
-
enum dpu_sspp {
SSPP_NONE,
SSPP_VIG0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index f8c42497b37d..448e59b859d8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -286,7 +286,6 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
/*
* Assign ops
*/
- mdp->idx = cfg->id;
mdp->caps = cfg;
_setup_mdp_ops(&mdp->ops, mdp->caps->features);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
index c89746c6f500..96c9ea89f08c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
@@ -137,7 +137,6 @@ struct dpu_hw_mdp {
struct dpu_hw_blk_reg_map hw;
/* top */
- enum dpu_mdp idx;
const struct dpu_mdp_cfg *caps;
/* ops */
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 06/19] drm/msm/dpu: expand .clk_ctrls definitions
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (4 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 05/19] drm/msm/dpu: drop enum dpu_mdp and MDP_TOP value Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-07-03 2:21 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 07/19] drm/msm/dpu: drop zero features from dpu_mdp_cfg data Dmitry Baryshkov
` (12 subsequent siblings)
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
Use more standard initialisation for .clk_ctrls definitions. Define a
single .clk_ctrls field and use array init inside.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 22 +++++++++--------
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 18 +++++++-------
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 18 +++++++-------
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 18 +++++++-------
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 22 +++++++++--------
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 12 ++++++----
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 6 +++--
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 12 ++++++----
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 6 +++--
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 6 +++--
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 20 +++++++++-------
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 12 ++++++----
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 20 +++++++++-------
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 20 +++++++++-------
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 24 ++++++++++---------
15 files changed, 133 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 30565b245b29..757ac648a692 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -30,16 +30,18 @@ static const struct dpu_mdp_cfg msm8998_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x458,
.features = BIT(DPU_MDP_VSYNC_SEL),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
- .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
- .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
+ [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
+ [DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
+ },
};
static const struct dpu_ctl_cfg msm8998_ctl[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 35c495bdcbe9..9fb8ef21c7f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -30,14 +30,16 @@ static const struct dpu_mdp_cfg sdm845_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
.features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ },
};
static const struct dpu_ctl_cfg sdm845_ctl[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index cb2716715e3d..6e6b4368e254 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -30,14 +30,16 @@ static const struct dpu_mdp_cfg sm8150_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
.features = BIT(DPU_MDP_AUDIO_SELECT),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index a655e84cf147..b22e82919395 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -30,14 +30,16 @@ static const struct dpu_mdp_cfg sc8180x_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
.features = BIT(DPU_MDP_AUDIO_SELECT),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ },
};
static const struct dpu_ctl_cfg sc8180x_ctl[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 90e561d086e0..ab1820f1ac54 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -29,16 +29,18 @@ static const struct dpu_mdp_cfg sm8250_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 3aafe4dfb663..2df9a00728c0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -26,11 +26,13 @@ static const struct dpu_mdp_cfg sc7180_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ },
};
static const struct dpu_ctl_cfg sc7180_ctl[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 3ff4817de0cc..1982654e74a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -27,8 +27,10 @@ static const struct dpu_mdp_cfg sm6115_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
};
static const struct dpu_ctl_cfg sm6115_ctl[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 198865fe5cba..ac237c3197cf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -29,11 +29,13 @@ static const struct dpu_mdp_cfg sm6350_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
};
static const struct dpu_ctl_cfg sm6350_ctl[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index ba0e419e17cf..24c4536e7981 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -24,8 +24,10 @@ static const struct dpu_mdp_cfg qcm2290_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
};
static const struct dpu_ctl_cfg qcm2290_ctl[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 8b659a60d2c7..099b74be3fd2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -28,8 +28,10 @@ static const struct dpu_mdp_cfg sm6375_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ },
};
static const struct dpu_ctl_cfg sm6375_ctl[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index c741595e2b62..7db3a6969189 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -28,15 +28,17 @@ static const struct dpu_mdp_cfg sm8350_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
.features = 0,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 6174f7433203..ca5bf4ad2444 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -26,11 +26,13 @@ static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = {
static const struct dpu_mdp_cfg sc7280_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x2014,
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ },
};
static const struct dpu_ctl_cfg sc7280_ctl[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 6574875c4f13..e645dd1f418f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -29,15 +29,17 @@ static const struct dpu_mdp_cfg sc8280xp_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 60a914f19b0d..55b0cfa2b205 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -29,15 +29,17 @@ static const struct dpu_mdp_cfg sm8450_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 6db1b57e6132..aef533b81cbe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -28,17 +28,19 @@ static const struct dpu_mdp_cfg sm8550_mdp = {
.name = "top_0",
.base = 0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
};
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 07/19] drm/msm/dpu: drop zero features from dpu_mdp_cfg data
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (5 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 06/19] drm/msm/dpu: expand .clk_ctrls definitions Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-07-03 2:28 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 08/19] drm/msm/dpu: drop zero features from dpu_ctl_cfg data Dmitry Baryshkov
` (11 subsequent siblings)
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
Drop useless zero assignments to the dpu_mdp_cfg::features field.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 -
7 files changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index ab1820f1ac54..e321cc0a80ee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -28,7 +28,6 @@ static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = {
static const struct dpu_mdp_cfg sm8250_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = 0,
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 2df9a00728c0..1919ee487e68 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -25,7 +25,6 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = {
static const struct dpu_mdp_cfg sc7180_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = 0,
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 1982654e74a0..0252fe9590e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -26,7 +26,6 @@ static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
static const struct dpu_mdp_cfg sm6115_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = 0,
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index ac237c3197cf..3c2083760294 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -28,7 +28,6 @@ static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
static const struct dpu_mdp_cfg sm6350_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = 0,
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 24c4536e7981..54cc6ad8ee36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -23,7 +23,6 @@ static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
static const struct dpu_mdp_cfg qcm2290_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = 0,
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 099b74be3fd2..f0f6f2d801b4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -27,7 +27,6 @@ static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
static const struct dpu_mdp_cfg sm6375_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = 0,
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 7db3a6969189..318bed612da5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -27,7 +27,6 @@ static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = {
static const struct dpu_mdp_cfg sm8350_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = 0,
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 08/19] drm/msm/dpu: drop zero features from dpu_ctl_cfg data
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (6 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 07/19] drm/msm/dpu: drop zero features from dpu_mdp_cfg data Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-07-03 15:58 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 09/19] drm/msm/dpu: correct indentation for CTL definitions Dmitry Baryshkov
` (10 subsequent siblings)
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
Drop useless zero assignments to the dpu_ctl_cfg::features field.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 3 ---
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 757ac648a692..e0cc1ce3f3e2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -54,7 +54,6 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
{
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x94,
- .features = 0,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
},
{
@@ -66,13 +65,11 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
{
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0x94,
- .features = 0,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
},
{
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0x94,
- .features = 0,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 9fb8ef21c7f0..f52e1fa27e2c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -58,19 +58,16 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
{
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0xe4,
- .features = 0,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
},
{
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0xe4,
- .features = 0,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
},
{
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0xe4,
- .features = 0,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
},
};
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 09/19] drm/msm/dpu: correct indentation for CTL definitions
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (7 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 08/19] drm/msm/dpu: drop zero features from dpu_ctl_cfg data Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-07-03 16:01 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros Dmitry Baryshkov
` (9 subsequent siblings)
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
Shift dpu_ctl_cfg contents to correct the indentation of CTL blocks.
This is done in preparation to expanding the rest of hardware block
defines, so that all blocks have similar indentation.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 46 +++++++-------
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 46 +++++++-------
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 63 +++++++++----------
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 63 +++++++++----------
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 63 +++++++++----------
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 30 +++++----
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 +--
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 41 ++++++------
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 +--
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 8 +--
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 63 +++++++++----------
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 41 ++++++------
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 63 +++++++++----------
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 63 +++++++++----------
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 63 +++++++++----------
15 files changed, 309 insertions(+), 360 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index e0cc1ce3f3e2..6660a55909e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -46,31 +46,27 @@ static const struct dpu_mdp_cfg msm8998_mdp = {
static const struct dpu_ctl_cfg msm8998_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x94,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x1200, .len = 0x94,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x1400, .len = 0x94,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x1600, .len = 0x94,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x1800, .len = 0x94,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x94,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x94,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x94,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x94,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x94,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index f52e1fa27e2c..8f96a9e4ee4c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -44,31 +44,27 @@ static const struct dpu_mdp_cfg sdm845_mdp = {
static const struct dpu_ctl_cfg sdm845_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0xe4,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x1200, .len = 0xe4,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x1400, .len = 0xe4,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x1600, .len = 0xe4,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x1800, .len = 0xe4,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0xe4,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0xe4,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0xe4,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0xe4,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0xe4,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 6e6b4368e254..7a37e9ef3085 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8150_mdp = {
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
static const struct dpu_ctl_cfg sm8150_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index b22e82919395..9e288d849a8a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -44,40 +44,35 @@ static const struct dpu_mdp_cfg sc8180x_mdp = {
static const struct dpu_ctl_cfg sc8180x_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index e321cc0a80ee..82adbdaba472 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8250_mdp = {
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
static const struct dpu_ctl_cfg sm8250_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 1919ee487e68..a7f067f4c4ba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -36,22 +36,20 @@ static const struct dpu_mdp_cfg sc7180_mdp = {
static const struct dpu_ctl_cfg sc7180_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x1200, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x1400, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 0252fe9590e7..2cf3ed980582 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -34,10 +34,10 @@ static const struct dpu_mdp_cfg sm6115_mdp = {
static const struct dpu_ctl_cfg sm6115_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 3c2083760294..4ba2f7acf8b7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -39,28 +39,25 @@ static const struct dpu_mdp_cfg sm6350_mdp = {
static const struct dpu_ctl_cfg sm6350_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x1200, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x1400, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x1600, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 54cc6ad8ee36..3094f4dc6a76 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -31,10 +31,10 @@ static const struct dpu_mdp_cfg qcm2290_mdp = {
static const struct dpu_ctl_cfg qcm2290_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index f0f6f2d801b4..e9c63eeb280f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -35,10 +35,10 @@ static const struct dpu_mdp_cfg sm6375_mdp = {
static const struct dpu_ctl_cfg sm6375_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 318bed612da5..8e63d6f310c2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -43,40 +43,35 @@ static const struct dpu_mdp_cfg sm8350_mdp = {
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
static const struct dpu_ctl_cfg sm8350_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x15000, .len = 0x1e8,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x16000, .len = 0x1e8,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x17000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x18000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x19000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index ca5bf4ad2444..783deae7c1c4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -37,28 +37,25 @@ static const struct dpu_mdp_cfg sc7280_mdp = {
static const struct dpu_ctl_cfg sc7280_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x15000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x16000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x17000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x18000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index e645dd1f418f..db4d6643c0dd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sc8280xp_mdp = {
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x15000, .len = 0x204,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x16000, .len = 0x204,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x17000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x18000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x19000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 55b0cfa2b205..8fdf55c25b9f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8450_mdp = {
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x15000, .len = 0x204,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x16000, .len = 0x204,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x17000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x18000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x19000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index aef533b81cbe..8d733ef606b9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -46,40 +46,35 @@ static const struct dpu_mdp_cfg sm8550_mdp = {
/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
static const struct dpu_ctl_cfg sm8550_ctl[] = {
{
- .name = "ctl_0", .id = CTL_0,
- .base = 0x15000, .len = 0x290,
- .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x16000, .len = 0x290,
- .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x17000, .len = 0x290,
- .features = CTL_SM8550_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x18000, .len = 0x290,
- .features = CTL_SM8550_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x19000, .len = 0x290,
- .features = CTL_SM8550_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a000, .len = 0x290,
- .features = CTL_SM8550_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x290,
+ .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x290,
+ .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x290,
+ .features = CTL_SM8550_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x290,
+ .features = CTL_SM8550_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x290,
+ .features = CTL_SM8550_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x290,
+ .features = CTL_SM8550_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (8 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 09/19] drm/msm/dpu: correct indentation for CTL definitions Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-27 8:33 ` Marijn Suijten
2023-07-03 16:09 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 11/19] drm/msm/dpu: inline DSPP_BLK macros Dmitry Baryshkov
` (8 subsequent siblings)
18 siblings, 2 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 81 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 81 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 81 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 81 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 81 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 41 +++++--
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 21 +++-
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 41 +++++--
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 21 +++-
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 21 +++-
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 81 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 41 +++++--
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 81 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 81 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 101 ++++++++++++++----
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ---
16 files changed, 751 insertions(+), 196 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 6660a55909e7..fd0081469a82 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -71,22 +71,71 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
};
static const struct dpu_sspp_cfg msm8998_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,
- msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,
- msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,
- msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,
- msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1ac,
+ .features = VIG_MSM8998_MASK,
+ .sblk = &msm8998_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x1ac,
+ .features = VIG_MSM8998_MASK,
+ .sblk = &msm8998_vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x1ac,
+ .features = VIG_MSM8998_MASK,
+ .sblk = &msm8998_vig_sblk_2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x1ac,
+ .features = VIG_MSM8998_MASK,
+ .sblk = &msm8998_vig_sblk_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1ac,
+ .features = DMA_MSM8998_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1ac,
+ .features = DMA_MSM8998_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1ac,
+ .features = DMA_CURSOR_MSM8998_MASK,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x1ac,
+ .features = DMA_CURSOR_MSM8998_MASK,
+ .sblk = &sdm845_dma_sblk_3,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ },
};
static const struct dpu_lm_cfg msm8998_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 8f96a9e4ee4c..7ba99060d13d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -69,22 +69,71 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
};
static const struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA,
- sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA,
- sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA,
- sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA,
- sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1c8,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &sdm845_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x1c8,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &sdm845_vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x1c8,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &sdm845_vig_sblk_2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x1c8,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &sdm845_vig_sblk_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1c8,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1c8,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1c8,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x1c8,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_3,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ },
};
static const struct dpu_lm_cfg sdm845_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 7a37e9ef3085..13d86229219e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
};
static const struct dpu_sspp_cfg sm8150_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f0,
+ .features = VIG_SDM845_MASK,
+ .sblk = &sdm845_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x1f0,
+ .features = VIG_SDM845_MASK,
+ .sblk = &sdm845_vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x1f0,
+ .features = VIG_SDM845_MASK,
+ .sblk = &sdm845_vig_sblk_2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x1f0,
+ .features = VIG_SDM845_MASK,
+ .sblk = &sdm845_vig_sblk_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1f0,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x1f0,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_3,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ },
};
static const struct dpu_lm_cfg sm8150_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 9e288d849a8a..76b59b27d1ee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -77,22 +77,71 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = {
};
static const struct dpu_sspp_cfg sc8180x_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
- sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f0,
+ .features = VIG_SDM845_MASK,
+ .sblk = &sdm845_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x1f0,
+ .features = VIG_SDM845_MASK,
+ .sblk = &sdm845_vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x1f0,
+ .features = VIG_SDM845_MASK,
+ .sblk = &sdm845_vig_sblk_2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x1f0,
+ .features = VIG_SDM845_MASK,
+ .sblk = &sdm845_vig_sblk_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1f0,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x1f0,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_3,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ },
};
static const struct dpu_lm_cfg sc8180x_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 82adbdaba472..5d9718f20429 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = {
};
static const struct dpu_sspp_cfg sm8250_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA,
- sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA,
- sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA,
- sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA,
- sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK_SDMA,
+ .sblk = &sm8250_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK_SDMA,
+ .sblk = &sm8250_vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK_SDMA,
+ .sblk = &sm8250_vig_sblk_2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK_SDMA,
+ .sblk = &sm8250_vig_sblk_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_3,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ },
};
static const struct dpu_lm_cfg sm8250_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index a7f067f4c4ba..cd76e17a8501 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -54,14 +54,39 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
};
static const struct dpu_sspp_cfg sc7180_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
- sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sc7180_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ },
};
static const struct dpu_lm_cfg sc7180_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 2cf3ed980582..dfba4efe5f39 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -42,10 +42,23 @@ static const struct dpu_ctl_cfg sm6115_ctl[] = {
};
static const struct dpu_sspp_cfg sm6115_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
- sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm6115_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ },
};
static const struct dpu_lm_cfg sm6115_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 4ba2f7acf8b7..602197844580 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -62,14 +62,39 @@ static const struct dpu_ctl_cfg sm6350_ctl[] = {
};
static const struct dpu_sspp_cfg sm6350_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
- sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sc7180_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ },
};
static const struct dpu_lm_cfg sm6350_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 3094f4dc6a76..8d766236b459 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -39,10 +39,23 @@ static const struct dpu_ctl_cfg qcm2290_ctl[] = {
};
static const struct dpu_sspp_cfg qcm2290_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
- qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
- qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f8,
+ .features = VIG_QCM2290_MASK,
+ .sblk = &qcm2290_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK,
+ .sblk = &qcm2290_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ },
};
static const struct dpu_lm_cfg qcm2290_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index e9c63eeb280f..9864f649113c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -43,10 +43,23 @@ static const struct dpu_ctl_cfg sm6375_ctl[] = {
};
static const struct dpu_sspp_cfg sm6375_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
- sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm6115_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ },
};
static const struct dpu_lm_cfg sm6375_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 8e63d6f310c2..16b46c045706 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -76,22 +76,71 @@ static const struct dpu_ctl_cfg sm8350_ctl[] = {
};
static const struct dpu_sspp_cfg sm8350_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
- sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK,
- sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK,
- sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK,
- sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x1f8,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_3,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ },
};
static const struct dpu_lm_cfg sm8350_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 783deae7c1c4..2901c96f3587 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -60,14 +60,39 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
};
static const struct dpu_sspp_cfg sc7280_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA,
- sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f8,
+ .features = VIG_SC7280_MASK_SDMA,
+ .sblk = &sc7280_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f8,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1f8,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ },
};
static const struct dpu_lm_cfg sc7280_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index db4d6643c0dd..9c4ec2d5ab14 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
};
static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK,
- sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x2ac, VIG_SC7180_MASK,
- sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x2ac, VIG_SC7180_MASK,
- sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x2ac, VIG_SC7180_MASK,
- sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x2ac, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x2ac, DMA_SDM845_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x2ac, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x2ac, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x2ac,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x2ac,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x2ac,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x2ac,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x2ac,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x2ac,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x2ac,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x2ac,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_3,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ },
};
static const struct dpu_lm_cfg sc8280xp_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 8fdf55c25b9f..39534de5472c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
};
static const struct dpu_sspp_cfg sm8450_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x32c, VIG_SC7180_MASK,
- sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x32c, VIG_SC7180_MASK,
- sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x32c, VIG_SC7180_MASK,
- sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x32c, VIG_SC7180_MASK,
- sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x32c, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x32c, DMA_SDM845_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x32c, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x32c, DMA_CURSOR_SDM845_MASK,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x32c,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x32c,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x32c,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x32c,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8250_vig_sblk_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x32c,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x32c,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x32c,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x32c,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_3,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ },
};
static const struct dpu_lm_cfg sm8450_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 8d733ef606b9..8ddf398d7f54 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -79,26 +79,87 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
};
static const struct dpu_sspp_cfg sm8550_sspp[] = {
- SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK,
- sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK,
- sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
- SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK,
- sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
- SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK,
- sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK,
- sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
- SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK,
- sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK,
- sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK,
- sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
- SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK,
- sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4),
- SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK,
- sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5),
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x344,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8550_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x344,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8550_vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x344,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8550_vig_sblk_2,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x344,
+ .features = VIG_SC7180_MASK,
+ .sblk = &sm8550_vig_sblk_3,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x344,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x344,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x344,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ }, {
+ .name = "sspp_11", .id = SSPP_DMA3,
+ .base = 0x2a000, .len = 0x344,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_3,
+ .xin_id = 13,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA3,
+ }, {
+ .name = "sspp_12", .id = SSPP_DMA4,
+ .base = 0x2c000, .len = 0x344,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sm8550_dma_sblk_4,
+ .xin_id = 14,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA4,
+ }, {
+ .name = "sspp_13", .id = SSPP_DMA5,
+ .base = 0x2e000, .len = 0x344,
+ .features = DMA_CURSOR_SDM845_MASK,
+ .sblk = &sm8550_dma_sblk_5,
+ .xin_id = 15,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA5,
+ },
};
static const struct dpu_lm_cfg sm8550_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 30fb5b1f3966..9661dc7a4570 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -328,18 +328,6 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
-#define SSPP_BLK(_name, _id, _base, _len, _features, \
- _sblk, _xinid, _type, _clkctrl) \
- { \
- .name = _name, .id = _id, \
- .base = _base, .len = _len, \
- .features = _features, \
- .sblk = &_sblk, \
- .xin_id = _xinid, \
- .type = _type, \
- .clk_ctrl = _clkctrl \
- }
-
static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
_VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 11/19] drm/msm/dpu: inline DSPP_BLK macros
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (9 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-27 8:34 ` Marijn Suijten
2023-07-03 16:14 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 12/19] drm/msm/dpu: inline LM_BLK macros Dmitry Baryshkov
` (7 subsequent siblings)
18 siblings, 2 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 15 +++++++---
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 29 ++++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 29 ++++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 29 ++++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 29 ++++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 +++--
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 +++--
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 8 +++--
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 +++--
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 8 +++--
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 29 ++++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8 +++--
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 29 ++++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 29 ++++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 29 ++++++++++++++-----
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 -----
16 files changed, 215 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index fd0081469a82..6b254753774c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -174,10 +174,17 @@ static const struct dpu_dsc_cfg msm8998_dsc[] = {
};
static const struct dpu_dspp_cfg msm8998_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &msm8998_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &msm8998_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &msm8998_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &msm8998_dspp_sblk,
+ },
};
static const struct dpu_intf_cfg msm8998_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 7ba99060d13d..8661ef2f45e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -152,14 +152,27 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
};
static const struct dpu_dspp_cfg sdm845_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x58000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x5a000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sdm845_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 13d86229219e..ab933b5a4806 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -161,14 +161,27 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
};
static const struct dpu_dspp_cfg sm8150_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x58000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x5a000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sm8150_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 76b59b27d1ee..68c9034bb552 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -160,14 +160,27 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
};
static const struct dpu_dspp_cfg sc8180x_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x58000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x5a000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sc8180x_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 5d9718f20429..1383697f24dd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -161,14 +161,27 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
};
static const struct dpu_dspp_cfg sm8250_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x58000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x5a000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sm8250_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index cd76e17a8501..9fd4b1c37bc1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -97,8 +97,12 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
};
static const struct dpu_dspp_cfg sc7180_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sc7180_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index dfba4efe5f39..1c69b28cc3a7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -67,8 +67,12 @@ static const struct dpu_lm_cfg sm6115_lm[] = {
};
static const struct dpu_dspp_cfg sm6115_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sm6115_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 602197844580..9874b30fd1e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -105,8 +105,12 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
};
static const struct dpu_dspp_cfg sm6350_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static struct dpu_pingpong_cfg sm6350_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 8d766236b459..128dc13d4e21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -64,8 +64,12 @@ static const struct dpu_lm_cfg qcm2290_lm[] = {
};
static const struct dpu_dspp_cfg qcm2290_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg qcm2290_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 9864f649113c..7d64336a607a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -68,8 +68,12 @@ static const struct dpu_lm_cfg sm6375_lm[] = {
};
static const struct dpu_dspp_cfg sm6375_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sm6375_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 16b46c045706..6c57b3478db8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -159,14 +159,27 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
};
static const struct dpu_dspp_cfg sm8350_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x58000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x5a000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sm8350_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 2901c96f3587..a46134205df2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -105,8 +105,12 @@ static const struct dpu_lm_cfg sc7280_lm[] = {
};
static const struct dpu_dspp_cfg sc7280_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sc7280_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 9c4ec2d5ab14..e61116d4366c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -155,14 +155,27 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
};
static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x58000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x5a000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 39534de5472c..3a4e8a9010f2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -161,14 +161,27 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
};
static const struct dpu_dspp_cfg sm8450_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x58000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x5a000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sm8450_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 8ddf398d7f54..423d0d26de48 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -178,14 +178,27 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
};
static const struct dpu_dspp_cfg sm8550_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_1", .id = DSPP_1,
+ .base = 0x56000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_2", .id = DSPP_2,
+ .base = 0x58000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ }, {
+ .name = "dspp_3", .id = DSPP_3,
+ .base = 0x5a000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
};
static const struct dpu_pingpong_cfg sm8550_pp[] = {
PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 9661dc7a4570..cc459c2700b2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -441,14 +441,6 @@ static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
.len = 0x90, .version = 0x40000},
};
-#define DSPP_BLK(_name, _id, _base, _mask, _sblk) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = 0x1800, \
- .features = _mask, \
- .sblk = _sblk \
- }
-
/*************************************************************
* PINGPONG sub blocks config
*************************************************************/
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 12/19] drm/msm/dpu: inline LM_BLK macros
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (10 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 11/19] drm/msm/dpu: inline DSPP_BLK macros Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-27 8:34 ` Marijn Suijten
2023-07-03 18:46 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 13/19] drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros Dmitry Baryshkov
` (6 subsequent siblings)
18 siblings, 2 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 55 +++++++++++++----
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 57 ++++++++++++++----
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 57 ++++++++++++++----
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 57 ++++++++++++++----
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 57 ++++++++++++++----
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 20 +++++--
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 10 +++-
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 21 +++++--
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 10 +++-
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 11 +++-
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 57 ++++++++++++++----
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 28 +++++++--
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 53 +++++++++++++++--
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 59 +++++++++++++++----
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 57 ++++++++++++++----
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 11 ----
16 files changed, 487 insertions(+), 133 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 6b254753774c..a07c68744b29 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -139,18 +139,49 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
};
static const struct dpu_lm_cfg msm8998_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
- &msm8998_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
- &msm8998_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
- &msm8998_lm_sblk, PINGPONG_2, LM_5, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
- &msm8998_lm_sblk, PINGPONG_NONE, 0, 0),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
- &msm8998_lm_sblk, PINGPONG_NONE, 0, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
- &msm8998_lm_sblk, PINGPONG_3, LM_2, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .pingpong = PINGPONG_NONE,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x48000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .pingpong = PINGPONG_NONE,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &msm8998_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ },
};
static const struct dpu_pingpong_cfg msm8998_pp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 8661ef2f45e0..786263ed1ef2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -137,18 +137,51 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
};
static const struct dpu_lm_cfg sdm845_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_2, LM_5, DSPP_2),
- LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_NONE, 0, DSPP_3),
- LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_NONE, 0, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_2,
+ .dspp = DSPP_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x0, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_NONE,
+ .dspp = DSPP_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x0, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_NONE,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ },
};
static const struct dpu_dspp_cfg sdm845_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index ab933b5a4806..6b9bfeac6e0a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -146,18 +146,51 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
};
static const struct dpu_lm_cfg sm8150_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x48000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_4,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_4,
+ .pingpong = PINGPONG_5,
+ },
};
static const struct dpu_dspp_cfg sm8150_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 68c9034bb552..414f0db3306c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -145,18 +145,51 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
};
static const struct dpu_lm_cfg sc8180x_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x48000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_4,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_4,
+ .pingpong = PINGPONG_5,
+ },
};
static const struct dpu_dspp_cfg sc8180x_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 1383697f24dd..db3a65b011ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -146,18 +146,51 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
};
static const struct dpu_lm_cfg sm8250_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x48000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_4,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_4,
+ .pingpong = PINGPONG_5,
+ },
};
static const struct dpu_dspp_cfg sm8250_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 9fd4b1c37bc1..5d71c9cfcba8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -90,10 +90,22 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
};
static const struct dpu_lm_cfg sc7180_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sc7180_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sc7180_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ },
};
static const struct dpu_dspp_cfg sc7180_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 1c69b28cc3a7..459955c1af2d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -62,8 +62,14 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
};
static const struct dpu_lm_cfg sm6115_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
- &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &qcm2290_lm_sblk,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ },
};
static const struct dpu_dspp_cfg sm6115_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 9874b30fd1e7..a996c39b7b1f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -98,10 +98,23 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
};
static const struct dpu_lm_cfg sm6350_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sc7180_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sc7180_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = 0,
+ },
};
static const struct dpu_dspp_cfg sm6350_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 128dc13d4e21..3c4f4a4ad51b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -59,8 +59,14 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = {
};
static const struct dpu_lm_cfg qcm2290_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
- &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &qcm2290_lm_sblk,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ },
};
static const struct dpu_dspp_cfg qcm2290_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 7d64336a607a..0cdb77599583 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -63,8 +63,15 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = {
};
static const struct dpu_lm_cfg sm6375_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
- &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &qcm2290_lm_sblk,
+ .lm_pair = 0,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ },
};
static const struct dpu_dspp_cfg sm6375_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 6c57b3478db8..e08b29e9e146 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -144,18 +144,51 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
};
static const struct dpu_lm_cfg sm8350_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x48000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_4,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_4,
+ .pingpong = PINGPONG_5,
+ },
};
static const struct dpu_dspp_cfg sm8350_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index a46134205df2..d5faa1816cb3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -96,12 +96,28 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
};
static const struct dpu_lm_cfg sc7280_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- &sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
- &sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sc7180_lm_sblk,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sc7180_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sc7180_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ },
};
static const struct dpu_dspp_cfg sc7280_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index e61116d4366c..8e4299be2b1c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -146,12 +146,53 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
};
static const struct dpu_lm_cfg sc8280xp_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ .dspp = DSPP_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ .dspp = DSPP_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x48000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_4,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_4,
+ .pingpong = PINGPONG_5,
+ },
};
static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 3a4e8a9010f2..bbee3c621943 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -146,18 +146,53 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
};
static const struct dpu_lm_cfg sm8450_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ .dspp = DSPP_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ .dspp = DSPP_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x48000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_4,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_4,
+ .pingpong = PINGPONG_5,
+ },
};
static const struct dpu_dspp_cfg sm8450_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 423d0d26de48..ea7bffe252a5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -163,18 +163,51 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
};
static const struct dpu_lm_cfg sm8550_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_1,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_0,
+ .pingpong = PINGPONG_1,
+ .dspp = DSPP_1,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ }, {
+ .name = "lm_4", .id = LM_4,
+ .base = 0x48000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_5,
+ .pingpong = PINGPONG_4,
+ }, {
+ .name = "lm_5", .id = LM_5,
+ .base = 0x49000, .len = 0x320,
+ .features = MIXER_SDM845_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_4,
+ .pingpong = PINGPONG_5,
+ },
};
static const struct dpu_dspp_cfg sm8550_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index cc459c2700b2..6ef0dc2e1a5d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -375,17 +375,6 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
* MIXER sub blocks config
*************************************************************/
-#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
- { \
- .name = _name, .id = _id, \
- .base = _base, .len = 0x320, \
- .features = _fmask, \
- .sblk = _sblk, \
- .pingpong = _pp, \
- .lm_pair = _lmpair, \
- .dspp = _dspp \
- }
-
/* MSM8998 */
static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 13/19] drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (11 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 12/19] drm/msm/dpu: inline LM_BLK macros Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-27 8:29 ` Marijn Suijten
2023-06-19 21:25 ` [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros Dmitry Baryshkov
` (5 subsequent siblings)
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 9 ++++-
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 17 +++++++--
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 21 +++++++++--
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 31 +++++++++++++---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 21 +++++++++--
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 6 ++-
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 6 ++-
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 25 +++++++++++--
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +++-
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 37 ++++++++++++++++---
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 25 +++++++++++--
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 25 +++++++++++--
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 --------
13 files changed, 189 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index a07c68744b29..d5111f3782a2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -200,8 +200,13 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = {
};
static const struct dpu_dsc_cfg msm8998_dsc[] = {
- DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
- DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
+ {
+ .name = "dsc_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x140,
+ }, {
+ .name = "dsc_1", .id = DSC_1,
+ .base = 0x80400, .len = 0x140,
+ },
};
static const struct dpu_dspp_cfg msm8998_dspp[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 786263ed1ef2..b6f52b3864ce 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -224,10 +224,19 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = {
};
static const struct dpu_dsc_cfg sdm845_dsc[] = {
- DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
- DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
- DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
- DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
+ {
+ .name = "dsc_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x140,
+ }, {
+ .name = "dsc_1", .id = DSC_1,
+ .base = 0x80400, .len = 0x140,
+ }, {
+ .name = "dsc_2", .id = DSC_2,
+ .base = 0x80800, .len = 0x140,
+ }, {
+ .name = "dsc_3", .id = DSC_3,
+ .base = 0x80c00, .len = 0x140,
+ },
};
static const struct dpu_intf_cfg sdm845_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 6b9bfeac6e0a..9b2de5986e82 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
};
static const struct dpu_dsc_cfg sm8150_dsc[] = {
- DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
+ {
+ .name = "dsc_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_1", .id = DSC_1,
+ .base = 0x80400, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_2", .id = DSC_2,
+ .base = 0x80800, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_3", .id = DSC_3,
+ .base = 0x80c00, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ },
};
static const struct dpu_intf_cfg sm8150_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 414f0db3306c..683602e54c0e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -244,12 +244,31 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
};
static const struct dpu_dsc_cfg sc8180x_dsc[] = {
- DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)),
+ {
+ .name = "dsc_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_1", .id = DSC_1,
+ .base = 0x80400, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_2", .id = DSC_2,
+ .base = 0x80800, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_3", .id = DSC_3,
+ .base = 0x80c00, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_4", .id = DSC_4,
+ .base = 0x81000, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_5", .id = DSC_5,
+ .base = 0x81400, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ },
};
static const struct dpu_intf_cfg sc8180x_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index db3a65b011ca..a98d63f6c47c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
};
static const struct dpu_dsc_cfg sm8250_dsc[] = {
- DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
- DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
+ {
+ .name = "dsc_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_1", .id = DSC_1,
+ .base = 0x80400, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_2", .id = DSC_2,
+ .base = 0x80800, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ }, {
+ .name = "dsc_3", .id = DSC_3,
+ .base = 0x80c00, .len = 0x140,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ },
};
static const struct dpu_intf_cfg sm8250_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index a996c39b7b1f..a9907010a4a2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -136,7 +136,11 @@ static struct dpu_pingpong_cfg sm6350_pp[] = {
};
static const struct dpu_dsc_cfg sm6350_dsc[] = {
- DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
+ {
+ .name = "dsc_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x1800,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ },
};
static const struct dpu_intf_cfg sm6350_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 0cdb77599583..e42f0dc3b2ab 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -90,7 +90,11 @@ static const struct dpu_pingpong_cfg sm6375_pp[] = {
};
static const struct dpu_dsc_cfg sm6375_dsc[] = {
- DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
+ {
+ .name = "dsc_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x1800,
+ .features = BIT(DPU_DSC_OUTPUT_CTRL),
+ },
};
static const struct dpu_intf_cfg sm6375_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index e08b29e9e146..8a9bfc4af72a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -248,10 +248,27 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
* its own different sub block address.
*/
static const struct dpu_dsc_cfg sm8350_dsc[] = {
- DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
- DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
- DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
- DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
+ {
+ .name = "dce_0_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_0_1", .id = DSC_1,
+ .base = 0x80000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_1,
+ }, {
+ .name = "dce_1_0", .id = DSC_2,
+ .base = 0x81000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_1_1", .id = DSC_3,
+ .base = 0x81000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_1,
+ },
};
static const struct dpu_intf_cfg sm8350_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index d5faa1816cb3..9c0beccce282 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -146,7 +146,12 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
/* NOTE: sc7280 only has one DSC hard slice encoder */
static const struct dpu_dsc_cfg sc7280_dsc[] = {
- DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
+ {
+ .name = "dce_0_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_0,
+ },
};
static const struct dpu_wb_cfg sc7280_wb[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 8e4299be2b1c..b676819db42c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -246,12 +246,37 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
* its own different sub block address.
*/
static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
- DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
- DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
- DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
- DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
- DSC_BLK_1_2("dce_2_0", DSC_4, 0x82000, 0x29c, 0, dsc_sblk_0),
- DSC_BLK_1_2("dce_2_1", DSC_5, 0x82000, 0x29c, 0, dsc_sblk_1),
+ {
+ .name = "dce_0_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_0_1", .id = DSC_1,
+ .base = 0x80000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_1,
+ }, {
+ .name = "dce_1_0", .id = DSC_2,
+ .base = 0x81000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_1_1", .id = DSC_3,
+ .base = 0x81000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_1,
+ }, {
+ .name = "dce_2_0", .id = DSC_4,
+ .base = 0x82000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_2_1", .id = DSC_5,
+ .base = 0x82000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_1,
+ },
};
/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index bbee3c621943..568523abc1d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -259,10 +259,27 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
* its own different sub block address.
*/
static const struct dpu_dsc_cfg sm8450_dsc[] = {
- DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
- DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
- DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
- DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
+ {
+ .name = "dce_0_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_0_1", .id = DSC_1,
+ .base = 0x80000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_1,
+ }, {
+ .name = "dce_1_0", .id = DSC_2,
+ .base = 0x81000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_1_1", .id = DSC_3,
+ .base = 0x81000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_1,
+ },
};
static const struct dpu_intf_cfg sm8450_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index ea7bffe252a5..419624948e83 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -273,10 +273,27 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
* its own different sub block address.
*/
static const struct dpu_dsc_cfg sm8550_dsc[] = {
- DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
- DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
- DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
- DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
+ {
+ .name = "dce_0_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_0_1", .id = DSC_1,
+ .base = 0x80000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2),
+ .sblk = &dsc_sblk_1,
+ }, {
+ .name = "dce_1_0", .id = DSC_2,
+ .base = 0x81000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_0,
+ }, {
+ .name = "dce_1_1", .id = DSC_3,
+ .base = 0x81000, .len = 0x29c,
+ .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &dsc_sblk_1,
+ },
};
static const struct dpu_intf_cfg sm8550_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 6ef0dc2e1a5d..ee24402bf253 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -495,21 +495,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
.ctl = {.base = 0xF80, .len = 0x10},
};
-#define DSC_BLK(_name, _id, _base, _features) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = 0x140, \
- .features = _features, \
- }
-
-#define DSC_BLK_1_2(_name, _id, _base, _len, _features, _sblk) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = _len, \
- .features = BIT(DPU_DSC_HW_REV_1_2) | _features, \
- .sblk = &_sblk, \
- }
-
/*************************************************************
* INTF sub blocks config
*************************************************************/
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (12 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 13/19] drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-27 8:34 ` Marijn Suijten
2023-07-03 20:29 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 15/19] drm/msm/dpu: inline various PP_BLK_* macros Dmitry Baryshkov
` (4 subsequent siblings)
18 siblings, 2 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 16 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 16 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 16 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 16 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 16 +++++++++++---
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 21 +++++++++++++++----
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 21 +++++++++++++++----
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 11 ----------
8 files changed, 99 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 9b2de5986e82..0e09e759dc99 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -239,9 +239,19 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
};
static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
- MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
- MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
- MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
+ {
+ .name = "merge_3d_0", .id = MERGE_3D_0,
+ .base = 0x83000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x83100, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_2", .id = MERGE_3D_2,
+ .base = 0x83200, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ },
};
static const struct dpu_dsc_cfg sm8150_dsc[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 683602e54c0e..4d2b0409a244 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -238,9 +238,19 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
};
static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
- MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
- MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
- MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
+ {
+ .name = "merge_3d_0", .id = MERGE_3D_0,
+ .base = 0x83000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x83100, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_2", .id = MERGE_3D_2,
+ .base = 0x83200, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ },
};
static const struct dpu_dsc_cfg sc8180x_dsc[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index a98d63f6c47c..50f857565dbf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -239,9 +239,19 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
};
static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
- MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
- MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
- MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
+ {
+ .name = "merge_3d_0", .id = MERGE_3D_0,
+ .base = 0x83000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x83100, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_2", .id = MERGE_3D_2,
+ .base = 0x83200, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ },
};
static const struct dpu_dsc_cfg sm8250_dsc[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 8a9bfc4af72a..0added438239 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -237,9 +237,19 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
};
static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
- MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
- MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
- MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
+ {
+ .name = "merge_3d_0", .id = MERGE_3D_0,
+ .base = 0x4e000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x4f000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_2", .id = MERGE_3D_2,
+ .base = 0x50000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ },
};
/*
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index b676819db42c..0b4915dabe7a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -235,9 +235,19 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
};
static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
- MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
- MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
- MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
+ {
+ .name = "merge_3d_0", .id = MERGE_3D_0,
+ .base = 0x4e000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x4f000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_2", .id = MERGE_3D_2,
+ .base = 0x50000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ },
};
/*
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 568523abc1d0..45cda9162685 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -247,10 +247,23 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
};
static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
- MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
- MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
- MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
- MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
+ {
+ .name = "merge_3d_0", .id = MERGE_3D_0,
+ .base = 0x4e000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x4f000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_2", .id = MERGE_3D_2,
+ .base = 0x50000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_3", .id = MERGE_3D_3,
+ .base = 0x65f00, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ },
};
/*
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 419624948e83..66dd414253f1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -261,10 +261,23 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
};
static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
- MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
- MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
- MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
- MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700),
+ {
+ .name = "merge_3d_0", .id = MERGE_3D_0,
+ .base = 0x4e000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x4f000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_2", .id = MERGE_3D_2,
+ .base = 0x50000, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ }, {
+ .name = "merge_3d_3", .id = MERGE_3D_3,
+ .base = 0x66700, .len = 0x8,
+ .features = MERGE_3D_SM8150_MASK,
+ },
};
/*
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index ee24402bf253..72634a8109e8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -471,17 +471,6 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
.intr_rdptr = _rdptr, \
}
-/*************************************************************
- * MERGE_3D sub blocks config
- *************************************************************/
-#define MERGE_3D_BLK(_name, _id, _base) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = 0x8, \
- .features = MERGE_3D_SM8150_MASK, \
- .sblk = NULL \
- }
-
/*************************************************************
* DSC sub blocks config
*************************************************************/
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 15/19] drm/msm/dpu: inline various PP_BLK_* macros
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (13 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-27 8:35 ` Marijn Suijten
2023-07-03 21:01 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 16/19] drm/msm/dpu: inline WB_BLK macros Dmitry Baryshkov
` (3 subsequent siblings)
18 siblings, 2 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 41 ++++++---
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 41 ++++++---
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 67 ++++++++++----
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 67 ++++++++++----
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 67 ++++++++++----
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 23 +++--
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 12 ++-
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 23 +++--
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 12 ++-
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 12 ++-
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 67 ++++++++++----
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 45 +++++++---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 61 ++++++++++---
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 89 ++++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 89 ++++++++++++++-----
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 21 -----
16 files changed, 527 insertions(+), 210 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index d5111f3782a2..9181d3ef8013 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -185,18 +185,35 @@ static const struct dpu_lm_cfg msm8998_lm[] = {
};
static const struct dpu_pingpong_cfg msm8998_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
- PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
- PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
- PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SDM845_TE2_MASK,
+ .sblk = &sdm845_pp_sblk_te,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SDM845_TE2_MASK,
+ .sblk = &sdm845_pp_sblk_te,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x71000, .len = 0xd4,
+ .features = PINGPONG_SDM845_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x71800, .len = 0xd4,
+ .features = PINGPONG_SDM845_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
+ },
};
static const struct dpu_dsc_cfg msm8998_dsc[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index b6f52b3864ce..8119a81ff260 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -209,18 +209,35 @@ static const struct dpu_dspp_cfg sdm845_dspp[] = {
};
static const struct dpu_pingpong_cfg sdm845_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
- PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
- PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
- PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SDM845_TE2_MASK,
+ .sblk = &sdm845_pp_sblk_te,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SDM845_TE2_MASK,
+ .sblk = &sdm845_pp_sblk_te,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x71000, .len = 0xd4,
+ .features = PINGPONG_SDM845_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x71800, .len = 0xd4,
+ .features = PINGPONG_SDM845_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
+ },
};
static const struct dpu_dsc_cfg sdm845_dsc[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 0e09e759dc99..2f6899ebad06 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -218,24 +218,55 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = {
};
static const struct dpu_pingpong_cfg sm8150_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- -1),
- PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
- -1),
- PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
- -1),
- PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
- -1),
- PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x71000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x71800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_4", .id = PINGPONG_4,
+ .base = 0x72000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_5", .id = PINGPONG_5,
+ .base = 0x72800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 4d2b0409a244..15975460dbad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -217,24 +217,55 @@ static const struct dpu_dspp_cfg sc8180x_dspp[] = {
};
static const struct dpu_pingpong_cfg sc8180x_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- -1),
- PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
- -1),
- PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
- -1),
- PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
- -1),
- PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x71000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x71800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_4", .id = PINGPONG_4,
+ .base = 0x72000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_5", .id = PINGPONG_5,
+ .base = 0x72800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 50f857565dbf..c8f4c6326a1a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -218,24 +218,55 @@ static const struct dpu_dspp_cfg sm8250_dspp[] = {
};
static const struct dpu_pingpong_cfg sm8250_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- -1),
- PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
- -1),
- PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
- -1),
- PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
- -1),
- PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x71000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x71800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_4", .id = PINGPONG_4,
+ .base = 0x72000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_5", .id = PINGPONG_5,
+ .base = 0x72800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 5d71c9cfcba8..d7d117e3af36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -118,12 +118,23 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = {
};
static const struct dpu_pingpong_cfg sc7180_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_intf_cfg sc7180_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 459955c1af2d..4236cd7317a1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -82,9 +82,15 @@ static const struct dpu_dspp_cfg sm6115_dspp[] = {
};
static const struct dpu_pingpong_cfg sm6115_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_intf_cfg sm6115_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index a9907010a4a2..82c04d2ce010 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -127,12 +127,23 @@ static const struct dpu_dspp_cfg sm6350_dspp[] = {
};
static struct dpu_pingpong_cfg sm6350_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_dsc_cfg sm6350_dsc[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 3c4f4a4ad51b..c6bf487e131b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -79,9 +79,15 @@ static const struct dpu_dspp_cfg qcm2290_dspp[] = {
};
static const struct dpu_pingpong_cfg qcm2290_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_intf_cfg qcm2290_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index e42f0dc3b2ab..97de7a1f52b4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -84,9 +84,15 @@ static const struct dpu_dspp_cfg sm6375_dspp[] = {
};
static const struct dpu_pingpong_cfg sm6375_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .sblk = &sdm845_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_dsc_cfg sm6375_dsc[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 0added438239..108e35cbcd90 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -216,24 +216,55 @@ static const struct dpu_dspp_cfg sm8350_dspp[] = {
};
static const struct dpu_pingpong_cfg sm8350_pp[] = {
- PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
- PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- -1),
- PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
- -1),
- PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
- -1),
- PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
- -1),
- PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x69000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x6a000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x6b000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x6c000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_4", .id = PINGPONG_4,
+ .base = 0x6d000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_5", .id = PINGPONG_5,
+ .base = 0x6e000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 9c0beccce282..3b67010f336b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -130,18 +130,39 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = {
};
static const struct dpu_pingpong_cfg sc7280_pp[] = {
- PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
- PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- -1),
- PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
- -1),
- PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x69000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x6a000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x6b000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x6c000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = 0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = -1,
+ },
};
/* NOTE: sc7280 only has one DSC hard slice encoder */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 0b4915dabe7a..062b17dedec7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -220,18 +220,55 @@ static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
};
static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
- PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
- PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),
- PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),
- PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),
- PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),
- PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x69000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x6a000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x6b000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x6c000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_4", .id = PINGPONG_4,
+ .base = 0x6d000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_5", .id = PINGPONG_5,
+ .base = 0x6e000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 45cda9162685..d92af1410c3e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -220,30 +220,71 @@ static const struct dpu_dspp_cfg sm8450_dspp[] = {
};
static const struct dpu_pingpong_cfg sm8450_pp[] = {
- PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
- PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- -1),
- PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
- -1),
- PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
- -1),
- PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
- -1),
- PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
- -1),
- PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sc7280_pp_sblk,
- -1,
- -1),
- PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sc7280_pp_sblk,
- -1,
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x69000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x6a000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x6b000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x6c000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_4", .id = PINGPONG_4,
+ .base = 0x6d000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_5", .id = PINGPONG_5,
+ .base = 0x6e000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_6", .id = PINGPONG_6,
+ .base = 0x65800, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_3,
+ .intr_done = -1,
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_7", .id = PINGPONG_7,
+ .base = 0x65c00, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_3,
+ .intr_done = -1,
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 66dd414253f1..32ffb9a9cfc7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -234,30 +234,71 @@ static const struct dpu_dspp_cfg sm8550_dspp[] = {
},
};
static const struct dpu_pingpong_cfg sm8550_pp[] = {
- PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
- -1),
- PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
- -1),
- PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
- -1),
- PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
- -1),
- PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
- -1),
- PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
- -1),
- PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk,
- -1,
- -1),
- PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk,
- -1,
- -1),
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x69000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x6a000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_0,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x6b000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x6c000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_4", .id = PINGPONG_4,
+ .base = 0x6d000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_5", .id = PINGPONG_5,
+ .base = 0x6e000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_2,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_6", .id = PINGPONG_6,
+ .base = 0x66000, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_3,
+ .intr_done = -1,
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_7", .id = PINGPONG_7,
+ .base = 0x66400, .len = 0,
+ .features = BIT(DPU_PINGPONG_DITHER),
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_3,
+ .intr_done = -1,
+ .intr_rdptr = -1,
+ },
};
static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 72634a8109e8..3ea63ca358a4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -450,27 +450,6 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
.len = 0x20, .version = 0x20000},
};
-#define PP_BLK_DITHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = 0, \
- .features = BIT(DPU_PINGPONG_DITHER), \
- .merge_3d = _merge_3d, \
- .sblk = &_sblk, \
- .intr_done = _done, \
- .intr_rdptr = _rdptr, \
- }
-#define PP_BLK(_name, _id, _base, _features, _merge_3d, _sblk, _done, _rdptr) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = 0xd4, \
- .features = _features, \
- .merge_3d = _merge_3d, \
- .sblk = &_sblk, \
- .intr_done = _done, \
- .intr_rdptr = _rdptr, \
- }
-
/*************************************************************
* DSC sub blocks config
*************************************************************/
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 16/19] drm/msm/dpu: inline WB_BLK macros
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (14 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 15/19] drm/msm/dpu: inline various PP_BLK_* macros Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-27 8:35 ` Marijn Suijten
2023-07-03 21:04 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros Dmitry Baryshkov
` (2 subsequent siblings)
18 siblings, 2 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 14 ++++++++++++--
.../drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 14 ++++++++++++--
.../drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 14 ++++++++++++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 18 ------------------
4 files changed, 36 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index c8f4c6326a1a..9148d7da62e4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -323,8 +323,18 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
};
static const struct dpu_wb_cfg sm8250_wb[] = {
- WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
- VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SM8250_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
};
static const struct dpu_perf_cfg sm8250_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index d7d117e3af36..904c758a60df 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -148,8 +148,18 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
};
static const struct dpu_wb_cfg sc7180_wb[] = {
- WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
- VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SM8250_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
};
static const struct dpu_perf_cfg sc7180_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 3b67010f336b..7b5c9a77b102 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -176,8 +176,18 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = {
};
static const struct dpu_wb_cfg sc7280_wb[] = {
- WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
- VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SM8250_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
};
static const struct dpu_intf_cfg sc7280_intf[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 3ea63ca358a4..d2bca1ec0e63 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -493,24 +493,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
.intr_tear_rd_ptr = _tear_rd_ptr, \
}
-/*************************************************************
- * Writeback blocks config
- *************************************************************/
-#define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
- __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
- { \
- .name = _name, .id = _id, \
- .base = _base, .len = 0x2c8, \
- .features = _features, \
- .format_list = wb2_formats, \
- .num_formats = ARRAY_SIZE(wb2_formats), \
- .clk_ctrl = _clk_ctrl, \
- .xin_id = __xin_id, \
- .vbif_idx = vbif_id, \
- .maxlinewidth = _max_linewidth, \
- .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
- }
-
/*************************************************************
* VBIF sub blocks config
*************************************************************/
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (15 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 16/19] drm/msm/dpu: inline WB_BLK macros Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-06-27 8:35 ` Marijn Suijten
2023-07-03 21:06 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 18/19] drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK Dmitry Baryshkov
2023-06-19 21:25 ` [PATCH v4 19/19] drm/msm/dpu: drop empty features mask INTF_SDM845_MASK Dmitry Baryshkov
18 siblings, 2 replies; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 52 ++++++--
.../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 53 ++++++--
.../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 55 ++++++--
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 82 +++++++++---
.../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 55 ++++++--
.../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 28 +++-
.../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 15 ++-
.../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 28 +++-
.../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 15 ++-
.../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 15 ++-
.../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 55 ++++++--
.../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 41 ++++--
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 120 +++++++++++++-----
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 55 ++++++--
.../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 55 ++++++--
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 30 -----
16 files changed, 545 insertions(+), 209 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 9181d3ef8013..4ce25ed4e36f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -241,18 +241,46 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
};
static const struct dpu_intf_cfg msm8998_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
- INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SDM845_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 21,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x280,
+ .features = INTF_SDM845_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 21,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x6b000, .len = 0x280,
+ .features = INTF_SDM845_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 21,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x6b800, .len = 0x280,
+ .features = INTF_SDM845_MASK,
+ .type = INTF_HDMI,
+ .prog_fetch_lines_worst_case = 21,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_perf_cfg msm8998_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 8119a81ff260..5ad82b109ebb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -257,18 +257,47 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
};
static const struct dpu_intf_cfg sdm845_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
- INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SDM845_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x280,
+ .features = INTF_SDM845_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x6b000, .len = 0x280,
+ .features = INTF_SDM845_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x6b800, .len = 0x280,
+ .features = INTF_SDM845_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_perf_cfg sdm845_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 2f6899ebad06..341ab9b84d20 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -306,20 +306,47 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
};
static const struct dpu_intf_cfg sm8150_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2bc,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x6b000, .len = 0x2bc,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x6b800, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_perf_cfg sm8150_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 15975460dbad..8dd36a85b685 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -313,27 +313,69 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = {
};
static const struct dpu_intf_cfg sc8180x_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2bc,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x6b000, .len = 0x2bc,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
+ },
/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
- INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),
- INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
+ {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x6b800, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = 999,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_4", .id = INTF_4,
+ .base = 0x6c000, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_5", .id = INTF_5,
+ .base = 0x6c800, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_2,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_perf_cfg sc8180x_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 9148d7da62e4..e16ffade5aca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -306,20 +306,47 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
};
static const struct dpu_intf_cfg sm8250_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x6b000, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x6b800, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_wb_cfg sm8250_wb[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 904c758a60df..0f59e372cf3e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -138,13 +138,27 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = {
};
static const struct dpu_intf_cfg sc7180_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ },
};
static const struct dpu_wb_cfg sc7180_wb[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 4236cd7317a1..f01eac27f405 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -94,10 +94,17 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
};
static const struct dpu_intf_cfg sm6115_intf[] = {
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+ {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ },
};
static const struct dpu_perf_cfg sm6115_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 82c04d2ce010..df4bf6510123 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -155,13 +155,27 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
};
static const struct dpu_intf_cfg sm6350_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 35, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 35, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 35,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 35,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ },
};
static const struct dpu_perf_cfg sm6350_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index c6bf487e131b..cb486bea6628 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -91,10 +91,17 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
};
static const struct dpu_intf_cfg qcm2290_intf[] = {
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+ {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ },
};
static const struct dpu_perf_cfg qcm2290_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 97de7a1f52b4..74dc032af7a4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -104,10 +104,17 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
};
static const struct dpu_intf_cfg sm6375_intf[] = {
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+ {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ },
};
static const struct dpu_perf_cfg sm6375_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 108e35cbcd90..d5191a663ae1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -313,20 +313,47 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = {
};
static const struct dpu_intf_cfg sm8350_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
- INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x34000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x35000, .len = 0x2c4,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x36000, .len = 0x2c4,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x37000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_perf_cfg sm8350_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 7b5c9a77b102..d3a18048972f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -191,16 +191,37 @@ static const struct dpu_wb_cfg sc7280_wb[] = {
};
static const struct dpu_intf_cfg sc7280_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
- INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x34000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x35000, .len = 0x2c4,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
+ }, {
+ .name = "intf_5", .id = INTF_5,
+ .base = 0x39000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_perf_cfg sc7280_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 062b17dedec7..9f94cc6369dd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -328,35 +328,97 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
static const struct dpu_intf_cfg sc8280xp_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
- INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
- INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),
- INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
- INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17)),
- INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19)),
- INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x34000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x35000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x36000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x37000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_NONE,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_4", .id = INTF_4,
+ .base = 0x38000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_5", .id = INTF_5,
+ .base = 0x39000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_3,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_6", .id = INTF_6,
+ .base = 0x3a000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_2,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_7", .id = INTF_7,
+ .base = 0x3b000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_NONE,
+ .controller_id = MSM_DP_CONTROLLER_2,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_8", .id = INTF_8,
+ .base = 0x3c000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_NONE,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_perf_cfg sc8280xp_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index d92af1410c3e..517629c4a168 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -337,20 +337,47 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = {
};
static const struct dpu_intf_cfg sm8450_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
- INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x34000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x35000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x36000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x37000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_perf_cfg sm8450_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 32ffb9a9cfc7..ed1d1d4092e8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -351,20 +351,47 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = {
};
static const struct dpu_intf_cfg sm8550_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
- INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
- DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
- INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
- DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
- INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x34000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x35000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x36000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x37000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ .intr_tear_rd_ptr = -1,
+ },
};
static const struct dpu_perf_cfg sm8550_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d2bca1ec0e63..6acd34e61aca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -463,36 +463,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
.ctl = {.base = 0xF80, .len = 0x10},
};
-/*************************************************************
- * INTF sub blocks config
- *************************************************************/
-#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = _len, \
- .features = _features, \
- .type = _type, \
- .controller_id = _ctrl_id, \
- .prog_fetch_lines_worst_case = _progfetch, \
- .intr_underrun = _underrun, \
- .intr_vsync = _vsync, \
- .intr_tear_rd_ptr = -1, \
- }
-
-/* DSI Interface sub-block with TEAR registers (since DPU 5.0.0) */
-#define INTF_BLK_DSI_TE(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync, _tear_rd_ptr) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = _len, \
- .features = _features, \
- .type = _type, \
- .controller_id = _ctrl_id, \
- .prog_fetch_lines_worst_case = _progfetch, \
- .intr_underrun = _underrun, \
- .intr_vsync = _vsync, \
- .intr_tear_rd_ptr = _tear_rd_ptr, \
- }
-
/*************************************************************
* VBIF sub blocks config
*************************************************************/
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 18/19] drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (16 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-07-03 21:08 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 19/19] drm/msm/dpu: drop empty features mask INTF_SDM845_MASK Dmitry Baryshkov
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
The MERGE_3D_SM8150_MASK features mask is zero. Drop it completely.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 --
8 files changed, 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 341ab9b84d20..e6d4a2bfc2be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -273,15 +273,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
{
.name = "merge_3d_0", .id = MERGE_3D_0,
.base = 0x83000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_1", .id = MERGE_3D_1,
.base = 0x83100, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_2", .id = MERGE_3D_2,
.base = 0x83200, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 8dd36a85b685..b4baf6707018 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -272,15 +272,12 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
{
.name = "merge_3d_0", .id = MERGE_3D_0,
.base = 0x83000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_1", .id = MERGE_3D_1,
.base = 0x83100, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_2", .id = MERGE_3D_2,
.base = 0x83200, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index e16ffade5aca..265d88b288b6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -273,15 +273,12 @@ static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
{
.name = "merge_3d_0", .id = MERGE_3D_0,
.base = 0x83000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_1", .id = MERGE_3D_1,
.base = 0x83100, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_2", .id = MERGE_3D_2,
.base = 0x83200, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index d5191a663ae1..59a96a4b250c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -271,15 +271,12 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
{
.name = "merge_3d_0", .id = MERGE_3D_0,
.base = 0x4e000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_1", .id = MERGE_3D_1,
.base = 0x4f000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_2", .id = MERGE_3D_2,
.base = 0x50000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 9f94cc6369dd..7110caae7251 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -275,15 +275,12 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
{
.name = "merge_3d_0", .id = MERGE_3D_0,
.base = 0x4e000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_1", .id = MERGE_3D_1,
.base = 0x4f000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_2", .id = MERGE_3D_2,
.base = 0x50000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 517629c4a168..dcafab3e4b1a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -291,19 +291,15 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
{
.name = "merge_3d_0", .id = MERGE_3D_0,
.base = 0x4e000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_1", .id = MERGE_3D_1,
.base = 0x4f000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_2", .id = MERGE_3D_2,
.base = 0x50000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_3", .id = MERGE_3D_3,
.base = 0x65f00, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index ed1d1d4092e8..7b96f827c2b1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -305,19 +305,15 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
{
.name = "merge_3d_0", .id = MERGE_3D_0,
.base = 0x4e000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_1", .id = MERGE_3D_1,
.base = 0x4f000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_2", .id = MERGE_3D_2,
.base = 0x50000, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
}, {
.name = "merge_3d_3", .id = MERGE_3D_3,
.base = 0x66700, .len = 0x8,
- .features = MERGE_3D_SM8150_MASK,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 6acd34e61aca..4a18fc66a412 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -93,8 +93,6 @@
#define CTL_SM8550_MASK \
(CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
-#define MERGE_3D_SM8150_MASK (0)
-
#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
#define INTF_SDM845_MASK (0)
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH v4 19/19] drm/msm/dpu: drop empty features mask INTF_SDM845_MASK
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
` (17 preceding siblings ...)
2023-06-19 21:25 ` [PATCH v4 18/19] drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK Dmitry Baryshkov
@ 2023-06-19 21:25 ` Dmitry Baryshkov
2023-07-03 21:12 ` Abhinav Kumar
18 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 21:25 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
The INTF_SDM845_MASK features mask is zero. Drop it completely.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 --
3 files changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 4ce25ed4e36f..7d87dc2d7b1b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -244,7 +244,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SDM845_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 21,
@@ -254,7 +253,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x280,
- .features = INTF_SDM845_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 21,
@@ -264,7 +262,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x6b000, .len = 0x280,
- .features = INTF_SDM845_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 21,
@@ -274,7 +271,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x6b800, .len = 0x280,
- .features = INTF_SDM845_MASK,
.type = INTF_HDMI,
.prog_fetch_lines_worst_case = 21,
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 5ad82b109ebb..66e3573eb613 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -260,7 +260,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SDM845_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -270,7 +269,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x280,
- .features = INTF_SDM845_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -280,7 +278,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x6b000, .len = 0x280,
- .features = INTF_SDM845_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -290,7 +287,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x6b800, .len = 0x280,
- .features = INTF_SDM845_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4a18fc66a412..3efa22429e5f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -95,8 +95,6 @@
#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
-#define INTF_SDM845_MASK (0)
-
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
BIT(DPU_INTF_TE) | \
--
2.39.2
^ permalink raw reply related [flat|nested] 59+ messages in thread
* Re: [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-06-19 21:25 ` [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field Dmitry Baryshkov
@ 2023-06-26 12:28 ` Marijn Suijten
2023-07-03 2:01 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Marijn Suijten @ 2023-06-26 12:28 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, Abhinav Kumar, dri-devel,
Stephen Boyd, linux-arm-msm
On 2023-06-20 00:25:04, Dmitry Baryshkov wrote:
> There is always a single MDP TOP block. Drop the mdp_count field and
> stop declaring dpu_mdp_cfg instances as arrays.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
<snip>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> index a1a9e44bed36..c89746c6f500 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> @@ -146,13 +146,11 @@ struct dpu_hw_mdp {
>
> /**
> * dpu_hw_mdptop_init - initializes the top driver for the passed idx
No index is passed anymore, only a pointer directly to const catalog
data. After fixing that:
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> - * @idx: Interface index for which driver object is required
> + * @cfg: MDP TOP configuration from catalog
> * @addr: Mapped register io address of MDP
> - * @m: Pointer to mdss catalog data
> */
> -struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
> - void __iomem *addr,
> - const struct dpu_mdss_cfg *m);
> +struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
> + void __iomem *addr);
>
> void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp);
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index aa8499de1b9f..882f20fc51cc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1092,8 +1092,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>
> dpu_kms->rm_init = true;
>
> - dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
> - dpu_kms->catalog);
> + dpu_kms->hw_mdp = dpu_hw_mdptop_init(dpu_kms->catalog->mdp,
> + dpu_kms->mmio);
> if (IS_ERR(dpu_kms->hw_mdp)) {
> rc = PTR_ERR(dpu_kms->hw_mdp);
> DPU_ERROR("failed to get hw_mdp: %d\n", rc);
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 13/19] drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros
2023-06-19 21:25 ` [PATCH v4 13/19] drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros Dmitry Baryshkov
@ 2023-06-27 8:29 ` Marijn Suijten
2023-07-03 18:52 ` Abhinav Kumar
0 siblings, 1 reply; 59+ messages in thread
From: Marijn Suijten @ 2023-06-27 8:29 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, Abhinav Kumar, dri-devel,
Stephen Boyd, linux-arm-msm
On 2023-06-20 00:25:13, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
You still have two 0x1800's that should be 0x140. Diffing the
disassembly:
diff --git a/baseline.dis b/dpu_hw_catalog.dis
index 5a45280..04df183 100644
--- a/baseline.dis
+++ b/dpu_hw_catalog.dis
@@ -1,5 +1,5 @@
-baseline.o: file format elf64-littleaarch64
+dpu_hw_catalog.o: file format elf64-littleaarch64
Disassembly of section .data:
@@ -2808,7 +2808,7 @@ Disassembly of section .rodata:
...
3b18: 00000001 udf #1
3b1c: 00080000 .inst 0x00080000 ; undefined
- 3b20: 00000140 udf #320
+ 3b20: 00001800 udf #6144
3b24: 00000000 udf #0
3b28: 00000002 udf #2
...
@@ -3112,7 +3112,7 @@ Disassembly of section .rodata:
...
43a8: 00000001 udf #1
43ac: 00080000 .inst 0x00080000 ; undefined
- 43b0: 00000140 udf #320
+ 43b0: 00001800 udf #6144
43b4: 00000000 udf #0
43b8: 00000002 udf #2
...
These are the freshly added SM6350/75, see below.
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 9 ++++-
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 17 +++++++--
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 21 +++++++++--
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 31 +++++++++++++---
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 21 +++++++++--
> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 6 ++-
> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 6 ++-
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 25 +++++++++++--
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +++-
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 37 ++++++++++++++++---
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 25 +++++++++++--
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 25 +++++++++++--
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 --------
> 13 files changed, 189 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index a07c68744b29..d5111f3782a2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -200,8 +200,13 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = {
> };
>
> static const struct dpu_dsc_cfg msm8998_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
> - DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x140,
> + }, {
> + .name = "dsc_1", .id = DSC_1,
> + .base = 0x80400, .len = 0x140,
> + },
> };
>
> static const struct dpu_dspp_cfg msm8998_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 786263ed1ef2..b6f52b3864ce 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -224,10 +224,19 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = {
> };
>
> static const struct dpu_dsc_cfg sdm845_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
> - DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
> - DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
> - DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x140,
> + }, {
> + .name = "dsc_1", .id = DSC_1,
> + .base = 0x80400, .len = 0x140,
> + }, {
> + .name = "dsc_2", .id = DSC_2,
> + .base = 0x80800, .len = 0x140,
> + }, {
> + .name = "dsc_3", .id = DSC_3,
> + .base = 0x80c00, .len = 0x140,
> + },
> };
>
> static const struct dpu_intf_cfg sdm845_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 6b9bfeac6e0a..9b2de5986e82 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
> };
>
> static const struct dpu_dsc_cfg sm8150_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_1", .id = DSC_1,
> + .base = 0x80400, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_2", .id = DSC_2,
> + .base = 0x80800, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_3", .id = DSC_3,
> + .base = 0x80c00, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + },
> };
>
> static const struct dpu_intf_cfg sm8150_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 414f0db3306c..683602e54c0e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -244,12 +244,31 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
> };
>
> static const struct dpu_dsc_cfg sc8180x_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_1", .id = DSC_1,
> + .base = 0x80400, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_2", .id = DSC_2,
> + .base = 0x80800, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_3", .id = DSC_3,
> + .base = 0x80c00, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_4", .id = DSC_4,
> + .base = 0x81000, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_5", .id = DSC_5,
> + .base = 0x81400, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + },
> };
>
> static const struct dpu_intf_cfg sc8180x_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index db3a65b011ca..a98d63f6c47c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
> };
>
> static const struct dpu_dsc_cfg sm8250_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
> - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_1", .id = DSC_1,
> + .base = 0x80400, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_2", .id = DSC_2,
> + .base = 0x80800, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + }, {
> + .name = "dsc_3", .id = DSC_3,
> + .base = 0x80c00, .len = 0x140,
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + },
> };
>
> static const struct dpu_intf_cfg sm8250_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index a996c39b7b1f..a9907010a4a2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -136,7 +136,11 @@ static struct dpu_pingpong_cfg sm6350_pp[] = {
> };
>
> static const struct dpu_dsc_cfg sm6350_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x1800,
Here.
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + },
> };
>
> static const struct dpu_intf_cfg sm6350_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 0cdb77599583..e42f0dc3b2ab 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -90,7 +90,11 @@ static const struct dpu_pingpong_cfg sm6375_pp[] = {
> };
>
> static const struct dpu_dsc_cfg sm6375_dsc[] = {
> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
> + {
> + .name = "dsc_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x1800,
And here.
- Marijn
> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
> + },
> };
>
> static const struct dpu_intf_cfg sm6375_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index e08b29e9e146..8a9bfc4af72a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -248,10 +248,27 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
> * its own different sub block address.
> */
> static const struct dpu_dsc_cfg sm8350_dsc[] = {
> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
> - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
> - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
> - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
> + {
> + .name = "dce_0_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_0,
> + }, {
> + .name = "dce_0_1", .id = DSC_1,
> + .base = 0x80000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_1,
> + }, {
> + .name = "dce_1_0", .id = DSC_2,
> + .base = 0x81000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .sblk = &dsc_sblk_0,
> + }, {
> + .name = "dce_1_1", .id = DSC_3,
> + .base = 0x81000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .sblk = &dsc_sblk_1,
> + },
> };
>
> static const struct dpu_intf_cfg sm8350_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index d5faa1816cb3..9c0beccce282 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -146,7 +146,12 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
>
> /* NOTE: sc7280 only has one DSC hard slice encoder */
> static const struct dpu_dsc_cfg sc7280_dsc[] = {
> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
> + {
> + .name = "dce_0_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .sblk = &dsc_sblk_0,
> + },
> };
>
> static const struct dpu_wb_cfg sc7280_wb[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 8e4299be2b1c..b676819db42c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -246,12 +246,37 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
> * its own different sub block address.
> */
> static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
> - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
> - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
> - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
> - DSC_BLK_1_2("dce_2_0", DSC_4, 0x82000, 0x29c, 0, dsc_sblk_0),
> - DSC_BLK_1_2("dce_2_1", DSC_5, 0x82000, 0x29c, 0, dsc_sblk_1),
> + {
> + .name = "dce_0_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_0,
> + }, {
> + .name = "dce_0_1", .id = DSC_1,
> + .base = 0x80000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_1,
> + }, {
> + .name = "dce_1_0", .id = DSC_2,
> + .base = 0x81000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .sblk = &dsc_sblk_0,
> + }, {
> + .name = "dce_1_1", .id = DSC_3,
> + .base = 0x81000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .sblk = &dsc_sblk_1,
> + }, {
> + .name = "dce_2_0", .id = DSC_4,
> + .base = 0x82000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_0,
> + }, {
> + .name = "dce_2_1", .id = DSC_5,
> + .base = 0x82000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_1,
> + },
> };
>
> /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index bbee3c621943..568523abc1d0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -259,10 +259,27 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
> * its own different sub block address.
> */
> static const struct dpu_dsc_cfg sm8450_dsc[] = {
> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
> - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
> - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
> - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
> + {
> + .name = "dce_0_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_0,
> + }, {
> + .name = "dce_0_1", .id = DSC_1,
> + .base = 0x80000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_1,
> + }, {
> + .name = "dce_1_0", .id = DSC_2,
> + .base = 0x81000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .sblk = &dsc_sblk_0,
> + }, {
> + .name = "dce_1_1", .id = DSC_3,
> + .base = 0x81000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .sblk = &dsc_sblk_1,
> + },
> };
>
> static const struct dpu_intf_cfg sm8450_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index ea7bffe252a5..419624948e83 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -273,10 +273,27 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
> * its own different sub block address.
> */
> static const struct dpu_dsc_cfg sm8550_dsc[] = {
> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
> - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
> - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
> - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
> + {
> + .name = "dce_0_0", .id = DSC_0,
> + .base = 0x80000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_0,
> + }, {
> + .name = "dce_0_1", .id = DSC_1,
> + .base = 0x80000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2),
> + .sblk = &dsc_sblk_1,
> + }, {
> + .name = "dce_1_0", .id = DSC_2,
> + .base = 0x81000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .sblk = &dsc_sblk_0,
> + }, {
> + .name = "dce_1_1", .id = DSC_3,
> + .base = 0x81000, .len = 0x29c,
> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .sblk = &dsc_sblk_1,
> + },
> };
>
> static const struct dpu_intf_cfg sm8550_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 6ef0dc2e1a5d..ee24402bf253 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -495,21 +495,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
> .ctl = {.base = 0xF80, .len = 0x10},
> };
>
> -#define DSC_BLK(_name, _id, _base, _features) \
> - {\
> - .name = _name, .id = _id, \
> - .base = _base, .len = 0x140, \
> - .features = _features, \
> - }
> -
> -#define DSC_BLK_1_2(_name, _id, _base, _len, _features, _sblk) \
> - {\
> - .name = _name, .id = _id, \
> - .base = _base, .len = _len, \
> - .features = BIT(DPU_DSC_HW_REV_1_2) | _features, \
> - .sblk = &_sblk, \
> - }
> -
> /*************************************************************
> * INTF sub blocks config
> *************************************************************/
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros
2023-06-19 21:25 ` [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros Dmitry Baryshkov
@ 2023-06-27 8:33 ` Marijn Suijten
2023-07-03 16:09 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Marijn Suijten @ 2023-06-27 8:33 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, Abhinav Kumar, dri-devel,
Stephen Boyd, linux-arm-msm
On 2023-06-20 00:25:10, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Validated that this incurs no changes by checksumming a stripped
dpu_hw_catalog.o.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 81 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 81 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 81 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 81 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 81 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 41 +++++--
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 21 +++-
> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 41 +++++--
> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 21 +++-
> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 21 +++-
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 81 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 41 +++++--
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 81 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 81 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 101 ++++++++++++++----
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ---
> 16 files changed, 751 insertions(+), 196 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 6660a55909e7..fd0081469a82 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -71,22 +71,71 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg msm8998_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,
> - msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,
> - msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,
> - msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,
> - msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1ac,
> + .features = VIG_MSM8998_MASK,
> + .sblk = &msm8998_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x1ac,
> + .features = VIG_MSM8998_MASK,
> + .sblk = &msm8998_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x1ac,
> + .features = VIG_MSM8998_MASK,
> + .sblk = &msm8998_vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x1ac,
> + .features = VIG_MSM8998_MASK,
> + .sblk = &msm8998_vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1ac,
> + .features = DMA_MSM8998_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1ac,
> + .features = DMA_MSM8998_MASK,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1ac,
> + .features = DMA_CURSOR_MSM8998_MASK,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x1ac,
> + .features = DMA_CURSOR_MSM8998_MASK,
> + .sblk = &sdm845_dma_sblk_3,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + },
> };
>
> static const struct dpu_lm_cfg msm8998_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 8f96a9e4ee4c..7ba99060d13d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -69,22 +69,71 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sdm845_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA,
> - sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA,
> - sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA,
> - sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA,
> - sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1c8,
> + .features = VIG_SDM845_MASK_SDMA,
> + .sblk = &sdm845_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x1c8,
> + .features = VIG_SDM845_MASK_SDMA,
> + .sblk = &sdm845_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x1c8,
> + .features = VIG_SDM845_MASK_SDMA,
> + .sblk = &sdm845_vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x1c8,
> + .features = VIG_SDM845_MASK_SDMA,
> + .sblk = &sdm845_vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1c8,
> + .features = DMA_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1c8,
> + .features = DMA_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1c8,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x1c8,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_3,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + },
> };
>
> static const struct dpu_lm_cfg sdm845_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 7a37e9ef3085..13d86229219e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm8150_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
> - sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
> - sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
> - sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
> - sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f0,
> + .features = VIG_SDM845_MASK,
> + .sblk = &sdm845_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x1f0,
> + .features = VIG_SDM845_MASK,
> + .sblk = &sdm845_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x1f0,
> + .features = VIG_SDM845_MASK,
> + .sblk = &sdm845_vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x1f0,
> + .features = VIG_SDM845_MASK,
> + .sblk = &sdm845_vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f0,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1f0,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1f0,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x1f0,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_3,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + },
> };
>
> static const struct dpu_lm_cfg sm8150_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 9e288d849a8a..76b59b27d1ee 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -77,22 +77,71 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sc8180x_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
> - sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
> - sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
> - sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
> - sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f0,
> + .features = VIG_SDM845_MASK,
> + .sblk = &sdm845_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x1f0,
> + .features = VIG_SDM845_MASK,
> + .sblk = &sdm845_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x1f0,
> + .features = VIG_SDM845_MASK,
> + .sblk = &sdm845_vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x1f0,
> + .features = VIG_SDM845_MASK,
> + .sblk = &sdm845_vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f0,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1f0,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1f0,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x1f0,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_3,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + },
> };
>
> static const struct dpu_lm_cfg sc8180x_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 82adbdaba472..5d9718f20429 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm8250_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA,
> - sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA,
> - sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA,
> - sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA,
> - sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK_SDMA,
> + .sblk = &sm8250_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK_SDMA,
> + .sblk = &sm8250_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK_SDMA,
> + .sblk = &sm8250_vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK_SDMA,
> + .sblk = &sm8250_vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_3,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + },
> };
>
> static const struct dpu_lm_cfg sm8250_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index a7f067f4c4ba..cd76e17a8501 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -54,14 +54,39 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sc7180_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> - sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sc7180_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + },
> };
>
> static const struct dpu_lm_cfg sc7180_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 2cf3ed980582..dfba4efe5f39 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -42,10 +42,23 @@ static const struct dpu_ctl_cfg sm6115_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm6115_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> - sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm6115_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + },
> };
>
> static const struct dpu_lm_cfg sm6115_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 4ba2f7acf8b7..602197844580 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -62,14 +62,39 @@ static const struct dpu_ctl_cfg sm6350_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm6350_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> - sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sc7180_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + },
> };
>
> static const struct dpu_lm_cfg sm6350_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 3094f4dc6a76..8d766236b459 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -39,10 +39,23 @@ static const struct dpu_ctl_cfg qcm2290_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
> - qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> - qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f8,
> + .features = VIG_QCM2290_MASK,
> + .sblk = &qcm2290_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK,
> + .sblk = &qcm2290_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + },
> };
>
> static const struct dpu_lm_cfg qcm2290_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index e9c63eeb280f..9864f649113c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -43,10 +43,23 @@ static const struct dpu_ctl_cfg sm6375_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm6375_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> - sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm6115_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + },
> };
>
> static const struct dpu_lm_cfg sm6375_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 8e63d6f310c2..16b46c045706 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -76,22 +76,71 @@ static const struct dpu_ctl_cfg sm8350_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm8350_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> - sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK,
> - sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK,
> - sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK,
> - sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x1f8,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_3,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + },
> };
>
> static const struct dpu_lm_cfg sm8350_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 783deae7c1c4..2901c96f3587 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -60,14 +60,39 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sc7280_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA,
> - sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1f8,
> + .features = VIG_SC7280_MASK_SDMA,
> + .sblk = &sc7280_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1f8,
> + .features = DMA_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x1f8,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + },
> };
>
> static const struct dpu_lm_cfg sc7280_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index db4d6643c0dd..9c4ec2d5ab14 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK,
> - sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x2ac, VIG_SC7180_MASK,
> - sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x2ac, VIG_SC7180_MASK,
> - sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x2ac, VIG_SC7180_MASK,
> - sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x2ac, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x2ac, DMA_SDM845_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x2ac, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x2ac, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x2ac,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x2ac,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x2ac,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x2ac,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x2ac,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x2ac,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x2ac,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x2ac,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_3,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + },
> };
>
> static const struct dpu_lm_cfg sc8280xp_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 8fdf55c25b9f..39534de5472c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm8450_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x32c, VIG_SC7180_MASK,
> - sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x32c, VIG_SC7180_MASK,
> - sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x32c, VIG_SC7180_MASK,
> - sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x32c, VIG_SC7180_MASK,
> - sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x32c, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x32c, DMA_SDM845_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x32c, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x32c, DMA_CURSOR_SDM845_MASK,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x32c,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x32c,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x32c,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x32c,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8250_vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x32c,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x32c,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x32c,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x32c,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_3,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + },
> };
>
> static const struct dpu_lm_cfg sm8450_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 8d733ef606b9..8ddf398d7f54 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -79,26 +79,87 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm8550_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK,
> - sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK,
> - sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK,
> - sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK,
> - sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> - SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK,
> - sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4),
> - SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK,
> - sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x344,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8550_vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x344,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8550_vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x344,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8550_vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x344,
> + .features = VIG_SC7180_MASK,
> + .sblk = &sm8550_vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x344,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x344,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA1,
> + }, {
> + .name = "sspp_10", .id = SSPP_DMA2,
> + .base = 0x28000, .len = 0x344,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_2,
> + .xin_id = 9,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA2,
> + }, {
> + .name = "sspp_11", .id = SSPP_DMA3,
> + .base = 0x2a000, .len = 0x344,
> + .features = DMA_SDM845_MASK,
> + .sblk = &sdm845_dma_sblk_3,
> + .xin_id = 13,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA3,
> + }, {
> + .name = "sspp_12", .id = SSPP_DMA4,
> + .base = 0x2c000, .len = 0x344,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sm8550_dma_sblk_4,
> + .xin_id = 14,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA4,
> + }, {
> + .name = "sspp_13", .id = SSPP_DMA5,
> + .base = 0x2e000, .len = 0x344,
> + .features = DMA_CURSOR_SDM845_MASK,
> + .sblk = &sm8550_dma_sblk_5,
> + .xin_id = 15,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA5,
> + },
> };
>
> static const struct dpu_lm_cfg sm8550_lm[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 30fb5b1f3966..9661dc7a4570 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -328,18 +328,6 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
>
> -#define SSPP_BLK(_name, _id, _base, _len, _features, \
> - _sblk, _xinid, _type, _clkctrl) \
> - { \
> - .name = _name, .id = _id, \
> - .base = _base, .len = _len, \
> - .features = _features, \
> - .sblk = &_sblk, \
> - .xin_id = _xinid, \
> - .type = _type, \
> - .clk_ctrl = _clkctrl \
> - }
> -
> static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
> _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
>
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 11/19] drm/msm/dpu: inline DSPP_BLK macros
2023-06-19 21:25 ` [PATCH v4 11/19] drm/msm/dpu: inline DSPP_BLK macros Dmitry Baryshkov
@ 2023-06-27 8:34 ` Marijn Suijten
2023-07-03 16:14 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Marijn Suijten @ 2023-06-27 8:34 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, Abhinav Kumar, dri-devel,
Stephen Boyd, linux-arm-msm
On 2023-06-20 00:25:11, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Validated that this incurs no changes by checksumming a stripped
dpu_hw_catalog.o.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 15 +++++++---
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 29 ++++++++++++++-----
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 29 ++++++++++++++-----
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 29 ++++++++++++++-----
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 29 ++++++++++++++-----
> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 +++--
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 +++--
> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 8 +++--
> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 +++--
> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 8 +++--
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 29 ++++++++++++++-----
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8 +++--
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 29 ++++++++++++++-----
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 29 ++++++++++++++-----
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 29 ++++++++++++++-----
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 -----
> 16 files changed, 215 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index fd0081469a82..6b254753774c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -174,10 +174,17 @@ static const struct dpu_dsc_cfg msm8998_dsc[] = {
> };
>
> static const struct dpu_dspp_cfg msm8998_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &msm8998_dspp_sblk),
> - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
> - &msm8998_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &msm8998_dspp_sblk,
> + }, {
> + .name = "dspp_1", .id = DSPP_1,
> + .base = 0x56000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &msm8998_dspp_sblk,
> + },
> };
>
> static const struct dpu_intf_cfg msm8998_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 7ba99060d13d..8661ef2f45e0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -152,14 +152,27 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sdm845_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_1", .id = DSPP_1,
> + .base = 0x56000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_2", .id = DSPP_2,
> + .base = 0x58000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_3", .id = DSPP_3,
> + .base = 0x5a000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sdm845_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 13d86229219e..ab933b5a4806 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -161,14 +161,27 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sm8150_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_1", .id = DSPP_1,
> + .base = 0x56000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_2", .id = DSPP_2,
> + .base = 0x58000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_3", .id = DSPP_3,
> + .base = 0x5a000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sm8150_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 76b59b27d1ee..68c9034bb552 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -160,14 +160,27 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sc8180x_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_1", .id = DSPP_1,
> + .base = 0x56000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_2", .id = DSPP_2,
> + .base = 0x58000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_3", .id = DSPP_3,
> + .base = 0x5a000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sc8180x_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 5d9718f20429..1383697f24dd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -161,14 +161,27 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sm8250_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_1", .id = DSPP_1,
> + .base = 0x56000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_2", .id = DSPP_2,
> + .base = 0x58000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_3", .id = DSPP_3,
> + .base = 0x5a000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sm8250_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index cd76e17a8501..9fd4b1c37bc1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -97,8 +97,12 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sc7180_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sc7180_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index dfba4efe5f39..1c69b28cc3a7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -67,8 +67,12 @@ static const struct dpu_lm_cfg sm6115_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sm6115_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sm6115_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 602197844580..9874b30fd1e7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -105,8 +105,12 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sm6350_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static struct dpu_pingpong_cfg sm6350_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 8d766236b459..128dc13d4e21 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -64,8 +64,12 @@ static const struct dpu_lm_cfg qcm2290_lm[] = {
> };
>
> static const struct dpu_dspp_cfg qcm2290_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg qcm2290_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 9864f649113c..7d64336a607a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -68,8 +68,12 @@ static const struct dpu_lm_cfg sm6375_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sm6375_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sm6375_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 16b46c045706..6c57b3478db8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -159,14 +159,27 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sm8350_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_1", .id = DSPP_1,
> + .base = 0x56000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_2", .id = DSPP_2,
> + .base = 0x58000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_3", .id = DSPP_3,
> + .base = 0x5a000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sm8350_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 2901c96f3587..a46134205df2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -105,8 +105,12 @@ static const struct dpu_lm_cfg sc7280_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sc7280_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sc7280_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 9c4ec2d5ab14..e61116d4366c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -155,14 +155,27 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_1", .id = DSPP_1,
> + .base = 0x56000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_2", .id = DSPP_2,
> + .base = 0x58000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_3", .id = DSPP_3,
> + .base = 0x5a000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 39534de5472c..3a4e8a9010f2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -161,14 +161,27 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sm8450_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_1", .id = DSPP_1,
> + .base = 0x56000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_2", .id = DSPP_2,
> + .base = 0x58000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_3", .id = DSPP_3,
> + .base = 0x5a000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
>
> static const struct dpu_pingpong_cfg sm8450_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 8ddf398d7f54..423d0d26de48 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -178,14 +178,27 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
> };
>
> static const struct dpu_dspp_cfg sm8550_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
> - &sm8150_dspp_sblk),
> + {
> + .name = "dspp_0", .id = DSPP_0,
> + .base = 0x54000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_1", .id = DSPP_1,
> + .base = 0x56000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_2", .id = DSPP_2,
> + .base = 0x58000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + }, {
> + .name = "dspp_3", .id = DSPP_3,
> + .base = 0x5a000, .len = 0x1800,
> + .features = DSPP_SC7180_MASK,
> + .sblk = &sm8150_dspp_sblk,
> + },
> };
> static const struct dpu_pingpong_cfg sm8550_pp[] = {
> PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 9661dc7a4570..cc459c2700b2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -441,14 +441,6 @@ static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
> .len = 0x90, .version = 0x40000},
> };
>
> -#define DSPP_BLK(_name, _id, _base, _mask, _sblk) \
> - {\
> - .name = _name, .id = _id, \
> - .base = _base, .len = 0x1800, \
> - .features = _mask, \
> - .sblk = _sblk \
> - }
> -
> /*************************************************************
> * PINGPONG sub blocks config
> *************************************************************/
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 12/19] drm/msm/dpu: inline LM_BLK macros
2023-06-19 21:25 ` [PATCH v4 12/19] drm/msm/dpu: inline LM_BLK macros Dmitry Baryshkov
@ 2023-06-27 8:34 ` Marijn Suijten
2023-07-03 18:46 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Marijn Suijten @ 2023-06-27 8:34 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, Abhinav Kumar, dri-devel,
Stephen Boyd, linux-arm-msm
On 2023-06-20 00:25:12, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Validated that this incurs no changes by checksumming a stripped
dpu_hw_catalog.o.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 55 +++++++++++++----
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 57 ++++++++++++++----
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 57 ++++++++++++++----
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 57 ++++++++++++++----
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 57 ++++++++++++++----
> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 20 +++++--
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 10 +++-
> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 21 +++++--
> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 10 +++-
> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 11 +++-
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 57 ++++++++++++++----
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 28 +++++++--
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 53 +++++++++++++++--
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 59 +++++++++++++++----
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 57 ++++++++++++++----
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 11 ----
> 16 files changed, 487 insertions(+), 133 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 6b254753774c..a07c68744b29 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -139,18 +139,49 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
> };
>
> static const struct dpu_lm_cfg msm8998_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
> - &msm8998_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
> - &msm8998_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
> - &msm8998_lm_sblk, PINGPONG_2, LM_5, 0),
> - LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
> - &msm8998_lm_sblk, PINGPONG_NONE, 0, 0),
> - LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
> - &msm8998_lm_sblk, PINGPONG_NONE, 0, 0),
> - LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
> - &msm8998_lm_sblk, PINGPONG_3, LM_2, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_MSM8998_MASK,
> + .sblk = &msm8998_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_MSM8998_MASK,
> + .sblk = &msm8998_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = DSPP_1,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_MSM8998_MASK,
> + .sblk = &msm8998_lm_sblk,
> + .lm_pair = LM_5,
> + .pingpong = PINGPONG_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x47000, .len = 0x320,
> + .features = MIXER_MSM8998_MASK,
> + .sblk = &msm8998_lm_sblk,
> + .pingpong = PINGPONG_NONE,
> + }, {
> + .name = "lm_4", .id = LM_4,
> + .base = 0x48000, .len = 0x320,
> + .features = MIXER_MSM8998_MASK,
> + .sblk = &msm8998_lm_sblk,
> + .pingpong = PINGPONG_NONE,
> + }, {
> + .name = "lm_5", .id = LM_5,
> + .base = 0x49000, .len = 0x320,
> + .features = MIXER_MSM8998_MASK,
> + .sblk = &msm8998_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + },
> };
>
> static const struct dpu_pingpong_cfg msm8998_pp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 8661ef2f45e0..786263ed1ef2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -137,18 +137,51 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sdm845_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_2, LM_5, DSPP_2),
> - LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_NONE, 0, DSPP_3),
> - LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_NONE, 0, 0),
> - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = DSPP_1,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_5,
> + .pingpong = PINGPONG_2,
> + .dspp = DSPP_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x0, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .pingpong = PINGPONG_NONE,
> + .dspp = DSPP_3,
> + }, {
> + .name = "lm_4", .id = LM_4,
> + .base = 0x0, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .pingpong = PINGPONG_NONE,
> + }, {
> + .name = "lm_5", .id = LM_5,
> + .base = 0x49000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + },
> };
>
> static const struct dpu_dspp_cfg sdm845_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index ab933b5a4806..6b9bfeac6e0a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -146,18 +146,51 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sm8150_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
> - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
> - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
> - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = DSPP_1,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_3,
> + .pingpong = PINGPONG_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x47000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + }, {
> + .name = "lm_4", .id = LM_4,
> + .base = 0x48000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_5,
> + .pingpong = PINGPONG_4,
> + }, {
> + .name = "lm_5", .id = LM_5,
> + .base = 0x49000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_4,
> + .pingpong = PINGPONG_5,
> + },
> };
>
> static const struct dpu_dspp_cfg sm8150_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 68c9034bb552..414f0db3306c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -145,18 +145,51 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sc8180x_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
> - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
> - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
> - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = DSPP_1,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_3,
> + .pingpong = PINGPONG_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x47000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + }, {
> + .name = "lm_4", .id = LM_4,
> + .base = 0x48000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_5,
> + .pingpong = PINGPONG_4,
> + }, {
> + .name = "lm_5", .id = LM_5,
> + .base = 0x49000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_4,
> + .pingpong = PINGPONG_5,
> + },
> };
>
> static const struct dpu_dspp_cfg sc8180x_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 1383697f24dd..db3a65b011ca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -146,18 +146,51 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sm8250_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
> - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
> - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
> - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = DSPP_1,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_3,
> + .pingpong = PINGPONG_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x47000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + }, {
> + .name = "lm_4", .id = LM_4,
> + .base = 0x48000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_5,
> + .pingpong = PINGPONG_4,
> + }, {
> + .name = "lm_5", .id = LM_5,
> + .base = 0x49000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_4,
> + .pingpong = PINGPONG_5,
> + },
> };
>
> static const struct dpu_dspp_cfg sm8250_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 9fd4b1c37bc1..5d71c9cfcba8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -90,10 +90,22 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sc7180_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> - &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sc7180_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sc7180_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + },
> };
>
> static const struct dpu_dspp_cfg sc7180_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 1c69b28cc3a7..459955c1af2d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -62,8 +62,14 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sm6115_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> - &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_QCM2290_MASK,
> + .sblk = &qcm2290_lm_sblk,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + },
> };
>
> static const struct dpu_dspp_cfg sm6115_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 9874b30fd1e7..a996c39b7b1f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -98,10 +98,23 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sm6350_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> - &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sc7180_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sc7180_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = 0,
> + },
> };
>
> static const struct dpu_dspp_cfg sm6350_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 128dc13d4e21..3c4f4a4ad51b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -59,8 +59,14 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = {
> };
>
> static const struct dpu_lm_cfg qcm2290_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> - &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_QCM2290_MASK,
> + .sblk = &qcm2290_lm_sblk,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + },
> };
>
> static const struct dpu_dspp_cfg qcm2290_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 7d64336a607a..0cdb77599583 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -63,8 +63,15 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sm6375_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
> - &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_QCM2290_MASK,
> + .sblk = &qcm2290_lm_sblk,
> + .lm_pair = 0,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + },
> };
>
> static const struct dpu_dspp_cfg sm6375_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 6c57b3478db8..e08b29e9e146 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -144,18 +144,51 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sm8350_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
> - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
> - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
> - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = DSPP_1,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_3,
> + .pingpong = PINGPONG_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x47000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + }, {
> + .name = "lm_4", .id = LM_4,
> + .base = 0x48000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_5,
> + .pingpong = PINGPONG_4,
> + }, {
> + .name = "lm_5", .id = LM_5,
> + .base = 0x49000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_4,
> + .pingpong = PINGPONG_5,
> + },
> };
>
> static const struct dpu_dspp_cfg sm8350_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index a46134205df2..d5faa1816cb3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -96,12 +96,28 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sc7280_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
> - &sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
> - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
> - &sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sc7180_lm_sblk,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sc7180_lm_sblk,
> + .lm_pair = LM_3,
> + .pingpong = PINGPONG_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x47000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sc7180_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + },
> };
>
> static const struct dpu_dspp_cfg sc7280_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index e61116d4366c..8e4299be2b1c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -146,12 +146,53 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sc8280xp_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
> - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
> - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
> - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = DSPP_1,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_3,
> + .pingpong = PINGPONG_2,
> + .dspp = DSPP_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x47000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + .dspp = DSPP_3,
> + }, {
> + .name = "lm_4", .id = LM_4,
> + .base = 0x48000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_5,
> + .pingpong = PINGPONG_4,
> + }, {
> + .name = "lm_5", .id = LM_5,
> + .base = 0x49000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_4,
> + .pingpong = PINGPONG_5,
> + },
> };
>
> static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 3a4e8a9010f2..bbee3c621943 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -146,18 +146,53 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sm8450_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
> - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
> - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
> - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = DSPP_1,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_3,
> + .pingpong = PINGPONG_2,
> + .dspp = DSPP_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x47000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + .dspp = DSPP_3,
> + }, {
> + .name = "lm_4", .id = LM_4,
> + .base = 0x48000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_5,
> + .pingpong = PINGPONG_4,
> + }, {
> + .name = "lm_5", .id = LM_5,
> + .base = 0x49000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_4,
> + .pingpong = PINGPONG_5,
> + },
> };
>
> static const struct dpu_dspp_cfg sm8450_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 423d0d26de48..ea7bffe252a5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -163,18 +163,51 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
> };
>
> static const struct dpu_lm_cfg sm8550_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
> - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
> - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
> - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
> - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
> - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
> - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
> + {
> + .name = "lm_0", .id = LM_0,
> + .base = 0x44000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_1,
> + .pingpong = PINGPONG_0,
> + .dspp = DSPP_0,
> + }, {
> + .name = "lm_1", .id = LM_1,
> + .base = 0x45000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_0,
> + .pingpong = PINGPONG_1,
> + .dspp = DSPP_1,
> + }, {
> + .name = "lm_2", .id = LM_2,
> + .base = 0x46000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_3,
> + .pingpong = PINGPONG_2,
> + }, {
> + .name = "lm_3", .id = LM_3,
> + .base = 0x47000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_2,
> + .pingpong = PINGPONG_3,
> + }, {
> + .name = "lm_4", .id = LM_4,
> + .base = 0x48000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_5,
> + .pingpong = PINGPONG_4,
> + }, {
> + .name = "lm_5", .id = LM_5,
> + .base = 0x49000, .len = 0x320,
> + .features = MIXER_SDM845_MASK,
> + .sblk = &sdm845_lm_sblk,
> + .lm_pair = LM_4,
> + .pingpong = PINGPONG_5,
> + },
> };
>
> static const struct dpu_dspp_cfg sm8550_dspp[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index cc459c2700b2..6ef0dc2e1a5d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -375,17 +375,6 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
> * MIXER sub blocks config
> *************************************************************/
>
> -#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
> - { \
> - .name = _name, .id = _id, \
> - .base = _base, .len = 0x320, \
> - .features = _fmask, \
> - .sblk = _sblk, \
> - .pingpong = _pp, \
> - .lm_pair = _lmpair, \
> - .dspp = _dspp \
> - }
> -
> /* MSM8998 */
>
> static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros
2023-06-19 21:25 ` [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros Dmitry Baryshkov
@ 2023-06-27 8:34 ` Marijn Suijten
2023-07-03 20:29 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Marijn Suijten @ 2023-06-27 8:34 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, Abhinav Kumar, dri-devel,
Stephen Boyd, linux-arm-msm
On 2023-06-20 00:25:14, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Validated that this incurs no changes by checksumming a stripped
dpu_hw_catalog.o.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 16 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 16 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 16 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 16 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 16 +++++++++++---
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 21 +++++++++++++++----
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 21 +++++++++++++++----
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 11 ----------
> 8 files changed, 99 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 9b2de5986e82..0e09e759dc99 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -239,9 +239,19 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
> };
>
> static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
> - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
> - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
> - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
> + {
> + .name = "merge_3d_0", .id = MERGE_3D_0,
> + .base = 0x83000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_1", .id = MERGE_3D_1,
> + .base = 0x83100, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_2", .id = MERGE_3D_2,
> + .base = 0x83200, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + },
> };
>
> static const struct dpu_dsc_cfg sm8150_dsc[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 683602e54c0e..4d2b0409a244 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -238,9 +238,19 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
> };
>
> static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
> - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
> - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
> - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
> + {
> + .name = "merge_3d_0", .id = MERGE_3D_0,
> + .base = 0x83000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_1", .id = MERGE_3D_1,
> + .base = 0x83100, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_2", .id = MERGE_3D_2,
> + .base = 0x83200, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + },
> };
>
> static const struct dpu_dsc_cfg sc8180x_dsc[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index a98d63f6c47c..50f857565dbf 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -239,9 +239,19 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
> };
>
> static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
> - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
> - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
> - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
> + {
> + .name = "merge_3d_0", .id = MERGE_3D_0,
> + .base = 0x83000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_1", .id = MERGE_3D_1,
> + .base = 0x83100, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_2", .id = MERGE_3D_2,
> + .base = 0x83200, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + },
> };
>
> static const struct dpu_dsc_cfg sm8250_dsc[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 8a9bfc4af72a..0added438239 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -237,9 +237,19 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
> };
>
> static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
> - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> + {
> + .name = "merge_3d_0", .id = MERGE_3D_0,
> + .base = 0x4e000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_1", .id = MERGE_3D_1,
> + .base = 0x4f000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_2", .id = MERGE_3D_2,
> + .base = 0x50000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + },
> };
>
> /*
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index b676819db42c..0b4915dabe7a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -235,9 +235,19 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
> };
>
> static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
> - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> + {
> + .name = "merge_3d_0", .id = MERGE_3D_0,
> + .base = 0x4e000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_1", .id = MERGE_3D_1,
> + .base = 0x4f000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_2", .id = MERGE_3D_2,
> + .base = 0x50000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + },
> };
>
> /*
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 568523abc1d0..45cda9162685 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -247,10 +247,23 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
> };
>
> static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
> - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> - MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
> + {
> + .name = "merge_3d_0", .id = MERGE_3D_0,
> + .base = 0x4e000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_1", .id = MERGE_3D_1,
> + .base = 0x4f000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_2", .id = MERGE_3D_2,
> + .base = 0x50000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_3", .id = MERGE_3D_3,
> + .base = 0x65f00, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + },
> };
>
> /*
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 419624948e83..66dd414253f1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -261,10 +261,23 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
> };
>
> static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
> - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
> - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
> - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
> - MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700),
> + {
> + .name = "merge_3d_0", .id = MERGE_3D_0,
> + .base = 0x4e000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_1", .id = MERGE_3D_1,
> + .base = 0x4f000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_2", .id = MERGE_3D_2,
> + .base = 0x50000, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + }, {
> + .name = "merge_3d_3", .id = MERGE_3D_3,
> + .base = 0x66700, .len = 0x8,
> + .features = MERGE_3D_SM8150_MASK,
> + },
> };
>
> /*
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index ee24402bf253..72634a8109e8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -471,17 +471,6 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
> .intr_rdptr = _rdptr, \
> }
>
> -/*************************************************************
> - * MERGE_3D sub blocks config
> - *************************************************************/
> -#define MERGE_3D_BLK(_name, _id, _base) \
> - {\
> - .name = _name, .id = _id, \
> - .base = _base, .len = 0x8, \
> - .features = MERGE_3D_SM8150_MASK, \
> - .sblk = NULL \
> - }
> -
> /*************************************************************
> * DSC sub blocks config
> *************************************************************/
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 15/19] drm/msm/dpu: inline various PP_BLK_* macros
2023-06-19 21:25 ` [PATCH v4 15/19] drm/msm/dpu: inline various PP_BLK_* macros Dmitry Baryshkov
@ 2023-06-27 8:35 ` Marijn Suijten
2023-07-03 21:01 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Marijn Suijten @ 2023-06-27 8:35 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, Abhinav Kumar, dri-devel,
Stephen Boyd, linux-arm-msm
On 2023-06-20 00:25:15, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Validated that this incurs no changes by checksumming a stripped
dpu_hw_catalog.o.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 41 ++++++---
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 41 ++++++---
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 67 ++++++++++----
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 67 ++++++++++----
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 67 ++++++++++----
> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 23 +++--
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 12 ++-
> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 23 +++--
> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 12 ++-
> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 12 ++-
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 67 ++++++++++----
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 45 +++++++---
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 61 ++++++++++---
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 89 ++++++++++++++-----
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 89 ++++++++++++++-----
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 21 -----
> 16 files changed, 527 insertions(+), 210 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index d5111f3782a2..9181d3ef8013 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -185,18 +185,35 @@ static const struct dpu_lm_cfg msm8998_lm[] = {
> };
>
> static const struct dpu_pingpong_cfg msm8998_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SDM845_TE2_MASK,
> + .sblk = &sdm845_pp_sblk_te,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x70800, .len = 0xd4,
> + .features = PINGPONG_SDM845_TE2_MASK,
> + .sblk = &sdm845_pp_sblk_te,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x71000, .len = 0xd4,
> + .features = PINGPONG_SDM845_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x71800, .len = 0xd4,
> + .features = PINGPONG_SDM845_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
> + },
> };
>
> static const struct dpu_dsc_cfg msm8998_dsc[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index b6f52b3864ce..8119a81ff260 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -209,18 +209,35 @@ static const struct dpu_dspp_cfg sdm845_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sdm845_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SDM845_TE2_MASK,
> + .sblk = &sdm845_pp_sblk_te,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x70800, .len = 0xd4,
> + .features = PINGPONG_SDM845_TE2_MASK,
> + .sblk = &sdm845_pp_sblk_te,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x71000, .len = 0xd4,
> + .features = PINGPONG_SDM845_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x71800, .len = 0xd4,
> + .features = PINGPONG_SDM845_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
> + },
> };
>
> static const struct dpu_dsc_cfg sdm845_dsc[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 0e09e759dc99..2f6899ebad06 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -218,24 +218,55 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm8150_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - -1),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> - -1),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> - -1),
> - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> - -1),
> - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x70800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x71000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x71800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_4", .id = PINGPONG_4,
> + .base = 0x72000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_5", .id = PINGPONG_5,
> + .base = 0x72800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 4d2b0409a244..15975460dbad 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -217,24 +217,55 @@ static const struct dpu_dspp_cfg sc8180x_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sc8180x_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - -1),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> - -1),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> - -1),
> - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> - -1),
> - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x70800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x71000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x71800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_4", .id = PINGPONG_4,
> + .base = 0x72000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_5", .id = PINGPONG_5,
> + .base = 0x72800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 50f857565dbf..c8f4c6326a1a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -218,24 +218,55 @@ static const struct dpu_dspp_cfg sm8250_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm8250_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - -1),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> - -1),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> - -1),
> - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> - -1),
> - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x70800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x71000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x71800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_4", .id = PINGPONG_4,
> + .base = 0x72000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_5", .id = PINGPONG_5,
> + .base = 0x72800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 5d71c9cfcba8..d7d117e3af36 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -118,12 +118,23 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sc7180_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x70800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_intf_cfg sc7180_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 459955c1af2d..4236cd7317a1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -82,9 +82,15 @@ static const struct dpu_dspp_cfg sm6115_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm6115_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_intf_cfg sm6115_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index a9907010a4a2..82c04d2ce010 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -127,12 +127,23 @@ static const struct dpu_dspp_cfg sm6350_dspp[] = {
> };
>
> static struct dpu_pingpong_cfg sm6350_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x70800, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_dsc_cfg sm6350_dsc[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 3c4f4a4ad51b..c6bf487e131b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -79,9 +79,15 @@ static const struct dpu_dspp_cfg qcm2290_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg qcm2290_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_intf_cfg qcm2290_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index e42f0dc3b2ab..97de7a1f52b4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -84,9 +84,15 @@ static const struct dpu_dspp_cfg sm6375_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm6375_pp[] = {
> - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x70000, .len = 0xd4,
> + .features = PINGPONG_SM8150_MASK,
> + .sblk = &sdm845_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_dsc_cfg sm6375_dsc[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 0added438239..108e35cbcd90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -216,24 +216,55 @@ static const struct dpu_dspp_cfg sm8350_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm8350_pp[] = {
> - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - -1),
> - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> - -1),
> - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> - -1),
> - PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> - -1),
> - PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x69000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x6a000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x6b000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x6c000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_4", .id = PINGPONG_4,
> + .base = 0x6d000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_5", .id = PINGPONG_5,
> + .base = 0x6e000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 9c0beccce282..3b67010f336b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -130,18 +130,39 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sc7280_pp[] = {
> - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - -1),
> - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> - -1),
> - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x69000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x6a000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x6b000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x6c000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = 0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = -1,
> + },
> };
>
> /* NOTE: sc7280 only has one DSC hard slice encoder */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 0b4915dabe7a..062b17dedec7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -220,18 +220,55 @@ static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
> - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
> - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),
> - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),
> - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),
> - PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),
> - PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x69000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x6a000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x6b000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x6c000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_4", .id = PINGPONG_4,
> + .base = 0x6d000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_5", .id = PINGPONG_5,
> + .base = 0x6e000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 45cda9162685..d92af1410c3e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -220,30 +220,71 @@ static const struct dpu_dspp_cfg sm8450_dspp[] = {
> };
>
> static const struct dpu_pingpong_cfg sm8450_pp[] = {
> - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - -1),
> - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> - -1),
> - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> - -1),
> - PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> - -1),
> - PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> - -1),
> - PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sc7280_pp_sblk,
> - -1,
> - -1),
> - PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sc7280_pp_sblk,
> - -1,
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x69000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x6a000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x6b000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x6c000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_4", .id = PINGPONG_4,
> + .base = 0x6d000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_5", .id = PINGPONG_5,
> + .base = 0x6e000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_6", .id = PINGPONG_6,
> + .base = 0x65800, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_3,
> + .intr_done = -1,
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_7", .id = PINGPONG_7,
> + .base = 0x65c00, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_3,
> + .intr_done = -1,
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 66dd414253f1..32ffb9a9cfc7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -234,30 +234,71 @@ static const struct dpu_dspp_cfg sm8550_dspp[] = {
> },
> };
> static const struct dpu_pingpong_cfg sm8550_pp[] = {
> - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> - -1),
> - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> - -1),
> - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> - -1),
> - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> - -1),
> - PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> - -1),
> - PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> - -1),
> - PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk,
> - -1,
> - -1),
> - PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk,
> - -1,
> - -1),
> + {
> + .name = "pingpong_0", .id = PINGPONG_0,
> + .base = 0x69000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_1", .id = PINGPONG_1,
> + .base = 0x6a000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_0,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_2", .id = PINGPONG_2,
> + .base = 0x6b000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_3", .id = PINGPONG_3,
> + .base = 0x6c000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_1,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_4", .id = PINGPONG_4,
> + .base = 0x6d000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_5", .id = PINGPONG_5,
> + .base = 0x6e000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_2,
> + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_6", .id = PINGPONG_6,
> + .base = 0x66000, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_3,
> + .intr_done = -1,
> + .intr_rdptr = -1,
> + }, {
> + .name = "pingpong_7", .id = PINGPONG_7,
> + .base = 0x66400, .len = 0,
> + .features = BIT(DPU_PINGPONG_DITHER),
> + .sblk = &sc7280_pp_sblk,
> + .merge_3d = MERGE_3D_3,
> + .intr_done = -1,
> + .intr_rdptr = -1,
> + },
> };
>
> static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 72634a8109e8..3ea63ca358a4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -450,27 +450,6 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
> .len = 0x20, .version = 0x20000},
> };
>
> -#define PP_BLK_DITHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
> - {\
> - .name = _name, .id = _id, \
> - .base = _base, .len = 0, \
> - .features = BIT(DPU_PINGPONG_DITHER), \
> - .merge_3d = _merge_3d, \
> - .sblk = &_sblk, \
> - .intr_done = _done, \
> - .intr_rdptr = _rdptr, \
> - }
> -#define PP_BLK(_name, _id, _base, _features, _merge_3d, _sblk, _done, _rdptr) \
> - {\
> - .name = _name, .id = _id, \
> - .base = _base, .len = 0xd4, \
> - .features = _features, \
> - .merge_3d = _merge_3d, \
> - .sblk = &_sblk, \
> - .intr_done = _done, \
> - .intr_rdptr = _rdptr, \
> - }
> -
> /*************************************************************
> * DSC sub blocks config
> *************************************************************/
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 16/19] drm/msm/dpu: inline WB_BLK macros
2023-06-19 21:25 ` [PATCH v4 16/19] drm/msm/dpu: inline WB_BLK macros Dmitry Baryshkov
@ 2023-06-27 8:35 ` Marijn Suijten
2023-07-03 21:04 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Marijn Suijten @ 2023-06-27 8:35 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, Abhinav Kumar, dri-devel,
Stephen Boyd, linux-arm-msm
On 2023-06-20 00:25:16, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Validated that this incurs no changes by checksumming a stripped
dpu_hw_catalog.o.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> .../drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 14 ++++++++++++--
> .../drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 14 ++++++++++++--
> .../drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 14 ++++++++++++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 18 ------------------
> 4 files changed, 36 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index c8f4c6326a1a..9148d7da62e4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -323,8 +323,18 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
> };
>
> static const struct dpu_wb_cfg sm8250_wb[] = {
> - WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
> - VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
> + {
> + .name = "wb_2", .id = WB_2,
> + .base = 0x65000, .len = 0x2c8,
> + .features = WB_SM8250_MASK,
> + .format_list = wb2_formats,
> + .num_formats = ARRAY_SIZE(wb2_formats),
> + .clk_ctrl = DPU_CLK_CTRL_WB2,
> + .xin_id = 6,
> + .vbif_idx = VBIF_RT,
> + .maxlinewidth = 4096,
> + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
> + },
> };
>
> static const struct dpu_perf_cfg sm8250_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index d7d117e3af36..904c758a60df 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -148,8 +148,18 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
> };
>
> static const struct dpu_wb_cfg sc7180_wb[] = {
> - WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
> - VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
> + {
> + .name = "wb_2", .id = WB_2,
> + .base = 0x65000, .len = 0x2c8,
> + .features = WB_SM8250_MASK,
> + .format_list = wb2_formats,
> + .num_formats = ARRAY_SIZE(wb2_formats),
> + .clk_ctrl = DPU_CLK_CTRL_WB2,
> + .xin_id = 6,
> + .vbif_idx = VBIF_RT,
> + .maxlinewidth = 4096,
> + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
> + },
> };
>
> static const struct dpu_perf_cfg sc7180_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 3b67010f336b..7b5c9a77b102 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -176,8 +176,18 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = {
> };
>
> static const struct dpu_wb_cfg sc7280_wb[] = {
> - WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
> - VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
> + {
> + .name = "wb_2", .id = WB_2,
> + .base = 0x65000, .len = 0x2c8,
> + .features = WB_SM8250_MASK,
> + .format_list = wb2_formats,
> + .num_formats = ARRAY_SIZE(wb2_formats),
> + .clk_ctrl = DPU_CLK_CTRL_WB2,
> + .xin_id = 6,
> + .vbif_idx = VBIF_RT,
> + .maxlinewidth = 4096,
> + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
> + },
> };
>
> static const struct dpu_intf_cfg sc7280_intf[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 3ea63ca358a4..d2bca1ec0e63 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -493,24 +493,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
> .intr_tear_rd_ptr = _tear_rd_ptr, \
> }
>
> -/*************************************************************
> - * Writeback blocks config
> - *************************************************************/
> -#define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
> - __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
> - { \
> - .name = _name, .id = _id, \
> - .base = _base, .len = 0x2c8, \
> - .features = _features, \
> - .format_list = wb2_formats, \
> - .num_formats = ARRAY_SIZE(wb2_formats), \
> - .clk_ctrl = _clk_ctrl, \
> - .xin_id = __xin_id, \
> - .vbif_idx = vbif_id, \
> - .maxlinewidth = _max_linewidth, \
> - .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
> - }
> -
> /*************************************************************
> * VBIF sub blocks config
> *************************************************************/
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros
2023-06-19 21:25 ` [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros Dmitry Baryshkov
@ 2023-06-27 8:35 ` Marijn Suijten
2023-07-03 21:06 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Marijn Suijten @ 2023-06-27 8:35 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, Abhinav Kumar, dri-devel,
Stephen Boyd, linux-arm-msm
On 2023-06-20 00:25:17, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Validated that this incurs no changes by checksumming a stripped
dpu_hw_catalog.o.
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 52 ++++++--
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 53 ++++++--
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 55 ++++++--
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 82 +++++++++---
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 55 ++++++--
> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 28 +++-
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 15 ++-
> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 28 +++-
> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 15 ++-
> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 15 ++-
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 55 ++++++--
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 41 ++++--
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 120 +++++++++++++-----
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 55 ++++++--
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 55 ++++++--
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 30 -----
> 16 files changed, 545 insertions(+), 209 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 9181d3ef8013..4ce25ed4e36f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -241,18 +241,46 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
> };
>
> static const struct dpu_intf_cfg msm8998_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x6a000, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 21,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 21,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x6b000, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 21,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x6b800, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_HDMI,
> + .prog_fetch_lines_worst_case = 21,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_perf_cfg msm8998_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 8119a81ff260..5ad82b109ebb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -257,18 +257,47 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sdm845_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x6a000, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x6b000, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x6b800, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_perf_cfg sdm845_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 2f6899ebad06..341ab9b84d20 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -306,20 +306,47 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sm8150_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x6a000, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x2bc,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x6b000, .len = 0x2bc,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x6b800, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_perf_cfg sm8150_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 15975460dbad..8dd36a85b685 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -313,27 +313,69 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sc8180x_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x6a000, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x2bc,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x6b000, .len = 0x2bc,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
> + },
> /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> - INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),
> - INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
> + {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x6b800, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = 999,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_4", .id = INTF_4,
> + .base = 0x6c000, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_5", .id = INTF_5,
> + .base = 0x6c800, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_2,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_perf_cfg sc8180x_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 9148d7da62e4..e16ffade5aca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -306,20 +306,47 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sm8250_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x6a000, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x2c0,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x6b000, .len = 0x2c0,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x6b800, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_wb_cfg sm8250_wb[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 904c758a60df..0f59e372cf3e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -138,13 +138,27 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = {
> };
>
> static const struct dpu_intf_cfg sc7180_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x6a000, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x2c0,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> + },
> };
>
> static const struct dpu_wb_cfg sc7180_wb[] = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 4236cd7317a1..f01eac27f405 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -94,10 +94,17 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
> };
>
> static const struct dpu_intf_cfg sm6115_intf[] = {
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> + {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x2c0,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> + },
> };
>
> static const struct dpu_perf_cfg sm6115_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 82c04d2ce010..df4bf6510123 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -155,13 +155,27 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sm6350_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 35, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 35, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x6a000, .len = 0x280,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 35,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x2c0,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 35,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> + },
> };
>
> static const struct dpu_perf_cfg sm6350_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index c6bf487e131b..cb486bea6628 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -91,10 +91,17 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
> };
>
> static const struct dpu_intf_cfg qcm2290_intf[] = {
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> + {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x2c0,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> + },
> };
>
> static const struct dpu_perf_cfg qcm2290_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 97de7a1f52b4..74dc032af7a4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -104,10 +104,17 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sm6375_intf[] = {
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
> + {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x2c0,
> + .features = INTF_SC7180_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> + },
> };
>
> static const struct dpu_perf_cfg sm6375_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 108e35cbcd90..d5191a663ae1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -313,20 +313,47 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sm8350_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x34000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x35000, .len = 0x2c4,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x36000, .len = 0x2c4,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2),
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x37000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_perf_cfg sm8350_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 7b5c9a77b102..d3a18048972f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -191,16 +191,37 @@ static const struct dpu_wb_cfg sc7280_wb[] = {
> };
>
> static const struct dpu_intf_cfg sc7280_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> - INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x34000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x35000, .len = 0x2c4,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
> + }, {
> + .name = "intf_5", .id = INTF_5,
> + .base = 0x39000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_perf_cfg sc7280_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 062b17dedec7..9f94cc6369dd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -328,35 +328,97 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
>
> /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
> static const struct dpu_intf_cfg sc8280xp_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> - INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)),
> - INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
> - INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17)),
> - INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19)),
> - INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x34000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x35000, .len = 0x300,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x36000, .len = 0x300,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2),
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x37000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_NONE,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_4", .id = INTF_4,
> + .base = 0x38000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_5", .id = INTF_5,
> + .base = 0x39000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_3,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_6", .id = INTF_6,
> + .base = 0x3a000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_2,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_7", .id = INTF_7,
> + .base = 0x3b000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_NONE,
> + .controller_id = MSM_DP_CONTROLLER_2,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_8", .id = INTF_8,
> + .base = 0x3c000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_NONE,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_perf_cfg sc8280xp_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index d92af1410c3e..517629c4a168 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -337,20 +337,47 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sm8450_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x34000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x35000, .len = 0x300,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x36000, .len = 0x300,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2),
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x37000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_perf_cfg sm8450_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 32ffb9a9cfc7..ed1d1d4092e8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -351,20 +351,47 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = {
> };
>
> static const struct dpu_intf_cfg sm8550_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x34000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x35000, .len = 0x300,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2),
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x36000, .len = 0x300,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2),
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x37000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + },
> };
>
> static const struct dpu_perf_cfg sm8550_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index d2bca1ec0e63..6acd34e61aca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -463,36 +463,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
> .ctl = {.base = 0xF80, .len = 0x10},
> };
>
> -/*************************************************************
> - * INTF sub blocks config
> - *************************************************************/
> -#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync) \
> - {\
> - .name = _name, .id = _id, \
> - .base = _base, .len = _len, \
> - .features = _features, \
> - .type = _type, \
> - .controller_id = _ctrl_id, \
> - .prog_fetch_lines_worst_case = _progfetch, \
> - .intr_underrun = _underrun, \
> - .intr_vsync = _vsync, \
> - .intr_tear_rd_ptr = -1, \
> - }
> -
> -/* DSI Interface sub-block with TEAR registers (since DPU 5.0.0) */
> -#define INTF_BLK_DSI_TE(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync, _tear_rd_ptr) \
> - {\
> - .name = _name, .id = _id, \
> - .base = _base, .len = _len, \
> - .features = _features, \
> - .type = _type, \
> - .controller_id = _ctrl_id, \
> - .prog_fetch_lines_worst_case = _progfetch, \
> - .intr_underrun = _underrun, \
> - .intr_vsync = _vsync, \
> - .intr_tear_rd_ptr = _tear_rd_ptr, \
> - }
> -
> /*************************************************************
> * VBIF sub blocks config
> *************************************************************/
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 02/19] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n
2023-06-19 21:25 ` [PATCH v4 02/19] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n Dmitry Baryshkov
@ 2023-07-03 0:53 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 0:53 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> In several catalog entries we did not use existing MSM_DP_CONTROLLER_n
> constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n
> for DSI interfaces.
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 03/19] drm/msm/dpu: simplify peer LM handling
2023-06-19 21:25 ` [PATCH v4 03/19] drm/msm/dpu: simplify peer LM handling Dmitry Baryshkov
@ 2023-07-03 1:34 ` Abhinav Kumar
2023-07-03 1:36 ` Dmitry Baryshkov
0 siblings, 1 reply; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 1:34 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> For each LM there is at max 1 peer LM which can be driven by the same
> CTL, so there no need to have a mask instead of just an ID of the peer
> LM.
>
The change is ok but the wording seems incorrect. Are you implying that
only LM0 and LM1 can be used for CTL0 and so-on? Because thats how this
is implying.
So any LM can be used with any CTL. Its just that each LM has only one
peer. No need to mention anything about CTL.
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 34 +++++++------------
> 3 files changed, 15 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 0de507d4d7b7..30fb5b1f3966 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -394,7 +394,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
> .features = _fmask, \
> .sblk = _sblk, \
> .pingpong = _pp, \
> - .lm_pair_mask = (1 << _lmpair), \
> + .lm_pair = _lmpair, \
> .dspp = _dspp \
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index b860784ade72..b07caa4b867e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -554,14 +554,14 @@ struct dpu_sspp_cfg {
> * @features bit mask identifying sub-blocks/features
> * @sblk: LM Sub-blocks information
> * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported
> - * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
> + * @lm_pair: ID of LM that can be controlled by same CTL
> */
> struct dpu_lm_cfg {
> DPU_HW_BLK_INFO;
> const struct dpu_lm_sub_blks *sblk;
> u32 pingpong;
> u32 dspp;
> - unsigned long lm_pair_mask;
> + unsigned long lm_pair;
> };
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 471842bbb950..e333f4eeafc1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -253,28 +253,19 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
> }
>
> /**
> - * _dpu_rm_check_lm_peer - check if a mixer is a peer of the primary
> + * _dpu_rm_get_lm_peer - get the id of a mixer which is a peer of the primary
> * @rm: dpu resource manager handle
> * @primary_idx: index of primary mixer in rm->mixer_blks[]
> - * @peer_idx: index of other mixer in rm->mixer_blks[]
> - * Return: true if rm->mixer_blks[peer_idx] is a peer of
> - * rm->mixer_blks[primary_idx]
> */
> -static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx,
> - int peer_idx)
> +static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx)
> {
> const struct dpu_lm_cfg *prim_lm_cfg;
> - const struct dpu_lm_cfg *peer_cfg;
>
> prim_lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[primary_idx])->cap;
> - peer_cfg = to_dpu_hw_mixer(rm->mixer_blks[peer_idx])->cap;
>
> - if (!test_bit(peer_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
> - DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id,
> - peer_cfg->id);
> - return false;
> - }
> - return true;
> + if (prim_lm_cfg->lm_pair >= LM_0 && prim_lm_cfg->lm_pair < LM_MAX)
> + return prim_lm_cfg->lm_pair - LM_0;
> + return -EINVAL;
> }
>
> /**
> @@ -351,7 +342,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
> int lm_idx[MAX_BLOCKS];
> int pp_idx[MAX_BLOCKS];
> int dspp_idx[MAX_BLOCKS] = {0};
> - int i, j, lm_count = 0;
> + int i, lm_count = 0;
>
> if (!reqs->topology.num_lm) {
> DPU_ERROR("invalid number of lm: %d\n", reqs->topology.num_lm);
> @@ -376,16 +367,15 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
> ++lm_count;
>
> /* Valid primary mixer found, find matching peers */
> - for (j = i + 1; j < ARRAY_SIZE(rm->mixer_blks) &&
> - lm_count < reqs->topology.num_lm; j++) {
> - if (!rm->mixer_blks[j])
> + if (lm_count < reqs->topology.num_lm) {
> + int j = _dpu_rm_get_lm_peer(rm, i);
> +
> + /* ignore the peer if there is an error or if the peer was already processed */
> + if (j < 0 || j < i)
> continue;
>
> - if (!_dpu_rm_check_lm_peer(rm, i, j)) {
> - DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j,
> - LM_0 + i);
> + if (!rm->mixer_blks[j])
> continue;
> - }
>
> if (!_dpu_rm_check_lm_and_get_connected_blks(rm,
> global_state, enc_id, j,
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 03/19] drm/msm/dpu: simplify peer LM handling
2023-07-03 1:34 ` Abhinav Kumar
@ 2023-07-03 1:36 ` Dmitry Baryshkov
2023-07-03 1:49 ` Abhinav Kumar
0 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-07-03 1:36 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten, Sean Paul
On Mon, 3 Jul 2023 at 04:34, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> > For each LM there is at max 1 peer LM which can be driven by the same
> > CTL, so there no need to have a mask instead of just an ID of the peer
> > LM.
> >
>
> The change is ok but the wording seems incorrect. Are you implying that
> only LM0 and LM1 can be used for CTL0 and so-on? Because thats how this
> is implying.
>
> So any LM can be used with any CTL. Its just that each LM has only one
> peer. No need to mention anything about CTL.
Please correct me if I am wrong, with pre-active CTL, each CTL could
drive any single LM or a fixed LM pair. That's what was meant here.
Would it be better if I rephrase the commit message in this way?
>
> > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> > Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +--
> > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 34 +++++++------------
> > 3 files changed, 15 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index 0de507d4d7b7..30fb5b1f3966 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -394,7 +394,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
> > .features = _fmask, \
> > .sblk = _sblk, \
> > .pingpong = _pp, \
> > - .lm_pair_mask = (1 << _lmpair), \
> > + .lm_pair = _lmpair, \
> > .dspp = _dspp \
> > }
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index b860784ade72..b07caa4b867e 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -554,14 +554,14 @@ struct dpu_sspp_cfg {
> > * @features bit mask identifying sub-blocks/features
> > * @sblk: LM Sub-blocks information
> > * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported
> > - * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
> > + * @lm_pair: ID of LM that can be controlled by same CTL
> > */
> > struct dpu_lm_cfg {
> > DPU_HW_BLK_INFO;
> > const struct dpu_lm_sub_blks *sblk;
> > u32 pingpong;
> > u32 dspp;
> > - unsigned long lm_pair_mask;
> > + unsigned long lm_pair;
> > };
> >
> > /**
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > index 471842bbb950..e333f4eeafc1 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > @@ -253,28 +253,19 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
> > }
> >
> > /**
> > - * _dpu_rm_check_lm_peer - check if a mixer is a peer of the primary
> > + * _dpu_rm_get_lm_peer - get the id of a mixer which is a peer of the primary
> > * @rm: dpu resource manager handle
> > * @primary_idx: index of primary mixer in rm->mixer_blks[]
> > - * @peer_idx: index of other mixer in rm->mixer_blks[]
> > - * Return: true if rm->mixer_blks[peer_idx] is a peer of
> > - * rm->mixer_blks[primary_idx]
> > */
> > -static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx,
> > - int peer_idx)
> > +static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx)
> > {
> > const struct dpu_lm_cfg *prim_lm_cfg;
> > - const struct dpu_lm_cfg *peer_cfg;
> >
> > prim_lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[primary_idx])->cap;
> > - peer_cfg = to_dpu_hw_mixer(rm->mixer_blks[peer_idx])->cap;
> >
> > - if (!test_bit(peer_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
> > - DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id,
> > - peer_cfg->id);
> > - return false;
> > - }
> > - return true;
> > + if (prim_lm_cfg->lm_pair >= LM_0 && prim_lm_cfg->lm_pair < LM_MAX)
> > + return prim_lm_cfg->lm_pair - LM_0;
> > + return -EINVAL;
> > }
> >
> > /**
> > @@ -351,7 +342,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
> > int lm_idx[MAX_BLOCKS];
> > int pp_idx[MAX_BLOCKS];
> > int dspp_idx[MAX_BLOCKS] = {0};
> > - int i, j, lm_count = 0;
> > + int i, lm_count = 0;
> >
> > if (!reqs->topology.num_lm) {
> > DPU_ERROR("invalid number of lm: %d\n", reqs->topology.num_lm);
> > @@ -376,16 +367,15 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
> > ++lm_count;
> >
> > /* Valid primary mixer found, find matching peers */
> > - for (j = i + 1; j < ARRAY_SIZE(rm->mixer_blks) &&
> > - lm_count < reqs->topology.num_lm; j++) {
> > - if (!rm->mixer_blks[j])
> > + if (lm_count < reqs->topology.num_lm) {
> > + int j = _dpu_rm_get_lm_peer(rm, i);
> > +
> > + /* ignore the peer if there is an error or if the peer was already processed */
> > + if (j < 0 || j < i)
> > continue;
> >
> > - if (!_dpu_rm_check_lm_peer(rm, i, j)) {
> > - DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j,
> > - LM_0 + i);
> > + if (!rm->mixer_blks[j])
> > continue;
> > - }
> >
> > if (!_dpu_rm_check_lm_and_get_connected_blks(rm,
> > global_state, enc_id, j,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 03/19] drm/msm/dpu: simplify peer LM handling
2023-07-03 1:36 ` Dmitry Baryshkov
@ 2023-07-03 1:49 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 1:49 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten, Sean Paul
On 7/2/2023 6:36 PM, Dmitry Baryshkov wrote:
> On Mon, 3 Jul 2023 at 04:34, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
>>> For each LM there is at max 1 peer LM which can be driven by the same
>>> CTL, so there no need to have a mask instead of just an ID of the peer
>>> LM.
>>>
>>
>> The change is ok but the wording seems incorrect. Are you implying that
>> only LM0 and LM1 can be used for CTL0 and so-on? Because thats how this
>> is implying.
>>
>> So any LM can be used with any CTL. Its just that each LM has only one
>> peer. No need to mention anything about CTL.
>
> Please correct me if I am wrong, with pre-active CTL, each CTL could
> drive any single LM or a fixed LM pair. That's what was meant here.
> Would it be better if I rephrase the commit message in this way?
>
hmmm, even that could be misleading. Quad LM can be possible in newer
chipsets.
Thats why I am hesitant to bring CTL into the mix. The binding is
between LMs and not LM and CTL.
>>
>>> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +--
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 34 +++++++------------
>>> 3 files changed, 15 insertions(+), 25 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> index 0de507d4d7b7..30fb5b1f3966 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> @@ -394,7 +394,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
>>> .features = _fmask, \
>>> .sblk = _sblk, \
>>> .pingpong = _pp, \
>>> - .lm_pair_mask = (1 << _lmpair), \
>>> + .lm_pair = _lmpair, \
>>> .dspp = _dspp \
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> index b860784ade72..b07caa4b867e 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> @@ -554,14 +554,14 @@ struct dpu_sspp_cfg {
>>> * @features bit mask identifying sub-blocks/features
>>> * @sblk: LM Sub-blocks information
>>> * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported
>>> - * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
>>> + * @lm_pair: ID of LM that can be controlled by same CTL
>>> */
>>> struct dpu_lm_cfg {
>>> DPU_HW_BLK_INFO;
>>> const struct dpu_lm_sub_blks *sblk;
>>> u32 pingpong;
>>> u32 dspp;
>>> - unsigned long lm_pair_mask;
>>> + unsigned long lm_pair;
>>> };
>>>
>>> /**
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> index 471842bbb950..e333f4eeafc1 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> @@ -253,28 +253,19 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
>>> }
>>>
>>> /**
>>> - * _dpu_rm_check_lm_peer - check if a mixer is a peer of the primary
>>> + * _dpu_rm_get_lm_peer - get the id of a mixer which is a peer of the primary
>>> * @rm: dpu resource manager handle
>>> * @primary_idx: index of primary mixer in rm->mixer_blks[]
>>> - * @peer_idx: index of other mixer in rm->mixer_blks[]
>>> - * Return: true if rm->mixer_blks[peer_idx] is a peer of
>>> - * rm->mixer_blks[primary_idx]
>>> */
>>> -static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx,
>>> - int peer_idx)
>>> +static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx)
>>> {
>>> const struct dpu_lm_cfg *prim_lm_cfg;
>>> - const struct dpu_lm_cfg *peer_cfg;
>>>
>>> prim_lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[primary_idx])->cap;
>>> - peer_cfg = to_dpu_hw_mixer(rm->mixer_blks[peer_idx])->cap;
>>>
>>> - if (!test_bit(peer_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
>>> - DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id,
>>> - peer_cfg->id);
>>> - return false;
>>> - }
>>> - return true;
>>> + if (prim_lm_cfg->lm_pair >= LM_0 && prim_lm_cfg->lm_pair < LM_MAX)
>>> + return prim_lm_cfg->lm_pair - LM_0;
>>> + return -EINVAL;
>>> }
>>>
>>> /**
>>> @@ -351,7 +342,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
>>> int lm_idx[MAX_BLOCKS];
>>> int pp_idx[MAX_BLOCKS];
>>> int dspp_idx[MAX_BLOCKS] = {0};
>>> - int i, j, lm_count = 0;
>>> + int i, lm_count = 0;
>>>
>>> if (!reqs->topology.num_lm) {
>>> DPU_ERROR("invalid number of lm: %d\n", reqs->topology.num_lm);
>>> @@ -376,16 +367,15 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
>>> ++lm_count;
>>>
>>> /* Valid primary mixer found, find matching peers */
>>> - for (j = i + 1; j < ARRAY_SIZE(rm->mixer_blks) &&
>>> - lm_count < reqs->topology.num_lm; j++) {
>>> - if (!rm->mixer_blks[j])
>>> + if (lm_count < reqs->topology.num_lm) {
>>> + int j = _dpu_rm_get_lm_peer(rm, i);
>>> +
>>> + /* ignore the peer if there is an error or if the peer was already processed */
>>> + if (j < 0 || j < i)
>>> continue;
>>>
>>> - if (!_dpu_rm_check_lm_peer(rm, i, j)) {
>>> - DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j,
>>> - LM_0 + i);
>>> + if (!rm->mixer_blks[j])
>>> continue;
>>> - }
>>>
>>> if (!_dpu_rm_check_lm_and_get_connected_blks(rm,
>>> global_state, enc_id, j,
>
>
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-06-19 21:25 ` [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field Dmitry Baryshkov
2023-06-26 12:28 ` Marijn Suijten
@ 2023-07-03 2:01 ` Abhinav Kumar
2023-07-04 2:20 ` Dmitry Baryshkov
1 sibling, 1 reply; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 2:01 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> There is always a single MDP TOP block. Drop the mdp_count field and
> stop declaring dpu_mdp_cfg instances as arrays.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
The change drops mdp_count and stops using the array which is fine and I
will support that.
But looking at the pattern I saw while using core_revision, both
DPU_MDP_VSYNC_SEL and DPU_MDP_AUDIO_SELECT can also be dropped from the
catalog in favor of using core_revision.
Hence for that, I request you not to stop passing dpu_mdss_cfg to
dpu_hw_mdptop_init as that has the necessary information of core_revision.
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38 +++----------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
> 19 files changed, 41 insertions(+), 115 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index be0514bf27ec..e0d2ee48d733 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
> .highest_bank_bit = 0x2,
> };
>
> -static const struct dpu_mdp_cfg msm8998_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg msm8998_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x458,
> .features = BIT(DPU_MDP_VSYNC_SEL),
> @@ -41,7 +40,6 @@ static const struct dpu_mdp_cfg msm8998_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
> .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
> .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
> - },
> };
>
> static const struct dpu_ctl_cfg msm8998_ctl[] = {
> @@ -192,8 +190,7 @@ static const struct dpu_perf_cfg msm8998_perf_data = {
> const struct dpu_mdss_cfg dpu_msm8998_cfg = {
> .caps = &msm8998_dpu_caps,
> .ubwc = &msm8998_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(msm8998_mdp),
> - .mdp = msm8998_mdp,
> + .mdp = &msm8998_mdp,
> .ctl_count = ARRAY_SIZE(msm8998_ctl),
> .ctl = msm8998_ctl,
> .sspp_count = ARRAY_SIZE(msm8998_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index b33472625fcb..72295d5a10dc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = {
> .highest_bank_bit = 0x2,
> };
>
> -static const struct dpu_mdp_cfg sdm845_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sdm845_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x45c,
> .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL),
> @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
> - },
> };
>
> static const struct dpu_ctl_cfg sdm845_ctl[] = {
> @@ -196,8 +194,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
> const struct dpu_mdss_cfg dpu_sdm845_cfg = {
> .caps = &sdm845_dpu_caps,
> .ubwc = &sdm845_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sdm845_mdp),
> - .mdp = sdm845_mdp,
> + .mdp = &sdm845_mdp,
> .ctl_count = ARRAY_SIZE(sdm845_ctl),
> .ctl = sdm845_ctl,
> .sspp_count = ARRAY_SIZE(sdm845_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 64ed10da1b73..418312b164b8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = {
> .highest_bank_bit = 0x2,
> };
>
> -static const struct dpu_mdp_cfg sm8150_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sm8150_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x45c,
> .features = BIT(DPU_MDP_AUDIO_SELECT),
> @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sm8150_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
> - },
> };
>
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> @@ -210,8 +208,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
> const struct dpu_mdss_cfg dpu_sm8150_cfg = {
> .caps = &sm8150_dpu_caps,
> .ubwc = &sm8150_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sm8150_mdp),
> - .mdp = sm8150_mdp,
> + .mdp = &sm8150_mdp,
> .ctl_count = ARRAY_SIZE(sm8150_ctl),
> .ctl = sm8150_ctl,
> .sspp_count = ARRAY_SIZE(sm8150_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 6ae1f6f67ec8..ffacf29926b3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
> .highest_bank_bit = 0x3,
> };
>
> -static const struct dpu_mdp_cfg sc8180x_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sc8180x_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x45c,
> .features = BIT(DPU_MDP_AUDIO_SELECT),
> @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
> - },
> };
>
> static const struct dpu_ctl_cfg sc8180x_ctl[] = {
> @@ -216,8 +214,7 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
> const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
> .caps = &sc8180x_dpu_caps,
> .ubwc = &sc8180x_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sc8180x_mdp),
> - .mdp = sc8180x_mdp,
> + .mdp = &sc8180x_mdp,
> .ctl_count = ARRAY_SIZE(sc8180x_ctl),
> .ctl = sc8180x_ctl,
> .sspp_count = ARRAY_SIZE(sc8180x_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 48c97e9f8a45..86dfc5745630 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = {
> .ubwc_swizzle = 0x6,
> };
>
> -static const struct dpu_mdp_cfg sm8250_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sm8250_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x494,
> .features = 0,
> @@ -40,7 +39,6 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
> - },
> };
>
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> @@ -216,8 +214,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
> const struct dpu_mdss_cfg dpu_sm8250_cfg = {
> .caps = &sm8250_dpu_caps,
> .ubwc = &sm8250_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sm8250_mdp),
> - .mdp = sm8250_mdp,
> + .mdp = &sm8250_mdp,
> .ctl_count = ARRAY_SIZE(sm8250_ctl),
> .ctl = sm8250_ctl,
> .sspp_count = ARRAY_SIZE(sm8250_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 00366f7fe969..f42f27707453 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -22,8 +22,7 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = {
> .highest_bank_bit = 0x3,
> };
>
> -static const struct dpu_mdp_cfg sc7180_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sc7180_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x494,
> .features = 0,
> @@ -32,7 +31,6 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
> - },
> };
>
> static const struct dpu_ctl_cfg sc7180_ctl[] = {
> @@ -134,8 +132,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
> const struct dpu_mdss_cfg dpu_sc7180_cfg = {
> .caps = &sc7180_dpu_caps,
> .ubwc = &sc7180_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sc7180_mdp),
> - .mdp = sc7180_mdp,
> + .mdp = &sc7180_mdp,
> .ctl_count = ARRAY_SIZE(sc7180_ctl),
> .ctl = sc7180_ctl,
> .sspp_count = ARRAY_SIZE(sc7180_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 8688f09dd560..1d21c33542a7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -23,14 +23,12 @@ static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
> .ubwc_swizzle = 0x7,
> };
>
> -static const struct dpu_mdp_cfg sm6115_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sm6115_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x494,
> .features = 0,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> - },
> };
>
> static const struct dpu_ctl_cfg sm6115_ctl[] = {
> @@ -104,8 +102,7 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
> const struct dpu_mdss_cfg dpu_sm6115_cfg = {
> .caps = &sm6115_dpu_caps,
> .ubwc = &sm6115_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sm6115_mdp),
> - .mdp = sm6115_mdp,
> + .mdp = &sm6115_mdp,
> .ctl_count = ARRAY_SIZE(sm6115_ctl),
> .ctl = sm6115_ctl,
> .sspp_count = ARRAY_SIZE(sm6115_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 2bb2346d27a0..6ad68764e13f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
> .highest_bank_bit = 1,
> };
>
> -static const struct dpu_mdp_cfg sm6350_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sm6350_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x494,
> .features = 0,
> @@ -35,7 +34,6 @@ static const struct dpu_mdp_cfg sm6350_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> - },
> };
>
> static const struct dpu_ctl_cfg sm6350_ctl[] = {
> @@ -143,8 +141,7 @@ static const struct dpu_perf_cfg sm6350_perf_data = {
> const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> .caps = &sm6350_dpu_caps,
> .ubwc = &sm6350_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sm6350_mdp),
> - .mdp = sm6350_mdp,
> + .mdp = &sm6350_mdp,
> .ctl_count = ARRAY_SIZE(sm6350_ctl),
> .ctl = sm6350_ctl,
> .sspp_count = ARRAY_SIZE(sm6350_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index d106ff28372d..80670e7cfc57 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -20,14 +20,12 @@ static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
> .highest_bank_bit = 0x2,
> };
>
> -static const struct dpu_mdp_cfg qcm2290_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg qcm2290_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x494,
> .features = 0,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> - },
> };
>
> static const struct dpu_ctl_cfg qcm2290_ctl[] = {
> @@ -94,8 +92,7 @@ static const struct dpu_perf_cfg qcm2290_perf_data = {
> const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
> .caps = &qcm2290_dpu_caps,
> .ubwc = &qcm2290_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(qcm2290_mdp),
> - .mdp = qcm2290_mdp,
> + .mdp = &qcm2290_mdp,
> .ctl_count = ARRAY_SIZE(qcm2290_ctl),
> .ctl = qcm2290_ctl,
> .sspp_count = ARRAY_SIZE(qcm2290_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 842ea5bcbe16..8e7dcb2e8762 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -24,14 +24,12 @@ static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
> .highest_bank_bit = 1,
> };
>
> -static const struct dpu_mdp_cfg sm6375_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sm6375_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x494,
> .features = 0,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> - },
> };
>
> static const struct dpu_ctl_cfg sm6375_ctl[] = {
> @@ -109,8 +107,7 @@ static const struct dpu_perf_cfg sm6375_perf_data = {
> const struct dpu_mdss_cfg dpu_sm6375_cfg = {
> .caps = &sm6375_dpu_caps,
> .ubwc = &sm6375_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sm6375_mdp),
> - .mdp = sm6375_mdp,
> + .mdp = &sm6375_mdp,
> .ctl_count = ARRAY_SIZE(sm6375_ctl),
> .ctl = sm6375_ctl,
> .sspp_count = ARRAY_SIZE(sm6375_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 8fa9d83a539d..83dafd3f2a41 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -24,8 +24,7 @@ static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = {
> .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> };
>
> -static const struct dpu_mdp_cfg sm8350_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sm8350_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x494,
> .features = 0,
> @@ -38,7 +37,6 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> - },
> };
>
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> @@ -215,8 +213,7 @@ static const struct dpu_perf_cfg sm8350_perf_data = {
> const struct dpu_mdss_cfg dpu_sm8350_cfg = {
> .caps = &sm8350_dpu_caps,
> .ubwc = &sm8350_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sm8350_mdp),
> - .mdp = sm8350_mdp,
> + .mdp = &sm8350_mdp,
> .ctl_count = ARRAY_SIZE(sm8350_ctl),
> .ctl = sm8350_ctl,
> .sspp_count = ARRAY_SIZE(sm8350_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 2862c64bbc3e..a7695f05beab 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -23,8 +23,7 @@ static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = {
> .ubwc_swizzle = 0x6,
> };
>
> -static const struct dpu_mdp_cfg sc7280_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sc7280_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x2014,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> @@ -32,7 +31,6 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
> - },
> };
>
> static const struct dpu_ctl_cfg sc7280_ctl[] = {
> @@ -156,8 +154,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
> const struct dpu_mdss_cfg dpu_sc7280_cfg = {
> .caps = &sc7280_dpu_caps,
> .ubwc = &sc7280_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sc7280_mdp),
> - .mdp = sc7280_mdp,
> + .mdp = &sc7280_mdp,
> .ctl_count = ARRAY_SIZE(sc7280_ctl),
> .ctl = sc7280_ctl,
> .sspp_count = ARRAY_SIZE(sc7280_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 520b210e8c0c..54543dc3985a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
> .ubwc_swizzle = 6,
> };
>
> -static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sc8280xp_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x494,
> .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> - },
> };
>
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> @@ -219,8 +217,7 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = {
> const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
> .caps = &sc8280xp_dpu_caps,
> .ubwc = &sc8280xp_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sc8280xp_mdp),
> - .mdp = sc8280xp_mdp,
> + .mdp = &sc8280xp_mdp,
> .ctl_count = ARRAY_SIZE(sc8280xp_ctl),
> .ctl = sc8280xp_ctl,
> .sspp_count = ARRAY_SIZE(sc8280xp_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index b782603642f4..0f8bf4465372 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = {
> .ubwc_swizzle = 0x6,
> };
>
> -static const struct dpu_mdp_cfg sm8450_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sm8450_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0x0, .len = 0x494,
> .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
> .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> - },
> };
>
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> @@ -223,8 +221,7 @@ static const struct dpu_perf_cfg sm8450_perf_data = {
> const struct dpu_mdss_cfg dpu_sm8450_cfg = {
> .caps = &sm8450_dpu_caps,
> .ubwc = &sm8450_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sm8450_mdp),
> - .mdp = sm8450_mdp,
> + .mdp = &sm8450_mdp,
> .ctl_count = ARRAY_SIZE(sm8450_ctl),
> .ctl = sm8450_ctl,
> .sspp_count = ARRAY_SIZE(sm8450_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 025a149bab97..851aa078a4bd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -24,8 +24,7 @@ static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = {
> .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> };
>
> -static const struct dpu_mdp_cfg sm8550_mdp[] = {
> - {
> +static const struct dpu_mdp_cfg sm8550_mdp = {
> .name = "top_0", .id = MDP_TOP,
> .base = 0, .len = 0x494,
> .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> @@ -40,7 +39,6 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = {
> .clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
> .clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 },
> .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> - },
> };
>
> /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> @@ -227,8 +225,7 @@ static const struct dpu_perf_cfg sm8550_perf_data = {
> const struct dpu_mdss_cfg dpu_sm8550_cfg = {
> .caps = &sm8550_dpu_caps,
> .ubwc = &sm8550_ubwc_cfg,
> - .mdp_count = ARRAY_SIZE(sm8550_mdp),
> - .mdp = sm8550_mdp,
> + .mdp = &sm8550_mdp,
> .ctl_count = ARRAY_SIZE(sm8550_ctl),
> .ctl = sm8550_ctl,
> .sspp_count = ARRAY_SIZE(sm8550_sspp),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index b07caa4b867e..3b816e36d12d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -809,7 +809,6 @@ struct dpu_mdss_cfg {
>
> const struct dpu_ubwc_cfg *ubwc;
>
> - u32 mdp_count;
> const struct dpu_mdp_cfg *mdp;
>
> u32 ctl_count;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> index 963bdb5e0252..f8c42497b37d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> @@ -268,51 +268,25 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> ops->intf_audio_select = dpu_hw_intf_audio_select;
> }
>
> -static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp,
> - const struct dpu_mdss_cfg *m,
> - void __iomem *addr,
> - struct dpu_hw_blk_reg_map *b)
> -{
> - int i;
> -
> - if (!m || !addr || !b)
> - return ERR_PTR(-EINVAL);
> -
> - for (i = 0; i < m->mdp_count; i++) {
> - if (mdp == m->mdp[i].id) {
> - b->blk_addr = addr + m->mdp[i].base;
> - b->log_mask = DPU_DBG_MASK_TOP;
> - return &m->mdp[i];
> - }
> - }
> -
> - return ERR_PTR(-EINVAL);
> -}
> -
> -struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
> - void __iomem *addr,
> - const struct dpu_mdss_cfg *m)
> +struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
> + void __iomem *addr)
> {
> struct dpu_hw_mdp *mdp;
> - const struct dpu_mdp_cfg *cfg;
>
> - if (!addr || !m)
> + if (!addr)
> return ERR_PTR(-EINVAL);
>
> mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
> if (!mdp)
> return ERR_PTR(-ENOMEM);
>
> - cfg = _top_offset(idx, m, addr, &mdp->hw);
> - if (IS_ERR_OR_NULL(cfg)) {
> - kfree(mdp);
> - return ERR_PTR(-EINVAL);
> - }
> + mdp->hw.blk_addr = addr + cfg->base;
> + mdp->hw.log_mask = DPU_DBG_MASK_TOP;
>
> /*
> * Assign ops
> */
> - mdp->idx = idx;
> + mdp->idx = cfg->id;
> mdp->caps = cfg;
> _setup_mdp_ops(&mdp->ops, mdp->caps->features);
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> index a1a9e44bed36..c89746c6f500 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> @@ -146,13 +146,11 @@ struct dpu_hw_mdp {
>
> /**
> * dpu_hw_mdptop_init - initializes the top driver for the passed idx
> - * @idx: Interface index for which driver object is required
> + * @cfg: MDP TOP configuration from catalog
> * @addr: Mapped register io address of MDP
> - * @m: Pointer to mdss catalog data
> */
> -struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
> - void __iomem *addr,
> - const struct dpu_mdss_cfg *m);
> +struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,
> + void __iomem *addr);
>
> void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp);
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index aa8499de1b9f..882f20fc51cc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1092,8 +1092,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>
> dpu_kms->rm_init = true;
>
> - dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
> - dpu_kms->catalog);
> + dpu_kms->hw_mdp = dpu_hw_mdptop_init(dpu_kms->catalog->mdp,
> + dpu_kms->mmio);
> if (IS_ERR(dpu_kms->hw_mdp)) {
> rc = PTR_ERR(dpu_kms->hw_mdp);
> DPU_ERROR("failed to get hw_mdp: %d\n", rc);
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 05/19] drm/msm/dpu: drop enum dpu_mdp and MDP_TOP value
2023-06-19 21:25 ` [PATCH v4 05/19] drm/msm/dpu: drop enum dpu_mdp and MDP_TOP value Dmitry Baryshkov
@ 2023-07-03 2:06 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 2:06 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> Since there is always just a single MDP_TOP instance, drop the enum
> dpu_mdp and corresponding index value.
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 06/19] drm/msm/dpu: expand .clk_ctrls definitions
2023-06-19 21:25 ` [PATCH v4 06/19] drm/msm/dpu: expand .clk_ctrls definitions Dmitry Baryshkov
@ 2023-07-03 2:21 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 2:21 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> Use more standard initialisation for .clk_ctrls definitions. Define a
> single .clk_ctrls field and use array init inside.
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 07/19] drm/msm/dpu: drop zero features from dpu_mdp_cfg data
2023-06-19 21:25 ` [PATCH v4 07/19] drm/msm/dpu: drop zero features from dpu_mdp_cfg data Dmitry Baryshkov
@ 2023-07-03 2:28 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 2:28 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> Drop useless zero assignments to the dpu_mdp_cfg::features field.
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 08/19] drm/msm/dpu: drop zero features from dpu_ctl_cfg data
2023-06-19 21:25 ` [PATCH v4 08/19] drm/msm/dpu: drop zero features from dpu_ctl_cfg data Dmitry Baryshkov
@ 2023-07-03 15:58 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 15:58 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> Drop useless zero assignments to the dpu_ctl_cfg::features field.
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 09/19] drm/msm/dpu: correct indentation for CTL definitions
2023-06-19 21:25 ` [PATCH v4 09/19] drm/msm/dpu: correct indentation for CTL definitions Dmitry Baryshkov
@ 2023-07-03 16:01 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 16:01 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> Shift dpu_ctl_cfg contents to correct the indentation of CTL blocks.
> This is done in preparation to expanding the rest of hardware block
> defines, so that all blocks have similar indentation.
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros
2023-06-19 21:25 ` [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros Dmitry Baryshkov
2023-06-27 8:33 ` Marijn Suijten
@ 2023-07-03 16:09 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 16:09 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
I checked a few of the entries to make sure there are no copy-paste
errors but not all of them.
I am going to rely on Marijn's checksum method results that there were
no differences in the checksum and go ahead with my,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 11/19] drm/msm/dpu: inline DSPP_BLK macros
2023-06-19 21:25 ` [PATCH v4 11/19] drm/msm/dpu: inline DSPP_BLK macros Dmitry Baryshkov
2023-06-27 8:34 ` Marijn Suijten
@ 2023-07-03 16:14 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 16:14 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 12/19] drm/msm/dpu: inline LM_BLK macros
2023-06-19 21:25 ` [PATCH v4 12/19] drm/msm/dpu: inline LM_BLK macros Dmitry Baryshkov
2023-06-27 8:34 ` Marijn Suijten
@ 2023-07-03 18:46 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 18:46 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Same comment as the other change, I have cross-checked most of the
entries to make sure they match the pre-inlining values.
For the rest, I am going to rely on Marijn's checksum method.
Hence,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 13/19] drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros
2023-06-27 8:29 ` Marijn Suijten
@ 2023-07-03 18:52 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 18:52 UTC (permalink / raw)
To: Marijn Suijten, Dmitry Baryshkov
Cc: freedreno, Sean Paul, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm
On 6/27/2023 1:29 AM, Marijn Suijten wrote:
> On 2023-06-20 00:25:13, Dmitry Baryshkov wrote:
>> To simplify making changes to the hardware block definitions, expand
>> corresponding macros. This way making all the changes are more obvious
>> and visible in the source files.
>>
>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> You still have two 0x1800's that should be 0x140. Diffing the
> disassembly:
>
> diff --git a/baseline.dis b/dpu_hw_catalog.dis
> index 5a45280..04df183 100644
> --- a/baseline.dis
> +++ b/dpu_hw_catalog.dis
> @@ -1,5 +1,5 @@
>
> -baseline.o: file format elf64-littleaarch64
> +dpu_hw_catalog.o: file format elf64-littleaarch64
>
>
> Disassembly of section .data:
> @@ -2808,7 +2808,7 @@ Disassembly of section .rodata:
> ...
> 3b18: 00000001 udf #1
> 3b1c: 00080000 .inst 0x00080000 ; undefined
> - 3b20: 00000140 udf #320
> + 3b20: 00001800 udf #6144
> 3b24: 00000000 udf #0
> 3b28: 00000002 udf #2
> ...
> @@ -3112,7 +3112,7 @@ Disassembly of section .rodata:
> ...
> 43a8: 00000001 udf #1
> 43ac: 00080000 .inst 0x00080000 ; undefined
> - 43b0: 00000140 udf #320
> + 43b0: 00001800 udf #6144
> 43b4: 00000000 udf #0
> 43b8: 00000002 udf #2
> ...
>
> These are the freshly added SM6350/75, see below.
>
Yup. Thats right. Nice catch !
Tough to catch that visually with all the numbers moving around.
>> ---
>> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 9 ++++-
>> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 17 +++++++--
>> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 21 +++++++++--
>> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 31 +++++++++++++---
>> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 21 +++++++++--
>> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 6 ++-
>> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 6 ++-
>> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 25 +++++++++++--
>> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +++-
>> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 37 ++++++++++++++++---
>> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 25 +++++++++++--
>> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 25 +++++++++++--
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 --------
>> 13 files changed, 189 insertions(+), 56 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
>> index a07c68744b29..d5111f3782a2 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
>> @@ -200,8 +200,13 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = {
>> };
>>
>> static const struct dpu_dsc_cfg msm8998_dsc[] = {
>> - DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
>> - DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
>> + {
>> + .name = "dsc_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x140,
>> + }, {
>> + .name = "dsc_1", .id = DSC_1,
>> + .base = 0x80400, .len = 0x140,
>> + },
>> };
>>
>> static const struct dpu_dspp_cfg msm8998_dspp[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
>> index 786263ed1ef2..b6f52b3864ce 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
>> @@ -224,10 +224,19 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = {
>> };
>>
>> static const struct dpu_dsc_cfg sdm845_dsc[] = {
>> - DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
>> - DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
>> - DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
>> - DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
>> + {
>> + .name = "dsc_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x140,
>> + }, {
>> + .name = "dsc_1", .id = DSC_1,
>> + .base = 0x80400, .len = 0x140,
>> + }, {
>> + .name = "dsc_2", .id = DSC_2,
>> + .base = 0x80800, .len = 0x140,
>> + }, {
>> + .name = "dsc_3", .id = DSC_3,
>> + .base = 0x80c00, .len = 0x140,
>> + },
>> };
>>
>> static const struct dpu_intf_cfg sdm845_intf[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
>> index 6b9bfeac6e0a..9b2de5986e82 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
>> @@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
>> };
>>
>> static const struct dpu_dsc_cfg sm8150_dsc[] = {
>> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
>> + {
>> + .name = "dsc_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_1", .id = DSC_1,
>> + .base = 0x80400, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_2", .id = DSC_2,
>> + .base = 0x80800, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_3", .id = DSC_3,
>> + .base = 0x80c00, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + },
>> };
>>
>> static const struct dpu_intf_cfg sm8150_intf[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
>> index 414f0db3306c..683602e54c0e 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
>> @@ -244,12 +244,31 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
>> };
>>
>> static const struct dpu_dsc_cfg sc8180x_dsc[] = {
>> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)),
>> + {
>> + .name = "dsc_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_1", .id = DSC_1,
>> + .base = 0x80400, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_2", .id = DSC_2,
>> + .base = 0x80800, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_3", .id = DSC_3,
>> + .base = 0x80c00, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_4", .id = DSC_4,
>> + .base = 0x81000, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_5", .id = DSC_5,
>> + .base = 0x81400, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + },
>> };
>>
>> static const struct dpu_intf_cfg sc8180x_intf[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
>> index db3a65b011ca..a98d63f6c47c 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
>> @@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
>> };
>>
>> static const struct dpu_dsc_cfg sm8250_dsc[] = {
>> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
>> - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
>> + {
>> + .name = "dsc_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_1", .id = DSC_1,
>> + .base = 0x80400, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_2", .id = DSC_2,
>> + .base = 0x80800, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + }, {
>> + .name = "dsc_3", .id = DSC_3,
>> + .base = 0x80c00, .len = 0x140,
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + },
>> };
>>
>> static const struct dpu_intf_cfg sm8250_intf[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> index a996c39b7b1f..a9907010a4a2 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
>> @@ -136,7 +136,11 @@ static struct dpu_pingpong_cfg sm6350_pp[] = {
>> };
>>
>> static const struct dpu_dsc_cfg sm6350_dsc[] = {
>> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
>> + {
>> + .name = "dsc_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x1800,
>
> Here.
>
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + },
>> };
>>
>> static const struct dpu_intf_cfg sm6350_intf[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
>> index 0cdb77599583..e42f0dc3b2ab 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
>> @@ -90,7 +90,11 @@ static const struct dpu_pingpong_cfg sm6375_pp[] = {
>> };
>>
>> static const struct dpu_dsc_cfg sm6375_dsc[] = {
>> - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
>> + {
>> + .name = "dsc_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x1800,
>
> And here.
>
> - Marijn
>
>> + .features = BIT(DPU_DSC_OUTPUT_CTRL),
>> + },
>> };
>>
>> static const struct dpu_intf_cfg sm6375_intf[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>> index e08b29e9e146..8a9bfc4af72a 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>> @@ -248,10 +248,27 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
>> * its own different sub block address.
>> */
>> static const struct dpu_dsc_cfg sm8350_dsc[] = {
>> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
>> - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
>> - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
>> - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
>> + {
>> + .name = "dce_0_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_0,
>> + }, {
>> + .name = "dce_0_1", .id = DSC_1,
>> + .base = 0x80000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_1,
>> + }, {
>> + .name = "dce_1_0", .id = DSC_2,
>> + .base = 0x81000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> + .sblk = &dsc_sblk_0,
>> + }, {
>> + .name = "dce_1_1", .id = DSC_3,
>> + .base = 0x81000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> + .sblk = &dsc_sblk_1,
>> + },
>> };
>>
>> static const struct dpu_intf_cfg sm8350_intf[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>> index d5faa1816cb3..9c0beccce282 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>> @@ -146,7 +146,12 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
>>
>> /* NOTE: sc7280 only has one DSC hard slice encoder */
>> static const struct dpu_dsc_cfg sc7280_dsc[] = {
>> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
>> + {
>> + .name = "dce_0_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> + .sblk = &dsc_sblk_0,
>> + },
>> };
>>
>> static const struct dpu_wb_cfg sc7280_wb[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
>> index 8e4299be2b1c..b676819db42c 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
>> @@ -246,12 +246,37 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
>> * its own different sub block address.
>> */
>> static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
>> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
>> - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
>> - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
>> - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
>> - DSC_BLK_1_2("dce_2_0", DSC_4, 0x82000, 0x29c, 0, dsc_sblk_0),
>> - DSC_BLK_1_2("dce_2_1", DSC_5, 0x82000, 0x29c, 0, dsc_sblk_1),
>> + {
>> + .name = "dce_0_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_0,
>> + }, {
>> + .name = "dce_0_1", .id = DSC_1,
>> + .base = 0x80000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_1,
>> + }, {
>> + .name = "dce_1_0", .id = DSC_2,
>> + .base = 0x81000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> + .sblk = &dsc_sblk_0,
>> + }, {
>> + .name = "dce_1_1", .id = DSC_3,
>> + .base = 0x81000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> + .sblk = &dsc_sblk_1,
>> + }, {
>> + .name = "dce_2_0", .id = DSC_4,
>> + .base = 0x82000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_0,
>> + }, {
>> + .name = "dce_2_1", .id = DSC_5,
>> + .base = 0x82000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_1,
>> + },
>> };
>>
>> /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
>> index bbee3c621943..568523abc1d0 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
>> @@ -259,10 +259,27 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
>> * its own different sub block address.
>> */
>> static const struct dpu_dsc_cfg sm8450_dsc[] = {
>> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
>> - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
>> - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
>> - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
>> + {
>> + .name = "dce_0_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_0,
>> + }, {
>> + .name = "dce_0_1", .id = DSC_1,
>> + .base = 0x80000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_1,
>> + }, {
>> + .name = "dce_1_0", .id = DSC_2,
>> + .base = 0x81000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> + .sblk = &dsc_sblk_0,
>> + }, {
>> + .name = "dce_1_1", .id = DSC_3,
>> + .base = 0x81000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> + .sblk = &dsc_sblk_1,
>> + },
>> };
>>
>> static const struct dpu_intf_cfg sm8450_intf[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>> index ea7bffe252a5..419624948e83 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>> @@ -273,10 +273,27 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
>> * its own different sub block address.
>> */
>> static const struct dpu_dsc_cfg sm8550_dsc[] = {
>> - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
>> - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
>> - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
>> - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
>> + {
>> + .name = "dce_0_0", .id = DSC_0,
>> + .base = 0x80000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_0,
>> + }, {
>> + .name = "dce_0_1", .id = DSC_1,
>> + .base = 0x80000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2),
>> + .sblk = &dsc_sblk_1,
>> + }, {
>> + .name = "dce_1_0", .id = DSC_2,
>> + .base = 0x81000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> + .sblk = &dsc_sblk_0,
>> + }, {
>> + .name = "dce_1_1", .id = DSC_3,
>> + .base = 0x81000, .len = 0x29c,
>> + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> + .sblk = &dsc_sblk_1,
>> + },
>> };
>>
>> static const struct dpu_intf_cfg sm8550_intf[] = {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 6ef0dc2e1a5d..ee24402bf253 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -495,21 +495,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
>> .ctl = {.base = 0xF80, .len = 0x10},
>> };
>>
>> -#define DSC_BLK(_name, _id, _base, _features) \
>> - {\
>> - .name = _name, .id = _id, \
>> - .base = _base, .len = 0x140, \
>> - .features = _features, \
>> - }
>> -
>> -#define DSC_BLK_1_2(_name, _id, _base, _len, _features, _sblk) \
>> - {\
>> - .name = _name, .id = _id, \
>> - .base = _base, .len = _len, \
>> - .features = BIT(DPU_DSC_HW_REV_1_2) | _features, \
>> - .sblk = &_sblk, \
>> - }
>> -
>> /*************************************************************
>> * INTF sub blocks config
>> *************************************************************/
>> --
>> 2.39.2
>>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros
2023-06-19 21:25 ` [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros Dmitry Baryshkov
2023-06-27 8:34 ` Marijn Suijten
@ 2023-07-03 20:29 ` Abhinav Kumar
2023-07-03 20:58 ` Dmitry Baryshkov
1 sibling, 1 reply; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 20:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
the value of MERGE_3D_SM8150_MASK is 0, so to be uniform with what has
been done with some of the prev patches to drop 0 feature fields
assignment, do you want to do the same here?
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros
2023-07-03 20:29 ` Abhinav Kumar
@ 2023-07-03 20:58 ` Dmitry Baryshkov
2023-07-03 20:59 ` Abhinav Kumar
0 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-07-03 20:58 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten, Sean Paul
On Mon, 3 Jul 2023 at 23:29, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> > To simplify making changes to the hardware block definitions, expand
> > corresponding macros. This way making all the changes are more obvious
> > and visible in the source files.
> >
> > Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
>
> the value of MERGE_3D_SM8150_MASK is 0, so to be uniform with what has
> been done with some of the prev patches to drop 0 feature fields
> assignment, do you want to do the same here?
These patches do macro expansion (+ obvious 0-field removal). So
removal of MERGE_3D_SM8150_MASK had to wait until patch 18.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros
2023-07-03 20:58 ` Dmitry Baryshkov
@ 2023-07-03 20:59 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 20:59 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten, Sean Paul
On 7/3/2023 1:58 PM, Dmitry Baryshkov wrote:
> On Mon, 3 Jul 2023 at 23:29, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
>>> To simplify making changes to the hardware block definitions, expand
>>> corresponding macros. This way making all the changes are more obvious
>>> and visible in the source files.
>>>
>>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>
>> the value of MERGE_3D_SM8150_MASK is 0, so to be uniform with what has
>> been done with some of the prev patches to drop 0 feature fields
>> assignment, do you want to do the same here?
>
> These patches do macro expansion (+ obvious 0-field removal). So
> removal of MERGE_3D_SM8150_MASK had to wait until patch 18.
>
Ah okay, got it.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 15/19] drm/msm/dpu: inline various PP_BLK_* macros
2023-06-19 21:25 ` [PATCH v4 15/19] drm/msm/dpu: inline various PP_BLK_* macros Dmitry Baryshkov
2023-06-27 8:35 ` Marijn Suijten
@ 2023-07-03 21:01 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 21:01 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 16/19] drm/msm/dpu: inline WB_BLK macros
2023-06-19 21:25 ` [PATCH v4 16/19] drm/msm/dpu: inline WB_BLK macros Dmitry Baryshkov
2023-06-27 8:35 ` Marijn Suijten
@ 2023-07-03 21:04 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 21:04 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros
2023-06-19 21:25 ` [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros Dmitry Baryshkov
2023-06-27 8:35 ` Marijn Suijten
@ 2023-07-03 21:06 ` Abhinav Kumar
1 sibling, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 21:06 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 18/19] drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK
2023-06-19 21:25 ` [PATCH v4 18/19] drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK Dmitry Baryshkov
@ 2023-07-03 21:08 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 21:08 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> The MERGE_3D_SM8150_MASK features mask is zero. Drop it completely.
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 19/19] drm/msm/dpu: drop empty features mask INTF_SDM845_MASK
2023-06-19 21:25 ` [PATCH v4 19/19] drm/msm/dpu: drop empty features mask INTF_SDM845_MASK Dmitry Baryshkov
@ 2023-07-03 21:12 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-03 21:12 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> The INTF_SDM845_MASK features mask is zero. Drop it completely.
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 --
> 3 files changed, 10 deletions(-)
>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-07-03 2:01 ` Abhinav Kumar
@ 2023-07-04 2:20 ` Dmitry Baryshkov
2023-07-04 4:04 ` Abhinav Kumar
0 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-07-04 2:20 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 03/07/2023 05:01, Abhinav Kumar wrote:
>
>
> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
>> There is always a single MDP TOP block. Drop the mdp_count field and
>> stop declaring dpu_mdp_cfg instances as arrays.
>>
>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>
> The change drops mdp_count and stops using the array which is fine and I
> will support that.
>
> But looking at the pattern I saw while using core_revision, both
> DPU_MDP_VSYNC_SEL and DPU_MDP_AUDIO_SELECT can also be dropped from the
> catalog in favor of using core_revision.
>
> Hence for that, I request you not to stop passing dpu_mdss_cfg to
> dpu_hw_mdptop_init as that has the necessary information of core_revision.
Sure, I'll restore it. Please note, however, that it might be better to
pass struct dpu_caps instead of the full struct dpu_mdss_cfg.
>
>> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
>> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38 +++----------------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
>> 19 files changed, 41 insertions(+), 115 deletions(-)
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-07-04 2:20 ` Dmitry Baryshkov
@ 2023-07-04 4:04 ` Abhinav Kumar
2023-07-04 10:06 ` Dmitry Baryshkov
0 siblings, 1 reply; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-04 4:04 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel,
Stephen Boyd, Marijn Suijten
On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
> On 03/07/2023 05:01, Abhinav Kumar wrote:
>>
>>
>> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
>>> There is always a single MDP TOP block. Drop the mdp_count field and
>>> stop declaring dpu_mdp_cfg instances as arrays.
>>>
>>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>
>> The change drops mdp_count and stops using the array which is fine and
>> I will support that.
>>
>> But looking at the pattern I saw while using core_revision, both
>> DPU_MDP_VSYNC_SEL and DPU_MDP_AUDIO_SELECT can also be dropped from
>> the catalog in favor of using core_revision.
>>
>> Hence for that, I request you not to stop passing dpu_mdss_cfg to
>> dpu_hw_mdptop_init as that has the necessary information of
>> core_revision.
>
> Sure, I'll restore it. Please note, however, that it might be better to
> pass struct dpu_caps instead of the full struct dpu_mdss_cfg.
>
Thanks for restoring.
Can you pls explain this better? dpu_core_rev is part of dpu_mdss_cfg,
so dpu_caps wont be enough for this one.
>>
>>> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
>>> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38 +++----------------
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
>>> 19 files changed, 41 insertions(+), 115 deletions(-)
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-07-04 4:04 ` Abhinav Kumar
@ 2023-07-04 10:06 ` Dmitry Baryshkov
2023-07-04 11:52 ` Dmitry Baryshkov
0 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-07-04 10:06 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten, Sean Paul
On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
> > On 03/07/2023 05:01, Abhinav Kumar wrote:
> >>
> >>
> >> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> >>> There is always a single MDP TOP block. Drop the mdp_count field and
> >>> stop declaring dpu_mdp_cfg instances as arrays.
> >>>
> >>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >>> ---
> >>
> >> The change drops mdp_count and stops using the array which is fine and
> >> I will support that.
> >>
> >> But looking at the pattern I saw while using core_revision, both
> >> DPU_MDP_VSYNC_SEL and DPU_MDP_AUDIO_SELECT can also be dropped from
> >> the catalog in favor of using core_revision.
> >>
> >> Hence for that, I request you not to stop passing dpu_mdss_cfg to
> >> dpu_hw_mdptop_init as that has the necessary information of
> >> core_revision.
> >
> > Sure, I'll restore it. Please note, however, that it might be better to
> > pass struct dpu_caps instead of the full struct dpu_mdss_cfg.
> >
>
> Thanks for restoring.
>
> Can you pls explain this better? dpu_core_rev is part of dpu_mdss_cfg,
> so dpu_caps wont be enough for this one.
Oh, true. For some reason I thought that version is a part of dpu_caps.
>
> >>
> >>> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
> >>> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
> >>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
> >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38 +++----------------
> >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
> >>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
> >>> 19 files changed, 41 insertions(+), 115 deletions(-)
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-07-04 10:06 ` Dmitry Baryshkov
@ 2023-07-04 11:52 ` Dmitry Baryshkov
2023-07-04 16:09 ` Abhinav Kumar
0 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-07-04 11:52 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten, Sean Paul
On Tue, 4 Jul 2023 at 13:06, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> >
> >
> >
> > On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
> > > On 03/07/2023 05:01, Abhinav Kumar wrote:
> > >>
> > >>
> > >> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> > >>> There is always a single MDP TOP block. Drop the mdp_count field and
> > >>> stop declaring dpu_mdp_cfg instances as arrays.
> > >>>
> > >>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> > >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > >>> ---
> > >>
> > >> The change drops mdp_count and stops using the array which is fine and
> > >> I will support that.
> > >>
> > >> But looking at the pattern I saw while using core_revision, both
> > >> DPU_MDP_VSYNC_SEL and DPU_MDP_AUDIO_SELECT can also be dropped from
> > >> the catalog in favor of using core_revision.
> > >>
> > >> Hence for that, I request you not to stop passing dpu_mdss_cfg to
> > >> dpu_hw_mdptop_init as that has the necessary information of
> > >> core_revision.
> > >
> > > Sure, I'll restore it. Please note, however, that it might be better to
> > > pass struct dpu_caps instead of the full struct dpu_mdss_cfg.
> > >
> >
> > Thanks for restoring.
> >
> > Can you pls explain this better? dpu_core_rev is part of dpu_mdss_cfg,
> > so dpu_caps wont be enough for this one.
>
> Oh, true. For some reason I thought that version is a part of dpu_caps.
And after additional thought. Maybe it would be better to add a
separate struct dpu_mdss_version and pass it to the hw block init
functions?
>
> >
> > >>
> > >>> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
> > >>> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
> > >>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
> > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38 +++----------------
> > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
> > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
> > >>> 19 files changed, 41 insertions(+), 115 deletions(-)
> > >
>
>
>
> --
> With best wishes
> Dmitry
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-07-04 11:52 ` Dmitry Baryshkov
@ 2023-07-04 16:09 ` Abhinav Kumar
2023-07-04 17:28 ` Dmitry Baryshkov
0 siblings, 1 reply; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-04 16:09 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten, Sean Paul
On 7/4/2023 4:52 AM, Dmitry Baryshkov wrote:
> On Tue, 4 Jul 2023 at 13:06, Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
>>
>> On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>>
>>>
>>>
>>> On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
>>>> On 03/07/2023 05:01, Abhinav Kumar wrote:
>>>>>
>>>>>
>>>>> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
>>>>>> There is always a single MDP TOP block. Drop the mdp_count field and
>>>>>> stop declaring dpu_mdp_cfg instances as arrays.
>>>>>>
>>>>>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
>>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>>> ---
>>>>>
>>>>> The change drops mdp_count and stops using the array which is fine and
>>>>> I will support that.
>>>>>
>>>>> But looking at the pattern I saw while using core_revision, both
>>>>> DPU_MDP_VSYNC_SEL and DPU_MDP_AUDIO_SELECT can also be dropped from
>>>>> the catalog in favor of using core_revision.
>>>>>
>>>>> Hence for that, I request you not to stop passing dpu_mdss_cfg to
>>>>> dpu_hw_mdptop_init as that has the necessary information of
>>>>> core_revision.
>>>>
>>>> Sure, I'll restore it. Please note, however, that it might be better to
>>>> pass struct dpu_caps instead of the full struct dpu_mdss_cfg.
>>>>
>>>
>>> Thanks for restoring.
>>>
>>> Can you pls explain this better? dpu_core_rev is part of dpu_mdss_cfg,
>>> so dpu_caps wont be enough for this one.
>>
>> Oh, true. For some reason I thought that version is a part of dpu_caps.
>
> And after additional thought. Maybe it would be better to add a
> separate struct dpu_mdss_version and pass it to the hw block init
> functions?
>
I would like to see this evolve. Today, we are assuming that only the hw
block init functions are the places we would use those.
From what I recall, the DSC over DP series needed the core_revision in
the timing gen code somewhere.
If we see that pattern is possible once that lands, why not.
Right now, I would leave it at dpu_mdss_cfg.
>>
>>>
>>>>>
>>>>>> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
>>>>>> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
>>>>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38 +++----------------
>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
>>>>>> 19 files changed, 41 insertions(+), 115 deletions(-)
>>>>
>>
>>
>>
>> --
>> With best wishes
>> Dmitry
>
>
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-07-04 16:09 ` Abhinav Kumar
@ 2023-07-04 17:28 ` Dmitry Baryshkov
2023-07-04 19:01 ` Abhinav Kumar
0 siblings, 1 reply; 59+ messages in thread
From: Dmitry Baryshkov @ 2023-07-04 17:28 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten, Sean Paul
On Tue, 4 Jul 2023 at 19:10, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
>
>
> On 7/4/2023 4:52 AM, Dmitry Baryshkov wrote:
> > On Tue, 4 Jul 2023 at 13:06, Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> >>
> >> On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> >>>
> >>>
> >>>
> >>> On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
> >>>> On 03/07/2023 05:01, Abhinav Kumar wrote:
> >>>>>
> >>>>>
> >>>>> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
> >>>>>> There is always a single MDP TOP block. Drop the mdp_count field and
> >>>>>> stop declaring dpu_mdp_cfg instances as arrays.
> >>>>>>
> >>>>>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
> >>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >>>>>> ---
> >>>>>
> >>>>> The change drops mdp_count and stops using the array which is fine and
> >>>>> I will support that.
> >>>>>
> >>>>> But looking at the pattern I saw while using core_revision, both
> >>>>> DPU_MDP_VSYNC_SEL and DPU_MDP_AUDIO_SELECT can also be dropped from
> >>>>> the catalog in favor of using core_revision.
> >>>>>
> >>>>> Hence for that, I request you not to stop passing dpu_mdss_cfg to
> >>>>> dpu_hw_mdptop_init as that has the necessary information of
> >>>>> core_revision.
> >>>>
> >>>> Sure, I'll restore it. Please note, however, that it might be better to
> >>>> pass struct dpu_caps instead of the full struct dpu_mdss_cfg.
> >>>>
> >>>
> >>> Thanks for restoring.
> >>>
> >>> Can you pls explain this better? dpu_core_rev is part of dpu_mdss_cfg,
> >>> so dpu_caps wont be enough for this one.
> >>
> >> Oh, true. For some reason I thought that version is a part of dpu_caps.
> >
> > And after additional thought. Maybe it would be better to add a
> > separate struct dpu_mdss_version and pass it to the hw block init
> > functions?
> >
>
> I would like to see this evolve. Today, we are assuming that only the hw
> block init functions are the places we would use those.
>
> From what I recall, the DSC over DP series needed the core_revision in
> the timing gen code somewhere.
I hope you are talking about the DPU driver here, not about the DP
driver. For the DP driver please use struct msm_dp_desc.
>
> If we see that pattern is possible once that lands, why not.
>
> Right now, I would leave it at dpu_mdss_cfg.
>
> >>
> >>>
> >>>>>
> >>>>>> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
> >>>>>> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
> >>>>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
> >>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38 +++----------------
> >>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
> >>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
> >>>>>> 19 files changed, 41 insertions(+), 115 deletions(-)
> >>>>
> >>
> >>
> >>
> >> --
> >> With best wishes
> >> Dmitry
> >
> >
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-07-04 17:28 ` Dmitry Baryshkov
@ 2023-07-04 19:01 ` Abhinav Kumar
2023-07-12 0:41 ` [Freedreno] " Abhinav Kumar
0 siblings, 1 reply; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-04 19:01 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten, Sean Paul
On 7/4/2023 10:28 AM, Dmitry Baryshkov wrote:
> On Tue, 4 Jul 2023 at 19:10, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>
>>
>>
>> On 7/4/2023 4:52 AM, Dmitry Baryshkov wrote:
>>> On Tue, 4 Jul 2023 at 13:06, Dmitry Baryshkov
>>> <dmitry.baryshkov@linaro.org> wrote:
>>>>
>>>> On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>>>>>
>>>>>
>>>>>
>>>>> On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
>>>>>> On 03/07/2023 05:01, Abhinav Kumar wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
>>>>>>>> There is always a single MDP TOP block. Drop the mdp_count field and
>>>>>>>> stop declaring dpu_mdp_cfg instances as arrays.
>>>>>>>>
>>>>>>>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
>>>>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>>>>> ---
>>>>>>>
>>>>>>> The change drops mdp_count and stops using the array which is fine and
>>>>>>> I will support that.
>>>>>>>
>>>>>>> But looking at the pattern I saw while using core_revision, both
>>>>>>> DPU_MDP_VSYNC_SEL and DPU_MDP_AUDIO_SELECT can also be dropped from
>>>>>>> the catalog in favor of using core_revision.
>>>>>>>
>>>>>>> Hence for that, I request you not to stop passing dpu_mdss_cfg to
>>>>>>> dpu_hw_mdptop_init as that has the necessary information of
>>>>>>> core_revision.
>>>>>>
>>>>>> Sure, I'll restore it. Please note, however, that it might be better to
>>>>>> pass struct dpu_caps instead of the full struct dpu_mdss_cfg.
>>>>>>
>>>>>
>>>>> Thanks for restoring.
>>>>>
>>>>> Can you pls explain this better? dpu_core_rev is part of dpu_mdss_cfg,
>>>>> so dpu_caps wont be enough for this one.
>>>>
>>>> Oh, true. For some reason I thought that version is a part of dpu_caps.
>>>
>>> And after additional thought. Maybe it would be better to add a
>>> separate struct dpu_mdss_version and pass it to the hw block init
>>> functions?
>>>
>>
>> I would like to see this evolve. Today, we are assuming that only the hw
>> block init functions are the places we would use those.
>>
>> From what I recall, the DSC over DP series needed the core_revision in
>> the timing gen code somewhere.
>
> I hope you are talking about the DPU driver here, not about the DP
> driver. For the DP driver please use struct msm_dp_desc.
>
Yes DPU driver.
>>
>> If we see that pattern is possible once that lands, why not.
>>
>> Right now, I would leave it at dpu_mdss_cfg.
>>
>>>>
>>>>>
>>>>>>>
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
>>>>>>>> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
>>>>>>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
>>>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38 +++----------------
>>>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
>>>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
>>>>>>>> 19 files changed, 41 insertions(+), 115 deletions(-)
>>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> With best wishes
>>>> Dmitry
>>>
>>>
>>>
>
>
>
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Freedreno] [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field
2023-07-04 19:01 ` Abhinav Kumar
@ 2023-07-12 0:41 ` Abhinav Kumar
0 siblings, 0 replies; 59+ messages in thread
From: Abhinav Kumar @ 2023-07-12 0:41 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Sean Paul, freedreno, Bjorn Andersson, dri-devel, Stephen Boyd,
linux-arm-msm, Marijn Suijten
On 7/4/2023 12:01 PM, Abhinav Kumar wrote:
>
>
> On 7/4/2023 10:28 AM, Dmitry Baryshkov wrote:
>> On Tue, 4 Jul 2023 at 19:10, Abhinav Kumar <quic_abhinavk@quicinc.com>
>> wrote:
>>>
>>>
>>>
>>> On 7/4/2023 4:52 AM, Dmitry Baryshkov wrote:
>>>> On Tue, 4 Jul 2023 at 13:06, Dmitry Baryshkov
>>>> <dmitry.baryshkov@linaro.org> wrote:
>>>>>
>>>>> On Tue, 4 Jul 2023 at 07:04, Abhinav Kumar
>>>>> <quic_abhinavk@quicinc.com> wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>> On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
>>>>>>> On 03/07/2023 05:01, Abhinav Kumar wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
>>>>>>>>> There is always a single MDP TOP block. Drop the mdp_count
>>>>>>>>> field and
>>>>>>>>> stop declaring dpu_mdp_cfg instances as arrays.
>>>>>>>>>
>>>>>>>>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
>>>>>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>>>>>> ---
>>>>>>>>
>>>>>>>> The change drops mdp_count and stops using the array which is
>>>>>>>> fine and
>>>>>>>> I will support that.
>>>>>>>>
>>>>>>>> But looking at the pattern I saw while using core_revision, both
>>>>>>>> DPU_MDP_VSYNC_SEL and DPU_MDP_AUDIO_SELECT can also be dropped from
>>>>>>>> the catalog in favor of using core_revision.
>>>>>>>>
>>>>>>>> Hence for that, I request you not to stop passing dpu_mdss_cfg to
>>>>>>>> dpu_hw_mdptop_init as that has the necessary information of
>>>>>>>> core_revision.
>>>>>>>
>>>>>>> Sure, I'll restore it. Please note, however, that it might be
>>>>>>> better to
>>>>>>> pass struct dpu_caps instead of the full struct dpu_mdss_cfg.
>>>>>>>
>>>>>>
>>>>>> Thanks for restoring.
>>>>>>
>>>>>> Can you pls explain this better? dpu_core_rev is part of
>>>>>> dpu_mdss_cfg,
>>>>>> so dpu_caps wont be enough for this one.
>>>>>
>>>>> Oh, true. For some reason I thought that version is a part of
>>>>> dpu_caps.
>>>>
>>>> And after additional thought. Maybe it would be better to add a
>>>> separate struct dpu_mdss_version and pass it to the hw block init
>>>> functions?
>>>>
>>>
>>> I would like to see this evolve. Today, we are assuming that only the hw
>>> block init functions are the places we would use those.
>>>
>>> From what I recall, the DSC over DP series needed the core_revision in
>>> the timing gen code somewhere.
>>
>> I hope you are talking about the DPU driver here, not about the DP
>> driver. For the DP driver please use struct msm_dp_desc.
>>
>
> Yes DPU driver.
>
>>>
>>> If we see that pattern is possible once that lands, why not.
>>>
>>> Right now, I would leave it at dpu_mdss_cfg.
>>>
Changed my mind on this due to two reasons:
1) the earlier agreement was to pass dpu_mdss_cfg but passing that will
be against the design of dpu_hw_*** functions because they have stopped
passing the index and as dpu_intf_cfg is encapsulated within
dpu_mdss_cfg, passing both is duplicated information.
2) I have cross-checked that even for DSC over DP, we should be able to
pass dpu_kms->catalog->mdss_rev with this approach like I have posted now
>>>>>
>>>>>>
>>>>>>>>
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 +---
>>>>>>>>> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 +---
>>>>>>>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
>>>>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 38
>>>>>>>>> +++----------------
>>>>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 8 ++--
>>>>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +-
>>>>>>>>> 19 files changed, 41 insertions(+), 115 deletions(-)
>>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> With best wishes
>>>>> Dmitry
>>>>
>>>>
>>>>
>>
>>
>>
^ permalink raw reply [flat|nested] 59+ messages in thread
end of thread, other threads:[~2023-07-12 0:41 UTC | newest]
Thread overview: 59+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-19 21:25 [PATCH v4 00/19] drm/msm/dpu: another catalog rework Dmitry Baryshkov
2023-06-19 21:25 ` [PATCH v4 01/19] drm/msm: enumerate DSI interfaces Dmitry Baryshkov
2023-06-19 21:25 ` [PATCH v4 02/19] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n Dmitry Baryshkov
2023-07-03 0:53 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 03/19] drm/msm/dpu: simplify peer LM handling Dmitry Baryshkov
2023-07-03 1:34 ` Abhinav Kumar
2023-07-03 1:36 ` Dmitry Baryshkov
2023-07-03 1:49 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 04/19] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field Dmitry Baryshkov
2023-06-26 12:28 ` Marijn Suijten
2023-07-03 2:01 ` Abhinav Kumar
2023-07-04 2:20 ` Dmitry Baryshkov
2023-07-04 4:04 ` Abhinav Kumar
2023-07-04 10:06 ` Dmitry Baryshkov
2023-07-04 11:52 ` Dmitry Baryshkov
2023-07-04 16:09 ` Abhinav Kumar
2023-07-04 17:28 ` Dmitry Baryshkov
2023-07-04 19:01 ` Abhinav Kumar
2023-07-12 0:41 ` [Freedreno] " Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 05/19] drm/msm/dpu: drop enum dpu_mdp and MDP_TOP value Dmitry Baryshkov
2023-07-03 2:06 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 06/19] drm/msm/dpu: expand .clk_ctrls definitions Dmitry Baryshkov
2023-07-03 2:21 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 07/19] drm/msm/dpu: drop zero features from dpu_mdp_cfg data Dmitry Baryshkov
2023-07-03 2:28 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 08/19] drm/msm/dpu: drop zero features from dpu_ctl_cfg data Dmitry Baryshkov
2023-07-03 15:58 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 09/19] drm/msm/dpu: correct indentation for CTL definitions Dmitry Baryshkov
2023-07-03 16:01 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros Dmitry Baryshkov
2023-06-27 8:33 ` Marijn Suijten
2023-07-03 16:09 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 11/19] drm/msm/dpu: inline DSPP_BLK macros Dmitry Baryshkov
2023-06-27 8:34 ` Marijn Suijten
2023-07-03 16:14 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 12/19] drm/msm/dpu: inline LM_BLK macros Dmitry Baryshkov
2023-06-27 8:34 ` Marijn Suijten
2023-07-03 18:46 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 13/19] drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros Dmitry Baryshkov
2023-06-27 8:29 ` Marijn Suijten
2023-07-03 18:52 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 14/19] drm/msm/dpu: inline MERGE_3D_BLK macros Dmitry Baryshkov
2023-06-27 8:34 ` Marijn Suijten
2023-07-03 20:29 ` Abhinav Kumar
2023-07-03 20:58 ` Dmitry Baryshkov
2023-07-03 20:59 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 15/19] drm/msm/dpu: inline various PP_BLK_* macros Dmitry Baryshkov
2023-06-27 8:35 ` Marijn Suijten
2023-07-03 21:01 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 16/19] drm/msm/dpu: inline WB_BLK macros Dmitry Baryshkov
2023-06-27 8:35 ` Marijn Suijten
2023-07-03 21:04 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros Dmitry Baryshkov
2023-06-27 8:35 ` Marijn Suijten
2023-07-03 21:06 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 18/19] drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK Dmitry Baryshkov
2023-07-03 21:08 ` Abhinav Kumar
2023-06-19 21:25 ` [PATCH v4 19/19] drm/msm/dpu: drop empty features mask INTF_SDM845_MASK Dmitry Baryshkov
2023-07-03 21:12 ` Abhinav Kumar
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).