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From: Adrian Hunter <adrian.hunter@intel.com>
To: Ritesh Harjani <riteshh@codeaurora.org>,
	ulf.hansson@linaro.org, linux-mmc@vger.kernel.org,
	sboyd@codeaurora.org, andy.gross@linaro.org
Cc: shawn.lin@rock-chips.com, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, david.brown@linaro.org,
	linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org,
	alex.lemberg@sandisk.com, mateusz.nowak@intel.com,
	Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org,
	david.griego@linaro.org, stummala@codeaurora.org,
	venkatg@codeaurora.org, rnayak@codeaurora.org,
	pramod.gurav@linaro.org, jeremymc@redhat.com
Subject: Re: [PATCH v8 10/16] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
Date: Fri, 18 Nov 2016 16:14:58 +0200	[thread overview]
Message-ID: <e34e5767-7557-d68c-6ab7-862991d17b6c@intel.com> (raw)
In-Reply-To: <1479312052-22396-11-git-send-email-riteshh@codeaurora.org>

On 16/11/16 18:00, Ritesh Harjani wrote:
> sdhci-msm controller may have different clk-rates for each
> bus speed mode. Thus implement set_clock callback for
> sdhci-msm driver.
> 
> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>

Yes my Ack stands.

> ---
>  drivers/mmc/host/sdhci-msm.c | 66 +++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 65 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 45ead68..6d02fc2 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -84,6 +84,7 @@ struct sdhci_msm_host {
>  	struct clk *pclk;	/* SDHC peripheral bus clock */
>  	struct clk *bus_clk;	/* SDHC bus voter clock */
>  	struct clk *xo_clk;	/* TCXO clk needed for FLL feature of cm_dll*/
> +	unsigned long clk_rate;
>  	struct mmc_host *mmc;
>  	bool use_14lpp_dll_reset;
>  };
> @@ -571,6 +572,69 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
>  	return SDHCI_MSM_MIN_CLOCK;
>  }
>  
> +/**
> + * __sdhci_msm_set_clock - sdhci_msm clock control.
> + *
> + * Description:
> + * MSM controller does not use internal divider and
> + * instead directly control the GCC clock as per
> + * HW recommendation.
> + **/
> +void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
> +{
> +	u16 clk;
> +	/*
> +	 * Keep actual_clock as zero -
> +	 * - since there is no divider used so no need of having actual_clock.
> +	 * - MSM controller uses SDCLK for data timeout calculation. If
> +	 *   actual_clock is zero, host->clock is taken for calculation.
> +	 */
> +	host->mmc->actual_clock = 0;
> +
> +	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> +
> +	if (clock == 0)
> +		return;
> +
> +	/*
> +	 * MSM controller do not use clock divider.
> +	 * Thus read SDHCI_CLOCK_CONTROL and only enable
> +	 * clock with no divider value programmed.
> +	 */
> +	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> +	sdhci_enable_clock(host, clk);
> +}
> +
> +/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
> +static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
> +	int rc;
> +
> +	if (!clock) {
> +		msm_host->clk_rate = clock;
> +		goto out;
> +	}
> +
> +	spin_unlock_irq(&host->lock);
> +
> +	rc = clk_set_rate(msm_host->clk, clock);
> +	if (rc) {
> +		pr_err("%s: Failed to set clock at rate %u\n",
> +		       mmc_hostname(host->mmc), clock);
> +		goto out_lock;
> +	}
> +	msm_host->clk_rate = clock;
> +	pr_debug("%s: Setting clock at rate %lu\n",
> +		 mmc_hostname(host->mmc), clk_get_rate(msm_host->clk));
> +
> +out_lock:
> +	spin_lock_irq(&host->lock);
> +out:
> +	__sdhci_msm_set_clock(host, clock);
> +}
> +
>  static const struct of_device_id sdhci_msm_dt_match[] = {
>  	{ .compatible = "qcom,sdhci-msm-v4" },
>  	{},
> @@ -581,7 +645,7 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
>  static const struct sdhci_ops sdhci_msm_ops = {
>  	.platform_execute_tuning = sdhci_msm_execute_tuning,
>  	.reset = sdhci_reset,
> -	.set_clock = sdhci_set_clock,
> +	.set_clock = sdhci_msm_set_clock,
>  	.get_min_clock = sdhci_msm_get_min_clock,
>  	.get_max_clock = sdhci_msm_get_max_clock,
>  	.set_bus_width = sdhci_set_bus_width,
> 

  reply	other threads:[~2016-11-18 14:20 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-16 16:00 [PATCH v8 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 01/16] clk: qcom: Add rcg ops to return floor value closest to the requested rate Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 03/16] mmc: sdhci-msm: Change poor style writel/readl of registers Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 04/16] ARM: dts: Add xo_clock to sdhc nodes on qcom platforms Ritesh Harjani
2016-11-17  0:43   ` [PATCH v8 04/16] ARM: dts: Add xo to sdhc clock node " Ritesh Harjani
2016-11-18  3:56     ` Andy Gross
2016-11-21  6:30       ` Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 05/16] dt-bindings: sdhci-msm: Add xo_clock property Ritesh Harjani
2016-11-16 19:13   ` Stephen Boyd
2016-11-17  0:41     ` Ritesh Harjani
2016-11-17  0:47     ` [PATCH v8 05/16] dt-bindings: sdhci-msm: Add xo property Ritesh Harjani
2016-11-17 23:03       ` Stephen Boyd
     [not found]         ` <20161117230352.GO25626-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-21  6:31           ` Ritesh Harjani
2016-11-21  6:31             ` Ritesh Harjani
     [not found]       ` <1479343623-31163-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-18 14:17         ` Rob Herring
2016-11-18 14:17           ` Rob Herring
2016-11-16 16:00 ` [PATCH v8 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback Ritesh Harjani
     [not found] ` <1479312052-22396-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-16 16:00   ` [PATCH v8 02/16] clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops Ritesh Harjani
2016-11-16 16:00     ` Ritesh Harjani
2016-11-16 16:00   ` [PATCH v8 06/16] mmc: sdhci-msm: Update DLL reset sequence Ritesh Harjani
2016-11-16 16:00     ` Ritesh Harjani
     [not found]     ` <1479312052-22396-7-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-17  0:50       ` Ritesh Harjani
2016-11-17  0:50         ` Ritesh Harjani
2016-11-16 16:00   ` [PATCH v8 08/16] mmc: sdhci-msm: Enable few quirks Ritesh Harjani
2016-11-16 16:00     ` Ritesh Harjani
2016-11-16 16:00   ` [PATCH v8 09/16] mmc: sdhci: Factor out sdhci_enable_clock Ritesh Harjani
2016-11-16 16:00     ` Ritesh Harjani
2016-11-18 13:56     ` Adrian Hunter
2016-11-21  6:31       ` Ritesh Harjani
2016-11-16 16:00   ` [PATCH v8 10/16] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm Ritesh Harjani
2016-11-16 16:00     ` Ritesh Harjani
2016-11-18 14:14     ` Adrian Hunter [this message]
2016-11-16 16:00   ` [PATCH v8 12/16] arm64: dts: qcom: msm8916: Add ddr support to sdhc1 Ritesh Harjani
2016-11-16 16:00     ` Ritesh Harjani
2016-11-17  0:52     ` Ritesh Harjani
2016-11-16 16:00   ` [PATCH v8 13/16] mmc: sdhci-msm: Add HS400 platform support Ritesh Harjani
2016-11-16 16:00     ` Ritesh Harjani
2016-11-16 16:00   ` [PATCH v8 16/16] sdhci: sdhci-msm: update dll configuration Ritesh Harjani
2016-11-16 16:00     ` Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 11/16] mmc: sdhci-msm: Add clock changes for DDR mode Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 14/16] mmc: sdhci-msm: Save the calculated tuning phase Ritesh Harjani
2016-11-16 16:00 ` [PATCH v8 15/16] mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit Ritesh Harjani
2016-11-17  0:08 ` [PATCH v8 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Jeremy McNicoll

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