From: Konrad Dybcio <konrad.dybcio@linaro.org> To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd <swboyd@chromium.org>, freedreno@lists.freedesktop.org Subject: Re: [PATCH v4 06/11] drm/msm/dsi/phy: rework register setting for 7nm PHY Date: Wed, 23 Nov 2022 12:43:48 +0100 [thread overview] Message-ID: <e416812c-5524-673f-4c34-8dab758e0de8@linaro.org> (raw) In-Reply-To: <20221122231235.3299737-7-dmitry.baryshkov@linaro.org> On 23.11.2022 00:12, Dmitry Baryshkov wrote: > In preparation to adding the sm8350 and sm8450 PHYs support, rearrange > register values calculations in dsi_7nm_phy_enable(). This change bears > no functional changes itself, it is merely a preparation for the next > patch. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 26 +++++++++++------------ > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 9e7fa7d88ead..0b780f9d3d0a 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -858,23 +858,34 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > /* Alter PHY configurations if data rate less than 1.5GHZ*/ > less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); > > + if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > + vreg_ctrl_1 = 0x55; > + glbl_pemph_ctrl_0 = 0x11; > + lane_ctrl0 = 0x17; > + } else { > + vreg_ctrl_1 = 0x5c; > + glbl_pemph_ctrl_0 = 0x00; > + lane_ctrl0 = 0x1f; > + } > + > if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > if (phy->cphy_mode) { > glbl_rescode_top_ctrl = 0x00; > glbl_rescode_bot_ctrl = 0x3c; > } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; > } > glbl_str_swi_cal_sel_ctrl = 0x00; > glbl_hstx_str_ctrl_0 = 0x88; > } else { > - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > if (phy->cphy_mode) { > glbl_str_swi_cal_sel_ctrl = 0x03; > glbl_hstx_str_ctrl_0 = 0x66; > } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; > glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; > } > @@ -882,17 +893,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > glbl_rescode_bot_ctrl = 0x3c; > } > > - if (phy->cphy_mode) { > - vreg_ctrl_0 = 0x51; > - vreg_ctrl_1 = 0x55; > - glbl_pemph_ctrl_0 = 0x11; > - lane_ctrl0 = 0x17; > - } else { > - vreg_ctrl_1 = 0x5c; > - glbl_pemph_ctrl_0 = 0x00; > - lane_ctrl0 = 0x1f; > - } > - > /* de-assert digital and pll power down */ > data = BIT(6) | BIT(5); > dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
WARNING: multiple messages have this Message-ID (diff)
From: Konrad Dybcio <konrad.dybcio@linaro.org> To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Stephen Boyd <swboyd@chromium.org>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: Re: [PATCH v4 06/11] drm/msm/dsi/phy: rework register setting for 7nm PHY Date: Wed, 23 Nov 2022 12:43:48 +0100 [thread overview] Message-ID: <e416812c-5524-673f-4c34-8dab758e0de8@linaro.org> (raw) In-Reply-To: <20221122231235.3299737-7-dmitry.baryshkov@linaro.org> On 23.11.2022 00:12, Dmitry Baryshkov wrote: > In preparation to adding the sm8350 and sm8450 PHYs support, rearrange > register values calculations in dsi_7nm_phy_enable(). This change bears > no functional changes itself, it is merely a preparation for the next > patch. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 26 +++++++++++------------ > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 9e7fa7d88ead..0b780f9d3d0a 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -858,23 +858,34 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > /* Alter PHY configurations if data rate less than 1.5GHZ*/ > less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); > > + if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > + vreg_ctrl_1 = 0x55; > + glbl_pemph_ctrl_0 = 0x11; > + lane_ctrl0 = 0x17; > + } else { > + vreg_ctrl_1 = 0x5c; > + glbl_pemph_ctrl_0 = 0x00; > + lane_ctrl0 = 0x1f; > + } > + > if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > if (phy->cphy_mode) { > glbl_rescode_top_ctrl = 0x00; > glbl_rescode_bot_ctrl = 0x3c; > } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; > } > glbl_str_swi_cal_sel_ctrl = 0x00; > glbl_hstx_str_ctrl_0 = 0x88; > } else { > - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > if (phy->cphy_mode) { > glbl_str_swi_cal_sel_ctrl = 0x03; > glbl_hstx_str_ctrl_0 = 0x66; > } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; > glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; > } > @@ -882,17 +893,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > glbl_rescode_bot_ctrl = 0x3c; > } > > - if (phy->cphy_mode) { > - vreg_ctrl_0 = 0x51; > - vreg_ctrl_1 = 0x55; > - glbl_pemph_ctrl_0 = 0x11; > - lane_ctrl0 = 0x17; > - } else { > - vreg_ctrl_1 = 0x5c; > - glbl_pemph_ctrl_0 = 0x00; > - lane_ctrl0 = 0x1f; > - } > - > /* de-assert digital and pll power down */ > data = BIT(6) | BIT(5); > dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
next prev parent reply other threads:[~2022-11-23 11:43 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-22 23:12 [PATCH v4 00/11] drm/msm: add support for SM8450 Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-22 23:12 ` [PATCH v4 01/11] dt-bindings: display/msm: *dpu.yaml: split required properties clauses Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-23 10:15 ` Krzysztof Kozlowski 2022-11-23 10:15 ` Krzysztof Kozlowski 2022-11-23 19:25 ` Dmitry Baryshkov 2022-11-23 19:25 ` Dmitry Baryshkov 2022-11-22 23:12 ` [PATCH v4 02/11] dt-bindings: display/msm: *mdss.yaml: " Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-23 10:15 ` Krzysztof Kozlowski 2022-11-23 10:15 ` Krzysztof Kozlowski 2022-11-22 23:12 ` [PATCH v4 03/11] dt-bindings: display/msm: mdss-common: make clock-names required Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-23 10:19 ` Krzysztof Kozlowski 2022-11-23 10:19 ` Krzysztof Kozlowski 2022-11-23 20:18 ` Dmitry Baryshkov 2022-11-23 20:18 ` Dmitry Baryshkov 2022-11-22 23:12 ` [PATCH v4 04/11] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-23 10:24 ` Krzysztof Kozlowski 2022-11-23 10:24 ` Krzysztof Kozlowski 2022-11-22 23:12 ` [PATCH v4 05/11] dt-bindings: display/msm: add support for the display on SM8450 Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-23 10:32 ` Krzysztof Kozlowski 2022-11-23 10:32 ` Krzysztof Kozlowski 2022-11-23 10:38 ` Dmitry Baryshkov 2022-11-23 10:38 ` Dmitry Baryshkov 2022-11-22 23:12 ` [PATCH v4 06/11] drm/msm/dsi/phy: rework register setting for 7nm PHY Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-23 11:43 ` Konrad Dybcio [this message] 2022-11-23 11:43 ` Konrad Dybcio 2022-11-22 23:12 ` [PATCH v4 07/11] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-23 11:41 ` Konrad Dybcio 2022-11-23 11:41 ` Konrad Dybcio 2022-11-22 23:12 ` [PATCH v4 08/11] drm/msm/dsi: add support for DSI 2.6.0 Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-22 23:12 ` [PATCH v4 09/11] drm/msm/dpu: add support for MDP_TOP blackhole Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-23 5:36 ` Abhinav Kumar 2022-11-23 5:36 ` Abhinav Kumar 2022-11-23 17:25 ` Neil Armstrong 2022-11-23 17:25 ` Neil Armstrong 2022-11-22 23:12 ` [PATCH v4 10/11] drm/msm/dpu: add support for SM8450 Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-22 23:12 ` [PATCH v4 11/11] drm/msm: mdss " Dmitry Baryshkov 2022-11-22 23:12 ` Dmitry Baryshkov 2022-11-23 10:23 ` [PATCH v4 00/11] drm/msm: " Krzysztof Kozlowski 2022-11-23 10:23 ` Krzysztof Kozlowski
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