From: Richard Henderson <richard.henderson@linaro.org>
To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: Re: [RFC v3 15/71] target/riscv: introduce more imm value modes in translator functions
Date: Thu, 6 Aug 2020 15:54:07 -0700 [thread overview]
Message-ID: <e5426634-26f6-cc43-cf23-5fffc49ff2b8@linaro.org> (raw)
In-Reply-To: <20200806104709.13235-16-frank.chang@sifive.com>
On 8/6/20 3:46 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Immediate value in translator function is extended not only
> zero-extended and sign-extended but with more modes to be applicable
> with multiple formats of vector instructions.
>
> * IMM_ZX: Zero-extended
> * IMM_SX: Sign-extended
> * IMM_TRUNC_SEW: Truncate to log(SEW) bit
> * IMM_TRUNC_2SEW: Truncate to log(2*SEW) bit
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 115 ++++++++++++++----------
> 1 file changed, 66 insertions(+), 49 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
> index c2d0865bb9b..0a4dd875e96 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -1281,8 +1281,32 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
>
> GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs)
>
> +enum {
> + IMM_ZX, /* Zero-extended */
> + IMM_SX, /* Sign-extended */
> + IMM_TRUNC_SEW, /* Truncate to log(SEW) bits */
> + IMM_TRUNC_2SEW, /* Truncate to log(2*SEW) bits */
> +};
Better to name the enumeration and use it...
> +
> +static int64_t extract_imm(DisasContext *s, uint32_t imm, int imm_mode)
... here.
> +{
> + switch (imm_mode) {
> + case IMM_ZX:
> + return extract64(imm, 0, 5);
> + case IMM_SX:
> + return sextract64(imm, 0, 5);
> + case IMM_TRUNC_SEW:
> + return extract64(imm, 0, 5) & ((1 << (s->sew + 3)) - 1);
> + case IMM_TRUNC_2SEW:
> + return extract64(imm, 0, 5) & ((2 << (s->sew + 3)) - 1);
The extract is redundant with the &.
Alternately, put sew into the extract, like so:
return extract64(imm, 0, s->sew + 3);
and
return extract64(imm, 0, s->sew + 4);
> + default:
> + g_assert_not_reached();
> + break;
Unreachable break.
> static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
> - gen_helper_opivx *fn, DisasContext *s, int zx)
> + gen_helper_opivx *fn, DisasContext *s, int imm_mode)
Use the enum.
> static inline bool
> do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
> - gen_helper_opivx *fn, int zx)
> + gen_helper_opivx *fn, int imm_mode)
Use the enum.
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: Re: [RFC v3 15/71] target/riscv: introduce more imm value modes in translator functions
Date: Thu, 6 Aug 2020 15:54:07 -0700 [thread overview]
Message-ID: <e5426634-26f6-cc43-cf23-5fffc49ff2b8@linaro.org> (raw)
In-Reply-To: <20200806104709.13235-16-frank.chang@sifive.com>
On 8/6/20 3:46 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Immediate value in translator function is extended not only
> zero-extended and sign-extended but with more modes to be applicable
> with multiple formats of vector instructions.
>
> * IMM_ZX: Zero-extended
> * IMM_SX: Sign-extended
> * IMM_TRUNC_SEW: Truncate to log(SEW) bit
> * IMM_TRUNC_2SEW: Truncate to log(2*SEW) bit
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.inc.c | 115 ++++++++++++++----------
> 1 file changed, 66 insertions(+), 49 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
> index c2d0865bb9b..0a4dd875e96 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -1281,8 +1281,32 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
>
> GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs)
>
> +enum {
> + IMM_ZX, /* Zero-extended */
> + IMM_SX, /* Sign-extended */
> + IMM_TRUNC_SEW, /* Truncate to log(SEW) bits */
> + IMM_TRUNC_2SEW, /* Truncate to log(2*SEW) bits */
> +};
Better to name the enumeration and use it...
> +
> +static int64_t extract_imm(DisasContext *s, uint32_t imm, int imm_mode)
... here.
> +{
> + switch (imm_mode) {
> + case IMM_ZX:
> + return extract64(imm, 0, 5);
> + case IMM_SX:
> + return sextract64(imm, 0, 5);
> + case IMM_TRUNC_SEW:
> + return extract64(imm, 0, 5) & ((1 << (s->sew + 3)) - 1);
> + case IMM_TRUNC_2SEW:
> + return extract64(imm, 0, 5) & ((2 << (s->sew + 3)) - 1);
The extract is redundant with the &.
Alternately, put sew into the extract, like so:
return extract64(imm, 0, s->sew + 3);
and
return extract64(imm, 0, s->sew + 4);
> + default:
> + g_assert_not_reached();
> + break;
Unreachable break.
> static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
> - gen_helper_opivx *fn, DisasContext *s, int zx)
> + gen_helper_opivx *fn, DisasContext *s, int imm_mode)
Use the enum.
> static inline bool
> do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
> - gen_helper_opivx *fn, int zx)
> + gen_helper_opivx *fn, int imm_mode)
Use the enum.
r~
next prev parent reply other threads:[~2020-08-06 22:54 UTC|newest]
Thread overview: 181+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-06 10:45 [RFC v3 00/71] target/riscv: support vector extension v1.0 frank.chang
2020-08-06 10:45 ` [RFC v3 01/71] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2020-08-06 10:45 ` frank.chang
2020-08-06 10:45 ` [RFC v3 02/71] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2020-08-06 10:45 ` frank.chang
2020-08-06 10:46 ` [RFC v3 03/71] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 04/71] target/riscv: rvv-1.0: add sstatus " frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 05/71] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 18:04 ` Richard Henderson
2020-08-06 18:04 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 06/71] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 18:08 ` Richard Henderson
2020-08-06 18:08 ` Richard Henderson
2020-08-06 18:30 ` Richard Henderson
2020-08-06 18:30 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 08/71] target/riscv: rvv-1.0: add vcsr register frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 09/71] target/riscv: rvv-1.0: add vlenb register frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 18:28 ` Richard Henderson
2020-08-06 18:28 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 11/71] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 18:36 ` Richard Henderson
2020-08-06 18:36 ` Richard Henderson
2020-08-14 3:12 ` Frank Chang
2020-08-14 3:12 ` Frank Chang
2020-08-06 10:46 ` [RFC v3 13/71] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 19:08 ` Richard Henderson
2020-08-06 19:08 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 14/71] target/riscv: rvv-1.0: update check functions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 15/71] target/riscv: introduce more imm value modes in translator functions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 22:54 ` Richard Henderson [this message]
2020-08-06 22:54 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 16/71] target/riscv: add fp16 nan-box check generator function frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 22:57 ` Richard Henderson
2020-08-06 22:57 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 17/71] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 22:58 ` Richard Henderson
2020-08-06 22:58 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 18/71] target/riscv: rvv-1.0: apply nanbox helper in opfvf_trans frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 23:00 ` Richard Henderson
2020-08-06 23:00 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 19/71] target/riscv: rvv-1.0: configure instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 23:40 ` Richard Henderson
2020-08-06 23:40 ` Richard Henderson
2020-08-06 10:46 ` [RFC v3 20/71] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 21/71] target/riscv: rvv-1.0: index " frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 22/71] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 23/71] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 24/71] target/riscv: rvv-1.0: amo operations frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 25/71] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-07 0:03 ` Richard Henderson
2020-08-07 0:03 ` Richard Henderson
2020-08-14 2:48 ` Frank Chang
2020-08-14 2:48 ` Frank Chang
2020-08-14 18:36 ` Richard Henderson
2020-08-14 18:36 ` Richard Henderson
2020-08-15 2:25 ` Frank Chang
2020-08-15 2:25 ` Frank Chang
2020-08-15 2:52 ` Frank Chang
2020-08-15 2:52 ` Frank Chang
2020-08-15 5:29 ` Richard Henderson
2020-08-15 5:29 ` Richard Henderson
2020-08-15 21:59 ` Frank Chang
2020-08-15 21:59 ` Frank Chang
2020-08-06 10:46 ` [RFC v3 27/71] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 29/71] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 30/71] target/riscv: rvv-1.0: mask population count instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 31/71] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 33/71] target/riscv: rvv-1.0: iota instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 34/71] target/riscv: rvv-1.0: element index instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 35/71] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 37/71] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 38/71] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 39/71] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 40/71] target/riscv: rvv-1.0: whole register " frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 41/71] target/riscv: rvv-1.0: integer extension instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 42/71] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 44/71] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 46/71] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 47/71] target/riscv: rvv-1.0: add Zvqmac extension frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 48/71] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 49/71] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 50/71] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 51/71] target/riscv: use softfloat lib float16 comparison functions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 52/71] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 53/71] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 54/71] target/riscv: rvv-1.0: slide instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 55/71] target/riscv: rvv-1.0: floating-point " frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 56/71] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 57/71] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 58/71] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 59/71] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 60/71] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 61/71] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:46 ` [RFC v3 62/71] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2020-08-06 10:46 ` frank.chang
2020-08-06 10:47 ` [RFC v3 63/71] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 64/71] target/riscv: introduce floating-point rounding mode enum frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 65/71] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 66/71] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 67/71] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 68/71] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 69/71] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 70/71] target/riscv: gdb: support vector registers for rv64 frank.chang
2020-08-06 10:47 ` frank.chang
2020-08-06 10:47 ` [RFC v3 71/71] target/riscv: gdb: support vector registers for rv32 frank.chang
2020-08-06 10:47 ` frank.chang
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