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From: Zong Li <zong.li@sifive.com>
To: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Zong Li <zong.li@sifive.com>
Subject: [PATCH v6 2/4] target/riscv/pmp.c: Fix the index offset on RV64
Date: Tue, 28 Jul 2020 16:26:15 +0800	[thread overview]
Message-ID: <efbd1fd27a166cc89228932bf498897c4b4744ef.1595924470.git.zong.li@sifive.com> (raw)
In-Reply-To: <cover.1595924470.git.zong.li@sifive.com>

On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp
entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original
implementation, the second parameter of pmp_write_cfg is
"reg_index * sizeof(target_ulong)", and we get the the result
which is started from 16 if reg_index is 2, but we expect that
it should be started from 8. Separate the implementation for
RV32 and RV64 respectively.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2a2b9f5363..aeba796484 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -318,6 +318,10 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         return;
     }
 
+#if defined(TARGET_RISCV64)
+    reg_index >>= 1;
+#endif
+
     for (i = 0; i < sizeof(target_ulong); i++) {
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
@@ -335,11 +339,16 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
     target_ulong cfg_val = 0;
     target_ulong val = 0;
 
+    trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
+
+#if defined(TARGET_RISCV64)
+    reg_index >>= 1;
+#endif
+
     for (i = 0; i < sizeof(target_ulong); i++) {
         val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
         cfg_val |= (val << (i * 8));
     }
-    trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
 
     return cfg_val;
 }
-- 
2.27.0



WARNING: multiple messages have this Message-ID (diff)
From: Zong Li <zong.li@sifive.com>
To: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Zong Li <zong.li@sifive.com>, Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v6 2/4] target/riscv/pmp.c: Fix the index offset on RV64
Date: Tue, 28 Jul 2020 16:26:15 +0800	[thread overview]
Message-ID: <efbd1fd27a166cc89228932bf498897c4b4744ef.1595924470.git.zong.li@sifive.com> (raw)
In-Reply-To: <cover.1595924470.git.zong.li@sifive.com>

On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp
entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original
implementation, the second parameter of pmp_write_cfg is
"reg_index * sizeof(target_ulong)", and we get the the result
which is started from 16 if reg_index is 2, but we expect that
it should be started from 8. Separate the implementation for
RV32 and RV64 respectively.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2a2b9f5363..aeba796484 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -318,6 +318,10 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
         return;
     }
 
+#if defined(TARGET_RISCV64)
+    reg_index >>= 1;
+#endif
+
     for (i = 0; i < sizeof(target_ulong); i++) {
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
@@ -335,11 +339,16 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
     target_ulong cfg_val = 0;
     target_ulong val = 0;
 
+    trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
+
+#if defined(TARGET_RISCV64)
+    reg_index >>= 1;
+#endif
+
     for (i = 0; i < sizeof(target_ulong); i++) {
         val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
         cfg_val |= (val << (i * 8));
     }
-    trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
 
     return cfg_val;
 }
-- 
2.27.0



  parent reply	other threads:[~2020-07-28  8:29 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-28  8:26 [PATCH v6 0/4] Fix some PMP implementations Zong Li
2020-07-28  8:26 ` [PATCH v6 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table Zong Li
2020-07-28  8:26   ` Zong Li
2020-07-28  8:26 ` Zong Li [this message]
2020-07-28  8:26   ` [PATCH v6 2/4] target/riscv/pmp.c: Fix the index offset on RV64 Zong Li
2020-07-28  8:26 ` [PATCH v6 3/4] target/riscv: Fix the translation of physical address Zong Li
2020-07-28 23:55   ` Alistair Francis
2020-07-28 23:55     ` Alistair Francis
2020-07-28  8:26 ` [PATCH v6 4/4] target/riscv: Change the TLB page size depends on PMP entries Zong Li
2020-08-05  2:43   ` Zong Li
2020-08-12 15:11   ` Alistair Francis
2020-08-12 15:11     ` Alistair Francis
2020-08-13  3:04     ` Zong Li
2020-08-13  3:04       ` Zong Li
2020-08-13 15:02       ` Alistair Francis
2020-08-13 15:02         ` Alistair Francis

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