From: Jan Beulich <jbeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: "George Dunlap" <George.Dunlap@eu.citrix.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>
Subject: [Xen-devel] [PATCH 3/9] x86/mm: honor opt_pcid also for 32-bit PV domains
Date: Wed, 11 Sep 2019 17:22:51 +0200 [thread overview]
Message-ID: <f58f9215-4005-9c1d-0701-1e7fe705b786@suse.com> (raw)
In-Reply-To: <f6accb8b-38d9-ad9a-ec68-992d75f36a88@suse.com>
I can't see any technical or performance reason why we should treat
32-bit PV different from 64-bit PV in this regard.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/pv/domain.c
+++ b/xen/arch/x86/pv/domain.c
@@ -180,7 +180,24 @@ int switch_compat(struct domain *d)
d->arch.x87_fip_width = 4;
d->arch.pv.xpti = false;
- d->arch.pv.pcid = false;
+
+ if ( use_invpcid && cpu_has_pcid )
+ switch ( ACCESS_ONCE(opt_pcid) )
+ {
+ case PCID_OFF:
+ case PCID_XPTI:
+ d->arch.pv.pcid = false;
+ break;
+
+ case PCID_ALL:
+ case PCID_NOXPTI:
+ d->arch.pv.pcid = true;
+ break;
+
+ default:
+ ASSERT_UNREACHABLE();
+ break;
+ }
return 0;
@@ -312,7 +329,7 @@ int pv_domain_initialise(struct domain *
d->arch.pv.xpti = is_hardware_domain(d) ? opt_xpti_hwdom : opt_xpti_domu;
- if ( !is_pv_32bit_domain(d) && use_invpcid && cpu_has_pcid )
+ if ( use_invpcid && cpu_has_pcid )
switch ( ACCESS_ONCE(opt_pcid) )
{
case PCID_OFF:
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next prev parent reply other threads:[~2019-09-11 15:23 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-11 15:15 [Xen-devel] [PATCH RESEND/PING 0/9] XSA-292 follow-up Jan Beulich
2019-09-11 15:21 ` [Xen-devel] [PATCH 1/9] x86: adjust cr3_pcid() return type Jan Beulich
2019-09-12 9:19 ` Roger Pau Monné
2019-09-11 15:22 ` [Xen-devel] [PATCH 2/9] x86: limit the amount of TLB flushing in switch_cr3_cr4() Jan Beulich
2019-09-12 9:54 ` Roger Pau Monné
2019-09-12 10:11 ` Jan Beulich
2019-09-12 10:38 ` Roger Pau Monné
2019-09-11 15:22 ` Jan Beulich [this message]
2019-09-12 10:34 ` [Xen-devel] [PATCH 3/9] x86/mm: honor opt_pcid also for 32-bit PV domains Roger Pau Monné
2019-09-12 10:45 ` Jan Beulich
2019-09-11 15:23 ` [Xen-devel] [PATCH 4/9] x86/HVM: move NOFLUSH handling out of hvm_set_cr3() Jan Beulich
2019-09-12 11:35 ` Roger Pau Monné
2019-09-12 11:52 ` Jan Beulich
2019-09-12 14:44 ` Roger Pau Monné
2019-09-12 14:47 ` Jan Beulich
2019-09-12 15:42 ` Roger Pau Monné
2019-09-12 15:52 ` Jan Beulich
2019-09-11 15:24 ` [Xen-devel] [PATCH 5/9] x86/HVM: refuse CR3 loads with reserved (upper) bits set Jan Beulich
2019-09-12 11:45 ` Roger Pau Monné
2019-09-12 12:01 ` Jan Beulich
2019-09-11 15:25 ` [Xen-devel] [PATCH 6/9] x86/HVM: relax shadow mode check in hvm_set_cr3() Jan Beulich
2019-09-12 14:50 ` Roger Pau Monné
2019-09-11 15:25 ` [Xen-devel] [PATCH 7/9] x86/HVM: cosmetics to hvm_set_cr3() Jan Beulich
2019-09-12 15:04 ` Roger Pau Monné
2019-09-11 15:26 ` [Xen-devel] [PATCH 8/9] x86/CPUID: drop INVPCID dependency on PCID Jan Beulich
2019-09-12 15:11 ` Roger Pau Monné
2019-09-11 15:26 ` [Xen-devel] [PATCH 9/9] x86: PCID is unused when !PV Jan Beulich
2019-09-12 15:31 ` Roger Pau Monné
2019-09-12 15:46 ` Jan Beulich
2019-09-12 15:48 ` Jan Beulich
2019-09-12 15:57 ` Roger Pau Monné
-- strict thread matches above, loose matches on Subject: below --
2019-05-02 11:35 [PATCH 0/9] XSA-292 follow-up Jan Beulich
2019-05-02 12:19 ` [Xen-devel] [PATCH 3/9] x86/mm: honor opt_pcid also for 32-bit PV domains Jan Beulich
2019-05-02 12:19 ` Jan Beulich
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