From: Matthew Auld <matthew.auld@intel.com> To: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: Re: [PATCH 3/3] drm/i915/gtt: ignore min_page_size for paging structures Date: Wed, 23 Jun 2021 14:38:14 +0100 [thread overview] Message-ID: <fbb13fc4-18bb-8e92-71b6-7a4a7d84b633@intel.com> (raw) In-Reply-To: <62c8a7a3-dcdd-ec6d-a976-7203e406d364@linux.intel.com> On 23/06/2021 14:32, Thomas Hellström wrote: > > On 6/23/21 1:26 PM, Matthew Auld wrote: >> The min_page_size is only needed for pages inserted into the GTT, and >> for our paging structures we only need at most 4K bytes, so simply >> ignore the min_page_size restrictions here, otherwise we might see some >> severe overallocation on some devices. >> >> Signed-off-by: Matthew Auld <matthew.auld@intel.com> >> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c >> b/drivers/gpu/drm/i915/gt/intel_gtt.c >> index 084ea65d59c0..61e8a8c25374 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c >> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c >> @@ -16,7 +16,7 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct >> i915_address_space *vm, int sz) >> { >> struct drm_i915_gem_object *obj; >> - obj = i915_gem_object_create_lmem(vm->i915, sz, 0); >> + obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0); > > So is this memory always required to be size aligned? or should it say > sz, PAGE_SIZE? The scratch page also hits this path, which is another can of worms. In terms of size it might need to be 64K(with proper physical alignment), which is why we can't force 4K here, and instead need to use the passed in size, where the returned page will have the same alignment. > > /Thomas > >
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com> To: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/gtt: ignore min_page_size for paging structures Date: Wed, 23 Jun 2021 14:38:14 +0100 [thread overview] Message-ID: <fbb13fc4-18bb-8e92-71b6-7a4a7d84b633@intel.com> (raw) In-Reply-To: <62c8a7a3-dcdd-ec6d-a976-7203e406d364@linux.intel.com> On 23/06/2021 14:32, Thomas Hellström wrote: > > On 6/23/21 1:26 PM, Matthew Auld wrote: >> The min_page_size is only needed for pages inserted into the GTT, and >> for our paging structures we only need at most 4K bytes, so simply >> ignore the min_page_size restrictions here, otherwise we might see some >> severe overallocation on some devices. >> >> Signed-off-by: Matthew Auld <matthew.auld@intel.com> >> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c >> b/drivers/gpu/drm/i915/gt/intel_gtt.c >> index 084ea65d59c0..61e8a8c25374 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c >> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c >> @@ -16,7 +16,7 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct >> i915_address_space *vm, int sz) >> { >> struct drm_i915_gem_object *obj; >> - obj = i915_gem_object_create_lmem(vm->i915, sz, 0); >> + obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0); > > So is this memory always required to be size aligned? or should it say > sz, PAGE_SIZE? The scratch page also hits this path, which is another can of worms. In terms of size it might need to be 64K(with proper physical alignment), which is why we can't force 4K here, and instead need to use the passed in size, where the returned page will have the same alignment. > > /Thomas > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-06-23 13:38 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-23 11:26 [PATCH 1/3] drm/i915/ttm: consider all placements for the page alignment Matthew Auld 2021-06-23 11:26 ` [Intel-gfx] " Matthew Auld 2021-06-23 11:26 ` [PATCH 2/3] drm/i915: support forcing the page size with lmem Matthew Auld 2021-06-23 11:26 ` [Intel-gfx] " Matthew Auld 2021-06-23 12:54 ` Thomas Hellström 2021-06-23 12:54 ` [Intel-gfx] " Thomas Hellström 2021-06-23 11:26 ` [PATCH 3/3] drm/i915/gtt: ignore min_page_size for paging structures Matthew Auld 2021-06-23 11:26 ` [Intel-gfx] " Matthew Auld 2021-06-23 11:51 ` Thomas Hellström 2021-06-23 11:51 ` [Intel-gfx] " Thomas Hellström 2021-06-23 12:25 ` Matthew Auld 2021-06-23 12:25 ` [Intel-gfx] " Matthew Auld 2021-06-23 12:44 ` Thomas Hellström 2021-06-23 12:44 ` [Intel-gfx] " Thomas Hellström 2021-06-23 13:32 ` Thomas Hellström 2021-06-23 13:32 ` [Intel-gfx] " Thomas Hellström 2021-06-23 13:38 ` Matthew Auld [this message] 2021-06-23 13:38 ` Matthew Auld 2021-06-23 13:39 ` Thomas Hellström 2021-06-23 13:39 ` [Intel-gfx] " Thomas Hellström 2021-06-23 12:50 ` [PATCH 1/3] drm/i915/ttm: consider all placements for the page alignment Thomas Hellström 2021-06-23 12:50 ` [Intel-gfx] " Thomas Hellström 2021-06-23 14:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] " Patchwork 2021-06-23 14:43 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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