From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Tomas Winkler <tomas.winkler@intel.com>, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/gt: nuke gen6_hw_id
Date: Wed, 21 Jul 2021 10:25:59 +0100 [thread overview]
Message-ID: <079da526-6b19-3b44-e3d0-c23e1a61e9b1@linux.intel.com> (raw)
In-Reply-To: <20210720232014.3302645-5-lucas.demarchi@intel.com>
On 21/07/2021 00:20, Lucas De Marchi wrote:
> This is only used by GRAPHICS_VER == 6 and GRAPHICS_VER == 7. All other
> recent platforms do not depend on this field, so it doesn't make much
> sense to keep it generic like that. Instead, just do a mapping from
> engine class to HW ID in the single place that is needed.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ------
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 --------
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> 3 files changed, 3 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 508221de411c..0a04e8d90e9e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -42,7 +42,6 @@
>
> #define MAX_MMIO_BASES 3
> struct engine_info {
> - u8 gen6_hw_id;
> u8 class;
> u8 instance;
> /* mmio bases table *must* be sorted in reverse graphics_ver order */
> @@ -54,7 +53,6 @@ struct engine_info {
>
> static const struct engine_info intel_engines[] = {
> [RCS0] = {
> - .gen6_hw_id = RCS0_HW,
> .class = RENDER_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -62,7 +60,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [BCS0] = {
> - .gen6_hw_id = BCS0_HW,
> .class = COPY_ENGINE_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -70,7 +67,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VCS0] = {
> - .gen6_hw_id = VCS0_HW,
> .class = VIDEO_DECODE_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -102,7 +98,6 @@ static const struct engine_info intel_engines[] = {
> },
> },
> [VECS0] = {
> - .gen6_hw_id = VECS0_HW,
> .class = VIDEO_ENHANCEMENT_CLASS,
> .instance = 0,
> .mmio_bases = {
> @@ -290,7 +285,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> engine->i915 = i915;
> engine->gt = gt;
> engine->uncore = gt->uncore;
> - engine->gen6_hw_id = info->gen6_hw_id;
> guc_class = engine_class_to_guc_class(info->class);
> engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
> engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 266422d8d1b1..64330bfb7641 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -28,13 +28,6 @@
> #include "intel_wakeref.h"
> #include "intel_workarounds_types.h"
>
> -/* Legacy HW Engine ID */
> -
> -#define RCS0_HW 0
> -#define VCS0_HW 1
> -#define BCS0_HW 2
> -#define VECS0_HW 3
> -
> /* Gen11+ HW Engine class + instance */
> #define RENDER_CLASS 0
> #define VIDEO_DECODE_CLASS 1
> @@ -268,7 +261,6 @@ struct intel_engine_cs {
>
> intel_engine_mask_t mask;
>
> - u8 gen6_hw_id;
> u8 class;
> u8 instance;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8750ffce9d61..d91386f4828e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2572,7 +2572,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define ARB_MODE_BWGTLB_DISABLE (1 << 9)
> #define ARB_MODE_SWIZZLE_BDW (1 << 1)
> #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
> -#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->gen6_hw_id)
> +
> +#define _GEN6_ENGINE_CLASS_TO_ID(class) _PICK((class), 0, 1, 3, 2)
> +#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * _GEN6_ENGINE_CLASS_TO_ID((engine)->class))
Makes sense to me.
Maybe HW_ID and HW_CLASS in the macro name? Not sure.
Only open I have is why the "Gen11+ HW Engine class + instance" comment
and now we would tie that, allegedly Gen11 concept, with Gen6-7. Care to
do some digging?
Regards,
Tvrtko
> #define GEN8_RING_FAULT_REG _MMIO(0x4094)
> #define GEN12_RING_FAULT_REG _MMIO(0xcec4)
> #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
>
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next prev parent reply other threads:[~2021-07-21 9:26 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-20 23:20 [Intel-gfx] [PATCH 0/4] Nuke legacy hw_id Lucas De Marchi
2021-07-20 23:20 ` [Intel-gfx] [PATCH 1/4] drm/i915/gt: fix platform prefix Lucas De Marchi
2021-07-21 9:11 ` Tvrtko Ursulin
2021-07-21 22:34 ` Matt Roper
2021-07-20 23:20 ` [Intel-gfx] [PATCH 2/4] drm/i915/gt: nuke unused legacy engine hw_id Lucas De Marchi
2021-07-21 9:18 ` Tvrtko Ursulin
2021-07-21 22:47 ` Matt Roper
2021-07-21 23:17 ` Lucas De Marchi
2021-07-20 23:20 ` [Intel-gfx] [PATCH 3/4] drm/i915/gt: rename legacy engine->hw_id to engine->gen6_hw_id Lucas De Marchi
2021-07-21 9:20 ` Tvrtko Ursulin
2021-07-21 22:51 ` Matt Roper
2021-07-22 5:11 ` Lucas De Marchi
2021-07-20 23:20 ` [Intel-gfx] [PATCH 4/4] drm/i915/gt: nuke gen6_hw_id Lucas De Marchi
2021-07-21 9:25 ` Tvrtko Ursulin [this message]
2021-07-21 18:44 ` Lucas De Marchi
2021-07-22 8:27 ` Tvrtko Ursulin
2021-07-21 23:02 ` Matt Roper
2021-07-21 0:35 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for Nuke legacy hw_id Patchwork
2021-07-21 0:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-21 3:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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