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From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 03/13] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format
Date: Wed, 26 Apr 2023 10:28:12 +0530	[thread overview]
Message-ID: <0b9f3525-26b4-65fb-b042-4098f7052d9a@intel.com> (raw)
In-Reply-To: <ZEZ2rWpuujlwbMN5@intel.com>

Hi Ville,

Thanks for pointing out the issues and suggestions.

I agree with the suggested changes and corrections and will make the 
changes in the next version.

Regards,

Ankit

On 4/24/2023 6:01 PM, Ville Syrjälä wrote:
> On Fri, Mar 31, 2023 at 03:46:03PM +0530, Ankit Nautiyal wrote:
>> The decision to use DFP output format conversion capabilities should be
>> during compute_config phase.
>>
>> This patch uses the members of intel_dp->dfp to only store the
>> format conversion capabilities of the DP device and uses the crtc_state
>> sink_format member, to program the protocol-converter for
>> colorspace/format conversion.
>>
>> v2: Use sink_format to determine the color conversion config for the
>> pcon (Ville).
>>
>> v3: Fix typo: missing 'break' in switch case (lkp kernel test robot).
>>
>> v4: Add helper to check if DP supports YCBCR420.
>>
>> v5: Simplify logic for computing output_format, based on the given
>> sink_format. (Ville).
>> Added scaler constraint for YCbCr420 output.
>>
>> v6: Split the patch for Scaler constraint for Ycbcr420.
>>
>> v7: Simplify the policy for selecting output_format:
>> Always try for RGB first, followed by YCBCR444, and finally by YCBCR420.
>>
>> v8: Removed redundant comments, minor refactoring. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 178 +++++++++++++++++-------
>>   1 file changed, 125 insertions(+), 53 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 450cb8ba3805..837532952936 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -827,24 +827,92 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>>   	return 0;
>>   }
>>   
>> +static bool source_can_output(struct intel_dp *intel_dp,
>> +			      enum intel_output_format format)
>> +{
>> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> +	bool ycbcr_supported = true;
>> +
>> +	/*
>> +	 * No YCbCr output support on gmch platforms.
>> +	 * Also, ILK doesn't seem capable of DP YCbCr output.
>> +	 * The displayed image is severly corrupted. SNB+ is fine.
>> +	 */
>> +	if (HAS_GMCH(i915) || IS_IRONLAKE(i915))
>> +		ycbcr_supported = false;
> That extra variable seems rather pointless...
>
>> +
>> +	switch (format) {
>> +	case INTEL_OUTPUT_FORMAT_RGB :
>> +		return true;
>> +
>> +	case INTEL_OUTPUT_FORMAT_YCBCR444:
>> +		return ycbcr_supported;
> could just 'return !GMCH && !ILK' here
>
>> +
>> +	case INTEL_OUTPUT_FORMAT_YCBCR420:
>> +		/* Platform < Gen 11 cannot output YCbCr420 format */
>> +		if (!ycbcr_supported || DISPLAY_VER(i915) < 11)
>> +			return false;
>> +
>> +		return true;
> and 'return DISPLAY_VER >= 11' here.
>
>> +
>> +	default:
>> +		MISSING_CASE(format);
>> +		return false;
>> +	}
>> +}
>> +
>> +static bool
>> +dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
>> +			 enum intel_output_format sink_format)
>> +{
>> +	if (!drm_dp_is_branch(intel_dp->dpcd))
>> +		return false;
>> +
>> +	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
>> +		return intel_dp->dfp.rgb_to_ycbcr;
>> +
>> +	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>> +		return intel_dp->dfp.rgb_to_ycbcr &&
>> +			intel_dp->dfp.ycbcr_444_to_420;
>> +
>> +	return false;
>> +}
>> +
>> +static bool
>> +dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
>> +			      enum intel_output_format sink_format)
>> +{
>> +	if (!drm_dp_is_branch(intel_dp->dpcd))
>> +		return false;
>> +
>> +	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>> +		return intel_dp->dfp.ycbcr_444_to_420;
>> +
>> +	return false;
>> +}
>> +
>>   static enum intel_output_format
>>   intel_dp_output_format(struct intel_connector *connector,
>>   		       enum intel_output_format sink_format)
>>   {
>>   	struct intel_dp *intel_dp = intel_attached_dp(connector);
>> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> +	enum intel_output_format output_format;
>>   
>> -	if (!connector->base.ycbcr_420_allowed ||
>> -	    sink_format != INTEL_OUTPUT_FORMAT_YCBCR420)
>> -		return INTEL_OUTPUT_FORMAT_RGB;
>> +	if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
>> +	    dfp_can_convert_from_rgb(intel_dp, sink_format))
>> +		output_format = INTEL_OUTPUT_FORMAT_RGB;
>>   
>> -	if (intel_dp->dfp.rgb_to_ycbcr &&
>> -	    intel_dp->dfp.ycbcr_444_to_420)
>> -		return INTEL_OUTPUT_FORMAT_RGB;
>> +	else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
>> +	    dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
>> +		output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
>>   
>> -	if (intel_dp->dfp.ycbcr_444_to_420)
>> -		return INTEL_OUTPUT_FORMAT_YCBCR444;
>>   	else
>> -		return INTEL_OUTPUT_FORMAT_YCBCR420;
>> +		output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
>> +
>> +	drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
>> +
>> +	return output_format;
>>   }
>>   
>>   int intel_dp_min_bpp(enum intel_output_format output_format)
>> @@ -2761,6 +2829,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>   					   const struct intel_crtc_state *crtc_state)
>>   {
>>   	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> +	bool ycbcr444_to_420 = false;
>> +	bool rgb_to_ycbcr = false;
>>   	u8 tmp;
>>   
>>   	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
>> @@ -2777,8 +2847,24 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>   		drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
>>   			    str_enable_disable(intel_dp->has_hdmi_sink));
>>   
>> -	tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
>> -		intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>> +	if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
>> +		switch (crtc_state->output_format) {
>> +		case INTEL_OUTPUT_FORMAT_YCBCR420:
>> +			break;
>> +		case INTEL_OUTPUT_FORMAT_YCBCR444:
>> +			ycbcr444_to_420 = true;
>> +			break;
>> +		case INTEL_OUTPUT_FORMAT_RGB:
>> +			rgb_to_ycbcr = true;
>> +			ycbcr444_to_420 = true;
>> +			break;
>> +		default:
>> +			MISSING_CASE(crtc_state->output_format);
>> +			break;
>> +		}
>> +	}
>> +
>> +	tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>>   
>>   	if (drm_dp_dpcd_writeb(&intel_dp->aux,
>>   			       DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
>> @@ -2786,13 +2872,12 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>   			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
>>   			    str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
>>   
>> -	tmp = intel_dp->dfp.rgb_to_ycbcr ?
>> -		DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>> +	tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>>   
>>   	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
>>   		drm_dbg_kms(&i915->drm,
>> -			   "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
>> -			   str_enable_disable(tmp));
>> +			    "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
>> +			    str_enable_disable(tmp));
>>   }
>>   
>>   bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>> @@ -4582,57 +4667,44 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
>>   	intel_dp_get_pcon_dsc_cap(intel_dp);
>>   }
>>   
>> +static bool
>> +intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
>> +{
>> +	if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
>> +	    (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
>> +		return true;
>> +
>> +	if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
>> +	    dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
>> +		return true;
>> +
>> +	if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
>> +	    dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
>> +		return INTEL_OUTPUT_FORMAT_YCBCR444;
> return true
>
> The rest looks good.
>
>> +
>> +	return false;
>> +}
>> +
>>   static void
>>   intel_dp_update_420(struct intel_dp *intel_dp)
>>   {
>>   	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>   	struct intel_connector *connector = intel_dp->attached_connector;
>> -	bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
>> -
>> -	/* No YCbCr output support on gmch platforms */
>> -	if (HAS_GMCH(i915))
>> -		return;
>>   
>> -	/*
>> -	 * ILK doesn't seem capable of DP YCbCr output. The
>> -	 * displayed image is severly corrupted. SNB+ is fine.
>> -	 */
>> -	if (IS_IRONLAKE(i915))
>> -		return;
>> -
>> -	is_branch = drm_dp_is_branch(intel_dp->dpcd);
>> -	ycbcr_420_passthrough =
>> +	intel_dp->dfp.ycbcr420_passthrough =
>>   		drm_dp_downstream_420_passthrough(intel_dp->dpcd,
>>   						  intel_dp->downstream_ports);
>>   	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
>> -	ycbcr_444_to_420 =
>> +	intel_dp->dfp.ycbcr_444_to_420 =
>>   		dp_to_dig_port(intel_dp)->lspcon.active ||
>>   		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
>>   							intel_dp->downstream_ports);
>> -	rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>> -								 intel_dp->downstream_ports,
>> -								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>> -
>> -	if (DISPLAY_VER(i915) >= 11) {
>> -		/* Let PCON convert from RGB->YCbCr if possible */
>> -		if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
>> -			intel_dp->dfp.rgb_to_ycbcr = true;
>> -			intel_dp->dfp.ycbcr_444_to_420 = true;
>> -			connector->base.ycbcr_420_allowed = true;
>> -		} else {
>> -		/* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
>> -			intel_dp->dfp.ycbcr_444_to_420 =
>> -				ycbcr_444_to_420 && !ycbcr_420_passthrough;
>> +	intel_dp->dfp.rgb_to_ycbcr =
>> +		drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>> +							  intel_dp->downstream_ports,
>> +							  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>>   
>> -			connector->base.ycbcr_420_allowed =
>> -				!is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
>> -		}
>> -	} else {
>> -		/* 4:4:4->4:2:0 conversion is the only way */
>> -		intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
>> -
>> -		connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
>> -	}
>> +	connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
>>   
>>   	drm_dbg_kms(&i915->drm,
>>   		    "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
>> -- 
>> 2.25.1

  reply	other threads:[~2023-04-26  4:58 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-31 10:16 [Intel-gfx] [PATCH 00/13] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
2023-03-31 10:16 ` [Intel-gfx] [PATCH 01/13] drm/i915/display: Add new member to configure PCON color conversion Ankit Nautiyal
2023-03-31 10:16 ` [Intel-gfx] [PATCH 02/13] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap Ankit Nautiyal
2023-04-24 12:46   ` Ville Syrjälä
2023-04-26  4:53     ` Nautiyal, Ankit K
2023-03-31 10:16 ` [Intel-gfx] [PATCH 03/13] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format Ankit Nautiyal
2023-04-24 12:31   ` Ville Syrjälä
2023-04-26  4:58     ` Nautiyal, Ankit K [this message]
2023-03-31 10:16 ` [Intel-gfx] [PATCH 04/13] drm/i915/dp: Configure PCON for conversion of output_format to YCbCr444 Ankit Nautiyal
2023-04-24 12:32   ` Ville Syrjälä
2023-03-31 10:16 ` [Intel-gfx] [PATCH 05/13] drm/i915/display: Use sink_format instead of ycbcr420_output flag Ankit Nautiyal
2023-04-24 12:37   ` Ville Syrjälä
2023-04-26  5:09     ` Nautiyal, Ankit K
2023-03-31 10:16 ` [Intel-gfx] [PATCH 06/13] drm/i915/dp: Add helper to get sink_format Ankit Nautiyal
2023-04-24 12:38   ` Ville Syrjälä
2023-03-31 10:16 ` [Intel-gfx] [PATCH 07/13] drm/i915/dp: Rearrange check for illegal mode and comments in mode_valid Ankit Nautiyal
2023-03-31 10:16 ` [Intel-gfx] [PATCH 08/13] drm/i915/dp: Consider output_format while computing dsc bpp Ankit Nautiyal
2023-04-24 12:51   ` Ville Syrjälä
2023-04-26  5:31     ` Nautiyal, Ankit K
2023-03-31 10:16 ` [Intel-gfx] [PATCH 09/13] drm/i915/dp_mst: Use output_format to get the final link bpp Ankit Nautiyal
2023-04-24 12:58   ` Ville Syrjälä
2023-03-31 10:16 ` [Intel-gfx] [PATCH 10/13] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC Ankit Nautiyal
2023-03-31 10:16 ` [Intel-gfx] [PATCH 11/13] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP Ankit Nautiyal
2023-03-31 10:16 ` [Intel-gfx] [PATCH 12/13] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints Ankit Nautiyal
2023-03-31 10:16 ` [Intel-gfx] [PATCH 13/13] drm/i915/dp: Use consistent name for link bpp and compressed bpp Ankit Nautiyal
2023-04-24 13:04   ` Ville Syrjälä
2023-04-26  6:10     ` Nautiyal, Ankit K
2023-03-31 16:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev13) Patchwork
2023-03-31 16:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-31 16:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-01 16:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-04-24 13:09 ` [Intel-gfx] [PATCH 00/13] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ville Syrjälä
2023-04-25  7:30   ` Nautiyal, Ankit K

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